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L64364 ATM-SAR Chip
ATMizer
March 2000
Order Number R14008.A
This document contains proprietary information Logic Corporation. information contained herein used disclosed third parties without express written permission officer Logic Corporation. Document DB14-000037-01, Second Edition (March 2000) This document describes Logic Corporation's L64364 ATMizer® ATM-SAR Chip will remain official reference source revisions this product until rescinded update. receive product literature, visit http://www.lsilogic.com. Logic Corporation reserves right make changes products herein time without notice. Logic does assume responsibility liability arising application product described herein, except expressly agreed writing Logic; does purchase product from Logic convey license under patent rights, copyrights, trademark rights, other intellectual property rights Logic third parties. Copyright 1995-1998, 2000 Logic Corporation. rights reserved.
TRADEMARK ACKNOWLEDGMENT
Logic logo design, CoreWare, G10, MiniRISC, ATMizer registered trademarks Logic Corporation. other brand product names trademarks their respective companies.
Contents
Preface Chapter Introduction Overview Functional Description Features Functional Overview Major Functional Units AProcessing Unit Enhanced ACell Interface Scheduler Timer Units Interface Endian Considerations Secondary Memory Controller Other Features Signal Descriptions Signals Summary Interface Secondary Memory Interface Utopia Interface Clocks Utility Signals Signals Serial EPROM Interface JTAG Test Interface Power Ground Pins
Chapter
Chapter
3-10 3-15 3-17 3-18 3-19 3-20
Contents
Chapter
AProcessing Unit Overview 4.1.1 Block Diagram 4.1.2 Features Architecture 4.2.1 CW4011 Core 4.2.2 Cache External Interface 4.2.3 CW4011 Pipeline Instruction Summary 4.3.1 Instruction Formats 4.3.2 Load Store Instructions 4.3.3 Computational Instructions 4.3.4 Jump Branch Instructions 4.3.5 Trap Instructions 4.3.6 Special Instructions 4.3.7 Coprocessor Instructions 4.3.8 System Control Coprocessor (CP0) Instructions 4.3.9 Cache Maintenance Instructions 4.3.10 CW4011 Instruction Extensions 4.3.11 ATMizer Instruction Extensions Data Manipulation Registers 4.4.1 Rotate Register (23) 4.4.2 Circular Mask Register (24) Cache Memory 4.5.1 Cache States 4.5.2 Address Cache Tags 4.5.3 D-Cache Scratch Mode 4.5.4 I-Cache Mode 4.5.5 Cache Instructions Exceptions 4.6.1 R3000 Exception Compatibility Mode 4.6.2 Exception Handling Registers 4.6.3 CW4011 Exceptions Memory 4.7.1 Operating Modes 4.7.2 ATMizer Chip Memory 4.7.3 Hardware Registers
4-10 4-13 4-14 4-17 4-24 4-28 4-29 4-29 4-30 4-31 4-31 4-42 4-49 4-49 4-49 4-50 4-50 4-52 4-53 4-54 4-54 4-59 4-61 4-62 4-79 4-95 4-95 4-96 4-97
Contents
4.10
4.11
ATMizer Chip Primary Secondary Port Access Interrupts 4.8.1 External Nonvectored Interrupts 4.8.2 External Vectored Interrupt Sources 4.8.3 Enabling Vectored Interrupts 4.8.4 Vectored Interrupt Processing 4.8.5 Status Checking 4.8.6 Coprocessor Condition Signals CW4011 Accesses Watchdog Timers 4.10.1 Watchdog Timer 4.10.2 Watchdog Timer 4.10.3 Priority Register 4.10.4 APU_Error Register 4.10.5 Error Register Boot Procedures 4.11.1 Boot Location 4.11.2 Serial Interface Boot Sequence 4.11.3 Cell Buffer Memory Boot Sequence 4.11.4 Secondary EPROM Boot Sequence 4.11.5 Access Serial EPROM
4.7.4
4-98 4-101 4-101 4-103 4-105 4-106 4-107 4-111 4-111 4-112 4-112 4-113 4-113 4-114 4-116 4-117 4-117 4-118 4-118 4-119 4-119
Chapter
Enhanced Overview Data Structures 5.2.1 Descriptor Structure 5.2.2 Buffer Descriptor EDMA Commands 5.3.1 RxCell Command 5.3.2 TxCell Command 5.3.3 Buff Command 5.3.4 Move Command 5.3.5 TxConClose/RxConClose Command 5.3.6 Checking Status 5.3.7 Buffer Completion Data Structures Locations
5-16 5-21 5-23 5-24 5-25 5-28 5-32 5-32 5-35 5-44
Contents
Chapter A6.1
5.4.1 Descriptors Address Calculation 5.4.2 Buffer Descriptors 5.4.3 Buffer Payload Register Descriptions 5.5.1 EDMA Control Register 5.5.2 EDMA Error Mask Register 5.5.3 EDMA Error Register AAL5 Mode Operation 5.6.1 Transmit Cell Processing Requests 5.6.2 Receive Cell Processing Requests 5.6.3 Free Buffers 5.6.4 Endian Little Endian AAL0 Mode Operation Cell Interface Overview Cell Size Layout Cell Descriptor Memory-Mapped Registers 6.4.1 ACI_Ctrl Register 6.4.2 ACI_FreeList Register 6.4.3 ACI_TxTimer Register 6.4.4 ACI_TxSize Register 6.4.5 ACI_TxLimit ACI_RxLimit Registers 6.4.6 ACI_RxMask Register 6.4.7 ACI_Free Register 6.4.8 ACI_RxRead Register 6.4.9 ACI_TxWrite Register 6.4.10 ACI_RxCells ACI_TxCells Registers 6.4.11 ACI_Error Register 6.4.12 ACI_RxSize Register 6.4.13 ACI_BadHEC Register 6.4.14 ACI_ClearBytes Register 6.4.15 ACI_FreeCount Register Cell Buffer Manager 6.5.1 Cell Buffer Initialization 6.5.2 Requesting Releasing Free Cell Location
5-44 5-46 5-48 5-50 5-52 5-54 5-57 5-58 5-58 5-60 5-62 5-62 5-63
6-10 6-12 6-13 6-14 6-14 6-14 6-14 6-15 6-15 6-16 6-16 6-17 6-17 6-18 6-18 6-18 6-19 6-20
Contents
6.10
6.5.3 Inserting Removing Cells from FIFO 6.5.4 Setting Checking FIFO Sizes Receiver 6.6.1 Receiver Operations 6.6.2 Receive FIFO Status 6.6.3 Receive Priority Scheme 6.6.4 Processing 6.6.5 CRC10 Verifications 6.6.6 Utopia Parity Checking Transmitter 6.7.1 Transmitter Operations 6.7.2 Transmit FIFO Status 6.7.3 Idle Cell Generation 6.7.4 Port Selection Port Polling 6.7.5 Generation 6.7.6 CRC10 Generation 6.7.7 Transmitter Time-Out 6.7.8 Utopia Parity Generation Polling Scheme Loopback Mode Utopia Interface 6.10.1 Utopia Clocks 6.10.2 Unused Pins
6-20 6-21 6-22 6-22 6-23 6-24 6-24 6-25 6-25 6-25 6-26 6-26 6-27 6-27 6-28 6-28 6-28 6-29 6-29 6-30 6-30 6-30 6-30
Chapter
Scheduler Unit Scheduler Overview Priority Mode Operation 7.2.1 Example Priority Mode Operation 7.2.2 Service Command 7.2.3 Schedule Command 7.2.4 Command Flat Mode Operation 7.3.1 Example Flat Mode Operation 7.3.2 Service Command 7.3.3 Schedule Command 7.3.4 Command Calendar Switching
7-10 7-11 7-11
Contents
Command Execution Register Descriptions 7.6.1 Scheduler Control Register 7.6.2 Calendar Size Register 7.6.3 SCD_Now Register 7.6.4 SCD_Serv, SCD_Sched, SCD_Tic Registers 7.6.5 SCD_HeadSel Register 7.6.6 SCD_Err Register 7.6.7 SCD_Class0-5 Registers 7.6.8 Calculating Descriptor Address 7.6.9 Calculating Calendar Table Address
7-13 7-14 7-15 7-15 7-15 7-16 7-16 7-16 7-17 7-18 7-19
Chapter
Timer Unit Introduction Timer Clock Selection 8.2.1 TM_ClockSel Register 8.2.2 TM_ClockSel2 Register Time-Out Events Interface Interface Overview Configuration Space Registers 9.2.1 Vendor Register 9.2.2 Device Register 9.2.3 Command Register 9.2.4 Status Register 9.2.5 Revision Register 9.2.6 Class Code Register 9.2.7 Cache Line Size Register 9.2.8 Latency Timer Register 9.2.9 Header Type Register 9.2.10 Base Address Register 9.2.11 Base Address Register 9.2.12 Subsystem Vendor Register 9.2.13 Subsystem Register 9.2.14 Interrupt Line Register 9.2.15 Interrupt Register
Chapter
9-10 9-10 9-11 9-11 9-12 9-12 9-13 9-15 9-15 9-16 9-16
viii
Contents
9.2.16 Minimum Grant Register 9.2.17 Maximum Latency Register 9.2.18 TRDY_Timer Register 9.2.19 Retry_Timer Register 9.2.20 Configuration Target Operation 9.2.21 Configuration Master Operation Primary Port Registers 9.3.1 XPP_Ctrl Register 9.3.2 PP_Ctrl Register 9.3.3 Primary Port Slave Prefetch Register 9.3.4 Primary Port Error Register 9.3.5 Primary Port Error Address Register Slave Transactions 9.4.1 Mailbox 9.4.2 Slave Write Timing 9.4.3 Slave Read Timing 9.4.4 Slave Errors Master Transactions 9.5.1 Master Write Timing 9.5.2 Master Write Errors 9.5.3 Master Read Timing 9.5.4 Master Read Errors Balancing Usage 9.6.1 Master Write 9.6.2 Master Read 9.6.3 Slave Write 9.6.4 Slave Read
9-17 9-17 9-18 9-18 9-19 9-20 9-21 9-22 9-24 9-25 9-27 9-29 9-29 9-30 9-32 9-34 9-36 9-36 9-37 9-39 9-40 9-43 9-44 9-44 9-45 9-45 9-46
Chapter
Secondary Memory Controller 10.1 Overview 10.2 Configuration 10.2.1 SP_Ctrl Register 10.2.2 Secondary Clock Control Register 10.3 Secondary Performance Considerations 10.4 SDRAM Controller 10.4.1 SDRAM Connections 10.4.2 SDRAM Controller Configuration
10-2 10-3 10-4 10-6 10-11 10-13 10-14 10-15
Contents
10.4.3 SDRAM Initialization 10.4.4 SDRAM Refresh 10.4.5 Secondary Time-Out 10.4.6 SDRAM Command Summary 10.4.7 SDRAM Read Transfer 10.4.8 SDRAM Write Transfer 10.5 SSRAM Controller 10.5.1 SSRAM Read Transfers 10.5.2 SSRAM Write Transfers 10.6 32-Bit SRAM/EPROM Controller 10.6.1 32-Bit SRAM/EPROM Read Transfer 10.6.2 32-Bit SRAM Write Transfers 10.6.3 32-Bit SRAM/EPROM SB_RDYn Timing 10.7 Controller 10.7.1 Read Transfers 10.7.2 Write Transfers 10.7.3 SB_RDYn Timing 10.8 Eight-Bit SRAM/EPROM Controller 10.8.1 Eight-Bit SRAM/EPROM Read Transfers 10.8.2 Eight-Bit SRAM/EPROM Write Transfers 10.8.3 Eight-Bit SRAM/EPROM SB_RDYn Timing 10.9 External Masters 10.10 Error Reporting Chapter System Clock 11.1 System Clock Options 11.2 Clock Synthesis 11.3 Design Considerations JTAG Interface 12.1 JTAG Instructions 12.1.1 BYPASS Instruction 12.1.2 SAMPLE/PRELOAD Instruction 12.1.3 EXTEST Instruction 12.1.4 HI-Z Instruction 12.2 Boundary Scan Chain Order
10-18 10-19 10-21 10-22 10-22 10-23 10-24 10-26 10-26 10-27 10-27 10-28 10-29 10-31 10-31 10-32 10-33 10-35 10-35 10-36 10-37 10-39 10-40
11-1 11-2 11-4
Chapter
12-1 12-2 12-2 12-2 12-3 12-3
Contents
Chapter
Specifications 13.1 Timing 13.2 Electrical Requirements 13.2.1 Drivers Receivers 13.2.2 Level Requirements 13.3 Summary 13.4 Package Information Register Summary ACell ACell Structure AAL5 Trailer Glossary Abbreviations Customer Feedback
13-1 13-10 13-10 13-13 13-14 13-15
Appendix Appendix
Appendix
Figures 4.10 4.11 4.12 4.13 L64364 Functional Block Diagram Signals (Utopia Master) Signals (Utopia Slave) Block Diagram CW4011 Block Diagram CW4011 Instruction Pipeline Instruction Formats Byte Specifications Loads/Stores Rotate Register CMask Register I-Cache D-Cache State Diagram D-Cache WriteBack State Diagram Cache Address Format Access Format Cache Instruction Format Test Mode Format 4-14 4-15 4-49 4-49 4-51 4-52 4-53 4-54 4-55 4-59
Contents
4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 4.28 4.29 4.30 4.31 4.32 4.33 4.34 4.35 4.36 4.37 4.38 4.39 4.40 4.41 4.42 4.43 4.44 4.45
Register Count Register Compare Register Status Register (R4000 Mode) Status Register (R3000 Mode) Cause Register Register PRId Register Register LLAdr Register Register Register BPCM Register BDAM Register Error Register Cold Reset Exception Warm Reset, Exceptions Common Exceptions Debug Exception External Vectored Interrupt Exception CW4011 Virtual Memory APU_AddrMap Register Primary Port Address Formation Secondary Address Formation Exception Vectors APU_VIntEnable Register APU_VIntBase Register Format Status Register Format APU_SCbus_Watchdog Register APU_OCAbus_Watchdog Register APU_Priority Register APU_Error Register OCA_Err Register EDMA Processors Virtual Connection Buffer Descriptors Virtual Connection Descriptor Descriptor Control Field BuffPres ConAct Bits Timing VCD_RxCtrl Usage
4-63 4-64 4-65 4-65 4-68 4-70 4-72 4-72 4-73 4-77 4-77 4-77 4-78 4-78 4-79 4-80 4-80 4-81 4-81 4-82 4-95 4-98 4-100 4-100 4-106 4-106 4-107 4-112 4-113 4-114 4-114 4-116 5-11 5-13 5-14
Contents
5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 5.24 5.25 5.26 5.27 5.28 5.29 5.30 5.31
Buffer Descriptor Buffer Descriptor Control Field EDMA Request Completion Queues EDMA_RxCell Register Format EDMA_TxCell Register Format EDMA_Buff Register Format EDMA_MoveSrc EDMA_MoveDst Register Format EDMA_MoveCount Register EDMA_MoveCount2 Register Tx/RxConClose Command Format EDMA_Status Register Primary Completion Queue Auxiliary Completion Queue Buffer Status Bits TX/RX_EDMA_VCD_Base Register Descriptor Address Calculation Memory Descriptor Address Calculation Local Cell Buffer Memory Buffer Descriptor Address Calculation EDMA_BFD_FBase Register EDMA_BFD_LBase Register EDMA_Ctrl Register EDMA_ErrMask Register EDMA_BusErr Register Byte Swapping Descriptor Control Fields (AAL0 Mode Uses CRC32 Field) Block Diagram Cell Layout Cell Descriptor Format ACI_Ctrl Register ACI_FreeList Register ACI_TxTimer Register Format ACI_TxWrite Register ACI_BadHEC Register Descriptor Format (Word Scheduler Calendar Table Priority Mode Priority Mode Calendar Table
5-16 5-18 5-21 5-23 5-25 5-26 5-28 5-29 5-30 5-32 5-33 5-36 5-36 5-37 5-45 5-45 5-46 5-47 5-47 5-47 5-52 5-54 5-57 5-63 5-64 6-10 6-13 6-13 6-16 6-17
Contents
xiii
7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 9.10 9.11 9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21
Priority Mode Calendar Table Service Command Return Value SCD_Sched Register Format Format SCD_HeadSel Register Priority Mode Calendar Table Flat Mode Calendar Table after Schedule Command Flat Mode Calendar Table after Command Flat Mode Calendar Table with SCD_HeadSel0 Format SCD_CalSwitch Register Flat Mode Calendar Table Flat Mode Calendar Table Scheduler Control Register Format SCD_Err Register SCD_Class0-5 Registers Format Descriptor Address Computations Calendar Table Address Computations Timer Clock Selection Registers Format Interface Block Diagram Configuration Space Registers Vendor Register Device Register Command Register Status Register Revision Register Class Code Register Cache Line Size Register Latency Timer Register Reader Type Register Base Address Register Base Address Register Subsystem Vendor Register Subsystem Register Interrupt Line Register Interrupt Register Minimum Grant Register Maximum Latency Register TRDY_Timer Register Retry_Timer Register
7-10 7-11 7-12 7-12 7-15 7-17 7-17 7-18 7-19 9-10 9-10 9-11 9-11 9-12 9-12 9-13 9-15 9-15 9-16 9-16 9-17 9-17 9-18 9-18
Contents
9.22 9.23 9.24 9.25 9.26 9.27 9.28 9.29 9.30 9.31 9.32 9.33 9.34 9.35 9.36 9.37 9.38 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12 10.13 10.14 10.15 10.16 10.17 10.18 10.19 10.20 10.21
Configuration Space Read Configuration Space Write XPP_Ctrl Register PP_Ctrl Register PP_SlavePFtch Register PP_Err Register PP_ErrAddr Register Mailbox Registers Slave Write Timing Slave Write Stop Timing Parity Error Timing Slave Read Timing Master Write Timing Master Write Stop Timing Master Read Timing Master Read Stop Timing Master Read Error Timing SP_Ctrl Register Clock Relationships Secondary Clock Control Register Effects SB_DCLK Delay Register Effects SB_CLKO Delay Register SP_SDRAM Register SDRAM Mode Register SP_Refresh Register SDRAM Refresh Timing SDRAM Read Timing SDRAM Write Timing SSRAM Read Timing SSRAM Write Timing SRAM Read Timing SRAM Write Timing 32-Bit SRAM/EPROM Read Timing with SB_RDYn 32-Bit SRAM/EPROM Write Timing with SB_RDYn Read Timing Write Timing Read Timing with SB_RDYn Write Timing with SB_RDYn
9-20 9-20 9-22 9-24 9-26 9-27 9-29 9-31 9-33 9-33 9-34 9-35 9-37 9-38 9-41 9-42 9-42 10-4 10-6 10-7 10-8 10-10 10-15 10-18 10-19 10-21 10-23 10-24 10-26 10-27 10-28 10-29 10-30 10-30 10-32 10-33 10-34 10-34
Contents
10.22 10.23 10.24 10.25 10.26 10.27 10.28 11.1 11.2 11.3 13.1 13.2 13.3 Tables 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18
Eight-Bit SRAM/EPROM Read Timing Eight-Bit SRAM Write Timing Eight-Bit SRAM/EPROM Read Timing with SB_RDYn Eight-Bit SRAM/EPROM Write Timing with SB_RDYn Secondary Grant Timing SB_Err Register SB_ErrAddr Register Clock Selection Synthesis Circuit Phase-Locked Loop Supply Filtering Output Signal Timing Reference Points Input Signal Timing Reference Points MQuad Mechanical Drawing (Sheet ACell Layout AAL5 Trailer Layout
10-36 10-37 10-38 10-38 10-39 10-40 10-41 11-2 11-3 11-4 13-1 13-2 13-16
Big/Little Endian Mapping Instruction Summary Load Store Instructions Summary Load Store Instruction Summary-MIPS Extensions Immediate Instruction Summary Three-Operand, Register Type-Instruction Summary Shift Instruction Summary Multiply/Divide Instruction Summary Execution Time Multiply Divide Instructions Instruction Extensions CW4011 Extensions Summary Rate Instruction Extensions Jump Instruction Summary Branch Instruction Summary Branch-Likely Instruction Summary-MIPS Extensions Trap Instruction Summary-MIPS Extensions Special Instruction Summary Coprocessor Instruction Summary Instruction Summary
4-10 4-16 4-17 4-18 4-19 4-20 4-21 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-29 4-30
Contents
4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 4.28 4.29 4.30 4.31 4.32 4.33 4.34 4.35 4.36 5.10 10.1 10.2 10.3
Instruction Extension Summary Cache Maintenance Instruction Summary D-Cache WriteBack Mode Cache Control Bits Encoding Exceptions Exception Processing Registers Exception Codes Exception Vector Base Addresses Exception Vector Offset Addresses Exception Priority Order Segment Properties ATMizer Chip Memory ATMizer Chip Hardware Register Nonvectored Interrupt Sources Vectored Interrupt Sources Coprocessor Condition Signals Boot Sequence EDMA Commands Descriptor Fields Descriptor Control Bits Buffer Descriptor Fields Buffer Descriptor Control Bits BFS_BuffFree, BFS_BuffLarge, BFS_FreeSel Encoders Completion Queue Messages Completion Queue Messages Buff Completion Queue Messages EDMA Memory Mapped Registers Cell Size Memory Mapped Registers Scheduler Registers Timer Unit Registers FIFO's ATMizer Chip External Memory Mbyte Secondary Memory Mbyte Secondary Memory Clocks Data Word
4-30 4-31 4-51 4-57 4-58 4-60 4-62 4-71 4-83 4-83 4-84 4-96 4-96 4-97 4-101 4-103 4-111 4-118 5-12 5-16 5-19 5-27 5-42 5-43 5-44 5-50 7-14 9-30 10-3 10-3 10-12
Contents
xvii
10.4 10.5 10.6 10.7 10.8 10.9 11.1 12.1 12.2 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9
Transfer Lead-Off Cycles ATMizer Chip SDRAM Interconnections SDRAM Command Summary SSRAM Configurations SSRAM Interconnections Secondary Device Connections Loop Filter Components JTAG Instruction Register Encoding L64364 Boundary Scan Chain Interface Timing Secondary Timing Utopia Interface Transmit Timing Utopia Interface Receive Timing Miscellaneous Timing Drivers Receivers Characteristics L64364 Summary Alphabetical List MQUAD Electrical Thermal Data
10-13 10-14 10-22 10-25 10-25 10-31 11-3 12-2 12-3 13-2 13-5 13-6 13-8 13-9 13-10 13-13 13-14 13-15
xviii
Contents
Preface
This book primary reference technical manual L64364 ATMizer® ATM-SAR Chip. contains complete functional description L64364 includes complete physical electrical specifications L64364.
Audience This book assumes that have some familiarity with concepts Asynchronous Transfer Mode (ATM), data communications, microprocessors, related support devices. people benefit from this book are:
Organization
Engineers managers evaluating L64364 possible Aapplications. Engineers designing L64364 into system. Software developers writing software L64364.
This book following chapters:
Chapter Introduction, provides overview ATMizer ATM-SAR Chip lists features. Chapter Functional Overview, describes ATMizer chip functional block level. Chapter Signal Descriptions, lists describes input/output signals ATMizer chip. Chapter AProcessing Unit, describes architecture, instruction set, registers, cache memory, memory map, interrupts, exceptions, boot procedures AProcessing Unit.
Preface
Chapter Enhanced DMA, describes data structures used EDMA, EDMA commands, registers, operation AAL0 AAL5 modes. Chapter ACell Interface, describes Acell size layout, cell descriptor, registers, Cell Buffer Manager, receiver, transmitter, Utopia polling schemes, loopback mode ACell Interface. Chapter Scheduler Unit, describes Scheduler Unit's modes operation, command execution, registers. Chapter Timer Unit, describes timer clocks selected, timer registers, time-out events. Chapter Interface, describes registers, master slave transactions, ATMizer chip balances usage. Chapter Secondary Memory Controller, describes controller configuration, discusses performance considerations, describes operation individual controllers. Chapter System Clock, discusses clock selection describes synthesis using phase-locked loop. Chapter JTAG Interface, describes JTAG instructions supported L64364 order L64364 boundary scan chain. Chapter Specifications, provides timing figures, electrical requirements, pinout information, package information ATMizer chip. Appendix Register Summary, provides brief summary registers ATMizer chip includes page number references their descriptions. Appendix ACell, describes layout fields Acell header AAL5 trailer. Appendix Glossary Abbreviations, lists abbreviations used manual defines them.
Preface
Related Publications Logic's MiniRISC® CW4011 Superscalar Microprocessor Core Technical Manual, Order C14040
AForum Utopia Level Level V1.0, af-phy-0039.00 Local Specification IEEE 1149.1, Standard Test Access Port Boundary Scan Architecture
Conventions Used This Manual following signal naming conventions used throughout this manual:
Signal names uppercase characters. Active-LOW signals have lowercase signal name (for example, RESETn) while active-HIGH signals not. Multiple control signals such external interrupts grouped (for example, EXT_INTn[5:0]), they treated control signals. Signal names, commands, register bits fields courier. CW4011 core CW4011 shell interface signals unidirectional.
word assert means drive signal true active. word deassert means drive signal false inactive. word means change registers, descriptors, etc.) from logical logical word clear means change from Hexadecimal numbers indicated prefix "0x"-for example, 0x32CF. Binary numbers indicated prefix "0b"-for example, 0b0011.0010.1100.1111. hexadecimal form used much possible numbers with four more bits. L64364 requires over internal external registers. These described appropriate chapters sections. Register references other sections manual followed page number their description parenthesis. addition, Appendix lists registers functional area, includes their addresses, provides page number references their descriptions.
Preface
xxii
Preface
Chapter Introduction
This chapter introduces Logic L64364 Application Specific Standard Product (ASSP) includes following sections:
Section 1.1, "Overview," page Section 1.2, "Functional Description," page Section 1.3, "Features," page
Overview
L64364 Application-Specific Standard Product highly integrated ASegmentation Reassembly (SAR) engine optimized internetworking applications. L64364 third generation device within Logic's ATMizer product family offers important enhancements over previous L64363 chip. primary feature ATMizer product family flexibility offered AProcessing Unit (APU), which based embedded MIPS processor. allows modify device behavior downloading code accommodate changes Astandards, particularly enhancements adaptations flow control algorithms. specific hardware functional blocks, including complete controller, support APU. These blocks off-load repetitive data manipulation tasks from APU, allowing achieve full-duplex, Mbits/s performance levels. L64364 currently implemented theLSI Logic G10®-p 0.35micron CMOS process available 240-pin MQUAD package.
L64364 ATMizer ATM-SAR Chip
Functional Description
L64364 designed provide Mbits/s full-duplex operation while performing segmentation reassembly AAdaptation Layer (AAL5) CS-PDUs. specialized hardwired AAL5 engine, called Enhanced (EDMA), assists MIPS-based AProcessing Unit segmentation reassembly tasks memory management functions. Although EDMA responsible basic segmentation reassembly functions, operates under full control APU. responsible traffic management, host messaging, other upper layer tasks. option, advanced functions hardwired units switched-off give full control operations. However, this will impact overall performance. AProcessing Unit based upon Logic MIPS compatible CW4011 MiniRISC microprocessor core. processor delivers MIPS peak (110 MIPS sustained) when operating MHz. instruction extended with Aspecific instructions enhance performance. These instructions accelerate cell rate calculations Available Rate (ABR) services allowing direct arithmetic operations (add, subtract, multiply) rates expressed AForum floating point 15-bit numbers. Scheduling policing different AQuality Service (QoS) connections achieved efficiently with help integrated hardware Scheduler that supports priority classes. Scheduler uses calendar tables create arbitrary traffic schemes limit Virtual Connections (VCs). primary interface device MHz, 32-bit wide, Bus. master, L64364 able autonomously access control data structures located system memory. slave, device provides transparent access local memory, internal Cell Buffer Memory (CBM), internal hardware registers external masters. interface implements four separate FIFOs maximize performance simultaneous read/write operations master slave.
Introduction
L64364 integrates memory controller that provides glueless interface asynchronous SRAMs, synchronous SRAMs, synchronous DRAMs that used local memory; also serve interface external physical layer devices such framers. memory controller allows booting from parallel, byte-wide EPROMs from serial EPROMs. device includes JTAG controller boundary scan logic simplify board-level tests.
Features
features L64364 are:
Supports full-duplex, OC-3 (155 Mbits/s) rate. Processes AAL1, AAL3/4, AAL5 protocol layers. Includes scatter/gather EDMA, which supports fragmented unaligned host data buffers. Virtual Connections. Supports operation management functions. Supports maximum traffic types. Supports flow control algorithms, including AForum rate-based scheme. Provides flexible Acell header translation mechanism. Performs error monitoring, statistics gathering, host messaging, diagnostics. MHz, 32-bit, compliant interface bus. MHz, 8-bit, Utopia Level compliant interface bus.
Features
Introduction
Chapter Functional Overview
This chapter provides overview L64364 ATMizer chip functional units. Then separate sections summarize features each functional unit. Subsequent chapters this manual provide more detailed descriptions each unit. This chapter contains following sections:
Section 2.1, "Major Functional Units," page Section 2.2, "AProcessing Unit," page Section 2.3, "Enhanced DMA," page Section 2.4, "ACell Interface," page Section 2.5, "Scheduler Timer Units," page Section 2.6, "PCI Interface," page Section 2.7, "Endian Considerations," page Section 2.8, "Secondary Memory Controller," page Section 2.9, "Other Features," page
Major Functional Units
shown Figure 2.1, L64364 includes following major functional units:
Enhanced (EDMA) AProcessing Unit (APU) Scheduler Unit Timer Unit ACell Interface (ACI)
L64364 ATMizer ATM-SAR Chip
Figure
Primary Port Interface Interface Secondary Port Memory Controller (SBC) Cell Buffer Memory (CBM) Separate Instruction Data Caches/RAM JTAG Controller Clock Phase-Locked Loop (PLL)
L64364 Functional Block Diagram
Local
Interface
Secondary Memory Controller Secondary Port
Primary Port Clock
AProcessing Unit
Enhanced
Scheduler Unit
Timer Unit
Kbyte Instruction Cache
Kbyte Data Cache
Kbyte Cell Buffer Memory
ACell Interface
Utopia
Functional Overview
AProcessing Unit
AProcessing Unit based CW4011 MiniRISC Core. features include following:
MIPS MiniRISC Processor with Aspecific extensions. native MIPS peak, native MIPS sustained MHz. Custom floating point processor Arate calculations. Kbyte Instruction Cache implemented sets. Each configurable cache RAM. Kbyte Data Cache implemented sets. Each configurable cache RAM. boot options include external serial EPROM, external byte-wide EPROM, host download ATMizer's Cell Buffer Memory. Messaging mailbox host-to-ATMizer communications.
Enhanced
Enhanced complete AAL5 engine with hardware assists other AALs. EDMA autonomously performs tasks, freeing scheduling user value functions. EDMA features include following.
AAL5 engine capable sustained Mbytes/s cell throughput. Hardware support AAL1 AAL3/4 functions. Scatter/gather support fragmented misaligned host data buffers. Support Virtual Connections (practical limit external memory). Support payload buffers (practical limit external memory). Independent Transmit, Receive, Buffer, Move engines optimize memory bandwidth utilization.
AProcessing Unit
Optional byte swapping support little endian hosts. Programmable cell length 53-65 bytes. Optional cell header insertion/deletion. CRC-32 generation/checking AAL5. UU/CPI support AAL5. Move command supports packet transfers from Secondary Memory. Insertion extraction congestion notification, EFCI CLP, per-cell per-CS-PDU basis.
ACell Interface
ACell Interface (ACI) consists Utopia, Multi-PHY, eight-bit interface, Cell Buffer Manager. Cell Buffer Manager maintains transmit FIFO, receive FIFO, error FIFO within Kbyte CBM. features include:
AForum Utopia Level Version compliant interface configurable either master slave.
Supports cell-level handshaking AForum Utopia Level Version 1.0. maximum Utopia Tx_Clk, Rx_Clk rate. Multi-PHY polling configurable round-robin fixed priority. Multi-PHY polling configurable direct slave devices maximum) multiplexed slave devices maximum). Cell FIFO size configurable Kbytes. Optional generation checking. CRC-10 generation checking AAL3/4. Optional idle cell insertion. Cell loopback. Optional Utopia parity generation checking. Utopia transmit timer prevent blocking unresponsive slave Multi-PHY applications.
Functional Overview
Scheduler Timer Units
Scheduler block provides hardware support traffic scheduling algorithms. Timer block consists 32-bit Time Stamp Counter eight general-purpose timers used support other traffic shaping maintenance functions. Specific features include:
Traffic scheduling per-VC basis (64K maximum). Support priorities traffic scheduling queues. Scheduler maintains Scheduler Calendar table external secondary memory internal CBM. Eight, 8-bit, cascadable, general-purpose timers with optional clock source including external clock. 32-bit Time Stamp Counter with optional clock source including external clock.
Interface
Interface designed write-optimized systems architected either cell packet transfers over Bus. high performance bridge allows host burst transmit packets secondary memory (slave write). EDMA bursts receive packets after reassembly secondary memory (master write). Master read slave read transfers also supported. Interface features include:
Protocol conforms Local Specification, Revision 2.1. MHz, 32-bit support. Four independent FIFOsMaster Read, Master Write Slave Write FIFOs each bytes; Slave Read FIFO bytes. ATMizer chip's CBM, Messaging Mailbox, internal hardware registers mapped memory space. Secondary Memory Mbytes) mapped memory space.
Scheduler Timer Units
Endian Considerations
ATMizer chip operates internally endian mode. ATMizer chip's external buses, however, little endian format. Internal master requests external local Secondary (SB) mapped such that internal masters buses endian resources. Similarly, external host (little endian) requests ATMizer chip's internal resources mapped such that host sees little endian resources. This done facilitate transfer word-based control structures between little endian domains. both endians, word addresses point same 32-bit word (data[31:0]). This allows little endian masters manipulate control structures with respect their domains. There need byte swapping control structures translating pointers control structures. Table shows internal endian external little endian requests ATMizer chip's three available memory resources: Cell Buffer Memory, Bus, Secondary Bus. Table Big/Little Endian Mapping
External Host (Little Endian) (Big Endian) data[31:24], be[3] data[23:16], be[2] data[15:8], be[1] data[7:0], be[0] data[31:24], be[0] data[23:16], be[1] data[15:8], be[2] data[7:0], be[3] (Little Endian) data[31:24], be[3] data[23:16], be[2] data[15:8], be[1] data[7:0], be[0] (Little Endian) data[31:24], be[3] data[23:16], be[2] data[15:8], be[1] data[7:0], be[0]
Internal Request (Big Endian) data[31:24], be[0] data[23:16], be[1] data[15:8], be[2] data[7:0], be[3]
facilitate transfer byte-based buffer payload data between little endian masters, EDMA swap data-byte positions within data word preserve data byte's address both endian domains. This applies data transferred using EDMA RxCell, TxCell, Move commands. RxCell TxCell commands, controlled EDMA_ByteSwap EDMA_Ctrl register (page 5-53). Move command, controlled LEndian EDMA_MoveCount2 register (page 5-31). Section 5.6.4, "Big Endian Little Endian," more detail EDMA byte swapping.
Functional Overview
Secondary Memory Controller
Secondary Memory Controller (SBC) provides access external memory used instructions SAR/scheduling data structures. also used access byte-wide EPROM boot management interface external devices. features include:
Mbytes maximum memory space. Memory controllers asynchronous SRAM, synchronous SRAM, synchronous DRAM, EPROM, peripheral devices. Arbitration support external secondary master.
Other Features
L64364 ATMizer chip also supports following features:
IEEE 1149.1 compliant boundary scan. Full scan with greater than stuck-at fault coverage manufacturing test. Phase-locked loop double frequency either clock input maximum clock input internal system clock.
Secondary Memory Controller
Functional Overview
Chapter Signal Descriptions
This chapter describes primary input output signals L64364 includes following sections:
Section 3.1, "I/O Signals Summary," page Section 3.2, "PCI Interface," page Section 3.3, "Secondary Memory Interface," page Section 3.4, "Utopia Interface," page 3-10 Section 3.5, "Clocks Utility Signals," page 3-15 Section 3.6, "APU Signals," page 3-17 Section 3.7, "Serial EPROM Interface," page 3-18 Section 3.8, "JTAG Test Interface," page 3-19 Section 3.9, "Power Ground Pins," page 3-20
Signals Summary
Figure illustrates L64364's input output signals when using Utopia master mode. Figure illustrates L64364's input output signals when using Utopia slave mode. differences Utopia interface noted signal descriptions following figures. Those descriptions grouped into interfaces shown figures. Signal names LOW-active signals terminate lower case "n," whereas HIGH-active signals clocks not. signals synchronous rising edge their respective clocks unless specified asynchronous signal descriptions. Refer Chapter MQUAD pinout information.
L64364 ATMizer ATM-SAR Chip
Figure
Signals (Utopia Master)
PCI_CLK PCI_RSTn PCI_AD[31:0] PCI_CBEn[3:0] PCI_PAR PCI_FRAMEn PCI_IRDYn PCI_TRDYn PCI_STOPn PCI_IDSEL PCI_DEVSELn PCI_REQn PCI_GNTn PCI_PERRn PCI_SERRn PCI_INTn L64364 SB_D[31:0] SB_A[21:2] SB_WEn[3:0] SB_OEn[3:0] SB_CLKO SB_PCSn[4:0] SB_RDYn SB_REQn SB_GNTn JTAG_TCLK JTAG_TDI JTAG_TDO JTAG_JTAG_TRSTn TEST_EN SCAN_EN SYS_CLK_PCI SYS_CLK SYS_PLL PLL_IDDTn PLL_LP2 TM_CLK SYS_OE PLLVSS PLLVDD PLLAGND SE_CLK SE_DI SE_ACK Serial EPROM Interface TX_DATA[7:0] TX_SOC TX_ENBn TX_CLK TX_PRTY TX_ADDR[4:0] TX_CLAV[3:0] Utopia Interface RX_DATA[7:0] RX_SOC RX_ENBn RX_CLK RX_PRTY RX_ADDR[4:0] RX_CLAV[3:0]
Interface
SYS_NMIn SYS_INTn[1:0] SYS_BOOT[1:0] SYS_PSTALLn SYS_CPCOND
Signals
Secondary
JTAG Interface
Clocks
Signal Descriptions
Figure
Signals (Utopia Slave)
PCI_CLK PCI_RSTn PCI_AD[31:0] PCI_CBEn[3:0] PCI_PAR PCI_FRAMEn PCI_IRDYn PCI_TRDYn PCI_STOPn PCI_IDSEL PCI_DEVSELn PCI_REQn PCI_GNTn PCI_PERRn PCI_SERRn PCI_INTn TX_DATA[7:0] TX_SOC TX_ENBn TX_CLK TX_PRTY TX_ADDR[4:0] TX_CLAV0 RX_DATA[7:0] RX_SOC RX_ENBn RX_CLK RX_PRTY RX_ADDR[4:0] RX_CLAV0
Interface
Utopia Interface
SB_D[31:0] SB_A[21:2] SB_WEn[3:0] Secondary SB_OEn[3:0] SB_CLKO SB_PCSn[4:0] SB_RDYn SB_REQn SB_GNTn JTAG_TCLK JTAG_TDI JTAG_TDO JTAG_JTAG_TRSTn TEST_EN SCAN_EN
L64364
SYS_NMIn SYS_INTn[1:0] SYS_BOOT[1:0] SYS_PSTALLn SYS_CPCOND
Signals
SE_CLK SE_DI SE_ACK
Serial EPROM Interface
JTAG Interface
SYS_CLK_PCI SYS_CLK SYS_PLL PLL_IDDTn PLL_LP2 TM_CLK SYS_OE PLLVSS PLLVDD PLLAGND
Clocks
Signals Summary
Interface
L64364 supports master slave transfers Interface. Interface conforms Local Specification 2.1. Details Interface functionality described Chapter defined little endian, which means that:
byte address address least significant byte (LSB) 32-bit data word which data byte PCI_AD[7:0]. byte address address most significant byte (MSB) 32-bit data word which data byte PCI_AD[31:24].
Interface signal descriptions provided below. PCI_CLK Clock Input PCI_CLK clock that provides timing transactions Bus. input signals, except PCI_RSTn, sampled rising edge PCI_CLK. Reset Input PCI_RSTn asynchronous signal that resets specific registers, state machines, signals initial state. Interface signals held 3-stated when PCI_RSTn asserted. This signal also master reset L64364. Deasserting PCI_RSTn causes initiate boot process. Refer Section 4.11, "Boot Procedures," further information. PCI_RSTn asserted internal control logic asynchronously deassertion synchronized system clock. When used, PCI_CLK SYS_CLK should stable three clock periods before PCI_RSTn deasserted. PCI_AD[31:0] Address Data Bidirectional PCI's 32-bit addresses 32-bit data multiplexed PCI_AD[31:0]. address phase clock cycle which PCI_FRAMEn asserted. During address phase, PCI_AD[31:0] contains physical memory address. 32-bit data word transferred PCI_AD[7:0], transferred
PCI_RSTn
Signal Descriptions
PCI_AD[31:24]. Write data stable when PCI_IRDYn asserted read data stable when PCI_TRDYn asserted. PCI_CBEn[3:0] Commands Data Byte Enables Bidirectional commands data byte enables multiplexed PCI_CBEn[3:0]. During address phase, PCI_CBEn[3:0] contains commands, some which shown following table.
PCI_CBEn[3:0] Command Type Memory Read Memory Write Configuration Read Configuration Write Memory Read Multiple Memory Read Line Memory Write Invalidate
During data phase, PCI_CBE[3:0] contains byte enables. PCI_CBE[0] enables data writes PCI_AD[7:0], LSB, PCI_CBE[3] enables data writes PCI_AD[31:24], MSB. PCI_PAR PCI_Parity Bidirectional PCI_PAR reset create even parity 36-bits that include PCI_AD[31:0] PCI_CBEn[3:0]. total number (bits logic one) PCI_AD[31:0] PCI_CBEn[3:0] odd, PCI_PAR otherwise, reset
PCI_FRAMEn Cycle Frame Bidirectional PCI_FRAMEn asserted current master indicate beginning duration access. PCI_FRAMEn asserted indicate start transaction. transfers continue while PCI_FRAMEn asserted they terminate when PCI_FRAMEn deasserted. When L64364 deasserts PCI_FRAMEn, drives high clock cycle then 3-states following cycles.
Interface
PCI_IRDYn
Initiator Ready Bidirectional initiator, which current master, asserts PCI_IRDYn indicate when there valid data PCI_AD[31:0] during write cycle, indicate that ready accept data from PCI_AD[31:0] during read cycle. data phase (transfer) completed clock cycle where both PCI_IRDYn PCI_TRDYn asserted. Wait cycles inserted until both PCI_IRDYn PCI_TRDYn asserted. When L64364 deasserts PCI_IRDYn, drives high clock cycle then 3-states following cycles. Target Ready Bidirectional target, which current slave, asserts PCI_TRDYn indicate when there valid data PCI_AD[31:0] during read cycle, indicate that ready accept data from PCI_AD[31:0] during write cycle. data phase transfer completes clock cycle when both PCI_IRDYn PCI_TRDYn asserted. L64364 inserts wait cycles until both PCI_IRDYn PCI_TRDYn asserted. When L64364 deasserts PCI_TRDYn, drives high clock cycle then 3-states following cycles. Stop Bidirectional target asserts PCI_STOPn stop current data transfer. master, L64364 terminates data transfer when PCI_STOPn asserted. slave, L64364 asserts PCI_STOPn under following conditions:
PCI_TRDYn
PCI_STOPn
Slave Write FIFO full. Slave Read FIFO empty.
When L64364 deasserts PCI_STOPn, drives high clock cycle then 3-states following cycles. PCI_IDSEL Initialization Device Select Input PCI_IDSEL chip select which input L64364 during configuration read configuration write cycles (bus command 0b1010 ob1011).
Signal Descriptions
PCI_DEVSELn Device Select Bidirectional target, whose address specified address phase current transfer, asserts PCI_DEVSELn. target, L64364 asserts PCI_DEVSELn clock cycles after master asserts PCI_FRAMEn (medium DEVSEL timing). When L64364 deasserts PCI_DEVSELn, drives high clock cycle then 3-states following cycles. master, L64364 aborts transfer PCI_DEVSELn asserted within clock cycles after PCI_FRAMEn asserted. PCI_REQn Request 3-State Output L64364 asserts PCI_REQn request master transfer Bus. Grant Input current master asserts PCI_GNTn indicate L64364 when ownership granted. After L64364 detects PCI_GNTn, asserts PCI_FRAMEn next clock then initiates transfer. Parity Error Bidirectional PCI_PERRn indicates data parity errors have occurred. During master read slave write, L64364 asserts PCI_PERRn within clock cycles after detecting parity error. both cases, asserts PCI_PERRn clock cycle. PCI_PERRn asserted more than clock cycle multiple parity errors occur burst transactions. When L64364 deasserts PCI_PERRn, drives high clock cycle then 3-states during following cycles. During master write, L64364 checks parity errors monitoring PCI_PERRn from target. target asserts PCI_PERRn during master write, L64364 interrupts APU. PCI_SERRn System Error Open Drain Output L64364 asserts PCI_SERRn when parity error detected PCI_AD[31:0] PCI_CBE[3:0] during address phase transfer.
PCI_GNTn
PCI_PERRn
Interface
PCI_INTn
Interrupt Open Drain Output L64364 asserts PCI_INTn when Transmit Messaging Mailbox empty interrupt enabled Primary Port Control register. Refer Section 9.3.1, "XPP_Ctrl Register," additional information.
Secondary Memory Interface
Secondary Memory Interface directly controls access synchronous DRAM, asynchronous SRAM, synchronous SRAM, some physical layer devices. Refer Chapter information about secondary memory configurations functionality. interface signals defined follows: SB_D[31:0] Secondary Data Bidirectional SB_D[31:0] 32-bit wide data which provides access secondary memory. byte-wide EPROM peripheral devices connect local memory through SB_D[31:24]. Secondary Address Output SB_A[21:2] 20-bit wide addressing SSRAM, SRAM, SDRAM, EPROM, peripheral devices. table below shows SB_A mapping these various devices.
SB_A[n] SB_A[21] SB_A[20] SB_A[19] SB_A[18] SB_A[17] SB_A[16] SB_A[15] SB_A[14] SB_A[13:2] SSRAM A[11:0] EPROM A[11:0] A[11:0] SDRAM used used used used A[11:0]
SB_A[21:2]
SB_WEn[3:0] Secondary Write Enables Output SB_WEn[3:0] byte write enables 32-bit Secondary Bus. Secondary defined little
Signal Descriptions
endian. SB_WEn[3] enables write data SB_D[31:24], MSB. SB_WEn[0] enables write data SB_D[7:0], LSB. Byte-wide peripheral devices must connect SB_WEn[0]. Write enables specific devices assigned following table.
SSRAM 32-Bit 8-Bit EPROM/ EPROM/ SRAM SRAM used used used
SB_WEn[n] SB_WEn[3] SB_WEn[2] SB_WEn[1] SB_WEn[0]
Peripheral SDRAM used used used used used used
SB_OEn[3:0] Secondary Output Enables Output SB_OEn[3:0] output enables and/or address controls SSRAMS, SDRAMS, EPROMs, peripheral devices defined following table.
SB_OEn[n] SSRAM EPROM/ SRAM Peripheral SDRAM1 (X8), DQMU (X16), DQM[3] (X32) (X8), DQML (X16), DQM[2] (X32) (X8), DQMU (X16), DQM[1] (X32) (X8), DQML (X16), DQM[0] (X32)
SB_OEn[3] used used used
SB_OEn[2] used used used
SB_OEn[1] used
SB_OEn[0]
LOW-active output enable byte-wide SDRAM. DQMU DQML LOW-active byte enables upper lower bytes 16-bit SDRAM.
SB_CLKO
Secondary Clock Output SSRAM, SDRAM SB_CLKO synchronization. address, data, control signals from SDRAM SSRAM synchronized rising edge SB_CLKO.
Secondary Memory Interface
SB_PCSn[4:0] Secondary Page Chip Select Output SB_PCSn[4:0] provide chip select function five pages that configured Secondary control registers. Normally, these signals connect chip select inputs memory devices (either directly conditioned with address decode). Refer Section 10.2, "SBC Configuration," details. SB_RDYn Secondary Ready Input SB_RDYn indicates valid input data available SB_D[n]. This asynchronous input used instead integrated wait state generator time read write transfers asynchronous SRAM, EPROM, peripheral devices. SB_RDYn sampled deasserting edge PCI_RSTn determine reset state SB_Wait fields SP_Ctrl Register. section 10.2.1 page 10-4. SB_RDYn sampled HIGH, then SB_Wait fields reset wait states). SB_RDYn sampled LOW, then SB_Wait fields reset (SB_RDYn terminated). SB_REQn Secondary Request Input SB_REQn asserted indicates external master requests Secondary ownership. asynchronous input. Secondary Grant Output L64364 asserts SB_GNTn response SB_REQn. Secondary ownership granted based roundrobin priority scheme between slave interface L64364 master. Secondary signals, except SB_CLKO SB_GNTn, held 3-stated until SB_REQn deasserted.
SB_GNTn
Utopia Interface
Utopia Interface conforms AForum's Utopia Level Specification, Version 1.0. Data control signals bidirectional since L64364 configured either Utopia master slave. Utopia interface signals described following paragraphs.
3-10
Signal Descriptions
TX_DATA[7:0] Transmit Cell Data Master Mode (output) Bidirectional
TX_DATA[7:0] Utopia transmit cell data output from L64364 external Physical Layer (PHY) devices. Transmit cells output from transmit FIFO L64364. Slave Mode (input) TX_DATA[7:0] Utopia transmit cell data input from external Utopia master device. Cell data input receive FIFO L64364. TX_SOC Transmit Start Cell Master Mode (output) Bidirectional
TX_SOC output from L64364 indicate first byte cell. This signal pulses HIGH Utopia transmitclock cycle first byte cell header when cell length bytes. TX_SOC pulses HIGH Utopia transmit-clock cycle first byte prepended routing when cell length exceeds bytes. Slave Mode (input) TX_SOC input L64364 from Utopia master indicate first byte cell. HIGH this signal when sampled with respect Utopia transmit clock indicates first byte cell header 52-53 byte cells first byte routing 56-65 byte cells. TX_ENBn Transmit Enable Master Mode (output) Bidirectional
L64364 asserts TX_ENBn designate valid transmit cell data TX_DATA[7:0]. Slave Mode (input) TX_ENBn asserted Utopia master L64364 designate valid transmit cell data TX_DATA[7:0]. Transmit cell data sampled rising edge TX_CLK when TX_ENBn asserted. TX_CLK Transmit Clock Input TX_CLK Alayer interface clock used synchronize transmit cell data transfers. TX_CLK
Utopia Interface
3-11
maximum frequency input that independent master slave configuration. TX_PRTY Transmit Parity Master Mode (output) Bidirectional
TX_PRTY logic signal parity over TX_PRTY TX_DATA[7:0] total number TX_DATA[7:0] even. reset logic total number TX_DATA[7:0] odd. Slave Mode (input) TX_PRTY reset Utopia master designate parity TX_DATA[7:0] described master mode. parity enabled, L64364 will interrupt handle errored cells. TX_ADDR[4:0] Transmit Address Master Mode (output) Bidirectional
TX_ADDR[4:0] output select device that destination next transmit cell. L64364 supports devices 0-23. Slave Mode (input) During polling Utopia master, L64364 monitors TX_ADDR[4:0] device address, which programmed Control register. device address range 0-30 slave mode. L64364 asserts TX_CLAV[0] whenever Receive FIFO accept transmit cell from Utopia master TX_ADDR[4:0] matches programmed device address. TX_CLAV[3:0] Transmit Cell Available Master Mode (input) Bidirectional
L64364 monitors TX_CLAV[3:0] signals determine target device capable accepting next cell from transmit FIFO. When TX_CLAV asserted, transmit cell transferred device TX_DATA[7:0]. TX_CLAV asserted prior expiration L64364's programmable watchdog timer, transmit cell moved Error FIFO optionally interrupted error handling.
3-12
Signal Descriptions
TX_CLAV definition dependent whether direct multiplexed polling selected. direct polling, four devices supported each connects TX_CLAV[3:0] inputs. Multiplexed polling uses only TX_CLAV[0] input. devices will then connect their TxCLAV outputs TX_CLAV[0]. Slave Mode (output) L64364, when selected Utopia master, asserts TX_CLAV[0] Receive FIFO room least cell. TX_CLAV[3:1] used. RX_DATA[7:0] Receive Cell Data Master Mode (input) Bidirectional
RX_DATA[7:0] Utopia receive cell data input from devices. Receive cell data destined receive FIFO L64364. Slave Mode (output) RX_DATA[7:0] Utopia receive cell data output from transmit FIFO L64364 Utopia master. RX_SOC Receive Start Cell Master Mode (input) Bidirectional
RX_SOC asserted L64364 first byte cell. This signal pulses HIGH Utopia receive-clock cycle first byte cell header when cell length bytes. RX_SOC pulses HIGH Utopia receive-clock cycle first byte prepended routing when cell length exceeds bytes. Slave Mode (output) L64364 asserts RX_SOC indicate first byte cell. HIGH this signal when sampled with respect Utopia receive clock indicates first byte cell header 52-53 byte cells first byte routing 56-65 byte cells. RX_ENBn Receive Enable Master Mode (output) Bidirectional
After device selected, L64364 asserts RX_ENBn indicate ready accept receive cell data.
Utopia Interface
3-13
single-PHY application, RX_ENBn remains asserted long receive FIFO full device cells available. This enables back-to-back cell reception. multi-PHY application, RX_ENBn remains asserted long receive FIFO full higher priority device does assert CLAV signal. Slave Mode (input) L64364 monitors RX_ENBn input determine when Utopia master ready receive cells from transmit FIFO. When selected Utopia master, L64364 uses RX_ENBn enable 3-state drivers RX_DATA[7:0] RX_SOC, then initiate Utopia receive cell transfer. RX_CLK Receive Clock Input RX_CLK Alayer interface clock used synchronize receive cell data transfers. RX_CLK maximum frequency input that independent master slave configurations. Receive Parity Master Mode (input) Bidirectional
RX_PRTY
RX_PRTY input L64364 device designate parity. logic when total number RX_DATA[7:0] even reset number RX_DATA[7:0] odd. parity enabled, L64364 interrupts handle errored cells. Slave Mode (output) RX_PRTY reset L64364 designate parity described master mode. RX_ADDR[4:0] Receive Address Master Mode (output) Bidirectional
L64364 places address device being polled RX_ADDR[4:0]. L64364 supports devices 0-23. Slave Mode (input) During polling Utopia master, L64364 monitors RX_ADDR[4:0] device address which
3-14
Signal Descriptions
programmed Control register. device address range 0-30 slave mode. When RX_ADDR[4:0] matches programmed device address, L64364 asserts RX_CLAV[0] transmit FIFO empty. L64364 also asserts RX_CLAV[0] device address zero idle cell generation enabled. RX_CLAV[3:0] Receive Cell Available Master Mode (input) Bidirectional
L64364 monitors RX_CLAV[3:0] signals determine target device receive cell available. When target device asserts RX_CLAV, L64364 asserts RX_ENBn enable receive cell transfer. definition RX_CLAV depends whether direct multiplexed polling selected. direct polling, four devices supported each connects RX_CLAV[3:0] inputs. Multiplexed polling uses only RX_CLAV[0] input. devices then connect their RxCLAV outputs RX_CLAV[0]. Slave Mode (output) L64364, when selected Utopia master, asserts RX_CLAV[0] transmit FIFO empty. RX_CLAV[3:1] used.
Clocks Utility Signals
This section defines clocks, clock select signals, miscellaneous control signals. Refer Chapter detailed information clocks clock control signals. SYS_CLK_PCI Clock Select Input SYS_CLK_PCI, when HIGH, selects PCI_CLK system clock source L64364. When SYS_CLK_PCI LOW, SYS_CLK selected system clock source. SYS_CLK_PCI must tied power ground must change during operation L64364.
Clocks Utility Signals
3-15
SYS_CLK
System Clock Input SYS_CLK system clock input L64364. maximum clock frequency MHz. Select Input When SYS_PLL HIGH, clock selected SYS_CLK_PCI multiplied internal phasedlock loop before being used internal system clock. When SYS_PLL LOW, selected clock used frequency. This signal must tied power ground must change during operation L64364 operation. Operations Input PLL_IDDTn enables manufacturing test internal phase-locked loop. This must tied logic ground (VSS) normal operation. Loop Filter Input Input PLL_LP2 line connecting PLL's phase detector charge pump output input. external loop filter, consisting resistor capacitors, must connected between this PLLAGND pin. Figure 11.2 configuration details. Ground uses reference ground isolated from other grounds. Power Input uses power isolated from other power lines. Analog Ground separate reference ground isolated from other grounds provided analog section PLL. Timer Reference Clock Input TM_CLK input used reference clock seven general-purpose timers Time Stamp Counter. TM_CLK maximum frequency one-third internal system clock rate asynchronous system clock. Refer Section 8.2, "Timer Clock Selection," additional information.
SYS_PLL
PLL_IDDTn
PLL_LP2
PLLVSS
PLLVDD
PLLAGND
TM_CLK
3-16
Signal Descriptions
SYS_OE
System Output Enable Input SYS_OE, when deasserted, 3-states outputs L64364.
Signals
section summarizes AProcessing Unit's (APU) external signals. SYS_NMIn System Nonmaskable Interrupt Input This signal provides nonmaskable interrupt APU. When asserted, causes unconditionally execute nonmaskable interrupt handler. System Interrupt Inputs vectored interrupts enabled, SYS_INTn[1] SYS_INTn[0] cause vectored interrupts respectively. SYS_INTn[1:0] asynchronous, level-sensitive inputs. They resynchronized L64364's system clock. SYS_INTn[1:0] must remain asserted until associated interrupt acknowledged interrupt service routine executed APU. information about vectored interrupts, their sources, they enabled, refer Section 4.8, "Interrupts." SYS_BOOT[1:0] System Boot Source Inputs SYS_BOOT[1:0] select boot source according table below. SYS_BOOT[1:0] sampled rising edge (deassertion) PCI_RSTn. Refer Section 4.11, "Boot Procedures," further information.
SYS_BOOT[1:0] 0b00 0b01 0b10 0b11 Boot Source Secondary EPROM Used Cell Buffer Memory Serial EPROM
SYS_INTn[1:0]
Signals
3-17
SYS_PSTALLn System Pipeline Stalled Output SYS_PSTALLn asserted when internal pipeline stalled. This signal system performance tuning. Refer Section 4.2.3, "CW4011 Pipeline," information about pipeline functionality performance considerations. SYS_CPCOND System Coprocessor Condition Code Input This signal sets state APU's Coprocessor Condition Code This allows directly test status external logic using Branch Coprocessor Condition instructions.
Serial EPROM Interface
Serial EPROM Interface provides optional boot source. This section describes Serial EPROM Interface signals. SE_CLK Serial EPROM Clock Output SE_CLK clock used load boot code from serial EPROM. SE_CLK frequency internal system clock frequency divided example, L64364 system clock MHz, SE_CLK will 2.06 MHz. Serial EPROM Data Input Input SE_DI boot code from serial EPROM. code packed first serial EPROM least significant byte (the most significant byte). Data SE_DI sampled rising edge SE_CLK. Serial EPROM Acknowledge Input External logic asserts this signal indicate when there valid serial EPROM data present SE_DI. When external logic asserts SE_ACK, L64364 captures data present SE_DI rising edge SE_CLK.
SE_DI
SE_ACK
3-18
Signal Descriptions
JTAG Test Interface
JTAG Test Interface conforms IEEE 1149.1, Standard Test Access Port Boundary Scan Architecture. interface signals described this section. JTAG_TCLK JTAG Test Clock Input JTAG_TCLK shifts boundary scan register maximum frequency MHz. JTAG Test Data Input Input test data input, JTAG_TDI, sampled rising edge JTAG_TCLK. JTAG Test Data Output Output JTAG_TDO test data output boundary scan register. output data synchronized falling edge JTAG_TCLK. JTAG Test Mode Input JTAG_is control input JTAG Test Access Port controller.
JTAG_TDI
JTAG_TDO
JTAG_
JTAG_TRSTn JTAG Test Reset Input JTAG_TRSTn, when asserted, resets JTAG Test Access Port controller. TEST_EN Factory Test Enable Input TEST_EN, when asserted, enables factory test. This signal must tied ground during normal operation. Factory Scan Test Enable Input SCAN_EN, when asserted, enables factory scan test chains. This signal must tied ground during normal operation.
SCAN_EN
JTAG Test Interface
3-19
Power Ground Pins
This section lists power ground pins. number power ground pins been selected provide reliable operation HIGH signal integrity. Logic Ground Thirteen pins dedicated reference ground internal chip logic. Logic Power Input Twelve pins dedicated supply voltage internal chip logic. Ground Nine pins dedicated reference ground ring. Power Nine pins dedicated powering ring. Nominal voltage Clamp Voltage Input Seven pins provide voltage input clamp diodes. This voltage required overvoltage specification Local Specification 2.1, Section 4.2.1.3. power dissipation associated with these pins. These pins sink current when inputs raised above
VSS2
VDD2
3-20
Signal Descriptions
Chapter AProcessing Unit
This chapter describes AProcessing Unit (APU) contains following sections:
Section 4.1, "APU Overview," page Section 4.2, "APU Architecture," page Section 4.3, "APU Instruction Summary," page 4-10 Section 4.4, "CP0 Data Manipulation Registers," page 4-49 Section 4.5, "Cache Memory," page 4-50 Section 4.6, "Exceptions," page 4-59 Section 4.7, "Memory Map," page 4-95 Section 4.8, "Interrupts," page 4-101 Section 4.9, "CW4011 Accesses," page 4-111 Section 4.10, "Bus Watchdog Timers," page 4-112 Section 4.11, "Boot Procedures," page 4-117 Register bits fields labeled "Reserved" don't cares. Descriptor bits fields labeled "Reserved" should modified.
Important:
Overview
built Logic's MiniRISC CW4011 Superscalar Microprocessor Core. CW4011 member Logic's MiniRISC family, next generation MIPS RISC products. Logic offers CW4011 CoreWare® product customer ASIC designs. Logic also embeds CW4011 Application-Specific Standard Products (ASSPs), such L64364 ATMizer chip. Refer
L64364 ATMizer ATM-SAR Chip
MiniRISC CW4011 Superscalar Microprocessor Core Technical Manual, Logic Order C14040, information about CW4011 covered this chapter.
4.1.1 Block Diagram
block diagram shown Figure 4.1. addition CW4011 core, contains following building blocks:
Direct-mapped two-way associative instruction cache Kbytes) Direct-mapped two-way associative data cache Kbytes) write back buffer write back cache mode floating-point multiplier unit AABR rate calculations
also includes logic that allows initial program loading from serial EPROM, byte-wide EPROM, host download ATMizer's Cell Buffer Memory (CBM). Figure Block Diagram
Bus*
Logic
Logic
Bus*
SCbus Interface
OCAbus Interface
Rate Multiplier CW4011 Core I-Cache
WriteBack Buffer
D-Cache
I-Cache Coprocessor Interface Internal ATMizer Busses
D-Cache
AProcessing Unit
4.1.2 Features
following features:
Full MIPS instruction implementation (R4000 32-bit mode compatible). Instruction extensions support AABR calculations. Superscalar execution: instructions clock cycle. 32-bit memory 64-bit cache interface. Dhrystone MIPS MHz. native MIPS peak (110 native MIPS sustained) with standard compiled MIPS code MHz. Integrated cache controllers with separate Kbyte instruction Kbyte data cache.
Architecture
fully compatibility with both R3000 R4000 32-bit instruction sets (MIPS MIPS uses updated hardware architecture provide higher absolute performance than other available MIPS solution. also provides substantially better instructions-per-clock performance than other MIPS processors. same time, hardware design remains compact compared other superscalar architectures. issue retire instructions cycle using combination four independent execution units:
Arithmetic Logic Unit (ALU) Load/Store/Add Unit (LSU) Branch Unit Rate Multiply Unit
execute load immediate instructions addition load store), making possible L64364 perform instruction same time executes another logical instruction.
Architecture
instructions, except multiply divide, completed single cycle. Load instructions have single hardware delay slot loads that cache, hardware interlocks register conflicts that required delay slot. load miss, extends hardware conflict detection that, load data required subsequent instructions pipeline, stalled. operation called load scheduling. supports store instructions with both write back cache write buffer. instruction prefetch queue branch prediction logic boost branch performance that correctly predicted branches retired with penalty, incorrectly predicted branches normally have penalty just cycle. accomplishes branch prediction with simple hardware algorithm that accuracy greater than most application code.
4.2.1 CW4011 Core
Figure shows block diagram CW4011 core. includes following blocks:
Ifetch Queue IDecode Unit Branch Unit Register File Load/Store/Add Unit (LSU) Integer Arithmetic Logic Unit (ALU) Floating-Point Rate Multiply Unit Interface Unit (BIU) Interface Coprocessor Interface System Control Coprocessor (CP0)
Ifetch Queue optimizes supply instructions microprocessor, even across breaks (jumps branches) sequential flow execution. IDecode Unit decodes instructions
AProcessing Unit
from Ifetch Queue; determines actions required instruction execution; manages Register File (RFile), LSU, ALU, Multiplier Units accordingly. Branch Unit used when branch jump instructions recognized within instruction stream. Register File contains APU's general purpose registers. supplies source operands execution units handles storage results target registers. Figure CW4011 Block Diagram
Instruction Schedule Unit (ISU) Ifetch Queue Register File IDecode Unit Branch Unit I-Cache
Internal Instruction Execution
D-Cache Write Buffer OCAbus
Load/Store/Add Unit (LSU)
Integer
Rate Multiply Unit
Interface Unit Address Data Control
Coprocessor Interface
SCbus Interface
Three units perform logical, arithmetic, data-movement operations. Load/Store/Add Unit (LSU) manages loads stores data values. Loads come from either D-Cache Interface event D-Cache miss. Stores pass D-Cache Interface through Write Buffer. also performs restricted arithmetic operations, including addition immediate offset required address calculations. Integer
Architecture
Unit calculates result arithmetic logical operation. Rate Multiply Unit performs integer multiply/divide operations floating point operations format adopted AForum calculations. Interface Unit manages flow instructions data between CW4011 core system using Interface. Interface provides main channel communication between CW4011 core other functional blocks ATMizer chip. Coprocessor Interface provides status ATMizer resources. Coprocessor Condition codes following:
CPCond3: EDMA RxCell Request Queue full CPCond2: EDMA TxCell Request Queue full CPCond1: EDMA Buffer Request Queue full CPCond0: SYS_CPCOND input L64364 asserted
These conditions used Branch Coprocessor (BCzT BCzF) instructions described Section 4.3.7, "Coprocessor Instructions." CPCond0 interrupts CW4011.
4.2.2 Cache External Interface
instruction cache controller integral part CW4011 Instruction Schedule Unit (ISU), data cache controller integral part LSU. Write Buffer also part LSU. addition, simple memory interface unit, BIU, provides interface Primary Memory, Secondary Memory, ATMizer's Cell Buffer Memory registers. presents nonmultiplexed interface with 32-bit data 32-bit address bus. write back buffer provided support write back mode data cache.
4.2.3 CW4011 Pipeline
shown Figure 4.3, superscalar CW4011 two, concurrent, six-stage pipelines slots-an even odd. first three stages labelled instruction fetch phase, last three stages labelled instruction execution phase.
AProcessing Unit
Figure
CW4011 Instruction Pipeline
Instruction Fetch Instruction Execution Even Pipeline
Pipeline
general, execution single CW4011 instruction consists following stages: (Instruction Fetch) CW4011 fetches instruction during this stage. (Queuing) Instructions enter this conditional stage they deal with branches register conflicts. instruction that does cause branch register conflict directly stage. (Read) During this stage, required operands read from Register File while instruction decoded. (Execute) instructions executed this stage. addition, conditional branches resolved load/store address calculations performed during this stage. (Cache Read) this stage, cache read operations performed load store instructions. Data returned register bypass logic stage. (WriteBack) Results written into Register File during this stage. Once accepted instruction from previous stage, each stage holds instruction re-execution pipeline stalls.
Architecture
4.2.3.1 Instruction Fetch Scheduling Stages stages fetch issue instructions cycle execute stage. simplicity, CW4011 fetches instructions doubleword aligned pairs (slot slot instruction decode stage, there two-instruction window. When only slot scheduled because slot dependency, window slides down instruction. other words, although instructions always fetched doubleword pairs, they scheduled single-word boundaries. stage executes branch instructions with minimal penalty. general, CW4011 fills stage whenever stage stall, which occurs fairly often register conflicts, cache misses, resource conflicts. Filling stage this case allows stage work ahead cycle. When branch instruction type encountered stage active, branch predicted taken instruction fetching starts branch address. this point, stage holds next nonbranch instructions executed. branch target enters stage, bypassing stage. When branch instruction enters Execute stage, branch condition resolved. branch correctly predicted, instructions stage cancelled. branch incorrectly predicted, branch target cancelled. this later case, nonbranch sequential instructions taken from stage, stage restarted nonbranch sequential stream. different case occurs when branch instruction instruction slot. general, branch instruction that correctly predicted from even slot with stage full cycle penalty associated with case where branch incorrectly predicted, branch one-cycle penalty. branch instruction slot, branch delay slot instruction always executes itself chance fill other execution slot. that reason, advantageous software assembler places branches even word addresses. branch prediction logic must capable looking instructions time, from either latches latches, depending whether stage active. instructions branch, offset that instruction passed into dedicated adder
AProcessing Unit
calculate branch address stage instruction fetch. Because this done speculatively, nonbranch value Program Counter (PC) also saved possible restart sequential instructions from stage. After instruction pair passes into stage, decoded and, same time, register source addresses passed register file operands read. Register dependencies resource dependencies checked this stage. instruction slot dependency register resource currently tied previous instruction, passed immediately into stage where forks appropriate execution unit. instruction slot also dependent resource register slot must checked dependencies against both slot previous unretired instruction. either instruction must held stage stage full, stage allowed continue order fill stage. stage full, then stages frozen (stalled). stage, register bypass opportunities considered bypass multiplexers control signals potential bypass cases from previous instruction still pipeline. 4.2.3.2 Execute Stage During instruction execution, pair instructions single instruction when there previous block) individually passed independent execution units. Each execution unit receives operands from register bypass logic instruction from instruction scheduler. Each instruction spends cycle execution unit. other single cycle instructions, result then register/bypass unit stage. 4.2.3.3 Cache Read WriteBack Stages load store instructions, cache lookup occurs during stage. load instructions, data returned register/bypass unit during stage, including data loads Coprocessor other instructions, holding stages used hold result execute stage write back register file.
Architecture
Instruction Summary
CW4011 instruction with ATMizer specific extensions summarized this section. Table summarizes instruction APU. supports both MIPS MIPS instructions, also implements some additional CW4011-specific APU-specific instructions. instructions 32-bits long. Table
Instruction Summary
Description Description
Arithmetic Instructions: Immediate ADDI ADDIU SLTI SLTIU Immediate Immediate Unsigned Less Than Immediate Less Than Immediate Unsigned ANDI XORI Immediate Immediate Exclusive Immediate Load Upper Immediate
Arithmetic Instructions: Three-Operand, Register-Type ADDU SUBU Unsigned Subtract Subtract Unsigned Less Than SLTU Less Than Unsigned Exclusive
Branch Likely Instructions1 BEQL BNEL BLEZL BGEZL Branch Equal Likely Branch Equal Likely Branch Less than Equal Zero Likely Branch Greater than Equal Zero Likely BGTZL BLTZL BLTZALL BGEZALL Branch Greater Than Zero Likely Branch Less Than Zero Likely Branch Less Than Zero Link Likely Branch Greater than Equal Zero Link Likely
(Sheet
4-10
AProcessing Unit
Table
Instruction Summary (Cont.)
Description Description
Cache Maintenance FLUSHI FLUSHD Flush I-Cache Flush D-Cache FLUSHID Flush I-Cache D-Cache
Coprocessor Instructions BCzT (BCzTL) Branch Coprocessor True (Likely) BCzF (BCzFL) Branch Coprocessor False (Likely)
Jump Branch Instructions JALR Jump Jump Link Jump Register Jump Link Register Branch Equal Branch Equal BLEZ BGTZ BLTZ BGEZ BLTZAL BGEZAL Branch Less than Equal Zero Branch Greater Than Zero Branch Less Than Zero Branch Greater than Equal Zero Branch Less Than Zero Link Branch Greater than Equal Zero Link
Load/Store Instructions Load Byte Load Byte Unsigned Load Halfword Load Halfword Unsigned Load Word Load Word Left Load Word Right Store Byte SYNC1 Store Halfword Store Word Store Word Left Store Word Right Load Linked Store Conditional Sync
(Sheet
Instruction Summary
4-11
Table
Instruction Summary (Cont.)
Description Description
Multiply/Divide Instructions MULT MULTU DIVU Multiply Multiply Unsigned Divide Divide Unsigned MFHI MFLO MTHI MTLO Move From Move From Move Move
Other Computational Instructions2 ADDCIU SELSR Circular Immediate Find First Find First Clear Select Shift Right SELSL SELRR Select Shift Left Minimum Maximum Select Rotate Right
Rate Instructions3 RMUL RADD RSUB Rate Multiply Rate Rate Subtract Rate Integer Integer Rate
Shift Instructions Shift Left Logical Shift Right Logical Shift Right Arithmetic SLLV SRLV SRAV Shift Left Logical Variable Shift Right Logical Variable Shift Right Arithmetic Variable
Special Instructions SYSCALL System Call BREAK Breakpoint
(Sheet
4-12
AProcessing Unit
Table
Instruction Summary (Cont.)
Description Description
System Control Coprocessor (CP0) Instructions MTC0 MFC0 ERET Move Move From Exception Return WAITI2 Restore From Exception Wait Interrupt
Trap Instructions1 TEQI TGEI TGEU TGEIU Trap Equal Trap Equal Immediate Trap Greater than Equal Trap Greater than Equal Immediate Trap Greater than Equal Unsigned Trap Greater than Equal Immediate Unsigned TLTI TLTU TLTIU TNEI Trap Less Than Trap Less Than Immediate Trap Less Than Unsigned Trap Less Than Immediate Unsigned Trap Equal Trap Equal Immediate
(Sheet MIPS Instructions. CW4011-specific instructions. APU-specific instructions.
4.3.1 Instruction Formats
Every instruction consists single word (32-bits) aligned word boundary. shown Figure 4.4, there three instruction formats: I-type (immediate), J-type (jump), R-type (register). restricted format approach simplifies instruction decoding. compiler assembler synthesize more complicated (and less frequently used) operations addressing modes.
Instruction Summary
4-13
Figure
Instruction Formats
I-type (Immediate)
immediate
J-type (Jump)
target
R-type (Register)
shamt funct
immediate target shamt funct
6-bit operation code 5-bit source register specifier 5-bit target (source/destination register) 16-bit immediate, branch displacement, address displacement 26-bit jump target address 5-bit destination register specifier 5-bit shift amount 6-bit function field
4.3.2 Load Store Instructions
load store instructions summarized Table I-type instructions move data between memory general registers. only addressing mode directly supported base architecture base register plus 16-bit signed immediate offset. MIPS extensions Load Linked Store Conditional instructions which support multiple processors, Sync instruction which synchronizes loads stores. supports these instructions. They summarized Table 4.3.
4-14
AProcessing Unit
load/store instruction operation code (opcode) determines access type, which turn indicates size data item loaded stored. bytes used within addressed word determined directly from access type low-order bits address shown Figure 4.5. Note that certain combinations access type low-order address bits never occur; only combinations shown Figure permissible. Figure Byte Specifications Loads/Stores
Low-Order Address Bits: Bytes Accessed Endian
Access Type
Word
Tribyte Byte
Halfword
Instruction Summary
4-15
Table
Instruction Load Byte
Load Store Instructions Summary
Format Description offset(base) Sign-extend 16-bit offset contents register base form address. Sign-extend contents addressed byte load into offset(base) Sign-extend 16-bit offset contents register base form address. Zero-extend contents addressed byte load into offset(base) Sign-extend 16-bit offset contents register base form address. Sign-extend contents addressed halfword load into offset(base) Sign-extend 16-bit offset contents register base form address. Zero-extend contents addressed halfword load into offset(base) Sign-extend 16-bit offset contents register base form address, load addressed word into offset(base) Sign-extend 16-bit offset contents register base form address. Shift addressed word left that addressed byte leftmost byte word. Merge bytes from memory with contents register load result into register offset(base) Sign-extend 16-bit offset contents register base form address. Shift addressed word right that addressed byte rightmost byte word. Merge bytes from memory with contents register load result into register offset(base) Sign-extend 16-bit offset contents register base form address. Store least-significant byte register addressed location. offset(base) Sign-extend 16-bit offset contents register base form address. Store least-significant halfword register addressed location. offset(base) Sign-extend 16-bit offset contents register base form address. Store contents register addressed location.
Load Byte Unsigned Load Halfword
Load Halfword Unsigned Load Word
Load Word Left
Load Word Right
Store Byte
Store Halfword
Store Word
(Sheet
4-16
AProcessing Unit
Table
Instruction Store Word Left
Load Store Instructions Summary (Cont.)
Format Description offset(base) Sign-extend 16-bit offset contents register base form address. Shift contents register right that leftmost byte word position addressed byte. Store word containing shifted bytes into word addressed byte. offset(base) Sign-extend 16-bit offset contents register base form address. Shift contents register left that rightmost byte word position addressed byte. Store word containing shifted bytes into word addressed byte.
Store Word Right
(Sheet
Table
Instruction Load Linked
Load Store Instruction Summary-MIPS Extensions
Format Description offset(base) Sign-extend 16-bit offset contents register base form address. Sign-extend contents addressed word load into register offset(base) Sign-extend 16-bit offset contents register base form address. Conditionally store low-order word register address, based whether load-link been "broken." SYNC Complete outstanding load store instructions before allowing load store instruction start.
Store Conditional
Sync
4.3.3 Computational Instructions
Computational instructions perform arithmetic, logical, shift operations values registers. Computational instructions occur both R-type (both operands registers) I-type (one operand 16-bit immediate) formats. There categories computational instructions:
Immediate instructions (see Table 4.4). 3-Operand, Register-Type instructions (see Table 4.5). Shift instructions (see Table 4.6).
Instruction Summary
4-17
Table
Instruction Immediate
Multiply/Divide instructions (see Table 4.7). Computational CW4011 Instruction Extensions (see Table 4.10). Rate Instruction Extensions (see Table 4.11).
Immediate Instruction Summary
Format Description ADDI immediate 16-bit, sign-extended immediate register place 32-bit result register Trap two's complement overflow. ADDIU immediate 16-bit, sign-extended immediate register place 32-bit result register trap overflow. SLTI immediate Compare 16-bit, sign-extended immediate with register signed 32-bit integers. Result less than immediate; otherwise result Place result register SLTIU immediate Compare 16-bit, sign-extended immediate with register unsigned 32-bit integers. Result less than immediate; otherwise result Place result register ANDI immediate Zero-extend 16-bit immediate, with contents register place result register immediate Zero-extend 16-bit immediate, with contents register place result register XORI immediate Zero-extend 16-bit immediate, exclusive with contents register place result register immediate Shift 16-bit immediate left 16-bits. least-significant 16-bits word zeros. Store result register
Immediate Unsigned Less Than Immediate
Less Than Immediate Unsigned Immediate
Immediate
Exclusive Immediate Load Upper Immediate
4-18
AProcessing Unit
Table
Instruction
Three-Operand, Register Type-Instruction Summary
Format Description contents registers place 32-bit result register Trap two's complement overflow. ADDU contents registers place 32-bit result register trap overflow. Subtract contents registers from place 32-bit result register Trap two's complement overflow.
Unsigned
Subtract
Subtract Unsigned SUBU Subtract contents registers from place 32-bit result register trap overflow. Less Than Compare contents register register signed, 32-bit integers). register less than otherwise, SLTU Compare contents register register unsigned, 32-bit integers). register less than otherwise, Bitwise contents registers place result register Bitwise contents registers place result register Bitwise exclusive contents registers place result register Bitwise contents registers place result register
Less Than Unsigned Exclusive
Instruction Summary
4-19
Table
Instruction
Shift Instruction Summary
Format Description shamt Shift contents register left shamt bits, inserting zeros into low-order bits. Place 32-bit result register shamt Shift contents register right shamt bits, inserting zeros into high-order bits. Place 32-bit result register SRA, shamt Shift contents register right shamt bits, sign-extending high-order bits. Place 32-bit result register SLLV Shift contents register left. Low-order 5-bits register specify number bits shift. Insert zeros into low-order bits place 32-bit result register SRLV Shift contents register right. Low-order 5-bits register specify number bits shift. Insert zeros into high-order bits place 32-bit result register SRAV Shift contents register right. Low-order 5-bits register specify number bits shift. Sign-extend high-order bits place 32-bit result register
Shift Left Logical
Shift Right Logical
Shift Right Arithmetic Shift Left Logical Variable Shift Right Logical Variable Shift Right Arithmetic Variable
4-20
AProcessing Unit
Table
Instruction Multiply
Multiply/Divide Instruction Summary
Format Description MULT Multiply contents registers two's complement values. Place 64-bit results special registers MULTU Multiply contents registers unsigned values. Place 64-bit results special registers Divide contents registers two's complement values. Place 32-bit quotient special register 32-bit remainder DIVU Divide contents registers unsigned values. Place 32-bit quotient special register 32-bit remainder MFHI Move contents special register register MFLO Move contents special register register MTHI Move contents register special register MTLO Move contents register special register
Multiply Unsigned
Divide
Divide Unsigned
Move From HIGH Move From Move HIGH Move
execution time multiply divide instructions shown Table 4.8. Table
Operation Multiply Divide
Execution Time Multiply Divide Instructions
Clocks 17/34
divide time shortened cycles divisor less than significant bits. addition standard MIPS instruction set, CW4011 implements instruction extensions described Table
Instruction Summary
4-21
provide greater application code performance. Table 4.10 Table 4.11 provide further information them. Table
Extension ADDCIU
Instruction Extensions
Description circular immediate. Does immediate, modified according value register CMask. Useful addressing circular buffers. Important other applications that circular buffers. Find first set/clear. Find first set/clear source register, return number destination register. Useful many applications such interrupt handlers, floating point emulation, graphics. Maximum. 32-bit signed contents general registers compared greater value moved destination register. This instruction useful scheduling algorithms. Minimum. 32-bit signed contents general registers compared lesser value moved destination register. This instruction useful scheduling algorithms. Rate Multiply. floating point operands general registers multiplied result stored register. Floating point numbers expressed AForum format. Rate Add. floating point operands general registers added result stored register. Floating point numbers expressed AForum format. Rate Subtract. difference floating point operands stored register. Floating point numbers expressed AForum format. Rate integer conversion. Converts floating point number AForum format unsigned 32-bit integer. Select rotate right. Selects bits from 64-bit source register pair rotates selected data right number bits specified register ROTATE. Useful data alignment operation graphics bit-field selection routines data transmission compression applications. Integer rate conversion. Converts 32-bit unsigned integer floating point number AForum format. Wait Interrupt. Halts power saving mode until hardware interrupt lines becomes active. Upon interrupt, normal execution resumed starting interrupt vector address.
FFS/FFC
RMUL
RADD
RSUB
SELRR
WAITI
4-22
AProcessing Unit
Table 4.10
Instruction Circular Immediate
CW4011 Extensions Summary
Format Description ADDCIU immediate 16-bit immediate sign extended added contents general register with result masked value register CMask according formula: !EXP(CMask)) ((rt immed) EXP(CMask)). Starting most significant register find first which one, return number register set, return with Starting most significant register find first which zero, return number register set, return with SELSR Using register 64-bit register pair, register ROTATE shift count, shift register pair rs||rt right number bits specified ROTATE, place least significant 32-bit value result register SELSL Using register 64-bit register pair, register ROTATE shift count, shift register pair rs||rt left number bits specified ROTATE, place most significant 32-bit value result register two's complement values registers compared smaller value stored register two's complement values registers compared larger value stored register
Find First
Find First Clear
Select Shift Right
Select Shift Left
Minimum
Maximum
Instruction Summary
4-23
Table 4.11
Instruction Rate Multiply
Rate Instruction Extensions
Format Description RMUL 15-bit floating point numbers registers multiplied result stored least significant bits register RADD 15-bit floating point numbers registers added result stored least significant bits register RSUB 15-bit floating point number register subtracted from 15-bit floating point number register result stored register 15-bit floating point value register converted 32-bit unsigned integer. result stored register 32-bit unsigned integer register converted into 15-bit floating point value. result stored register
Rate
Rate Subtract
Rate Integer Conversion Integer Rate Conversion
4.3.4 Jump Branch Instructions
Jump branch instructions change control flow program. MIPS jump branch instructions always occur with one-instruction delay. That instruction immediately following jump branch always executed while target instruction being fetched from storage. There additional cycle penalties, depending circumstances implementation, penalties interlocked hardware. MIPS extensions branch likely class instructions that operate exactly like their nonlikely counterparts, except that when branch taken, instruction following branch cancelled. J-type instruction format used both jump jump-and-link instructions subroutine calls. J-type format, 26-bit target address shifted left bits combined with high-order bits current program counter form 32-bit absolute address. R-type instruction format, which takes 32-bit byte address contained register, used returns, dispatches, cross-page jumps.
4-24
AProcessing Unit
Branches have 16-bit signed offsets relative program counter (I-type). Jump-and-link branch-and-link instructions save return address register Table 4.12 summarizes jump instructions, Table 4.13 summarizes branch instructions, Table 4.14 summarizes branch-likely instructions. Table 4.12
Instruction Jump
Jump Instruction Summary
Format Description target Shift 26-bit target address left bits, combine with four high-order bits jump address with one-instruction delay. target Shift 26-bit target address left bits, combine with four high-order bits jump address with one-instruction delay. Place address instruction following delay slot Link register (R31). Jump address contained register with one-instruction delay. JALR Jump address contained register with one-instruction delay. Place address instruction following delay slot
Jump Link
Jump Register Jump Link Register
Instruction Summary
4-25
Table 4.13
Instruction
Branch Instruction Summary
Format Description offset Branch target address1 register equal register
Branch Equal
Branch Equal offset Branch target address register does equal register Branch Less than Equal Zero Branch Greater Than Zero Branch Less Than Zero BLEZ offset Branch target address register less than equal BGTZ offset Branch target address register greater than BLTZ offset Branch target address register less than
Branch Greater BGEZ offset than Equal Zero Branch target address register greater than equal Branch Less Than Zero Link Branch Greater than Equal Zero Link BLTZAL offset Place address instruction following delay slot Link register (R31). Branch target address register less than BGEZAL offset Place address instruction following delay slot Link register (R31). Branch target address register greater than equal
branch-instruction target addresses computed follows: address instruction delay slot 16-bit offset (shifted left bits sign-extended 32-bits). branches occur with delay instruction.
4-26
AProcessing Unit
Table 4.14
Instruction
Branch-Likely Instruction Summary-MIPS Extensions
Format Description BEQL offset Branch target address1 register equal register BNEL offset Branch target address register does equal register BLEZL offset Branch target address register less than equal BGTZL offset Branch target address register greater than BLTZL offset Branch target address register less than BGEZL offset Branch target address register greater than equal BLTZALL offset Place address instruction following delay slot Link register (R31). Branch target address register less than BGEZALL offset Place address instruction following delay slot Link register (R31). Branch target address register greater than equal
Branch Equal Likely Branch Equal Likely Branch Less than Equal Zero Likely Branch Greater Than Zero Likely Branch Less Than Zero Likely Branch Greater than Equal Zero Likely Branch Less Than Zero Link Likely Branch Greater than Equal Zero Link Likely
branch-instruction target addresses computed follows: address instruction delay slot 16-bit offset (shifted left bits sign-extended 32-bits). branches occur with delay instruction.
Instruction Summary
4-27
4.3.5 Trap Instructions
Trap instructions part MIPS instruction provide instructions that conditionally create exception, based same conditions tested branch instructions. (See Table 4.15.) Table 4.15
Instruction Trap Equal Trap Equal Immediate Trap Greater than Equal Trap Greater Than Equal Immediate Trap Greater than Equal Unsigned
Trap Instruction Summary-MIPS Extensions
Format Description Trap register equal register TEQI immediate Trap register equal immediate value. Trap register greater than equal register TGEI immediate Trap register greater than equal immediate value. TGEU Trap register greater than equal register
Trap Greater TGEIU immediate Than Equal Trap register greater than equal immediate value. Immediate Unsigned Trap Less Than Trap Less Than Immediate Trap Less Than Unsigned Trap register less than register TLTI immediate Trap register less than immediate value. TLTU Trap register less than register
Trap Less Than TLTIU immediate Immediate Unsigned Trap register less than immediate value. Trap Equal Trap Equal Immediate Trap register equal TNEI immediate Trap register equal immediate value.
4-28
AProcessing Unit
4.3.6 Special Instructions
Special instructions cause unconditional branch general exception-handling vector. Special instructions always R-type summarized Table 4.16. Table 4.16
Instruction System Call Breakpoint
Special Instruction Summary
Format Description SYSCALL Initiates system call trap, immediately transferring control exception handler. BREAK Initiates breakpoint trap, immediately transferring control exception handler.
4.3.7 Coprocessor Instructions
CW4011 supports external (on-chip) coprocessors. ATMizer chip, Coprocessor Condition codes used monitor EDMA Request Queues full status (see Section 4.8.6, "Coprocessor Condition Signals"). Table 4.17 summarizes coprocessor instructions supported APU. Table 4.17
Instruction Branch Coprocessor True (Likely)
Coprocessor Instruction Summary
Format Description BCzT offset, (BCzTL offset) Compute branch target address adding address instruction 16-bit offset (shifted left bits sign-extended 32-bits). Branch target address (with delay instruction) coprocessor condition line true. case Branch Likely, delay slot instruction executed when branch taken. BCzF offset, (BCzFL offset) Compute branch target address adding address instruction 16-bit offset (shifted left bits sign-extended 32-bits). Branch target address (with delay instruction) coprocessor condition line false. case Branch Likely, delay slot instruction executed when branch taken.
Branch Coprocessor False (Likely)
Instruction Summary
4-29
4.3.8 System Control Coprocessor (CP0) Instructions
Coprocessor instructions perform operations system control coprocessor (CP0) registers manipulate exception-handling facilities processor. Table 4.18 summarizes instructions Table 4.19 shows extension. Table 4.18
Instruction Move
Instruction Summary
Format Description MTC0 Load contents register into register This instruction delay slot should followed operation (NOP) instruction. MFC0 Load contents register into register This instruction delay slot should followed operation (NOP) instruction. ERET Load from ErrorEPC (SR2 1:Error Exception) (SR2 Exception) clear (SR2 (SR2 Status register. Status register bit[2]. Restore previous interrupt mask mode bits Status register into current status bits. Restore status bits into previous status bits.
Move From
Exception Return
Restore From Exception
Table 4.19
Instruction Wait Interrupt
Instruction Extension Summary
Format Description WAITI Stops execution instructions places processor into power save condition until hardware interrupt reset received. This instruction must followed more operation (NOP) instructions.
4-30
AProcessing Unit
4.3.9 Cache Maintenance Instructions
Cache Maintenance instructions always I-type. Cache instructions must followed three operation (NOP) instructions. Table 4.20 summarizes these instructions. Table 4.20
Instruction Flush I-Cache Flush D-Cache Flush I-Cache D-Cache WriteBack
Cache Maintenance Instruction Summary
Format Description FLUSHI Flush I-Cache. stall cycles will needed. FLUSHD Flush D-Cache. stall cycles will needed. FLUSHID Flush both I-Cache D-Cache stall cycles. offset(base) WriteBack D-Cache line addressed offset GPR[base].
4.3.10 CW4011 Instruction Extensions
instruction extensions, including cache maintenance instructions, further defined this section. They listed alphabetical order, instruction page.
Instruction Summary
4-31
ADDCIU
with Circular Mask Immediate
Format
ADDCIU 011100 immediate immediate
Syntax
ADDCIU immediate
Description
immediate field instruction sign-extended added contents general register result which masked with expanded value special register CMask according equation. CMask register register number valid bits [4:0]. sign_extend_immed (immediate15)16 immediate15.0 GPR[rt] GPR[rs]31.cmask (GPR[rs] sign_extend_immed)cmask-1.0
Exceptions
None
4-32
AProcessing Unit
Find First Clear
Format
SPECIAL 000000 00000 001011
Syntax
Description
contents general register examined starting with most significant bit. number first clear returned general register set, ones returned
Exceptions
None
Instruction Summary
4-33
Find First
Format
SPECIAL 000000 00000 001010
Syntax
Description
contents general register examined starting with most significant bit. number first returned general register set, ones returned
Exceptions
None
4-34
AProcessing Unit
FLUSHD
FLUSH Data Cache
Format
CACHE 101111 00000 FLUSHD 00010
Syntax
FLUSHD
Description
FLUSHD flushes Data Cache lines causes clocks stall cycles regardless cache size. This instruction must followed three operation (NOP) instructions. Note: Cache instructions only work enabled cache sets. IE0, IE1, DE0, bits register, page 4-73.
Exceptions
None
Instruction Summary
4-35
FLUSHI
FLUSH Instruction Cache
Format
CACHE 101111 00000 FLUSHI 00001
Syntax
FLUSHI
Description
FLUSHI flushes Instruction Cache lines causes clocks stall cycles regardless cache size. This instruction must followed three operation (NOP) instructions. Note: Cache instructions only work enabled cache sets. IE0, IE1, DE0, bits register, page 4-73.
Exceptions
None
4-36
AProcessing Unit
FLUSHID
FLUSH Instruction Data Cache
Format
CACHE 101111 00000 FLUSHID 00011
Syntax
FLUSHID
Description
FLUSHID flushes Data Instruction Cache lines causes clocks stall cycles regardless cache size. This instruction must followed three operation (NOP) instructions. Note: Cache instructions only work enabled cache sets. IE0, IE1, DE0, bits register, page 4-73.
Exceptions
None
Instruction Summary
4-37
SELSL
Select Shift Left
Format
SPECIAL 000000 00000 SELSL 000101
Syntax
SELSL
Description
contents general register contents general register combined form 64-bit doubleword. doubleword shifted left number bits specified register ROTATE, upper 32-bits result placed general register This ROTATE register register number with valid bits [4:0]. ROTATE4.0 GPR[rd] GPR[rs]31-s.0 GPR[rt]31.32-s
Exceptions
None
4-38
AProcessing Unit
SELSR
Select Shift Right
Format
SPECIAL 000000 00000 SELSR 000001
Syntax
SELSR
Description
contents general register contents general register combined form 64-bit doubleword. doubleword shifted right number bits specified register ROTATE, lower 32-bits result placed general register This ROTATE register register number Valid bits [4:0]. ROTATE4.0 GPR[rd] GPR[rs]s-1.0 GPR[rt]31.s
Exceptions
None
Instruction Summary
4-39
WAITI
Wait Interrupt
Format
COP0 000000 10000 00000 00000 00000 WAITI 100000
Syntax
WAITI
Description
Execution this instruction causes main processor clock stop halts instruction execution. Execution resumes with reception hardware interrupt, NMI, reset exception. While wait mode, processor power saving mode, using very little current because clock turned most circuitry. WAITI must followed more operation (NOP) instructions; otherwise, results undefined.
Exceptions
None
4-40
AProcessing Unit
WriteBack Data Cache
Format
CACHE 101111 base base 00100 offset offset
Syntax
offset (base)
Description
Eight words Data cache line addressed offset GPR[base] written back memory line dirty. Upper bits offset GPR[base] ignored. This instruction must followed three operation (NOP) instructions.
Exceptions
None
Instruction Summary
4-41
4.3.11 ATMizer Instruction Extensions
This section defines instruction extensions that support calculations.
Maximum
Format
SPECIAL 000000 00000 101001
Syntax
Description
contents general register contents general register compared with both operands treated 32-bit signed values. maximum value stored general register Note: This instruction used identify maximum rate floating point numbers.
Exceptions
None
4-42
AProcessing Unit
Minimum
Format
SPECIAL 000000 00000 101000
Syntax
Description
contents general register contents general register compared with both operands treated 32-bit signed values. minimum value stored general register Note: This instruction used identify minimum rate floating point numbers.
Exceptions
None
Instruction Summary
4-43
RADD
Rate Addition
Format
SPECIAL 000000 RADD 00010 MULT 011000
Syntax
RADD
Description
least significant bits general register least significant bits general register added with both operands treated 15-bit floating point numbers. result stored special register most significant bits register clear.
Exceptions
IntRateExc exception generated floating point overflow underflow.
4-44
AProcessing Unit
RMUL
Rate Multiply
Format
SPECIAL 000000 RMUL 00001 MULT 011000
Syntax
RMUL
Description
least significant bits general register least significant bits general register multiplied with both operands treated 15-bit floating point numbers. result stored special register most significant bits register clear.
Exceptions
IntRateExc exception generated floating point overflow underflow.
Instruction Summary
4-45
RSUB
Rate Subtraction
Format
SPECIAL 000000 RSUB 00011 MULT 011000
Syntax
RSUB
Description
least significant bits general register subtracted from least significant bits general register with both operands treated 15-bit floating point numbers. result stored special register most significant bits register clear.
Exceptions
IntRateExc exception generated floating point overflow underflow.
4-46
AProcessing Unit
Rate Integer Conversion
Format
SPECIAL 000000 00100 MULT 011000
Syntax
Description
least significant bits general register converted from rate floating point format unsigned 32-bit integer. result placed special register fractional portion floating point number truncated.
Exceptions
None
Instruction Summary
4-47
Integer Rate Conversion
Format
SPECIAL 000000 00101 MULT 011000
Syntax
Description
32-bit unsigned integer general register converted into rate floating point format. result stored least significant bits special register most significant bits register clear.
Exceptions
None
4-48
AProcessing Unit
Data Manipulation Registers
System Control Coprocessor (CP0) contains registers that used CW4011 instruction extensions data manipulation operations. They the:
Rotate Register (CW4011 register CMask Register (CW4011 register
also includes registers that used exception handling. description these registers, Section 4.6.2, "Exception Handling Registers."
4.4.1 Rotate Register (23)
Figure shows format Rotate register. CW4011 instruction extensions Rotate register. Specifically, Select Shift Right (SELSR) instruction Select Shift Left (SELSL) instruction five-bit rotate value shift count. These instructions used graphic's data alignment operations bit-field selection routines required data transmission compression applications. Figure
Rotate Register
rotate[4:0]
4.4.2 Circular Mask Register (24)
Figure shows format CMask register. CW4011 instruction extensions Circular Mask (CMask) register. Load/Store (word/halfword/byte) with update circular instructions store value destination register update base address register with addition base offset, modified according five-bit value contained CMask register. This capability useful other applications that circular buffers. Figure
CMask Register
cmask[4:0]
Data Manipulation Registers
4-49
Cache Memory
instruction cache data cache include following features:
Direct mapped two-way associative selectable I-Cache D-Cache, respectively. Least Recently Used (LRU) algorithm used two-way associative cache replacement. I-Cache consists sets Kbytes Kbytes total). D-Cache consists sets Kbytes Kbytes total). Each configurable either direct-mapped two-way associative. load store instructions, cache performs check. physical address data compared with cache determine there cache miss. cache line words doublewords bytes 256-bits). Refill address ordering wraparound from missing address. Cache WriteBack WriteThrough operation selected with register. Cache configured Scratch RAM.
4.5.1 Cache States
I-Cache states. D-Cache states depend whether D-Cache WriteThrough WriteBack mode. 4.5.1.1 I-Cache WriteThrough D-Cache States I-Cache WriteThrough mode D-Cache have states, Invalid Valid Clean. Each cache line Validity that indicates whether line Invalid Valid Clean Initialization sets cache lines Invalid. This invalidation done using Cache Flush instruction (see page 4-56) setting Invalidate mode register (see page 4-56). Figure shows state diagram I-Cache WriteThrough D-Cache. state cache line changes from Invalid Valid Clean when line refilled after cache miss occurs. cache state remains Valid Clean until line invalidated another Cache Flush instruction (see page 4-56) invalidate mode
4-50
AProcessing Unit
register (see page 4-56 Section 4.6.2.9, "Configuration Cache Control Register (16)"). Figure I-Cache D-Cache State Diagram
Load-Miss, then Refill
Invalid Valid Clean
Invalidation
Load-Miss, Refill Load-Hit Store-Miss Store-Hit
4.5.1.2 WriteBack D-Cache States When D-Cache operates WriteBack mode, there three states each cache line; Invalid, Valid Clean, Valid Dirty. each line indicate state shown Table 4.21. Table 4.21
State Invalid Valid Clean Valid Dirty
D-Cache WriteBack Mode
Condition cache line does contain valid information. cache line includes valid information consistent with memory. cache line includes valid information, consistent with memory.
Figure shows state diagram D-Cache WriteBack mode.
Cache Memory
4-51
Figure
D-Cache WriteBack State Diagram
Invalid
Invalidation
Invalidation
Load-Miss, then Refill
Store-Hit Load-Hit Store-Miss Store-Hit
Valid Dirty Valid Clean
Load-Miss, then WriteBack Refill
Load-Miss, Refill Load-Hit Store-Miss
store-hit occurs when Validity address matches physical address store data. When store-miss occurs, store data written into D-Cache, state condition cache line changed. Instead, store data written external Write Buffer. From Write Buffer data written external main memory. WriteBack mode, some lines, known dirty lines, contain more recent information than main memory. Dirty line data written back main memory using WriteBack Data Cache (WB) instruction (refer page 4-41). WriteBack Data Cache instruction write back each line both sets two-way associative configuration. instruction does check address miss. WriteBack (WB) state cache line set, line data written back main memory. Write back requires several stall cycles read data from D-Cache.
4.5.2 Address Cache Tags
Figure 4.10 illustrates format instruction data address both direct two-way associative caches. Cache field contains physical address this line cache data. Line Number field provides address cache line, which eight-word block cache data. Word Offset field addresses word cache line.
4-52
AProcessing Unit
Figure 4.10 Cache Address Format
Cache 9+n1 Line Number
Word Offset
Byte Offset
D-Cache I-Cache
4.5.3 D-Cache Scratch Mode
Either Data Cache configured local, high-speed, Scratch RAM. access Scratch local memory access without stall cycles. Scratch must located cacheable virtual address space. Section 4.7.1, "Operating Modes." desired address Scratch must programmed into cache (all locations) before enabling Scratch mode using bits register (see Section 4.6.2.9, "Configuration Cache Control Register (16)"). program Data enter cache maintenance mode isolate desired RAM: register desired DE1/DE0 register accessed using mfc0 mtc0 instructions (see Section 4.5.5.3, "Cache Maintenance"). Once cache maintenance mode entered, load store instructions access selected using format shown Figure 4.11. Each line should programmed with same value. Data location Scratch (Address bits[31: 9+n]) valid must
locations accessed eight-word boundaries following addresses: 0x0000 0x0020 0x0040 0x0060 0x0080 location location location location location
Cache Memory
4-53
Once been programmed, Scratch enabled setting corresponding register. Figure 4.11 Access Format
Data 9+n1
D-Cache I-Cache
D-Cache Scratch enabled, access Scratch area local memory access without stall cycle.
4.5.4 I-Cache Mode
I-Cache configured Instruction setting (26) register (page 4-73) one. cannot configure I-Cache Instruction RAM. However, achieve same effect leaving memories true caches mapping code that would reside Instruction into cacheable memory area mapping other code into uncacheable area.
4.5.5 Cache Instructions
Instruction Cache configured Instruction RAM. This allows lock frequently used code into Instruction Cache. cannot configure Instruction Cache Instruction RAM. However, achieve same effect leaving both sets true caches, mapping code that should reside Instruction into cacheable memory area, mapping other code into uncacheable area. this work, cacheable code must contained within b
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