CMOS ARINC Interface Circuit HS-3282 high performance CMOS interf
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HS-3282
CMOS ARINC Interface Circuit
HS-3282 high performance CMOS interface circuit that intended meet requirements ARINC Specification 429, similar encoded, time multiplexed serial data protocols. This device intended used with HS-3182, monolithic bipolar differential line driver designed meet specifications ARINC 429. ARINC interface circuit consists receivers transmitter operating independently shown Figure receivers operate frequency that (10) times receiver data rate, which same different from transmitter data rate. Although receivers operate same frequency, they functionally independent each receives serial data asynchronously. transmitter section ARINC interface circuit consists mainly First-In First-Out (FIFO) memory timing circuit. FIFO memory used hold eight ARINC data words transmission serially. timing circuit used correctly separate each ARINC word required ARINC Specification 429. Even though ARINC Specification specifies 32-bit word, including parity, HS-3282 programmed also operate with word length bits. incoming receiver data word parity checked, parity status stored receiver latch output BD08 during word. logic indicates that number logic were received stored; logic indicates that even number logic "1"s were received stored]. transmitter parity generator will generate either even parity depending upon status PARCK control signal. logic BD12 will cause parity used output data stream. Versatility provided both transmitter receiver external clock input which allows interface circuit operate data rates from kilobits. external clock must (10) times data rate insure data ambiguity. ARINC interface circuit fully guaranteed support data rates ARINC specification over both voltage (±5%) full military temperature range. interfaces with CMOS NMOS support circuitry, uses standard 5-volt supply.
REFERENCE AN400
March 1997
Features
ARlNC Specification Compatible Data Rates Kilobits 12.5 Kilobits Separate Receiver Transmitter Section Dual Independent Receivers, Connecting Directly ARINC Serial Parallel Receiver Data Conversion Parallel Serial Transmitter Data Conversion Word Lengths Bits Parity Status Received Data Generate Parity Transmitter Data Automatic Word Timer Single Supply Power Dissipation Full Military Temperature Range
Ordering Information
PACKAGE CERDIP SMD# CLCC -40oC +85oC -55oC +125oC SMD# TEMP. RANGE -55oC +125oC PART NUMBER HS1-3282-8 5962-8688001QA HS4-3282-9+ HS4-3282-8 5962-8688001XA PKG. F40.6 F40.6 J44.A J44.A J44.A
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Intersil (and design) trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2002. Rights Reserved
FN2964.2
HS-3282 Pinouts
HS-3282 (CERDIP) VIEW
429DI1(A) 429DI1(B) 429DI2(A) 429DI2(B) D/R1 D/R2 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 CWSTR ENTX 429D0 429D0 TX/R BD00 BD01 BD02 BD03 BD04 BD05
HS-3282 (CLCC) VIEW
429DI2(A) 429DI1(B) 429DI2(B) 429DI1(A) TXCLK
D/R1 D/R2 BD15 BD14 BD13 BD12 BD11
CWSTR ENTX 429D0 429D0 TX/R BD00 BD01
BD10 BD09 BD08 BD07 BD06 BD05 BD04 BD03 BD02
HS-3282 SYMBOL D/R1 D/R2 BD15 SECTION Recs/Trans Receiver Receiver Receiver Receiver Receiver Receiver Receiver Receiver Receiver Recs/Trans Supply volts ±5%. ARlNC data input Receiver ARlNC data input Receiver ARINC data input Receiver ARINC data input Receiver Device ready flag output from Receiver indicating valid data word ready fetched. Device ready flag output from Receiver indicating valid data word ready fetched. Data Selector Input signal select 16-bit words from either Receiver Input signal enable data from Receiver onto data bus. Input signal enable data from Receiver onto data bus. Bi-directional data fetching data from either Receivers, loading data into Transmitter memory control word register. Control Word Table description Control Word bits. Circuit Ground. Control Word function applicable. Control Word function applicable. Control Word function applicable. Control Word function applicable. Control Word function applicable. Parallel load input signal loading first 16-bit word into Transmitter memory. Parallel load input signal loading first 16-bit word into Transmitter memory initiates data transfer into memory stack. Transmitter flag output indicate memory empty. DESCRIPTION
BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 BD05 BD04 BD03 BD02 BD01 BD00
Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Recs/Trans Transmitter Transmitter
TX/R
Transmitter
HS-3282 SYMBOL 429D0 429D0 ENTX CWSTR (Continued) SECTION Transmitter Transmitter Transmitter Recs/Trans Data output from Transmitter Data output from Transmitter. Transmitter Enable input signal initiate data transmission from FIFO memory. Control word input strobe signal latch control word from databus into control word register. connection. Must left open. connection. Must left open tied never tied high. External clock input. either (10) eighty (80) times data rate. using both ARINC data rates must (10) times highest data rate, (typically 1MHz). Transmitter Clock output. Delivers clock frequency equal transmitter data rate. Master Reset. Active pulse used reset FIFO, counters, timer, word count signal, TX/R various other flags controls. Master reset does reset control word register. Usually only used Power-Up System Reset. Connection. DESCRIPTION
Recs/Trans
TXCLK
Transmitter Recs/Trans
Pinout
HS-3282 Operational HS-3282 designed support ARINC Specification other serial data protocols that similar format collecting receiving, transmitting, synchronizing, timing parity functions single, power circuit. goes beyond ARlNC requirements providing either even parity, giving user choice either 32-bit word lengths. receiver transmitter sections operate independently each other. serial-toparallel conversion required receiver parallelto-serial conversion requirements transmitter have been incorporated into interface circuit. Provisions have been made through external clock input provide data rate flexibility. This requires external clock that times data rate. obtain flexibility discussed above, number external control signals required, reduce count requirements, internal control word register used. control word latched from data into register Control Word Strobe (CWSTR) signal going logic "1". Eleven (11) control functions used, along with Data (BD) line listed below:
Control Word
NAME BD05 SYMBOL SLFTST FUNCTION Connects self test signal from transmitter directly receiver shift registers, bypassing input receivers. Receiver receives Data True Receiver receives Data Not. Note that transmitter output remains active. (Logic SLFTST Enables Self Test). Signal Activate Source/Destination (S/D) Decoder Receiver (Logic activates Decoder). SDENB1 then this compared with ARlNC Data also matches (see Y1), word will accepted Receiver SDENB1 this becomes don't care. SDENBI then this compared with ARINC Data #10. also matches (see X1), word will accepted Receiver SDENB1 this becomes don't care. Signal activate Source/Destination (S/D) Decoder Receiver (Logic activates Decoder). SDENB2 then this compared with ARlNC Data also matches (see Y2), word will accepted Receiver SDENB2 this becomes don't care. SDENB2 then this compared with ARINC Data #10. also matches (see X2), word will accepted Receiver SDENB2 this becomes don't care. Signal used invert transmitter parity test parity circuits. Logic selects normal parity. Logic selects even parity. Selects high Transmitter data rate. TXSEL then transmitter data rate equal clock rate divided (10). TXSEL then transmitter data rate equal clock rate divided eighty (80). Selects high Receiver data rate. RCVSEL then received data rate should equal clock rate divided (10), RCVSEL "then received data rate should equal clock rate divided eighty (80). Selects word length. WLSEL 32-bit word format will selected. WLSEL 25-Bit word format will selected.
BD06 BD07 BD08 BD09 BD10 BD11 BD12 BD13 BD14
SDENB1 SDENB2 PARCK TXSEL RCVSEL
BD15
WLSEL
ARlNC DATA FORMAT input Receiver output from Transmitter follows:
TABLE ARINC 32-BIT DATA FORMAT ARINC FUNCTION Label Data Data Sign Parity Status
This format shuffled when seen sixteen bidirectional input/outputs. format shown below used from receivers input transmitter:
TABLE WORD FORMAT BI-DIRECTIONAL
FUNCTION Data Data Status Parity Status Label
ARINC
HS-3282
TABLE WORD FORMAT BI-DIRECTIONAL BlT#
FUNCTION Sign Data
ARINC BIT#
Line Receiver functions voltage level translator. transforms volt differential line voltage, ARINC format, into volt internal logic level. output Line Receiver inputs Self-Test Data Selector (SEL). other input Data Selector Self-Test Signal from Transmitter section. incoming data, either Self-Test ARlNC 429, double sampled Word Timer generate Data Clock. Receiver sample frequency (RCVCLK), 1MHz, 125kHz, generated Receiver/Transmitter Timing Circuit. This sampling frequency times Data Rate ensure data ambiguity. derived data clock then shifts data down 32-Bit long Data Shift Register (Data S/RI). Data Word Length selectable either Bits Bits long Control Signal (WLSEL). soon data word completely received, internal signal (WDCNT1) generated Word Timer Circuit. Source/Destination (S/D) Decoder compares user code with Bits Data Word. codes matched, positive signal generated enable WDCNT1 signal latch received data. Otherwise, data word ignored latching action takes place. Decoder Enabled Disabled control signal ENB. data word latched, indicator flag (D/R1) set. This indicates valid data word ready fetched user. After receiver data been shifted down shift register, placed holding register. device ready flag will then indicating that data ready fetched. data ignored left holding register, will written over when next data word received. received data 32-bit holding register placed form (2)16-bit words regardless whether format 25-bit data words. Either word accessed first repeatedly until next received data word falls into holding register. parity incoming word checked status (i.e., logic parity logic even parity) stored receiver latch output BD08 during Word Assuming user desires access data, first sets Data Select Line (SEL) Logic level pulses Enable (EN1) line. This action causes Data Selector (SELl) select first-data word, which contains label field Enable onto Data Bus. obtain second data word, user sets line Logic level pulse Enable (EN1) line again. Enable pulse duration matched user circuit requirement needed read Data Word from Data Bus. second Enable pulse also used reset Device Ready (D/R1) flip-flop. This completes receiving cycle.
Receiver Parity Status: Parity Even Parity receiver input data word string broken before entire data word received, receiver will reset ignore partially received data word. transmitter used transmit consecutive data words, each word will separated four "null" state (both positive negative outputs will maintain zero volt level.)
TABLE ARINC 25-BIT DATA FORMAT ARINC FUNCTION Label Data Parity Status
TABLE WORD FORMAT BI-DIRECTIONAL BIT#
FUNCTION Don't Care Parity Status Label
ARINC BIT#
TABLE WORD FORMAT BI-DIRECTIONAL BIT#
FUNCTION Data
ARINC BlT#
Receiver Parity Status: Parity Even Parity Source/Destination (S/D) 25-Bit format. Receiver Operation Since receivers functionally identical, only will discussed detail, block diagram will used reference this discussion. receiver consists following circuits:
HS-3282
Transmitter Operation Transmitter section consists 8-word deep 31Bit long FIFO Memory, Parity Generator, Transmitter Word Timing Circuit Driver Circuit. FlFO Memory organized such that data loaded input register automatically transferred output register Serial Data Transmission. This eliminates large amount data managing time since data need clocked from input register output register. FIFO input register made sets D-type flip-flops, which clocked parallel load signals (PL1 PL2). must always precede PL2. Multiple PL1's occur data will written over. soon received, data transferred FIFO. data from Data clocked into D-type flip-flop positive going edge signals. FIFO memory initially empty, stack full, data will automatically transferred down Memory Stack into output register last empty FIFO storage register. Transmitter Enable signal (ENTX) active, Logic "0", data remains output register. FIFO Memory storage locations hold eight 31-bit words. memory full data again strobed with data input register written over data. Data will remain Memory until ENTX goes Logic "1". This activates FIFO Clock data shifted serially Transmitter Driver. Data loaded into FIFO only while ENTX inactive (low). possible write data into FIFO while transmitting. WARNING: applied while ENTX high, i.e., while transmitting, FlFO disrupted such that would require (Master Reset) signal recover. Output Register FIFO designed such that shift word Bits long Bits long. This word length again controlled WLSEL bit. word Timer Circuit also automatically inserts equivalent 4-Bit Times between each word. This gives minimum requirement 29-Bit time 36-Bit time each word transmission. Assuming signal, ENTX, remains Logic "1", transfer stack signal generated transfer data down Memory Stack position. This action continued until last word shifted FIFO memory. this time Transmitter Ready (TX/R) flag generated signal user that Transmitter ready receive eight more data words. During transmission, ENTX taken then high again, transmission will cease leaving portion word untransmitted, data integrity FIFO will destroyed. Counter used detect last shifted FIFO memory appends Parity generated Parity Generator. Parity Generator control signal, Parity Check (PARCK), which establishes whether even parity used output data word. PARCK logic will result parity when logic will result even parity. Sample Interface Technique From Figure that Data time shared between Receiver Transmitter. Therefore, controlling must synchronously shared between Receiver Transmitter. Figure shows typical interface timing control ARlNC Chip Receiving function Transmitting function. Timing sequence loading Transmitter FIFO Memory shown Timing Interval transmitter Ready (TX/R) Flag signals user that Transmitter Memory empty. user then Enables Transmitter Data, 16-Bit word, Data strobes Transmitter with Parallel Load (PL1) Signal. second part 32-Bit word similarly loaded into Transmitter with PL2, which also initiates data transfer stack. This continuous until Memory full, which eight 31-Bit words. user must keep track number words loaded into Memory ensure data written over other data. During time user loading Transmitter, does have service Receiver, even Receiver flags user with signal D/R1 that valid received word ready fetched. This shown Timing interval user decides obtain received data before Transmitter completely loaded, sets parallel load signals (PL1 PL2) Logic state, strobes while signal Logic state. After negative edge EN1, first 16-Bit segment received word becomes valid Data Bus. positive edge EN1, user should toggle signal ready Receiver second 16-Bit word. Strobing Receiver with EN1, second time, enables second 16-Bit word resets Receiver Ready Flag D/R1. user should reset signal Logic state ready Receiver another Read Cycle. During time period that user fetching received words, load transmitter. This done interlacing signals with signals shown Timing Interval Servicing Receiver similar illustrated Timing interval Timing interval shows rest Transmitter loading sequence beginning transmission switching signal Enable Logic state. Timing interval time takes transmit data from FlFO Memory, either times times. Repeater Operation This mode operation allows data word that been received placed directly FIFO transmission. timing diagram shown Figure 32-bit word used this example. data word shifted into shift register flag goes low. logic placed line strobed. This same normal receiver operation places half data word bits) data bus. strobing same time EN1, these bits will taken placed FIFO. brought back high strobed again second bits data word. Again strobing same time second bits will placed FIFO. parity will have been stripped away leaving 31-bit data word FIFO ready transmission shown Figure
HS-3282
RCVSEL WDCNT WORD TXSEL DATA CLOCK DATA LATCH DECODER WDCNT WDCNT LATCH LINE RECEIV. SELF TEST WLSEL BD15BD00 DATA DATA DATA CLOCK WORD WDCNT PARCK SELF TEST 429D0 WLSEL TIMING CONTROL WORD REGISTER (BD05) ENB1 (BD06) ENB2 (BD09) (BD07) (BD06) (BD10) (BD11) PARCK (BD12) TXSEL (BD13) RCVSEL (BD14) WLSEL (BD15) CWSTR
WLSEL SELF TEST 429D11 LINE RECEIV. TEST S/DENB
429D11
CODER 429D12
WORD
ENTX
429D12
FIFO PARITY
DRVR
429D0
D/R1 D/R2
TX/R
FIGURE SINGLE CHIP ARINC INTERFACE FUNCTIONAL BLOCK DIAGRAM
HS-3282
Absolute Maximum Ratings
Supply Voltage +7.0V Input, Output Voltage Applied (Except Pins -0.3V +0.3V Input Voltage Applied (Pins -29V +29V Classification Class
Thermal Information
Thermal Resistance
(oC/W) (oC/W)
CDIP Package CLCC Package Maximum Junction Temperature. +175oC Maximum Storage Temperature Range .-65oC +150oC Maximum Lead Temperature (Soldering 10s). +300oC
Operating Conditions
Operating Voltage Range +4.75V +5.25V Operating Temperature Range HS-3282-5. .0oC +70oC HS-3282-8. -55oC +125oC
Characteristics
Gate Count 2632 Gates
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
Electrical Performance Specifications ±5%, +70oC (HS-3282-5),
-55oC +125oC (HS-3282-8) LIMITS PARAMETER ARlNC INPUTS Pins 2-3,4-5 Logic Input Voltage Logic Input Voltage Null Input Voltage Common Mode Voltage Input Leakage Input Leakage Differential Input Impedance Input lmpedance Input lmpedance VNUL 5.25V 5.25V 4.75V, 5.25V 4.75V, 5.25V 5.25V, ±6.5V 5.25V, 0.0V 5.25V, +5V, 5.25V, Open, 5.0V -13.0 -2.5 -5.0 -450 13.0 -6.7 +2.5 +5.0 SYMBOL CONDITIONS UNITS
BIDIRECTIONAL INPUTS Pins 11-20, 22-27 Logic Input Voltage Logic Input Voltage Input Leakage Input Leakage 5.25V 4.75V 5.25V,VIN 5.25V 5.25V, 0.0V -1.5
OTHER INPUTS Pins 8-10, Logic Input Voltage Logic Input Voltage Input Leakage Input Leakage 5.25V 4.75V 5.25V, 5.25V 5.25V, 0.0V
OUTPUTS Pins 11-20, 22-27, 30-32, Supply Logic Output Voltage Logic Output Voltage Standby Supply Current Operating Supply Current lCC1 lCC2 4.75V, -1.5mA 4.75V lOL= 1.8mA 5.25V, Except 9,10, 5.25V 5.25V, 5.25V Except 0.0V, 1MHz
HS-3282
Electrical Performance Specifications ±5%, +70oC (HS-3282-5),
-55oC +125oC (HS-3282-8) LIMITS PARAMETER Clock Frequency Data Rate Data Rate Master Reset Pulse Width RECEIVER TIMING Receiver Ready Time From 32nd Receiver Ready Time From 32nd Device Ready Enable Time Data Enable Pulse Width Data Enable Data Enable Time Data Enable Device Ready Reset Time Output Data Valid Enable Time Data Enable Data Select Time Data Select Data Enable Time Output Data Disable Time CONTROL WORD TIMING Control Word Strobe Pulse Width Control Word Setup Time Control Word Hold Time TRANSMITTER FIFO Write Timing Parallel Load Pulse Width Parallel Load Parallel Load Delay Transmitter Ready Delay Time Data Word Setup Time Data Word Hold Time TRANSMITTER Output Timing Enable Transmit Output Data Valid Time Enable Transmit Output Data Valid Time Output Data Time Output Data Time Output Data Null Time Output Data Null Time TENDAT TENDAT TBlT TBlT TNULL TNULL 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V 4.95 39.6 4.95 39.6 5.05 40.4 5.05 40.4 TPL12 TTX/R TDWSET TDWHLD 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V TCWSTR TCWSET TCWHLD 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V TD/R2 TD/R2 TD/REN TENEN TEND/R TENDATA TENSEL TSELEN TDATAEN 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V SYMBOL CONDITIONS 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V 12.5 UNITS
HS-3282
Electrical Performance Specifications ±5%, +70oC (HS-3282-5),
-55oC +125oC (HS-3282-8) (Continued) LIMITS PARAMETER Data Word Time Data Word Time Data Transmission Word TX/R Time Enable Transmit Turnoff Time REPEATER OPERATION TIMING Data Enable Parallel Load Delay Time Data Enable Hold Parallel Load Time Enable Transmit Delay Time NOTES: 100kHz Data Rate. 12.5kHz Data Rate. TENPL TPLEN TTX/REN 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V SYMBOL TGAP TGAP TDTX/R TENTX/R CONDITIONS 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V 39.6 316.8 40.4 323.2 UNITS
Electrical Performance Specifications ±5%, +70oC (HS-3282-5),
-55oC +125oC (HS-3282-8) LIMITS PARAMETER Differential Input Capacitance Input Capacitance lnput Capacitance Input Capacitance Output Capacitance Clock Rise Time Clock Fall Time Input Rise Time Input Fall Time NOTES: parameters listed this table controlled design process parameters directly tested. These parameters characterized upon initial design after major process and/or design changes affecting these parameters. measurements referenced device GND. Pins 2-3, 4-5. Pins 8-10, Pins 11-20, 22-27, 30-32, Pins 8-20, 22-29, SYMBOL TLHC THLC TLHI THLI (NOTE CONDITIONS Open, 1MHz, Note GND, 1MHz, Note Open, 1MHz, Note Open, 1MHz, Note Open, 1MHz, Note 1MHz, From 0.7V 3.5V 1MHz, From 3.5V 0.7V From 0.7V 3.5V, Note From 3.5V 0.7V, Note UNITS
HS-3282 Timing Waveforms
TX/R ENABLE DATA D/R1 D/R2 TIME INTERVAL TIME INTERVAL TIME INTERVAL TIME INTERVAL TIME INTERVAL
BEING USED OUTPUT
BEING USED INPUT
FIGURE TYPICAL INTERFACE TIMING SEQUENCE
429DI
tD/R tEND/R
tD/REN tSELEN tENDATA BD00-15 WORD tSELEN tENSEL tDATAEN tENDATA WORD tDATAEN tENSEL tENEN
BD00-15
WORD
WORD
FIGURE RECEIVER TIMING
HS-3282 Timing Waveforms
(Continued)
tCWSTR CWSTR tCWHLD
tCWSET BD00-15 CONTROL WORD
FIGURE CONTROL WORD TIMING
TX/R tDWSET tDWHLD BD00-15 WORD WORD tDWSET tDWHLD tPL12
tTX/R
FIGURE TRANSMITTER FIFO WRITE TIMING
TX/R tENTX/R ENTX tENDAT 42900
tBIT tNUL
tNUL
tGAP
tNUL
tDTX/R
FIGURE TRANSMITTER OUTPUT TIMING
HS-3282 Timing Waveforms
(Continued)
429DI
tD/R tD/REN tSELEN tENPL tENPL tPLEN tENEN tSELEN tENSEL
tEND/R
tENSEL
tPLEN
tTX/R TX/R tTX/REN ENTX tENDAT 429D0 tDTX/R tNUL tENTX/R
FIGURE REPEATER OPERATION TIMING
HS-3282 Burn-In Circuits
HS-3282 CERDIP
DI1(A) DI1(B) DI2(A) DI2(B) D/R1 D/R2 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 CWSTR ENTX 429D0 429D0 TX/R BD00 BD01 BD02 BD03 BD04 BD05
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, www.intersil.com
Burn-In Circuits
HS-3282 CLCC
CWSTR ENTX TX/R BD00 BD01 BD09 BD08 BD07 BD06 BD05 BD04 BD03 BD02
DI2(B)
DI2(A)
DI1(B)
DI1(A)
TXCLK
D/R1 D/R2
BD15 BD14 BD13 BD12 BD11 BD10
NOTES: Resistors 47k, 1/4W (Min) Ground +5.5V, ±0.5V 0.01mF/Socket (Min) 100kHz, F0/2, F14/2
Characteristics
DIMENSIONS: mils) (6250 5700 483µm) METALLIZATION: Type: Si-Al Thickness: GLASSIVATION: Type: SiO2 Thickness: WORST CASE CURRENT DENSITY: A/cm2
Metallization Mask Layout
HS-3282
429DI2(B)
429DI2(A) 429DI1(B)
429DI1(A)
(38)
D/R2 (36)
(37) (35) (34) CWSTR (33) ENTX (32) 429D0 (31) 429D0 (30) TX/R (29) (28) (27) BD00
D/R1
(40) BD04 (23) BD03 (24)
(10)
BD15 (11) BD14 (12) BD13 (13) BD12 (14) BD11 (15) BD10 (16)
BD09 (17)
BD08 (18)
BD07 (19)
BD06 (20)
BD05 (22)
(39) BD02 (25)
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, www.intersil.com
BD01 (26)
(21)
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