Address Sequencer Matrix Math Operations December 1999

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Address Sequencer Matrix Math Operations December 1999

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HSP45240/883
Address Sequencer
Matrix Math Operations
December 1999
Features
ODUC PRODUCT RSIL TITUT OBSO SUBS 1-888-INTE cation sil.co ntral Appli pp@inter call email: Processing
This Circuit Processed Accordance MIL-STD883 Fully Conformant Under Provisions Paragraph 1.2.1. Block Oriented 24-Bit Sequencer Configurable Independent 12-Bit Sequencers Crosspoint Switch Programmable Delay Outputs Multi-Chip Synchronization Signals Standard Interface 100pF Drive Outputs 40MHz Clock Rate
Ordering Information
PART NUMBER HSP45240GM-25/883 HSP45240GM-33/883 HSP45240GM-40/883 TEMP. RANGE PACKAGE PKG.
Description
Intersil HSP45240/883 high speed Address Sequencer which provides specialized addressing functions like FFTs, filtering, matrix operations, image manipulation. sequencer supports block oriented addressing large data sets bits clock speeds 40MHz.
Applications
1-D, Filtering Pan/Zoom Addressing
Block Diagram
STARTOUT ADDVAL DONE BLOCKDONE STARTIN START CIRCUITRY SEQUENCE GENERATOR CROSS-POINT SWITCH OUT12-23 DELAY OUT0-11 PROCESSOR INTERFACE BUSY
DLYBLK
D0-6,
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Intersil (and design) trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2002. Rights Reserved
FN2816.4
HSP45240/883
Absolute Maximum Ratings
Supply Voltage +8.0V Input, Output Voltage Applied. -0.5V +0.5V Classification Class
Thermal Information
Thermal Resistance (Typical, Note oC/W) (oC/W) Package 37.1 10.1 Maximum Package Power Dissipation 125oC Package 1.35W Maximum Junction Temperature. 175oC Maximum Storage Temperature Range -65oC 150oC Maximum Lead Temperature (Soldering 10s). 300oC
Operating Conditions
Temperature Range -55oC 125oC Voltage Range +4.5V +5.5V
Characteristics
Gate Count .8,388
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air. TABLE ELECTRICAL SPECIFICATIONS Device Guaranteed 100% Tested GROUP SUBGROUPS LIMITS TEMPERATURE UNITS
PARAMETER Logical Input Voltage Logical Zero Input Voltage Output HlGH Voltage Output Voltage Input Leakage Current Output Leakage Current Clock lnput High Clock Input Standby Power Supply Current Operating Power Supply Current Functional Test
SYMBOL
TEST CONDITIONS 5.5V 4.5V -400µA 4.5V (Note
+2.0mA
4.5V (Note 5.5V VOUT 5.5V 5.5V 4.5V 5.5V, Outputs Open 33MHz 5.5V (Note (Note
VIHC VILC
ICCSB
ICCOP
NOTES: Interchanging force sense conditions permitted. Operating Supply Current proportional frequency, typical rating 3mA/MHz. Tested follows: 1MHz, 2.6, 0.4, 1.5V, 1.5V, VIHC 3.4V, VILC 0.4V.
HSP45240/883
TABLE ELECTRICAL SPECIFICATIONS Device Guaranteed 100% Tested GROUP SUBGROUP 9,10,11 TEMPERATURE (oC) (25MHz) (33MHz) (40MHz) UNITS
PARAMETER Clock Period Clock Pulse Width High Clock Pulse Width Setup Time D0-6 High Hold Time D0-6 from Setup Time Hold Time from High Pulse Width Pulse Width High Cycle Time Set-up Time STARTIN, DLYBLK, Clock High Hold Time STARTlN, DLYBLK, Clock High Clock Output Prop. Delay OUT0-23 Clock Prop. Delay, STARTOUT, BLKDONE, DONE, ADVAL, BUSY Output Enable Time (Note Time NOTES:
SYMBOL tWRL tWRH tPDO tPDS
tRST
Clock Cycles
Testing: 4.5V 5.5V, inputs driven 3.0V Logic 0.0V Logic "0". Input output timing measurements made 1.5V both logic "`0". driven 4.0V measured 2.0V. Transition measured ±200mV from steady state voltage with loading specified test load circuit 40pF. TABLE ELECTRICAL PERFORMANCE SPECIFICATIONS (25MHz) NOTES TEMPERATURE (33MHz) (40MHz) UNITS
PARAMETERS Input Capacitance
SYMBOL
TEST CONDITIONS Open, 1MHz, measurements referenced device GND. Open, 1MHz, measurements referenced device GND.
Output Capacitance
COUT
Output Disable
tOEZ
HSP45240/883
TABLE ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) (25MHz) NOTES TEMPERATURE (33MHz) (40MHz) UNITS
PARAMETERS Output Rise Time Output Fall Time NOTES:
SYMBOL
TEST CONDITIONS
Parameters listed Table controlled design process parameters directly tested. These parameters characterized upon initial design after major process and/or design changes. Loading specified test load circuit with 40pF. TABLE ELECTRICAL TEST REQUIREMENTS CONFORMANCE GROUPS Initial Test Interim Test Final Test Group Groups METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS
HSP45240/883 Burn-In Circuit
START BLOCK DONE OUT1 OUT2
START BUSY
DONE OUTO
OUT3
OUT4
OUT5
OUT6 OUT7
OUT9
OUT8
OUT10 OUT11
OUT12
OUT22 OUT21 OUT18 OUT17
OUT14
OUT23
OUT20 OUT19
OUT16 OUT15 OUT13
NOTES:
NAME OUT23 OUT20 OUT19 OUT16 OUT15 OUT13 OUT22 OUT21 OUT18 OUT17
BURNIN SIGNAL VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
NAME OUT14 OUT12 OUT10 OUT11 OUT9
BURNIN SIGNAL VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
NAME OUT8 OUT6 OUT7 OUTS RSTB OUT4 OELB START1NB ADVALB
BURNIN SIGNAL VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
NAME BUSYB DONEB OUT0 OUT3 OEHB DLYBLK STARTOUTB BLOCKDONEB OUT1 OUT2
BURNIN SIGNAL VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
(2.7V ±10%) used outputs only. (±20%) resistor connected pins except GND. ±0.5V. 0.1µF (min) capacitor between position. 100kHz ±10%, F0/2, F1/2., F10/2, -60% Duty Cycle. Input voltage limits: 0.8V max., 4.5V ±10%.
HSP45240/883 Characteristics
DIMENSIONS: mils mils ±1mils METALLIZATION: Type: Si-Al-Cu Thickness: WORST CASE CURRENT DENSITY: 105A/cm GLASSIVATION: Type: Nitrox Thickness:
Metallization Mask Layout
HSP45240/883
OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14 OUT13
OUT12 OUT11 OUT10 OUT9 OUT8
OUT4 OUT3 OUT7 OUT6 OUT5
STARTOUT
DLYBLK
STARTIN
ADDVAL
BLOCKDONE
DONE
BUSY
OUT0
Intersil semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries. information regarding Intersil Corporation products, site http://www.intersil.com
OUT1
OUT2

Address Sequencer Matrix Math Operations December 1999

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