FN2785.5 Digital Filter HSP43891 video-speed Digital Filter

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FN2785.5 Digital Filter HSP43891 video-speed Digital Filter

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HSP43891
FN2785.5
Digital Filter
HSP43891 video-speed Digital Filter (DF) designed efficiently implement vector operations such digital filters. comprised eight filter cells cascaded internally shift output stage, single integrated circuit. Each filter cell contains two's complement multiplier, three decimation registers 26-bit accumulator. output stage contains additional 26-bit accumulator which contents filter cell accumulator output stage accumulator shifted right 8-bits. HSP43891 maximum sample rate 30MHz. effective multiply-accumulate (mac) rate 240MHz. HSP43891 configured process expanded coefficient word sizes. Multiple cascaded larger filter lengths without degrading sample rate single process larger filter lengths less than 30MHz with multiple passes. architecture permits processing filter lengths over 1000 taps with guarantee overflows. practice, most filter coefficients less than 1.0, making even larger filter lengths possible. provides 8-bit unsigned 9-bit two's complement arithmetic, independently selectable coefficients signal data. Each filter cell contains three resampling decimation registers which permit output sample rate reduction rates 1/2, input sample rate. These registers also provide capability perform operations such matrix multiplication spatial correlations/convolutions image processing applications.
Features
Eight Filter Cells 0MHz 30MHz Sample Rate 9-Bit Coefficients Signal Data 26-Bit Accumulator Stage Filter Lengths Over 1000 Taps Expandable Coefficient Size, Data Size Filter Length Decimation
Applications
Filters Radar/Sonar Digital Video Adaptive Filters Echo Cancellation Complex Multiply-Add Sample Rate Converters
Ordering Information
PART NUMBER HSP43891VC-20 HSP43891VC-25 HSP43891VC-30 HSP43891JC-20 HSP43891JC-25 HSP43891JC-30 HSP43891GC-20 HSP43891GC-25 HSP43891GC-30 TEMP. RANGE PACKAGE PKG.
Lead MQFP Q100.14x20 Lead MQFP Q100.14x20 Lead MQFP Q100.14x20 Lead PLCC Lead PLCC Lead PLCC CPGA CPGA CPGA N84.1.15 N84.1.15 N84.1.15 G85.A G85.A G85.A
Block Diagram
DIENB CIENB DCM0 ERASE CIN0 RESET ADRO DIN0 DIN8
FILTER CELL
FILTER CELL
FILTER CELL
FILTER CELL
FILTER CELL
FILTER CELL
FILTER CELL
FILTER CELL
COUT0 COENB
RESET SHADD SENBL SENBH ADR0, ADR1, ADR2 OUTPUT STAGE SUM0
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Intersil (and design) trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2002. Rights Reserved
HSP43891 Pinout
GRID ARRAY (PGA)
COENB DIN6 DIN3 DIN0 CIN8 CIN6 CIN4 DCM1 SUM23 SUM22 SUM21 SUM18 SUM14 SUM13 SUM11 SUM9 COUT7 COUT8 ERASE DIN8 DIN1 DIN2 CIENB CIN7 SENBH SUM24 DIENB DIN5 DIN4 CIN5 CIN3 SUM25 ADR1 ADR0 ADR2 DCM0 COUT0 SHADD COUT1 COUT2 COUT3 COUT4 SENBH SUM24 SUM19 SUM15 SUM12 SUM10 SUM8 SUM6 COENB RESET DIN7 DIN6 DIN3 DIN0 CIN8 COUT5COUT6 ALIGN DIENB DIN5 DIN4 CIN5 CIN3 CIN2 CIN1 CIN0 SENBL SUM5 SUM4 SUM20 SUM17 SUM16 SUM7 SUM19 SUM15 SUM12 SUM10 SUM8 SUM6
RESET DIN7
ALIGN COUT5 COUT6 COUT3 COUT4
CIN2
COUT1
COUT2
CIN1
CIN0 SENBL
HSP43891
COUT0 SHADD ADR2 DCM0
HSP43891
BOTTOM VIEW PINS
SUM1 SUM3 SUM2
VIEW PINS DOWN
SUM0
SUM0
SUM1 SUM3 SUM2
ADR1
ADR0
SUM5 SUM4
SUM25
SUM20 SUM17 SUM16
SUM7
COUT7 COUT8 ERASE DIN8
DIN1
DIN2 CIENB CIN7
CIN6
CIN4
DCM1 SUM23 SUM22 SUM21 SUM18 SUM14
SUM13
SUM11 SUM9
LEAD PLASTIC LEADED CHIP CARRIER (PLCC)
SUM24 DCM1 SUM25 SENBH ADDR0 ADDR1 DCM0 ADDR2 SHADD COUT0 COUT1 COUT2 COUT3 COUT4 COUT5 SUM23 SUM22 SUM21 SUM20 SUM19 SUM18 SUM17 SUM16 SUM15 SUM14 SUM13 SUM12 SUM11 SUM10 SUM9 SUM8 SUM7 COUT6 COUT7 COUT8 COENB ERASE RESET DIENB DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 CIENB CIN8
HSP43891
VIEW
SUM6 SUM5 SUM4 SUM3 SUM2 SUM1 SUM0 SENBL CIN0 CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7
HSP43891 Pinout
(Continued) LEAD MQFP VIEW
DCM1 SUM24 SUM23 SUM22 SUM21 SUM20 SUM19 SUM18 SUM17 SUM16 SUM15 SUM14 SUM13 SUM12 SUM11 SUM10 SUM9 SUM8 SUM7 SUM6 SUM5 SUM4 SUM3 SUM2 SUM1 SUM0 SENBL CIN0 CIN1 CIN2 CIN3 CIN4 CIN5 COUT4 COUT5 COUT6 COUT7 COUT8 COENB ERASE RESET DIENB DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 CIENB CIN8 CIN7 CIN6
SENBH ADDR0 ADDR1 DCM0 ADDR2 SHADD COUT0 COUT1 COUT2 COUT3
SUM25
HSP43891 Description
SYMBOL NUMBER A10, F10, A11, F11, A5-8, B5-7, TYPE power supply input. NAME FUNCTION
Power supply ground input.
DIN0-8
input provides system sample clock. maximum clock frequency 30MHz. These nine inputs data sample input bus. Nine-bit data samples synchronously loaded through these pins register each filter cell simultaneously. DIENB signal enables loading, which synchronous rising edge clock signal. data samples either 9-bit two's complement 8-bit unsigned values. 9-bit two's complement values, DIN8 sign bit. 8-bit unsigned values, DIN8 must held logical zero.
DIENB
this input enables data sample input (DIN0-8) filter cells. rising edge signal occurring while DIENB will load register every filter cell with 9-bit value present DIN0-8. high this input forces bits data sample input zero; rising edge when DIENB high will load register every filter cell with zeros. This signal latched inside device, delaying effect clock internal device. Therefore must during clock cycle immediately preceding presentation desired data DIN0-8 inputs. Detailed operation shown later timing diagrams. These nine inputs used input 9-bit coefficients. coefficients synchronously loaded into register filter CELL0 rising edge occurs while CIENB low. CIENB signal delayed clock discussed below. coefficients either 9-bit two's complement 8-bit unsigned values. 9-bit two's complement values, CIN8 sign bit. 8-bit unsigned values, CIN8 must held logical zero.
CIN0-8
B9-11, C10, C11, D10,
ALIGN CIENB
Used aligning chip socket printed circuit board. This must left connect circuit. this input enables register every filter cell (decimation) registers every filter cell according state DCM0-1 inputs. rising edge signal occurring while CIENB will load register appropriate registers with coefficient data present their inputs. This provides mechanism shifting coefficients from cell cell through device. high this input freezes contents register registers, ignoring signal. This signal latched delayed clock internal Therefore must during clock cycle immediately preceding presentation desired coefficient CIN0-8 inputs. Detailed operation shown later timing diagrams. These nine three-state outputs used output 9-bit coefficients from filter CELL7. These outputs enabled COENB signal low. These outputs tied CIN0-8 inputs same recirculate coefficients, they tied CIN0-8 inputs another cascade longer filter lengths. COENB input enables COUT0-8 outputs. high this input places these outputs their high impedance state. These inputs determine internal decimation registers follows: DCM1 DCM0 DECIMATION FUNCTION Decimation registers used decimation register used decimation registers used Three decimation registers used
COUT0-8
COENB DCM0-1
coefficients pass from cell cell rate determined number decimation registers used. When decimation registers used, coefficients move from cell cell each clock. When decimation register used, coefficients move from cell cell every other clock, etc. These signals latched delayed clock internal device.
HSP43891 Description
SYMBOL SUM0-25 (Continued)
NUMBER G9-G11, H10, H11, J5-J7, J10, K7-K11, L2-L6, L10,
TYPE
NAME FUNCTION These three-state outputs used output results internal filter cell computations. Individual filter cell results result shift output stage output. individual filter cell result output, ADR0-2 signals select filter cell result. SHADD signal determines whether selected filter cell result output stage adder result output. signals SENBH SENBL enable most significant least significant bits SUM0-25 result respectively. Both SENBH SENBL enabled simultaneously system 26-bit larger bus. However individual enables provided facilitate with 16-bit bus. this input enables result bits SUM16-25. high this input places these bits their high impedance state. this input enables result bits SUM0-15. high this input places these bits their high impedance state. These three inputs select cell whose accumulator will read through output (SUM025) added output stage accumulator. They also determine which accumulator will cleared when ERASE low. These inputs latched delayed clock internal device. ADR0-2 remains same address more than clock, output SUM0-25 will change reflect subsequent accumulator updates addressed cell. Only result available during first clock, when ADR0-2 selects cell, will output. This does hinder normal operation since ADR0-2 lines changed sequentially. This feature facilitates interface with slow memories where output required fixed more than clock. SHADD input controls activation shift operation output stage. This signal latched chip delayed clock internal device. Detailed explanation given Output Stage section. this input synchronously clears internal registers, except cell accumulators used with ERASE also clear accumulators simultaneously. This signal latched delayed clock internal device. this input synchronously clears cell accumulator selected ADR0-2 signals. RESET also simultaneously, cell accumulators cleared.
SENBH SENBL ADR0-2
SHADD
RESET
ERASE
Functional Description
Digital Filter Processor (DF) composed eight filter cells cascaded together output stage combining selecting filter cell outputs (See Block Diagram). Each filter cell contains multiplier-accumulator several registers (Figure Each 9-bit coefficient multiplied 9-bit data sample, with result added 26-bit accumulator contents. coefficient output each cell cascaded coefficient input next cell right.
Filter Cell
9-bit coefficient (CIN0-8) enters each cell through register left exits cell right signals COUT0-8. With decimation, coefficient moves directly from register output, valid clock following entrance. When decimation selected coefficient exit delayed clocks passing through more decimation registers (D1, D3). combination registers through which coefficient passes determined state DCM0 DCM1. output signals (COUT0-8) connected CIN0-8 inputs next cell right. COENB input signal enables COUT0-8 outputs right most cell COUT0-8 pins device.
registers enabled loading CIENB. Loading synchronous with when CIENB low. Note that CIENB latched internally. enables register loading after next following onset CIENB low. Actual loading occurs second following onset CIENB low. Therefore CIENB must during clock cycle immediately preceding presentation coefficient CIN0-8 inputs. most basic operations, CIENB will throughout process, this latching delay sequence only important during initialization phase. When CIENB high, coefficients frozen. registers cleared synchronously under control RESET, which latched delayed exactly like CIENB. output register (C0-8) input multiplier. other input multiplier comes from output register. This register loaded with data sample from device input signals DIN0-8 discussed above. register enabled loading DIENB. Loading synchronous with when DIENB low. Note that DIENB latched internally. enables register loading after next following onset DIENB low. Actual loading occurs second following onset
HSP43891
DIENB low; therefore, DIENB must during clock cycle immediately preceding presentation data sample DIN0-8 inputs. most basic operations, DIENB will throughout process, this latching delay sequence only important during initialization phase. When DIENB high, register loaded with zeros. multiplier pipelined modeled multiplier core followed pipeline registers, MREG0 MREG1 (Figure multiplier output sign extended input operand 26-bit adder. other adder operand output 26-bit accumulator. adder output loaded synchronously into both accumulator TREG. TREG loading disabled cell select signal, CELLn, where cell number. cell select decoded from ADR0-2 signals generate TREG load enable. cell select inverted applied load enable TREG. Operation such that TREG loaded whenever cell selected. Therefore, TREG loaded every clock except clock following cell selection. purpose TREG hold result sum-of-products calculation during clock when accumulator cleared prepare next sum-of-products calculation. This allows continuous accumulation without wasting clocks. accumulator loaded with adder output every clock unless cleared. cleared synchronously ways. When RESET ERASE both low, accumulator cleared along with other registers device. Since ERASE RESET latched delayed clock internally, clearing occurs second following onset both ERASE RESET low. second accumulator clearing mechanism clears single accumulator selected cell. cell select signal, CELLn, decoded from ADR0-2 ERASE signal enable clearing accumulator next CLK. ERASE RESET signals clear internal registers states follows:
ERASE RESET CLEARING EFFECT clearing occurs, internal state remains same. RESET only active, registers except accumulators cleared, including internal pipeline registers. ERASE only active, accumulator whose address given ADR0-2 inputs cleared. Both RESET ERASE active, accumulators well other registers cleared.
Output Stage
output stage consists 26-bit adder, 26-bit register, feedback multiplexer from register adder, output multiplexer 26-bit three-state driver stage (Figure 26-bit output adder filter cell accumulator result most significant bits output buffer. This result stored back output buffer. This operation takes place clock period. eight LSBs output buffer lost. filter cell accumulator selected ADR0-2 inputs. MSBs output buffer actually pass through zero their output adder input. zero controlled SHADD input signal selects either output buffer MSBs zeros adder input. SHADD input selects zero. high SHADD input selects output buffer MSBs, thus, activating shift-and-add operation. SHADD signal latched delayed clock internally.
HSP43891
DCM1.D DCM0.D RESET.D CIENB.D CIN0-8 D0-8 RESET.D DIENB.D DIN0-8 X0-8 MULTIX PLIER CORE P0-17 C0-8 COUT0-8 COENB THREE-STATE BUFFERS CELL ONLY
C0-8
MREG0 RESET.D LATCHES DCM1 DCM0 RESET DIENB CIENB ADR0 ADR1 ADR2 ERASE DCM1.D DCM0.D RESET.D DIENB.D CIENB.D ADR0.D ADR1.D ADR2.D ERASE.D ADDER ACC0-25 ACC.D0-25 0-17 SIGN EXTENSION MREG1
ERASE.D
CELLn ADR0 ADR1 ADR2 DECODER CELL CELL
CELL CELLn
AOUT0-25
FIGURE HSP43891 FILTER CELL
HSP43891
CELL RESULTS
ADR0.D ADR2.D
CELL RESULT 0-18
SUM0-25 output controlled SENBH SENBL signals. SENBL enables bits SUM0-15. SENBH enables bits SUM16-25. Thus, bits output simultaneously external system 26-bit larger bus. external system only bits, bits enabled groups bits (sign extended).
SIGN 18-25 (LSBs) 0-17
Arithmetic
RESET.D
SHADD
SHADD.D
ZERO
OUTPUT BUFFER
RESET.D
0-17
8-25
Both data samples coefficients represented either 8-bit unsigned 9-bit two's complement numbers. multiplier each cell expects 9-bit two's complement operands. binary format 8-bit two's complement shown below. Note that most significant sign held logical zero, 9-bit two's complement multiplier multiply 8-bit unsigned operands. Only upper (positive) half two's complement binary range used. multiplier output bits accumulator bits. accumulator width determines maximum possible number terms products without overflow. maximum number terms depends also number system distribution coefficient data values. Then maximum numbers terms products are:
MAXIMUM TERMS NUMBER SYSTEM Unsigned Vectors Two's Complement Vectors 8-BIT 1032 9-BIT
MSBs SHIFTED BITS RIGHT
RESET.D
OUTPUT
SENBL SENBH
3-STATE BUFFER
SUM0-25
Positive Vectors Negative Vectors Positive Negative Vector Unsigned 8-Bit Vector Two's Complement Vector Positive Two's Complement Vector Negative Two's Complement Vector
2080 2047 2064
1032 1024 1028
FIGURE HSP43891 OUTPUT STAGE
least significant bits (LSBs) from either cell accumulator output buffer output SUM0-25 bus. output determines whether cell accumulator selected ADR0-2 output buffer output bus. This controlled SHADD input signal. Control based state SHADD during successive clocks; other words, output selection contains memory. SHADD during clock cycle during previous clock, output selects contents filter cell accumulator addressed ADR0-2. Otherwise output selects contents output buffer. ADR0-2 lines remain same address more than clock, output SUM0-25 will change reflect subsequent accumulator updates addressed cell. Only result available during first clock when ADR0-2 selects cell will output. This does hinder normal operation since ADR0-2 lines changed sequentially. This feature facilitates interface with slow memories where output required fixed more than clock.
1036 1028
1032 1028
practical filters, coefficients never near maximum value, even larger vectors possible practice.
Basic Operation
simple, 30MHz 8-tap filter example serves illustrate more clearly operation sequence table (Table shows results multiply accumulate each cell after each clock. coefficient sequence, enters left moves from left right through cells. data sample sequence, enters from top, with each cell receiving same sample simultaneously. Each cell accumulates products output point. Eight sums products calculated simultaneously, staggered time that output available every system clock.
HSP43891
TABLE HSP43891 30MHz, 8-TAP FILTER SEQUENCE
HSP43891 Y15,
CELL
CELL
CELL
CELL
CELL
CELL
CELL
CELL
SUM/CLR Cell (Y7) Cell (Y8) Cell (Y9) Cell (Y10) Cell (Y11) Cell (Y12) Cell (Y13) Cell (Y14) Cell (Y15)
SAMPLE DATA (XN) 30MHz CLOCK 3-BIT COUNTER
ADR2 ADR1 ADR0 SHADD SENBH SENBL DIN0-8 DIENB SUM0-25
(YN)
HSP43891
D0-D8 COEFF. RAM/ROM
CIN0-8 COUT0-8
CIENB DCM1 DCM0 RESET ERASE COENB
SYSTEM RESET ERASE
FIGURE HSP43891 30MHz, 8-TAP FILTER APPLICATION SCHEMATIC
HSP43891
Detailed operation perform basic 8-tap, 9-bit coefficient, 9-bit data, 30MHz filter best understood observing schematic (Figure timing diagram (Figure internal pipeline length four clock cycles, corresponding register levels CREG XREG), MREG0, MREG1, TREG (Figures Therefore, delay from presentation data coefficients DIN0-8 CIN0-8 inputs appearing SUM0-25 output where filter
RESET ERASE DIN0-8 DIENB CIN0-8 CIENB ADR0-2 SUM0-25 SHADD SENBL SENBH DCM0-1
length internal pipeline delay After pipeline filled, output sample available every clock. delay last sample output from last sample input output sums, shown timing diagram derived from sum-of-products equation.
FIGURE HSP43891 30MHz, 8-TAP FILTER TIMING
SAMPLE DATA (XN) 30MHz CLOCK
ADR1 ADR0 DIN0-8 DIENB ADR2 SHADD SENBL SENBH SUM0-25 ADR1 ADR0 DIN0-8 DIENB ADR2
SHADD SENBL SENBH SUM0-25
4-BIT RESET 9x16 COEFF RAM/ROM D0-D8
HSP43891
HSP43891
CIN0-8 COUT0-8 DCM1 RESET DCM0 CIENB ERASE COENB
CIN0-8 COUT0-8 DCM1 RESET DCM0 CIENB ERASE COENB
SYSTEM RESET
(YN)
FIGURE HSP43891 30MHz, 16-TAP FILTER CASCADE APPLICATION SCHEMATIC
HSP43891 Extended Filter Length Filter
lengths greater that eight taps created either cascading together multiple devices "reusing" single device. Using multiple devices, filter over 1000 taps constructed operate 30MHz sample rate. Using single device clocked 30MHz, filter over taps constructed operate less than 30MHz sample rate. Combinations these techniques also possible.
Cascade Configuration
design filter length L>8, cascaded connecting COUT0-8 outputs (i)th CIN08 inputs (i+1)th DIN0-8fs inputs SUM0-25 outputs also tied together. specific example cascaded illustrates technique (Figure Timing (Figure similar simple 8-tap FIR, except ERASE SENBL/SENBH signals must enabled independently order clear correct accumulators enable SUM0-25 output signals proper times.
TABLE
DATA SEQUENCE INPUT COEFFICIENT SEQUENCE INPUT C14, C15, C14, HSP43891 Y23, Y15,
CELL +C14 +C13 +C12 +C11 +C10 +C14
CELL
CELL
CELL +C14 +C13 +C12 +C11 +C10
CELL
CELL
CELL
CELL +C14 +C13 +C12 +C11 +C10 +C14 +C13 +C12 +C11 +C10
SUM/CLR Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell Cell
+C15
HSP43891 Single Configuration
Using single filter length constructed processing passes, illustrated Table 16-tap FIR. Each pass composed cycles computes eight output samples. pass sample with indices +(L-1) enter DIN0-8 inputs. coefficients enter CIN0-8 inputs, followed seven zeros. these zeros entered, result samples output accumulators reset. Initial filing pipeline shown this sequence table. Filter outputs through FIFO even sample rate.
Decimation/Resampling
HSP43891 provides mechanism decimating factors From filter cell block diagram (Figure note three registers multiplexers coefficient path through cell. These allow coefficients delayed clocks through cell. sequence table (Table decimate-by-two filter illustrates technique (internal cell pipelining ignored simplicity). Detailed timing 30MHz input sample rate, 15MHz output sample rate (i.e., decimate-by-two), 16-tap filter, including pipelining, shown Figure This filter requires only single HSP43891
Extended Coefficient Data Sample Word Size
sample coefficient word size extended utilizing several parallel maximum sample rate single with resulting lower sample rates. technique compute partial products combine these partial products shifting adding obtain final result. shifting adding accomplished with external adders full speed) with DF's shift-and-add mechanism contained output stage reduced speed).
RESET ERASE ERASE
FIGURE HSP43891 16-TAP 30MHz FILTER TIMING USING CASCADED HSP43891s
DIN0-8
CIN0-8 CIENB ADR0-2 SUM0-25 SUM0-25 SHADD SENBL/H SENBL/H DCM0-1
HSP43891
HSP43891
TABLE HSP43891 16-TAP DECIMATE-BY-TWO FILTER SEQUENCE; 30MHz 15MHz
DATA SEQUENCE INPUT COEFFICIENT SEQUENCE INPUT C15, C13, C14, HSP43891 Y19, ,Y17,
CELL +C14 +C13 +C12 +C11 +C10
CELL +C14 +C13 +C12 +C11 +C10
CELL +C14 +C13 +C12 +C11 +C10
CELL +C11 +C10 +C14 +C13 +C12 +C11 +C10
CELL +C14
CELL +C14 +C13 +C12 +C11 +C10 +C15 +C14 +C13 +C12 +C11 +C10
CELL
CELL +C14 +C13 +C12 +C11 +C10 +C14
SUM/CLR Cell0 (Y15) Cell1 (Y17) Cell2 (Y19) Cell3 (Y21) Cell4 (Y23) Cell5 (Y25) Cell6 (Y27) Cell7 (Y29) Cell8 (Y31)
RESET
ERASE
DIN0-8 DIENB CIN0-8 CIENB ADR0-2 SUM0-25 SHADD SENBL SENBH DCM0-1
HSP43891
FIGURE HSP43891 16-TAP DECIMATE-BY-TWO FILTER TIMING; 30MHz 15MHz
HSP43891
Absolute Maximum Ratings
Maximum Supply Voltage +8.0V Input, Output Voltage .GND -0.5V +0.5V Maximum Storage Temperature -65oC 150oC Class Junction Temperature PLCC .150oC CPGA .175oC Maximum Lead Temperature (Soldering 10s) .300oC
Thermal Information
Thermal Resistance (Typical, Note oC/W)JC oC/W) MQFP Package PLCC Package. CPGA Package 34.66 7.78 Typical Package Power Dissipation 70oC MQFP Package .1.7W PLCC Package. .2.2W CPGA Package 2.88W Gate Count 17763 (PLCC MQFP Lead Tips Only)
Operating Conditions
Voltage Range Temperature Range. 70oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER Power Supply Current Standby Power Supply Current Input Leakage Current Output Leakage Current Logical Input Voltage Logical Zero Input Voltage Logical Output Voltage Logical Zero Output Voltage Clock Input High Clock Input Input Capacitance PLCC CPGA Output Capacitance PLCC CPGA NOTES: Operating supply current proportional frequency. Typical rating 7mA/MHz. Controlled design process parameters directly tested. Characterized upon initial design after major process and/or design changes. Output load test load circuit 40pF. COUT SYMBOL ICCOP ICCSB VIHC TEST CONDITIONS Max, Frequency 20MHz (Notes (Note Max, Input Max, Input -400µA, 2mA, Frequency 1MHz measurements referenced GND, 25oC (Note UNITS
HSP43891
Electrical Specifications
±5%, 70oC TEST CONDITIONS (20MHz) Note Note Note (25.6MHz) (30MHz) UNITS
PARAMETER Clock Period Clock Clock High Input Setup Input Hold Coefficient Output Delay Output Enable Delay Output Disable Delay Output Delay Output Rise Output Fall NOTE:
SYMBOL tODC tOED tODD tODS
Controlled design process parameters directly tested. Characterized upon initial design after major process and/or design changes.
Test Load Circuit
(NOTE) INCLUDES STRAY CAPACITANCE EQUIVALENT CIRCUIT
1.5V
NOTE: Switch Open ICCSB ICCOP Tests.
HSP43891 Waveforms
2.0V 2.0V 2.0V 2.0V 3.0V INPUT 0.0V 1.5V 1.5V
4.0V 0.0V
NOTE: Input includes:DIN0-7, CIN0-7, DIENB, CIENB, ERASE, RESET, DCM0-1, ADR0-1, TCS, TCCI, SHADD FIGURE CLOCK PARAMETERS FIGURE INPUT SETUP HOLD
2.0V tODC, tODS SUM0-25 COUT0-8
1.5V OUTPUT
FIGURE SUM0-25, COUT0-8, OUTPUT DELAYS
FIGURE RISE FALL TIMES
ENABLE
1.5V
1.5V
3.0V INPUT 0.0V tODD
1.5V
DEVICE UNDER TEST
1.5V
tOED 1.7V OUTPUT 1.5V 1.3V
NOTE: Testing: Inputs driven 3.0V Logic 0.0V Logic "0". Input output timing measurements made 1.5V both Logic "0". driven 4.0V measured 2.0V. FIGURE TESTING INPUT, OUTPUT WAVEFORM
FIGURE OUTPUT ENABLE, DISABLE TIMING
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FN2785.5 Digital Filter HSP43891 video-speed Digital Filter

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