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Am29F002B/Am29F002NB
following docu ment specifies Spansion products that offered both Advanced Micro Devices jitsu Although ment marked with company that originally developed specification, ducts will offered tomers both Fujitsu.
Continuity Specifications
There change datasheet result offer device Spansion produ changes that have been result normal datasheet provement noted docum revision mary, suppor ted. Future routine evisions will occur when appropriate, changes will noted revision
Continuity Ordering Part Numbers
Fujitsu continue upport existing mbers beginning with "Am" "MBM". order these products, please only rderin Part bers listed this document.
More Information
Please contac your local ales offic additional mation abou Span sion solutions.
Public atio Number 21527 evisio
Amendment Issue ovemb
PAGE INTENTIONALLY BLANK.
Am29F002B/Am29F002NB
Megabit (256 8-Bit) CMOS Volt-only Boot Sector Flash
DISTINCTIVE CHARACTERIST
ingle powe supply operation Volt-o rase, ogra ratio imizes system level ireme 0.32 proce echnology patibl with 9F00 device High rform ance times powe umption alues MHz) curr rase Flexible Kbyte, byte byte, thre byte full chip erase ecto tecti featur ckin sector erase ration withi sector Sectors locked programming uipme Temp Unpr otect llows code previo usly locked sectors bottom boot block configura tions availa dded Algorithms autom atically rams entire mbin ation esign ated sector ogra orith utoma ites ifies data cifi Minimum ,000 cycle guara ntee tent liab life system option PDIP patibility with JEDE ftwar with gle-po supp dver write otection Polling toggle rovid softwa metho dete ctin rase pera tion comp letio rase Suspe nd/E uspe data sector rase resu eratio rese rdwa metho rese device rray availa Am29 2NB)
Website ww.amd.c latest inform ation.
GENERAL DESCRIPTION
memo evices nized ,144 9F00 nctio offe PDIP ackag device esig mmed system with stand system supp uire vice ramme stand mmers. MD's rocess techn offe featur fits 9F00 which using roce techn ffer times owin icro cesso pera witho wait tes. elimi nate ntion nabl ntro ingle upply ncti rated volta rovide rogr ration device rely mmand comp atible with single-pow supply Flas andard. Comm stan micro cesso ming ister chin rite cycles nter latch resse ratio device simil other device Device rammi ting rogra nter time rogr veri cell rgin rase rithm- orith that autom atic efor cutin evice auto matically times ulse ifies marg syste rase ratio plete llin ggle After rase cycle comp leted evice rray data accept other mman erase archite cture llows sectors rased ramme with affe ctin rase when factor Hardw data prot ection sure inclu ctor utoma tically hibits write opera tions nsiti hardw prot tion featur bles ogram eration mbination ctors memor This chieved progra mmin uipment. uspe rase time from, data ctor that lected rasu ckgr ieved. mina ratio ress sets mach rray data system circui syste rese eset evice, abli system microp roce ot-up firm from Flash memo This ture avail able m29F0 NB.) system place device into standby mode Power tion grea duced this mode. ighe levels lity, relia bility cost effectiven ess. vice ctrica ases mmed lectron njectio
F002 B/Am
TABLE CONTENTS
roduc elec uide Block Diagram Connec tion Diagram Configura tion. Logic mbol ring vice perations
Table Am29F002B/Am29F 002NB Device Oper ations
Requirement Reading Array riting Commands/Command Sequences Program rase Operat andby Mode RESE Hardware Reset Output Disable Mode Table Am29F002B/Am29F002NB Boot Block Sector Address Table Table Am29F002B/Am29F002NB Bottom Boot Block Sector Address Table Autoselect Mode Table Am29F002B/Am29F002NB Autoselect Codes (High Voltage Method) Sector rotection/Unprotection Temporary Sect Unprotect Figure Temporary Sector Unprotect Operation Hardware Data Protection Write Inhibit Write Pulse "Glitch" Protection Logical Inhibit Power-Up Write Inhibit finitions Reading Array Reset Command Autoselect Command equence rogram Command Sequence Figure Program Operation Chip Erase Command Sequence Sector rase Command Sequence Figure Erase Operation Erase Suspend/ Erase Resume Commands Command Definit ions Table Am29F002B/Am29F002NB Command Definitions Write peration DQ7: Data# olling
Figure Data# Polling Algorithm DQ6: Toggle DQ2: Toggle Reading Toggle Bits DQ6/DQ2 DQ5: Exceeded Timing Limit DQ3: Sector rase Timer Figure Toggle Algorithm Table Write Operation Status olut Maxim ings Figure Maximum Negative Overshoot Waveform Figure Maximum Positive Overshoot Waveform perat Range Chara rist Conditions Figure Test Setup Table Test Specifications ching form Chara rist Figure Read Operations Timings Figure RESET# Timings Figure Program Operation Timings Figure Chip/Sector Erase Operation Timings Figure Data# Polling Timings (During Embedded Algorithms) Figure Toggle Timings (During Embedded Algorithms) Figure Figure Temporary Sector Unprotect Timing Diagram (Am29F002B only) Figure Alternate Controlled Write Operation Timings rase rogra erforma tchup Charac teristics pacita Capac ance tention ensions 032-32-P Plastic 032-32-Pin Plastic Leaded Chip Carrier 032-32-P andard Thin mall ackage vision Revision (July 1998) Revision (January 1999) Revision (November 1999) Revision (November 2000)
F002 B/Am
PRODUCT SELECT GUIDE
Speed Option acces time, cess time, acces time, -120 29F002B m29F002NB
Characteristics page full spec ifications.
F002 B/Am
BLOCK DIAGRAM
-DQ7 RESET
Switches Eras Voltage Generator Input/Output Buffers
State Control Command Register
Voltage Generator Chip Enable Output Enable Logic Latch
Addres Latch
ecoder
Y-Gating
Detec
X-Decoder
Cell Matrix
A0-A17
CONNECTION DIAG RAMS
RESET#
PDIP
RESET#
RESET#
Standar
CONFIGURATION
utpu able utpu able ilab rating oltag toler nter
OGIC SYMBOL
A0-A17 DQ0-DQ7
RESET
ORDERING INFORMATION Standard Product
(Valid ation form inatio ents low. 002B 29F002N
TEMPERATURE RANGE Commerc (0°C +70°C) Commerc (0°C +70°C) Pb-free Package Extended (-55 +125° Industrial (--0°C Pb-free Package Industrial (-40 +85° Extended (-55 +125° Pb-free Package
PACKAGE TYPE 32-Pin Plastic 032) 32-Pin Rectangular Plastic Leaded Chip arrier 032) 32-Pin Thin Small Outline Package (TSOP) Standard Pinout 032) SPEED OPTION Product Selector Guide Valid Combinations BOOT CODE SECTOR ARCHITECTURE sector Bottom sector DEVICE NUMBER/DESCRIPTION Am29F002B/Am29F002NB Megabit (256 8-Bit) CMOS lash Memory Volt-only Program Erase
Valid ation 29F002BT-55 29F002BB-55 29F002NBT-55 29F002NBB-55 29F002BT-70 29F002BB-70 29F002NBT-70 29F002NBB-70 29F002BT-90 29F002BB-90 29F002NBT-90 29F002NBB-90 29F002BT-120 29F002BB-120 29F002NBT-120 29F002NBB-120
Voltage
Valid inations Valid ombinations onfigurations planned supported volume this ice. Consult local sales office confirm availability ific alid binations check newly releas combinations.
DEVICE OPERATIONS
tion uire itiated thro ter. able ation ster latc tore ation tate utpu tate uire ultin outp ation etail
evice RESET# m29F 002NB
Operatio Read Write Standby Standby Output Disable (n/a Am29F002N Temporary nprotec (See Note)
A0-A17
DQ0-DQ7 High-Z High-Z High-Z High-Z
end:
Logic VIL, Logic High VIH, 12.0 Don't Care, Data DOUT Data Out, Address
sections Sector Group Protection Temporary Sector Unprotect more information. This function requires RESET# therefore available Am29F002NB device.
Requirem ents Reading Array Data
rray utputs trol rray tern arra -up, after ata. tand alid ntil ata" infor rati iagr eform tion adin ata.
ration tor, ultip tire ctor ique tor. efinitio etail g/res ration nters nter rate rray utos Autos ntain diag rite
gram Erase Operation Status Writing Comm ands/Co mmand Sequ ences
rogr data tatu adin tatus Stan tion
tion teri stic agra
RESET#: Hardware Reset
thod ettin rray ata. atio data outp atte arra ata. that itia tegr ity. ters tied itry. ling ot-up from eter
Standby Mode
adin rren ptio atly utputs plac tate, nters tric olta uire ithe efore ata. in." cted gram pera tion leted tand ific ation
Disable Mode
outp from utpu tate.
Secto
Secto Size (Kbytes) dress ange hexadecim 00000h-0F 10000h-1F 20000h-2F 30000h-37FFF 38000h-39FFF 3A000h-3BFFFh 3C000h-3F FFFh
Secto
Secto Size (Kbytes) dress ange hexadecim 00000h-03FFF 04000h-05FFF 06000h-07FFF 08000h-0F 10000h-1F 20000h-2F 30000h-3F
Autoselect Mode
ntific ation rotec rific atio tifi tend rogr utom gram elec thro ter. ethod tabl dition rify otec tion iate its. ding Table finition tabl that gram ntifier ster, efin itio ble. uire efini etails autos
elec ltag
escription Manufacturer Devic Am29F002B/Am29F002NB (Top Boot Block Devic Am29F002B/Am29F002NB (Bottom Boot Block)
(protec ted) Sector Protec tion Verification (unprotec ted)
Logic Logic High Sector Address, Don't care.
Sector Protection/Un protection
atur bles rogr ratio
tion otec nted ires etail ontac entativ tain offers ption rotec ting ethe rotec rote cted "Autos etails
Hardware Data Protection
rten efin ition llow rote ctio enta -dow ition egis ntern gram uits able ntil ntro nten ites rite Glitch puls than initia rite rite ding rite ring rray
Tempo rary Secto Unprotect
refore ilab rote cted data ttin ting otec gain lgor ithm this ature
STAR
ESET (Note
Perform Erase Program Operations
RESET#
emporary Sector nprotec pleted (Note
Notes:
protected sectors unprotected. previously protected sectors protected once again.
COMMAND DEFINITIONS
into nitia pera tions efinitio table alid riting ata. latc llin latc efer cter until ration lete. auto must itten ding utos
Read Array Data
atic rray fter orith fter epts tatu ata. Afte leting ratio rray ption atio this and." aram eters gram iagra
select Sequence
nufac ture ethe itio ethod ative etho inten uire ritin itho itia noth etriev ture retur etur that bles rite utos rray data.
Byte Program mand Sequence
nitiate itte rithm rthe ntrol atic ally prov nter nall nera gram rify nition irem ithm lete, eter tatus gram eratio
Reset mmand
rray ata. lete. gram
ation Status ation thes tatus bits nates rein itiate retur rray data, ntegr ity. llow Atte ptin ata# ation
llow et-up itiona rite llow invo rith ithm auto atic ally rifies tter ratio finition table uire ents nly, ation iately initia rray integ rity. dete ratio tatus its. rithm lete, etur rray latc
START
Write Program Command Sequence
Embedded Program algorithm progress
Data Poll from System
illu ates e/Pro tabl eter ip/Se ration efor
Sector Erase Sequence
ratio itia itin rite follo eras ithm utom rifies ctor atter tric itte ritte adin buffe from tors ditio othe terr pted
Verify Data?
Increment Address
Last Address?
Programming Completed
appropriate Command Definitions table program command sequence.
Chip Erase Command uence
eras itiate
able tten nitor deter ctor r.") fina ratio othe nly, that grity. ithm tatus rite ation tatus infor ation tatus bits llus rith ration efer e/Pr ogra ration tabl ration
START
Write Erase Command Sequence
Data Poll from System
Embedded Erase algorithm progress
Data FFh?
Erasure Completed
otes:
appropriate Command Definitions table erase command sequence. DQ3: Secto more information.
Erase Suspen d/Erase Resume Comm ands
ration ctor ritten ation ogra lgor n't- riti ritten ring ritten out, term nate pera tion. fter eras re.) rite defin ply.
eter ration atio gram tion lete, stem rray ithi tatus tatus gram tatu atio tore rray. autos infor ation ontinu rthe ites othe
Command Definitions
efin ition ycles Cycles (Notes 2-4) First (SA) Second Third Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
mand Sequence (Note Read (Note Reset Note Manufac turer Autoselect (Note Devic Boot Block Devic Bottom Boot Block Sector Protect Verify (Note Program Chip Erase Sector Eras Erase pend (Note Erase Resume (Note
Legend
Don't care Address memory location read. Data read from location during read operation. Address memory location programmed. Addresses latch falling edge pulse, whichever happens later.
Notes:
Data programmed location Data latches rising edge pulse, whichever happens first. Address sector verified autoselect mode) erased. Address bits A17-A13 uniquely select sector.
Table description operations. values hexadecimal. Except when reading array autoselect data, cycles write operations. Address bits A17-A11 don't cares unlock command cycles, except when required. unlock command cycles required when reading array data. Reset command required return reading array data when device autoselect mode, goes high (while device providing status data).
fourth cycle autoselect command sequence read cycle. data unprotected sector protected sector. "Autoselect Command Sequence" more information. system read program non-erasing sectors, enter autoselect mode, when Erase Suspend mode. Erase Suspend command valid only during sector erase operation. Erase Resume command valid only during Erase Suspend mode.
WRITE OPERATION STATUS
tatus ation tion tions bits ffer pera tion lete bits utpu ata# llin ata# llin
START
DQ7: Data# Polling
ether rithm Polli alid gram rithm rogr rithm utpu atum atio ogra fall ithin ately rray data. rithm ata# ling lgor ithm ata# llin ent/tr datu ithm outp ithin tatu atio fter tten lling atel then ted, lgor ithm otec tors etec ata, llowi utpu arac trates
Read DQ7-DQ0 Addr
Data?
Read DQ7-DQ0 Addr
Data?
FAIL
otes:
PASS
Valid address programming. During sector erase operation, valid address address within sector selected erasure. During chip erase, valid address non-protected sector address. should rechecked even because change simultaneously with DQ5.
llin rith
DQ6: Togg
ethe ithm lete, hethe ntere alid afte pera tion) gle. ither ntrol ration lete, tops togg ling fter tten eras rotec ggle prox then eturn rotec ethe eterm heth (that rith glin deter Alter tion ata# ling ithi tor, ately itte rray data. plete. ration table outpu efer igur ggle lgor ithm figu iffe
tingu hethe ethe tors ation Table rith Togg lain 19." iffer betw
Reading Toggle Bits DQ6/DQ2
llow tatus eter lly, togg firs Afte togg ing, leted ation afte otes ethe dete ethe glin ggle topp glin ggli full eted tion. till pera tion lly, adin ata. eter togg ling lter nativ ely, erfor othe rithm etur dete pera tion (top
DQ2: Togg
"Togg ndic (tha lgor ithm rogr fter eith ntro
DQ5: Exceeded Limits
ndic hethe gram ifie ilur ates rogr ted.
itio trie ation that rogr atio dition its, both ditio ata.
START
Read DQ7-DQ0
DQ3: Sector Erase Timer
ritin eter tion tire lies fter dition antee than ctor fter itte lling ggle pted inter olle rthe othe than until ation lete. eras pted, follow ctor pted. Table
Read DQ7-DQ0
Toggle Toggle?
Read DQ7-DQ0 Twice
otes
Toggle Toggle?
Program/Erase Operation Complete, Write Reset Command
Notes:
Program/Erase Operation Complete
Read toggle twice determine whether toggling. text. Recheck toggle because stop toggling changes "1". text.
Oper ation Standard Mode Embedded Program Algorithm Embedded Eras Algor ithm eading ithin Eras Suspended Sector eading ithin Non-Eras Suspended Sector Erase-Suspend-Program
rite DQ7# Data DQ7# Toggle Toggle toggle Data Toggle (Note Data Data toggle Toggle Toggle
Erase Suspend Mode
tes:
require valid address when reading status information. Refer appropriate subsection ther details. switches when Embedded Program Embedded Erase operation exceeded maximum timing limits. "DQ5: Exceeded Timing Limits" page more information.
ABSOLUTE MAXIMUM RATINGS
ratur ature lied Voltag .-2.0 .-0.5 utpu -2.0 ative +0.8 -0.5
tes:
Minimum voltage input pins -0.5 During voltage transitions, input pins overshoot -2.0 periods Figure Maximum voltage input pins +0.5 During voltage transitions, input pins overshoot +2.0 periods Figure Minimum input voltage pins OE#, RESET# -0.5 During voltage transitions, OE#, RESET# overshoot -2.0 periods Figure Maximum input voltage +12.5 which overshoot +13.5 periods (RESET# available Am29F002NB) more than output shorted ground time. Duration short circuit should greater than second. Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this data sheet implied. Exposure device absolute maximum rating conditions extended periods affect device reliability.
+2.0 +0.5
vefo
OPERAT RANGES
vices ature vices ature ature ltag
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS TTL/NMOS patible
ameter ICC1 ICC2 ICC3 ICC4 Descriptio Input Load Current OE#, RESET# Input Load Current (Notes Output Leakage urrent Active Current (Notes Test itio OE#, RESET 12.5
±1.0 ±1.0
-0.5
12.5 0.45
Active Write urrent otes Standby Current (Note urrent (Notes Input Voltage Input High Voltage Voltage Autos elec Temporary Sector Unprotect Output Voltage Output High Voltage Lock -Out Voltage CE#, RESET#
11.5
-2.5
tes:
RESET# available Am29F002NB. Maximum specifications tested with current listed typically less than mA/MHz, with active while Embedded Erase Embedded Program progress. 100% tested.
CHARACTERISTICS CMOS Compatible
ameter Output High Voltage Lock-Out Voltage -100
escr iption Input Load Current OE#, RESET# Input Load Current otes Output Leak Current tive Current (Notes tive rite urrent (Notes Standby Current (Notes Reset Current (Notes Input Voltage Input High Voltage Voltage Autoselect porary Sector Unprotect Output Voltage
Test ditions OE#, RESET# 12.5 ESET#
±1.0 ±1.0
-0.5
12.5 0.45
11.5
-2.5
0.85 -0.4
tes:
RESET# available Am29F002NB. Maximum specifications tested with current listed typically less than mA/MHz, with active while Embedded Erase Embedded Program progress. 100% tested. extended temperature (>+85°
TEST CONDITIONS
Test itio Under Test Input Fall Input Pulse Levels Input timing measurement reference levels 0.0-3.0 0.45-2.4 0.8, Output Load Output Load Capacitance, (including apacitance) gate others ific atio
Note: Diodes IN3064 equivalent
Output measurement reference levels 0.8,
SWITCHING WAVEFORMS
WAVEF INPUT Steady Changing from Changing from Don't are, hange mitted Does Apply Changing, State nown enter Line High pedance State OUTPUT
CHARACTERISTICS Read Operations
Param eter JEDEC Descr tion Read (Note Address Output elay Chip Enable Output Delay Output Enable Output Delay Chip Enable Output High (Note Output Enable Output High Output Enable Hold Time Read Toggle Data# Polling Test Setup Options -120 Unit
Output Hold From Addres ses, OE#, hever First (Note
tes:
100% tested. Table Figure test specifications.
Addresses tOEH HIGH Outputs RESET#
Am29F002NB
Addresses Stable tACC
HIGH Output Valid
atio
CHARACTERISTICS Hardware Reset (RESET
Param eter JEDEC escr iption ESET# (During Embedded Algorithms Read Write (See Note ESET# (NOT uring bedded Algorithms Read Write (See Note ESET# Puls Width ESET# High Before Read (See Note Test Setup Speed Optio
100% tested. RESET# available Am29F002NB.
CE#, RESET#
Am29F002NB
tReady
Reset Timings during Embedded Algorithms Reset Timings during Embedded Algorithms
RESET#
Am29F002NB
CHARACTERISTICS Erase/Program Operations
eter JEDEC Descr tion Write Time Address Setup Address Hold Data Setup Time Data Time Output Enable Setup Time Read Recovery Before Write (OE# Setup Hold Write Pulse Width Write Pulse Width Programming Operation (Note Erase Operation (Note Setup (Note Speed tion -120
tes:
100% tested. "Erase Programming Performance" page more information.
CHARACTERISTICS
Program Command Sequence (last cycles) Addresses 555h Data Status DOUT tWPH tWHWH1 Read Status Data (last cycles)
tVCS
otes:
program address, program data, true data program address.
atio
CHARACTERISTICS
Erase Command Sequence (last cycles) Addresses 2AAh
555h chip erase
Read Status Data
tWPH
tWHWH2
Data tVCS
tes:
Chip Erase
Progress
Complete
sector address (for Sector Erase), Valid Address reading status data ("see "Write Operation Status" page 18).
atio
CHARACTERISTICS
Addresses tACC tOEH
High
Complement
Complement
True
Valid Data
High
DQ0-DQ6
Status Data
Status Data
True
Valid Data
Note: Valid address. Illustration shows first status cycle after command sequence, last status read cycle, array data read cycle.
llin
Addresses tACC tOEH DQ6/DQ2
High
Valid Status (first read)
Valid Status (second read)
Valid Status (stops toggling)
Valid Data
Note: Valid address; required DQ6. Illustration shows first status cycle after command sequence, last status read
cycle, array data read cycle.
CHARACTERISTICS
Enter Embedded Erasing Eras Suspend Erase Enter Eras Suspend Program Erase Suspend Program Eras Resum Erase Suspend Read Eras Erase plete
Erase pend Read
Note: system toggle DQ6. toggles only when read address within
erase-suspended sector.
Tempo rary Secto Unprotect (Am29F002B only)
ameter Std. escription Rise Fall Time (See ote) ESET# Setup Time Temporary nprotec Speed tion
100% tested.
RESET# tVIDR Program Erase Command Sequence tVIDR
tRSP RY/BY#
CHARACTERISTICS Alternate Contro lled Erase/Program Operation
ameter JEDEC Descriptio Write (Note Addres Setup Time Addres Hold Time Data Setup Data Hold Output Enable Setup Read ecovery Time Before Write (OE# High Low) Setup Time Time Puls Width Puls Width Programm Operation Sector Eras Operation Speed Options -120 Unit
100% tested. "Erase Programming Performance" page more information.
CHARACTERISTICS
program erase program sector erase chip erase
Data# Polling
Addresses tGHEL tCPH Data
program erase program sector erase chip erase
tWHWH1
DQ7#
DOUT
RESET#
Notes:
Program Address, Program Data, DQ7# complement data written device, data itten device. Figure indicates last cycles command sequence.
lter atio
ERASE PROGRAMMING PERFORMANCE
ameter Sector Erase Time Chip Erase Byte Programming Chip Program ming Time (Note ents cludes programm prior erasure (Note cludes ystem level overhead (Note
tes:
Typical program erase times assume following conditions: 1,000,000 cycles. Additionally, programming typicals assume checkerboard patter Under worst case conditions 90°C, (4.75 devices), 1,000,000 cycles. typical chip programming time considerably less than maximum chip programming time listed, since most bytes program faster than maximum program times listed. pre-programming step Embedded Erase algorithm, bytes programmed before erasure. System-level overhead time required execute four-bus-cycle sequence program command. Table further information command definitions. device minimum guaranteed erase program cycle endurance 1,000,000 cycles.
LATCHUP CHARACTERIST
escr iption Input voltage with respect pins except pins (including OE#, RESET Input voltage with respect pins urrent -1.0 -1.0 -100 12.5 +100
Includes pins except Test conditions: time. RESET# available Am29F002NB.
TSOP CAPACITANCE
Param eter Param eter Descriptio Input apac itance Output Capacitance Control Capacitanc Test Setup
tes:
Sampled, 100% tested. Test conditions 25°C, MHz.
PLCC PDIP CAPACITANCE
Param eter ameter Description Input apacitanc Output Capacitanc ontrol Capacitanc Test itio
tes:
Sampled, 100% tested. Test conditions MHz.
DATA RETENTION
ameter Minimum Pattern Data Retention Time 125° Years Test itio 150° Unit Years
PHYSICAL DIMENSIONS 032-32-Pin Plastic
10/99
PHYSICAL DIMENSIONS (continued 032-32-Pin Plastic Leaded Chip Carrier
10/99
PHYSICAL DIMENSIONS (continued 032-32-Pin Standard Thin Package
10/99
REVISION SUMMARY Revision 1998)
Initia rist
ific ation
Revision (January 1999)
istin istic
Revision (November 1999)
istics leted efor ysic figu detai tration
ntion
iable ratio
HQZ: optio
from tics-
tWLA hange tion tDVWH hange peed option from tWLWH hange option
tics- lter tion
Revision (November 2000)
tabl nten atio leted n-in ption on't
tDVEH hang peed optio tELEH tion from tELAX hange peed option from
istics tible
Revision (Novem 2004)
atio Valid ption
tions
produc described this document designed, developed manufac tured ontemplated genera use, luding ithout limita tion, ordinar industrial use, genera offic use, persona use, usehold use, designed, developed manufac tured contemplated includes fatal risks ngers that, unless extremely fety ured, could have serious effec public, directly death, persona injur severe physica other loss i.e., lear ctio control nuclear cility, raft flight ntrol, traffic ntrol, mass transpor ontro medic life suppo stem, missile launc ontro weapon stem), where chanc ilure into lerable (i.e., submersible repea rtificial satellite). Please note that nsio will and/or third claims rising onnec tion vementioned uses produc semico nduc have inherent chanc failure. must protect ainst injury, loss from such failures orpora ting fety design measures into your cility equipment such redunda fire protec tion, prevention ver- current other rmal operating nditio products described this cument represent goods gies subject certain restrictio expor under Foreign Exchange oreig Japa Export Administration Regulations pplicable other ountry, prior uthoriza tion respec tive ernment entity will required export those products. arks opyrig 000-20 dvanced Micro evices, Inc. reserved. bina gistered Advan icro Devices, ExpressF lash nced Micro Devices, Prod this lication ntification purpo only arks resp ective comp anies.

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