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Appendix Die. requirements. timing measurement details table 03-0


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Appendix Die. requirements. timing measurement details table
03-04-23
Thomas Hess
Correct supply voltage designations from VCC. storage conditions paragraph 1.4. Revise figure show detail. Revise figure waveforms correctly show signal positions. Update boilerplate MIL-PRF-38535 requirements.
04-11-22
Thomas Hess
SHEET SHEET STATUS SHEETS
SHEET PREPARED
PMIC
Thanh Nguyen
STANDARD MICROCIRCUIT DRAWING
THIS DRAWING AVAILABLE DEPARTMENTS AGENCIES DEPARTMENT DEFENSE
CHECKED Thanh Nguyen APPROVED Charles Saffle DRAWING APPROVAL DATE 01-08-02 REVISION LEVEL SIZE
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http://www.dscc.dla.mil
MICROCIRCUIT, DIGITAL, 32-BIT SPARC PROCESSOR, MONOLITHIC SILICON
CAGE CODE
AMSC
SHEET
67268
5962-00540
DSCC FORM 2233
5962-E039-05
SCOPE Scope. This drawing documents product assurance class levels consisting high reliability (device classes space application (device class choice case outlines lead finishes available reflected Part Identifying Number (PIN). When available, choice Radiation Hardness Assurance (RHA) levels reflected PIN. PIN. shown following example: 5962 00540
Federal stock class designator
designator (see 1.2.1) Drawing number
Device type (see 1.2.2)
Device class designator (see 1.2.3)
Case outline (see 1.2.4)
Lead finish (see 1.2.5)
1.2.1 designator. Device classes marked devices meet MIL-PRF-38535 specified levels marked with appropriate designator. Device class marked devices meet MIL-PRF-38535, appendix specified levels marked with appropriate designator. dash indicates non-RHA device. 1.2.2 Device type(s). device type(s) identify circuit function follows: Device type Generic number TSC695F Circuit function 32-bit SPARC processor Frequency
1.2.3 Device class designator. device class designator single letter identifying product assurance level follows: Device class Device requirements documentation Vendor self-certification requirements MIL-STD-883 compliant, non-JAN class level microcircuits accordance with MIL-PRF-38535, appendix Certification qualification MIL-PRF-38535
1.2.4 Case outline(s). case outline(s) designated MIL-STD-1835 follows: Outline letter Descriptive designator figure Terminals Package style Ceramic quad flat package
1.2.5 Lead finish. lead finish specified MIL-PRF-38535 device classes MIL-PRF-38535, appendix device class
STANDARD MICROCIRCUIT DRAWING
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Absolute maximum ratings. Supply voltage range (VCC) Input voltage range (VIN) Output current (IOUT). Maximum power dissipation (continuous) (PD) Storage temperature range (TSTG). Lead temperature (soldering, seconds). Thermal resistance, junction-to-case (JC). Junction temperature (TJ). Recommended operating conditions. Operating supply voltage range (VCC). +4.5 +5.5 Case operating temperature range (TC) -55°C +125°C Storage conditions packaged devices 30°C, dust free, original packing Radiation features. Maximum total dose (dose rate rads (Si)/s). rads (Si) Single event phenomenon (SEP) effective linear energy threshold (LET) with upset error rate 1.5E-8 devices/day with latchup MeV-cm2/mg -0.5 +7.0 -0.5 +0.5 -65°C +150°C +265°C 3°C/W +165°C
APPLICABLE DOCUMENTS Government specification, standards, handbooks. following specification, standards, handbooks form part this drawing extent specified herein. Unless otherwise specified, issues these documents those cited solicitation contract. DEPARTMENT DEFENSE SPECIFICATION MIL-PRF-38535 Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines.
DEPARTMENT DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 List Standard Microcircuit Drawings. Standard Microcircuit Drawings.
(Copies these documents available online http://assist.daps.dla.mil from Standardization Document Order Desk, Robbins Avenue, Building Philadelphia, 19111-5094.)
Stresses above absolute maximum rating cause permanent damage device. Extended operation maximum levels degrade performance affect reliability. Device functional from +4.5 +5.5 with reference ground. (VCC should exceed +7.0 This maximum current single output. Duration seconds maximum distance less than from device body, same lead shall resoldered until minutes have elapsed.
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Non-Government publications. following document(s) form part this document extent specified herein. Unless otherwise specified, issues documents which adopted those listed issue DODISS cited solicitation. Unless otherwise specified, issues documents listed DODISS issues documents cited solicitation. INSTITUTE ELECTRICAL ELECTRONICS ENGINEERS (IEEE) IEEE Standard 1149.1 IEEE Standard Test Access Port Boundary Scan Architecture. (Applications copies should addressed Institute Electrical Electronics Engineers, Hoes Lane, Piscataway, 08854-4150.) Order precedence. event conflict between text this drawing references cited herein, text this drawing takes precedence. Nothing this document, however, supersedes applicable laws regulations unless specific exemption been obtained.
REQUIREMENTS Item requirements. individual item requirements device classes shall accordance with MIL-PRF-38535 specified herein modified device manufacturer's Quality Management (QM) plan. modification plan shall affect form, fit, function described herein. individual item requirements device class shall accordance with MIL-PRF-38535, appendix non-JAN class level devices specified herein. 3.1.1 Microcircuit die. requirements microcircuit die, appendix this document. Design, construction, physical dimensions. design, construction, physical dimensions shall specified MIL-PRF-38535 herein device classes MIL-PRF-38535, appendix herein device class 3.2.1 Case outline. case outline shall accordance with 1.2.4 herein figure herein. 3.2.2 Terminal connections. terminal connections shall specified figure 3.2.3 Block diagram. block diagram shall specified figure 3.2.4 Boundary scan instruction codes. boundary scan instruction codes shall specified figure 3.2.5 Timing waveforms. timing waveforms shall specified figure 3.2.6 Radiation exposure connections. radiation exposure connections shall specified figure Electrical performance characteristics postirradiation parameter limits. Unless otherwise specified herein, electrical performance characteristics postirradiation parameter limits specified table shall apply over full case operating temperature range. Electrical test requirements. electrical test requirements shall subgroups specified table IIA. electrical tests each subgroup defined table Marking. part shall marked with listed herein. addition, manufacturer's also marked. packages where marking entire number feasible space limitations, manufacturer option marking "5962-" device. product using this option, designator shall still marked. Marking device classes shall accordance with MIL-PRF-38535. Marking device class shall accordance with MIL-PRF-38535, appendix 3.5.1 Certification/compliance mark. certification mark device classes shall "QML" required MIL-PRF-38535. compliance mark device class shall required MIL-PRF-38535, appendix
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Certificate compliance. device classes certificate compliance shall required from QML-38535 listed manufacturer order supply requirements this drawing (see 6.6.1 herein). device class certificate compliance shall required from manufacturer order listed approved source supply MIL-HDBK-103 (see 6.6.2 herein). certificate compliance submitted DSCC-VA prior listing approved source supply this drawing shall affirm that manufacturer's product meets, device classes requirements MIL-PRF-38535 herein device class requirements MIL-PRF-38535, appendix herein. Certificate conformance. certificate conformance required device classes MIL-PRF-38535 device class MIL-PRF-38535, appendix shall provided with each microcircuits delivered this drawing. Notification change device class device class notification DSCC-VA change product (see herein) involving devices acquired this drawing required change that affects this drawing. Verification review device class device class DSCC, DSCC's agent, acquiring activity retain option review manufacturer's facility applicable required documentation. Offshore documentation shall made available onshore option reviewer. 3.10 Microcircuit group assignment device class Device class devices covered this drawing shall microcircuit group number (see MIL-PRF-38535, appendix 3.11 IEEE 1149.1 compliance. These devices shall compliant IEEE 1149.1.
VERIFICATION Sampling inspection. device classes sampling inspection procedures shall accordance with MIL-PRF-38535 modified device manufacturer's Quality Management (QM) plan. modification plan shall affect form, fit, function described herein. device class sampling inspection procedures shall accordance with MIL-PRF-38535, appendix Screening. device classes screening shall accordance with MIL-PRF-38535, shall conducted devices prior qualification technology conformance inspection. device class screening shall accordance with method 5004 MIL-STD-883, shall conducted devices prior quality conformance inspection. 4.2.1 Additional criteria device class Burn-in test, method 1015 MIL-STD-883. Test condition test circuit shall maintained manufacturer under document revision level control shall made available preparing acquiring activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified method 1015. +125°C, minimum.
Interim final electrical test parameters shall specified table herein.
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TABLE Electrical performance characteristics. Test Symbol Conditions -55°C +125°C +4.5 +5.5 unless otherwise specified Group subgroups Device type Limits Unit
High level input voltage level input voltage High level output voltage
VIHCR
=4.5 -6.0
Minimum maximum values recorded VOHB =4.5 -16.0 Minimum maximum values recorded level output voltage =4.5 Minimum maximum values recorded VOLB =4.5 12.0 Minimum maximum values recorded High level input current level input current IILT Three-state leakage current Three-state leakage current Supply current (idle) IVCC pins Supply current (internal) IVCC pins Input capacitance IOZH IOZL ICCIDLE ICCIN 25°C 4.4.1c 1.45 1.55 4.4.1b
Functional test
footnotes table.
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions -55°C +125°C +4.5 +5.5 unless otherwise specified Group subgroups Device type Limits 9.75 Unit
CLK2 period
SYSCLK period
SYSCLK frequency figure
CLK2 high pulse width RA[31:0], RAPAR, RSIZE, RLDSTO, LOCK output delay
MEMCS[9 ROMCS EXMCS output delay DDIR, DDIR output delay
MEMWR IOMWR output delay
12.5
SYSCLK frequency figure SYSCLK frequency NOPAR either figure
11.5
23.5 20.5
(HL) output delay
Data setup time during load
Data hold time during load Data output delay Data output valid output delay
output delay
SYSCLK frequency figure
BUFFEN (HL) output delay MHOLD output delay DRDY output delay MEXC output delay RASI[3:0], RSIZE[1:0], RASPAR setup time footnotes table.
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions -55°C +125°C +4.5 +5.5 unless otherwise specified SYSCLK frequency figure Group subgroups Device type Limits Unit
RASI[3:0], RSIZE[1:0], RASPAR hold time BOOT PROM address output delay BUSRDY setup time BUSRDY hold time IOSEL output delay DMAAS setup time DMAAS hold time
DMAREQ setup time DMAGNT output delay RA[31:0], RAPAR, CPAR setup time RA[31:0], RAPAR, CPAR hold time period setup time hold time setup time hold time
output delay INULL output delay
RESET CPUHALT output delay SYSERR SYSAV output delay IUERR output delay EXTINT[4:0] setup time EXTINT[4:0] hold time EXTINTACK output delay footnotes table.
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TABLE Electrical performance characteristics Continued. Test Symbol Conditions -55°C +125°C +4.5 +5.5 unless otherwise specified SYSCLK frequency figure Group subgroups Device type Limits Unit
(LH) output delay mode) BUFFEN (LH) output delay INST output delay Data output delay low-Z
devices supplied this drawing characterized levels irradiation. However, this device only tested level. Post irradiation values identical unless otherwise specified table When performing post irradiation electrical measurements level, +25°C. recorded Tested go/no-go during functional test. Applies RA[31:0], RAPAR, RASI[3:0], RSIZE[1:0], RASPAR, CPAR, D[31:0], CB[6:0], DPAR, RLDSTO, DXFER, LOCK, WRT, PROM8 ROMWRT BUSRDY BUSERR DMAREQ DMAAS, SYSHALT NOPAR IWDE, WDCLK, CLK2, TMODE[1:0], DEBUG, TCK, TRST TMS, TDI.
Applies RxA, RxB, GPI[7:0], EXTINT[4:0], EWDINT, SYSRESET Applies RAPAR, RASI[3:0], RSIZE[1:0], RASPAR, CPAR, D[31:0], CB[6:0], DPAR, RLDSTO, DXFER, LOCK,
WRT, MHOLD MEXC BA[1:0], ROMCS MEMCS[9 BUFFEN DDIR, DDIR IOSEL[3 IOWR
EXMCS DMAGNT DRDY IUERR CPUHALT SYSERR SYSAV, INULL, INST, FLUSH, DIA, RTC, TxA, TxB, GPIINT, EXTINTACK, SYSCLK, RESET TDO. Applies RA[31:0], MEMWR Applies PROM8 ROMWRT BUSRDY BUSERR DMAREQ DMAAS, SYSHALT NOPAR RxA, RxB, EXTINT[4:0], IWDE, EWDINT, WDCLK, CLK2, SYSRESET TMODE[1:0], DEBUG, TCK, TRST TMS, TDI. Applies PROM8 ROMWRT BUSRDY BUSERR DMAREQ DMAAS, SYSHALT NOPAR RxA, RxB, EXTINT[4:0], IWDE, EWDINT, WDCLK, CLK2, SYSRESET TMODE[1:0], DEBUG TCK, TRST Applies TMS, TDI.
Applies RA[31:0], RAPAR, RASI[3:0], RSIZE[1:0], RASPAR, CPAR, D[31:0], CB[6:0], DPAR, RLDSTO, DXFER, LOCK, WRT, GPI[7:0].
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TABLE Electrical performance characteristics Continued.
Tested during tests recorded. With reference edge SYSCLK+. With reference edge SYSCLK-. With reference edge TCK+. With reference edge TCK-.
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Case outline
Symbol
Millimeters 3.18 2.56 0.36 0.25 0.20 55.74 37.34 .095 .081 .002 .006 .004 2.095 1.450
Inches .125 .101 .014 .010 .008 2.195 1.470
D1/E1 N1/N2
2.41 2.06 0.05 0.15 0.10 53.23 36.83
0.508 8.20 9.20
.020 .323 .362
FIGURE Case outline.
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Case number name GPIINT GPI[7] VCCO VSSO GPI[6] GPI[5] GPI[4] GPI[3] VCCO VSSO GPI[2] GPI[1] GPI[0] D[31] D[30] VCCO VSSO D[29] D[28] VCCI VSSI D[27] D[26] VCCO VSSO D[25] D[24] D[23] D[22] VCCO VSSO D[21] number name D[20] D[19] D[18] VCCO VSSO D[17] D[16] VCCI VSSI D[15] D[14] VCCO VSSO D[13] D[12] D[11] D[10] VCCO VSSO D[9] D[8] D[7] D[6] VCCO VSSO D[5] D[4] D[3] D[2] VCCO VSSO D[1] number name D[0] RSIZE[1] RSIZE[0] RASI[3] VCCO VSSO RASI[2] RASI[1] RASI[0] RA[31] RA[30] VCCO VSSO RA[29] RA[28] RA[27] VCCO VSSO RA[26] RA[25] RA[24] VCCI VSSI VCCO VSSO RA[23] RA[22] RA[21] VCCO VSSO RA[20] RA[19] number name RA[18] VCCO VSSO RA[17] RA[16] RA[15] VCCO VSSO RA[14] VCCI VSSI RA[13] RA[12] VCCO VSSO RA[11] RA[10] RA[9] VCCO VSSO RA[8] RA[7] RA[6] VCCO VSSO RA[5] RA[4] RA[3] VCCO VSSO RA[2] RA[1]
FIGURE Terminal connections.
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Case number name RA[0] VCCO VSSO RAPAR number name SYSERR SYSAV EXTINT[4] EXTINT[3] number name DXFER MEXC VCCO VSSO number name MEMCS[3] VCCO VSSO
MEMCS[2] MEMCS[1] MEMCS[0] VCCI VSSI VCCO VSSO
MEMWR
RASPAR DPAR VCCO VSSO SYSCLK TRST CLK2
DRDY
EXTINT[2] EXTINT[1] EXTINT[0] VCCI VSSI EXTINTACK IUERR VCCO VSSO CPAR IOWR IOSEL[3] VCCO VSSO IOSEL[2] IOSEL[1] IOSEL[0]
RESET SYSRESET BA[1] BA[0] CB[6] CB[5] VCCO VSSO CB[4] CB[3] CB[2] CB[1] VCCO VSSO CB[0]
BUFFEN DDIR VCCO VSSO
DDIR
DMAAS VCCO VSSO DMAGNT EXMCS VCCI VSSI DMAREQ BUSERR BUSRDY ROMWRT NOPAR SYSHALT CPUHALT VCCO VSSO
MHOLD WDCLK IWDE EWDINT TMODE[1] TMODE[0] DEBUG INULL VCCO VSSO FLUSH INST
VCCI VSSI PROM8 ROMCS MEMCS[9] VCCO VSSO MEMCS[8] MEMCS[7] MEMCS[6] MEMCS[5] MEMCS[4]
VCCO VSSO RLDSTO LOCK
FIGURE Terminal connections Continued.
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FIGURE Block diagram.
Device type Instruction name BYPASS EXTEST SAMPLE/PRELOAD INTEST code Reserved emulation Reserved emulation Reserved emulation Reserved emulation Reserved emulation Reserved emulation Instruction code 11.1111 00.0000 00.0001 00.0011 10.0000 01.1000 01.1001 01.1010 01.1100 01.1101 01.1110
FIGURE Boundary scan instruction codes.
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FIGURE Timing waveforms.
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FIGURE Timing waveforms Continued.
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FIGURE Timing waveforms Continued.
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FIGURE Timing waveforms Continued.
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FIGURE Timing waveforms Continued.
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FIGURE Timing waveforms Continued.
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FIGURE Timing waveforms Continued.
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FIGURE Timing waveforms Continued.
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FIGURE Timing waveforms Continued.
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FIGURE Timing waveforms Continued.
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FIGURE Timing waveforms Continued.
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FIGURE Timing waveforms Continued.
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FIGURE Timing waveforms Continued.
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FIGURE Timing waveforms Continued.
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FIGURE Timing waveforms Continued.
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FIGURE Timing waveforms Continued.
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FIGURE Timing waveforms Continued.
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Case outline
±0.5 103, 105, 106, 110, 115, 120, 125, 130, 135, 137, 138, 142, 144, 146, 150, 155, 159, 168, 172, 181, 188, 195, 197, 199, 200, 203, 206, 208, 209, 212, 213, 218, 226, 231, 233, 234, 239, 243, 252,
Ground 104, 107, 111, 116, 121, 126, 131, 136, 139, 145, 147, 151, 156, 160, 169, 173, 182, 189, 196, 198, 201, 202, 204, 205, 207, 210, 211, 214, 219, 227, 232, 235, 240, 249,
Other
Notes: (TDO) high-impedance (High state. (CLK2) activated frequency (below Hz). product reset mode. following pins have serial resistors with specified value attached: 134, 143, 145, 157, 167, 176, 177, 198, 201, 202, 208, 211, 215, 249. 102, 105, 108, 109, 114, 119, 124, 129, 132, 133, 137, 138, 144, 148, 149, 158, 161, 162, 170, 171, 174, 175, 180, 187, 194, 197, 199, 200, 212, 216, 217, 225, 230, 233, 238, 243, 250, 251, 256. other pins, serial resistor attached. following output pins have output buffer capacitors with specified value attached: 102, 105, 108, 109, 114, 119, 124, 129, 233, 236. other output pins, output buffers following pins Input reset: 134, 201, 202, 208, 211. VCCO/VSSO Output buffers. VCCI/VSSI Internal logic. FIGURE Radiation exposure connections.
TABLE test limits. Device type Temperature ±10°C Effective upsets [MeV/(mg/cm2)] Maximum device cross section (LET (cm2) 2E-5 Bias latch-up test latch-up
+25°C
Devices that contain cross coupled resistance must tested maximum rated test condition, 4.4.4 herein. Technology characterization model verification supplemented in-line data used lieu end-of-line. Test plan must approved qualifying activity. Worst case temperature +125°C.
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4.2.2 Additional criteria device classes burn-in test duration, test condition test temperature, approved alternatives shall specified device manufacturer's plan accordance with MIL-PRF-38535. burn-in test circuit shall maintained under document revision level control device manufacturer's Technology Review Board (TRB) accordance with MIL-PRF-38535 shall made available acquiring preparing activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified method 1015 MIL-STD-883. Interim final electrical test parameters shall specified table herein. Additional screening device class beyond requirements device class shall specified MIL-PRF-38535, appendix
Qualification inspection device classes Qualification inspection device classes shall accordance with MIL-PRF-38535. Inspections performed shall those specified MIL-PRF-38535 herein groups inspections (see 4.4.1 through 4.4.4). Conformance inspection. Technology conformance inspection classes shall accordance with MIL-PRF-38535 including groups inspections specified herein. Quality conformance inspection device class shall accordance with MIL-PRF-38535, appendix specified herein. Inspections performed device class shall those specified method 5005 MIL-STD-883 herein groups inspections (see 4.4.1 through 4.4.4). 4.4.1 Group inspection. Tests shall specified table herein. device class subgroups tests shall verify instruction set. instruction forms part vendor's test tape shall maintained available review from approved sources supply. device classes subgroups shall include verifying functionality device. Subgroup (CIN measurement) shall measured only initial test after process design changes which affect input capacitance. minimum sample devices with zero rejects shall required.
4.4.2 Group inspection. group inspection end-point electrical parameters shall specified table herein. 4.4.2.1 Additional criteria device class Steady-state life test conditions, method 1005 MIL-STD-883: Test condition test circuit shall maintained manufacturer under document revision level control shall made available preparing acquiring activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified test method 1005 MIL-STD-883. +125°C, minimum. Test duration: 1,000 hours, except permitted method 1005 MIL-STD-883.
4.4.2.2 Additional criteria device classes steady-state life test duration, test condition test temperature, approved alternatives shall specified device manufacturer's plan accordance with MIL-PRF-38535. test circuit shall maintained under document revision level control device manufacturer's accordance with MIL-PRF-38535 shall made available acquiring preparing activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified method 1005 MIL-STD-883.
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TABLE IIA. Electrical test requirements. Test requirements Subgroups accordance with MIL-STD-883, method 5005, table Device class Interim electrical parameters (see 4.2) Final electrical parameters (see 4.2) Group test requirements (see 4.4) Group end-point electrical parameters (see 4.4) Group end-point electrical parameters (see 4.4) Group end-point electrical parameters (see 4.4) Subgroups accordance with MIL-PRF-38535, table III) Device class Device class
applies subgroup applies subgroups Delta limits specified table herein shall required where specified table
TABLE IIB. Delta limits. Parameter IOZH IOZL Limit
±0.1 ±0.1 ±0.1 ±0.1 ±0.1 ±0.1
Unit
parameters shall recorded before after required burn-in life test determine delta limits.
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4.4.3 Group inspection. group inspection end-point electrical parameters shall specified table herein. 4.4.4 Group inspection. Group inspection required only parts intended marked radiation hardness assured (see herein). End-point electrical parameters shall specified table herein. device classes devices test vehicle shall subjected radiation hardness assured tests specified MIL-PRF-38535 level being tested. device class devices shall subjected radiation hardness assured tests specified MIL-PRF-38535, appendix level being tested. device classes must meet postirradiation end-point electrical parameter limits defined table +25°C ±5°C, after exposure, subgroups specified table herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall performed accordance with MIL-STD-883, test method 1019 (condition specified herein. 4.4.4.1.1 Accelerated aging test. Accelerated aging tests shall performed devices requiring level greater than rads (Si). post-anneal end-point electrical parameter limits shall specified table herein shall preirradiation end-point electrical parameter limit 25°C ±5°C. Testing shall performed initial qualification after design process changes which affect response device. 4.4.4.2 Dose rate induced latchup testing. Dose rate induced latchup testing shall performed accordance with test method 1020 MIL-STD-883 specified herein (see paragraph 1.5). Tests shall performed devices, Standard Evaluation Circuit (SEC), approved test structures technology qualification after design process changes which effect capability process. 4.4.4.3 Dose rate upset testing. Dose rate upset testing shall performed accordance with MIL-STD-883, test method 1021 herein (see paragraph 1.5). Transient dose rate upset testing shall performed initial qualification after design process changes which effect performance devices. Test devices with defects unless otherwise specified. Transient dose rate upset testing class devices shall performed specified approved radiation hardness assurance plan MIL-PRF-38535.
4.4.4.4 Single event phenomena (SEP). testing shall required class devices (see paragraph 1.5). testing shall performed alternate test vehicle approved qualifying activity initial qualification after design process changes which effect upset latchup characteristics. recommended test conditions follows: beam angle incidence shall between normal surface normal, inclusive (i.e. angle 60°). shadowing beam fixturing package related effects allowed. fluence shall errors ions/cm2. flux shall between ions/cm2/s. cross-section shall verified flux independent measuring cross-section flux rates which differ least order magnitude. particle range shall microns silicon. upset test temperature shall +25°C latchup test temperature maximum rated operating temperature ±10°C. Bias conditions shall defined manufacturer latchup measurements. Test four devices with zero failures. test limits, table herein.
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PACKAGING Packaging requirements. requirements packaging shall accordance with MIL-PRF-38535 device classes MIL-PRF-38535, appendix device class NOTES Intended use. Microcircuits conforming this drawing intended Government microcircuit applications (original equipment), design applications, logistics purposes. 6.1.1 Replaceability. Microcircuits covered this drawing will replace same generic device covered contractor-prepared specification drawing. 6.1.2 Substitutability. Device class devices will replace device class devices. Configuration control SMD's. proposed changes existing SMD's will coordinated with users record individual documents. This coordination will accomplished using Form 1692, Engineering Change Proposal. Record users. Military industrial users should inform Defense Supply Center Columbus (DSCC) when system application requires configuration control which SMD's applicable that system. DSCC will maintain record users this list will used coordination distribution changes drawings. Users drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. Comments. Comments this drawing should directed DSCC-VA Columbus, Ohio 43218-3990, telephone (614) 692-0547. Abbreviations, symbols, definitions. abbreviations, symbols, definitions used herein defined MIL-PRF-38535, MIL-HDBK-1331, table herein. Sources supply. 6.6.1 Sources supply device classes Sources supply device classes listed QML-38535. vendors listed QML-38535 have submitted certificate compliance (see herein) DSCC-VA have agreed this drawing. 6.6.2 Approved sources supply device class Approved sources supply class listed MIL-HDBK-103. vendors listed MIL-HDBK-103 have agreed this drawing certificate compliance (see herein) been submitted accepted DSCC-VA. Additional information. copy following additional data shall maintained available from device manufacturer: upset levels. Test conditions (SEP). Number upsets (SEP). Number transients (SEP). Occurrence latchup (SEP).
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TABLE III. Terminal descriptions. name Type Description
Signals
RA[31:0]
Registered address bus. address device output bus. Inside processor, address used perform decoding, generate select signals check against memory access protection scheme. also used address system registers. save board space, address sent registered external resources. This means that internal D-type flip-flop's implemented inside device memorize address each rising edge SYSCLK enabled signal. This registered address always driven device even during system registers accesses. case session, address device input bus. unit must drives itself registered address available parts processor during session external resources (SRAM's, ROM's, I/O's Organization addressing data memory follows "Big-Endian" convention wherein lower addresses contain higher-order bytes. Attempting access misaligned data will generate memory-address-not-aligned trap
RAPAR
Registered address parity. This output parity over 32-bit address bus. save board space, this signal sent registered same timing RA[31:0]. case session, this signal must driven unit parity enabled. This input requires same timing RA[31:0].
RASI[3:0]
4-bit registered address space identifier. These four bits constitute Address Space Identifier (ASI), which identifies memory address space which instruction data access being directed. bits provided detect supervisor user mode, instruction data access. Inside processor, these identifiers used control accesses on-chip peripherals. save board space, these outputs sent registered same timing RA[31:0]. case session, these signals must driven unit. These inputs require same timing RA[31:0].
RSIZE[1:0]
2-bit registered transaction size. coding these pins specifies size data being transferred during instruction data fetch. save board space, these outputs sent registered same timing RA[31:0]. Registered SIZE parity. This output parity over RASI[3:0] RSIZE[1:0] signals. save board space, this output sent registered same timing RA[31:0]. case session, this signal must driven unit parity enabled. This input requires same timing RA[31:0].
RASPAR
CPAR
Control parity. This output parity over RLDSTO, DXFER, LOCK, WRT, signals. This signal sent unregistered must latched externally before used. case session, this signal must driven unit parity enabled.
footnote table.
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TABLE III. Terminal descriptions Continued. name Type Description
Signals Continued
D[31:0]
32-bit data bus. These signals form 32-bit bidirectional data that serves interface between device external memory. data driven device during system registers accesses, only driven during execution integer floating-point store instructions store cycle atomic-load-store instructions external memory. Store data valid during second data cycle store single access, second third data cycle store double access, third data cycle atomic-load-store access. Alignment load store instructions performed processor. Doublewords aligned 8-byte boundaries, words 4-byte boundaries, halfwords 2-byte boundaries. doubleword, word, halfword load store instruction generates improperly aligned address, memory address aligned trap will occur. Instructions operands always expected reside 32-bit wide memory. D[31] corresponds most significant most significant byte 32-bit word going from memory.
CB[6:0]
7-bit check-bit bus. CB[6:0] EDAC checkword over 33-bit data consisting D[31:0] parity (DPAR). When device performs write operation main memory, will assert EDAC checkword CB[6:0]. During read access from main memory, CB[6:0] input signals will used checking correction data word parity bit. During read access areas which generate parity bit, device will latch data from accessed address drive correct parity DPAR pin. Data parity. This used device check generate parity over 32-bit data during write cycles. DPAR (D[31] D[30] D[1] D[0]) case session, this signal must driven unit parity enabled. Registered atomic load-store. This signal used identify atomic load-store system asserted during data cycles (the load cycle both store cycles) atomic load-store instructions. save board space, LDSTO sent registered. case session, this signal must driven unlatched unit.
DPAR
RLDSTO
Address latch enable. This output asserted when internal address from latched. This latch operation assumed internal latch. case session, this signal intended used enable clock input (SYSCLK) external flip-flop used latch generated address from unit.
DXFER
Data transfer. DXFER used differentiate between addresses being sent instruction fetches addresses data fetches. DXFER asserted processor during address cycles data transfer cycles, including both cycles store single three cycles store double atomic load-store. DXFER sent unregistered must latched externally before used. unit must supply this signal during session.
LOCK
lock. LOCK asserted processor when needs retain control (address data) multiple cycle transactions (Load Double, Store Single Double, Atomic Load-Store). will granted another master long LOCK asserted. Note that MHOLD when reflects internal signal "Bus Hold", should asserted processor clock cycle which follows cycle which LOCK asserted. LOCK sent unregistered must latched externally before used. unit must supply this signal during session.
footnote table.
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TABLE III. Terminal descriptions Continued. name Type Description
Signals Continued
Read access. sent during address portion access specify whether current memory access read "1") write "0") operation. only during address cycles store instructions. atomic load-store instructions, high during load address cycle during store address cycles. used, conjunction with SIZE[1:0], ASI[7:0], LDSTO, determine type check read/write access rights transactions Extended General area. sent unregistered must latched externally before used. unit must supply this signal during session. Memory hold. signal asserted when "Memory Hold" (MHOLD), "Floating Point Hold" (FHOLD) "Floating Point Condition Codes Valid" (FCCV) Hold (BHOLD) internally generated. Note that MHOLD must driven HIGH while RESET LOW.
"Memory Hold"
MHOLD
"Memory Hold" used freeze pipeline both accessing slow memory during memory exception. internal outputs return stay value they rising edge SYSCLK cycle which "Memory Hold" asserted. "Memory Hold" tested falling edge (midpoint cycle) SYSCLK. memory wait state controller device inserts, this way, wait states during external accesses.
"Floating-Point Hold"
"Floating-Point Hold" asserted situation arises which cannot continue execution. checks dependencies decode stage instruction asserts "Floating-Point Hold" necessary) next cycle. receives "Floating-Point Hold", freezes instruction pipeline same cycle. Once conditions causing "Floating-Point Hold" resolved, deasserts command, releasing instruction pipeline. "Floating-Point Hold" asserted encounters STFSR instruction with more FPops pending queue, either resource operand dependency exists between FPop being decoded FPops already being executed, floating-point queue full.
"Floating-Point Condition Codes Valid"
"Floating-Point Condition Codes Valid" specialized hold used synchronize compare instructions with floating-point branch instructions. asserted (the normal condition) whenever "Floating-Point Condition Codes" bits (FCC[1:0]) valid. deasserts these bits "0") soon floating-point compare instruction enters floating-point queue, unless exception detected. Deasserting "Floating-Point Condition Codes" bits freezes pipeline, preventing further compares from entering pipeline. "Floating-Point Condition Codes" bits reasserted when compare completed condition codes valid, thus ensuring that condition codes match proper compare instruction.
"Bus Hold"
"Bus Hold" asserted during accesses. Assertion this hold signal will freeze processor pipeline, after deassertion "Bus Hold", external logic must guarantee that data inputs device same before "Bus Hold" asserted. This hold signal tested falling edge (midpoint cycle) SYSCLK. footnote table.
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TABLE III. Terminal descriptions Continued. name Type Description
Signals Continued
Write enable. asserted during cycle which store data data bus. store single instruction, this during second store address cycle, second third store address cycles store double instructions third load-store address cycle atomic load-store instructions. avoid writing memory during memory exceptions, must externally qualified MHOLD when this holding reflects internal signal "Memory Hold". sent unregistered must latched externally before used. unit must supply this signal during session, asserted write deasserted high read accesses.
Advanced write. early write signal, asserted processor during first store address cycle integer single double store instructions, first store address cycle floating-point single double store instructions, second load-store address cycle atomic load-store instructions. sent unregistered must latched externally before used. unit must supply this signal during session, deasserted read asserted high write accesses.
Memory data strobe. asserted memory access controller device enable clock IU's instruction register (during instruction fetch) load result register (during data fetch) while pipeline frozen with MHOLD system with slow memories, tells processor when read data available bus. also used strobe MEXC memory exception signal. only asserted when pipeline frozen with MHOLD
MEXC
Memory exception. Assertion this signal memory access controller device initiates memory exception indicates that memory system unable supply valid instruction data. MEXC asserted during instruction fetch cycle, generates instruction access exception trap (tt=1). asserted during data cycle, generates data access exception trap (tt=9). denotes parity error, uncorrectable EDAC error, access violation, time-out system error detected. MEXC used qualifier signal, asserted when both MHOLD already asserted. applied without MEXC device accepts contents data valid. MEXC accompanies exception generated data content ignored. MEXC latched rising edge SYSCLK used following cycle. MEXC deasserted same clock cycle which MHOLD deasserted. this signal asserted during transfer, must withdraw request cycle.
footnote table.
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TABLE III. Terminal descriptions Continued. name Type Description
Memory System Interface Signals
PROM8
Select 8-bit wide PROM. This input indicates that only 8-bit wide PROM connected device. eight data lines from PROM connected D[7:0] signals. processor will perform 8-bit 32-bit conversion when reads from PROM (the conversion visible data bus). There EDAC parity checking accesses PROM when PROM8 asserted, EDAC parity bits must supplied PROM when PROM8 deasserted.
BA[1:0]
Latched address used 8-bit wide boot PROM. These outputs used when 8-bit wide PROM connected device. During fetch 32-bit load access PROM, BA[1:0] will asserted four times order four bytes needed generate 32-bit word.
ROMCS ROMWRT
PROM chip select. This output asserted whenever there access boot extended PROM areas. connected directly PROM chip select pins. write enable. Assertion this signal will enable Memory Configuration Register (MCNFR). This logic allows on-board programming (write operations) boot PROM when EEPROM FLASH devices used. Memory chip select. MEMCS[9 asserted during access main memory. MEMCS[9 redundant signals, used substitute nominal memory banks when memory connected MEMCS[7 malfunctions.
MEMCS[9
MEMWR
Memory write. MEMWR asserted during write access (store) boot PROM area, extended PROM area, area extended area. intended used write strobe memory devices. Memory output enable. asserted during fetch load accesses main memory. intended used control memory devices with output enable features. Data buffer enable. BUFFEN asserted during memory accesses excepted area (RAM area does needs data buffers). intended used buffer enable data, check parity buffers boot PROM area, extended PROM area, exchange memory area, extended area, area, extended area extended general area these areas share same buffers. Data buffer direction. DDIR used determining direction data buffers enabled BUFFEN valid during memory accesses. DDIR asserted high during store operations.
BUFFEN
DDIR
DDIR
Data buffer direction. DDIR used determining direction data buffers enabled BUFFEN valid during memory accesses. DDIR asserted high during fetch load operations.
IOSEL[3 IOWR
chip select. These four select signals used enable four possible address areas. exchange memory write strobe. IOWR asserted during write operations area, extended area exchange memory area.
footnote table.
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TABLE III. Terminal descriptions Continued. name Type Description
Memory System Interface Signals Continued
EXMCS BUSRDY
Exchange memory chip select. EXMCS asserted when exchange memory accessed. ready. BUSRDY generated unit area, exchange memory area extended areas, which requires extended time when accessed addition preprogrammed number wait states. (Note however that wait states preprogrammed units extended general area, only extended I/O, boot PROM RAM).
Error, DMA, Halt, Check Signals
BUSERR
error. BUSERR generated together with BUSRDY unit area, exchange memory area extended areas error detected accessed unit during access. request. DMAREQ issued unit requesting access processor master. device include session timeout function preventing unit lockout IU/FPU asserting request long time. grant. DMAGNT generated device response DMAREQ DMAGNT sent after that device asserted "Bus Hold". memory cycle started processor interrupted access before finished. unit access system registers integrated peripherals device. also access memory controlled memory access controller device.
DMAREQ
DMAGNT
DMAAS
address strobe. During transfers (when external master) this input used inform device that address from valid that access cycle shall start. DMAAS asserted multiple times during grant. Data ready during access. During read transfers (when external master) this output used inform unit that data valid. During write transfers this signal indicates that data have been written into memory. error. This signal asserted when (master) enters "error mode" state. This happens synchronous trap occurs while traps disabled (the %PSR's Before enters error mode state, device saves %nPC sets trap type (tt) trap causing error mode into %TBR. then asserts error signal halts. only restart processor which error mode state trigger reset asserting RESET signal.
DRDY
IUERR
CPUHALT
Processor FPU) halt freeze. This output informs that "halt" mode. used halt other units system. CPUHALT signal also used advise "freeze" mode generated OCD.
SYSERR
System error. This signal asserted whenever unmasked error Error Reset Status Register (ERRRSR). stays asserted until ERRRSR cleared. error originate from either error hardware error) system registers (system hardware error). SYSERR IUERR used signal application system.
footnote table.
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TABLE III. Terminal descriptions Continued. name Type Description
Error, DMA, Halt, Check Signals Continued
SYSHALT
System halt. Assertion this will halt device, freezing IU/FPU execution. SYSCLK internal CLK2 running timers watchdog halted UART operation stopped. accesses allowed during halt mode. When SYSHALT deasserted, previous mode entered.
SYSAV
System availability. This signal asserted whenever system available, i.e. when sysav ERRRSR CPUHALT SYSERR signals deasserted. sysav cleared reset programmable software.
NOPAR
parity. Assertion this signal will disable parity checking signals related device internal buses. parity generation data (towards units) affected this signal, note that parity checking disabled NOPAR asserted. This static signal shall change when running. When this signal asserted parity), disables bits Memory Configuration Register (MCNFR) pa3, pa2, pa1, bits Configuration Register.
INULL
Integer unit nullify cycle. processor asserts INULL indicate that current memory access being nullified. asserted beginning cycle which address being nullified active. INULL used disable memory exception generation current memory access. This means that MEXC asserted memory access which INULL INULL asserted under following conditions: during second data cycle store instruction (including Atomic Load-Store) nullify second occurrence store address, traps, nullify third instruction fetch after trapped instruction. reset, nullifies error-producing address, load which hardware interlock activated, JMPL RETT instructions.
INST
Instruction fetch. INST signal asserted whenever instruction being fetched. used latch instruction currently internal data into instruction buffer. have instruction buffers save last fetched instructions. When INST asserted, instruction enters buffer instruction that moves buffer instruction flush. This signal asserted whenever takes trap. FLUSH used flush instructions instruction buffers. These instructions, well instructions annulled pipeline, restarted after trap handler finished. trap caused floating-point exception, instructions already floating-point queue continue their execution. trap caused floating-point exception, Fpqueue must emptied before resume execution. Delay instruction annulled. This signal asserted when delay instruction annulled (c.f. delayed control transfer). This signal used trace execution pipe.
FLUSH
footnote table.
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TABLE III. Terminal descriptions Continued. name Type Description
Interrupt, Clock, UART, GPI, Timer, TAP, Test Signals
RxA/RxB TxA/TxB GPI[7:0] GPIINT
Real time clock counter output. This signal generated when delay time elapsed "Real Time Clock Timer". This output asserted high SYSCLK period. Receive data UART "B". serial data input channel UART. serial data input channel UART. Transmit data UART "B". serial data output channel UART. serial data output channel UART. General purpose interface. Each programmable input output General purpose interface interrupt. edge detection (rising falling) made each input configured input. GPIINT result logical these detections. This output asserted high SYSCLK periods. External interrupt. five external interrupt inputs programmable level edge sensitive, active high (rising) active (falling). External interrupt acknowledge. EXTINTACK used giving acknowledge interrupting unit which requires such signal. programmable which five external interrupt inputs associated. issued soon recognized interrupt. Internal watch enable. This static signal commands multiplexer placed front watch timeout interrupt "Interrupt Pending Register". internal watch dog, IWDE must high. This input enables input EWDINT external watch disables entirely internal watch (not running). value IWDE copied into "System Control Register" External watch input interrupt. This input enabled IWDE receives external watch timeout. Another usage this input NMI. This input must asserted high minimum SYSCLK periods. Watch clock. WDCLK clock input this clock also used clock input UART interface. clock frequency WDCLK must less than clock frequency SYSCLK, i.e. fWDCLK fSYSCLK. Double frequency clock. CLK2 input clock device. frequency this clock must twice clock frequency fSYSCLK used drive FPU. Note that some external timings device affected duty cycle CLK2. System clock. SYSCLK nominally duty-cycle clock generated device from CLK2 used clocking well other system logic. Note that timing device referenced SYSCLK. Output reset. RESET will asserted when device synchronously reset. This occurs when either SYSRESET asserted device initiates reset error programming command. minimum pulse width RESET 1024 SYSCLK periods authorize implementation FLASH memories application.
EXTINT[4:0] EXTINTACK
IWDE
EWDINT
WDCLK
CLK2
SYSCLK
RESET
SYSRESET
System input reset. Assertion this will reset device. Following this assertion, RESET generated minimum 1024 SYSCLK periods. SYSRESET must asserted minimum SYSCLK periods.
footnote table.
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TABLE III. Terminal descriptions Continued. name Type Description
Interrupt, Clock, UART, GPI, Timer, TAP, Test Signals Continued
TMODE[1:0] DEBUG
Factory test mode. This test mode only dedicated factory test mode. user functional mode TMODE[1:0] "00". Software debug mode. DEBUG directly enables setting halt bits "Timer Control Register" freeze integrated peripherals. DEBUG phlt freeze internal watch internal timers, DEBUG phlt ahlt freeze channel internal UART, DEBUG phlt bhlt freeze channel internal UART.
final application, this must grounded. This allows keep software included debug facilities. TRST Test (JTAG) clock. Test clock scan registers. Test (JTAG) reset. Asynchronous reset controller. final application, this must grounded. Test (JTAG) mode select. Selects test mode controller. Test (JTAG) data input. Test scan register data input. Test (JTAG) data output. Test scan register data output.
Power Signals
VCCO/VCCI
Power. VCCO pins supply output bidirectional pins device. VCCI pins supply input main internal circuitry device.
VSSO/VSSI
Ground. VSSO pins provide ground return output bidirectional pins device. VSSI pins provide ground return input main internal circuitry device.
Input; Ouput.
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APPENDIX APPENDIX FORMS PART 5962-00540
SCOPE A.1.1 Scope. This appendix establishes minimum requirements microcircuit supplied under Qualified Manufacturers List (QML) Program. microcircuit meeting requirements MIL-PRF-38535 manufacturers approved plan monolithic microcircuits, multi-chip modules (MCMs), hybrids, electronic modules, devices using chip wire designs accordance with MIL-PRF-38534 specified herein. product assurance classes consisting military high reliability (device class space application (device Class reflected Part Identification Number (PIN). When available choice Radiation Hardiness Assurance (RHA) levels reflected PIN. A.1.2 PIN. shown following example: 5962 00540
Federal stock class designator
designator (see A.1.2.1) Drawing number
Device type (see A.1.2.2)
Device class designator (see A.1.2.3)
code
details (see A.1.2.4)
A.1.2.1 designator. Device classes identified shall meet MIL-PRF-38535 specified levels. dash indicates non-RHA die. A.1.2.2 Device type(s). device type(s) shall identify circuit function follows: Device type A.1.2.3 Device class designator. Device class Device requirements documentation Certification qualification requirements MIL-PRF-38535 Generic number TSC695F Circuit function 32-bit SPARC processor Frequency
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APPENDIX APPENDIX FORMS PART 5962-00540
A.1.2.4 Details. details designation shall unique letter which designates die's physical dimensions, bonding location(s) related electrical function(s), interface materials, other assembly related information, each product variant supplied this appendix. A.1.2.4.1 physical dimensions. type Figure number
A.1.2.4.2 bonding locations electrical functions. type A.1.2.4.3 Interface materials. type A.1.2.4.4 Assembly related information. type A.1.3 Absolute maximum ratings. paragraph herein details. A.1.4 Recommended operating conditions. paragraph herein details. Figure number Figure number Figure number
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APPENDIX APPENDIX FORMS PART 5962-00540 APPLICABLE DOCUMENTS. A.2.1 Government specifications, standards, handbooks. Unless otherwise specified, following specification, standard, handbook issue listed that issue Department Defense Index Specifications Standards specified solicitation, form part this drawing extent specified herein. SPECIFICATION DEPARTMENT DEFENSE MIL-PRF-38535 Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT DEFENSE MIL-STD-883 Test Method Standard Microcircuits. HANDBOOK DEPARTMENT DEFENSE MIL-HDBK-103 List Standard Microcircuit Drawings. (Copies specification, standard, handbook required manufacturers connection with specific acquisition functions should obtained from contracting activity directed contracting activity). A.2.2 Order precedence. event conflict between text this drawing references cited herein, text this drawing shall take precedence. REQUIREMENTS A.3.1 Item requirements. individual item requirements device classes shall accordance with MIL-PRF-38535 specified herein modified device manufacturer's Quality Management (QM) plan. modification plan shall effect form, function described herein. A.3.2 Design, construction physical dimensions. design, construction physical dimensions shall specified MIL-PRF-38535 manufacturer's plan, device classes herein. A.3.2.1 physical dimensions. physical dimensions shall specified A.1.2.4.1 figure A-1. A.3.2.2 bonding locations electrical functions. bonding locations electrical functions shall specified A.1.2.4.2 figure A-1. A.3.2.3 Interface materials. interface materials shall specified A.1.2.4.3 figure A-1. A.3.2.4 Assembly related information. assembly related information shall specified A.1.2.4.4 figure A-1. A.3.2.5 Radiation exposure connections. radiation exposure connections shall defined paragraph 3.2.6 herein. A.3.3 Electrical performance characteristics post-irradiation parameter limits. Unless otherwise specified herein, electrical performance characteristics post-irradiation parameter limits specified table body this document. A.3.4 Electrical test requirements. wafer probe test requirements shall include functional parametric testing sufficient make packaged capable meeting electrical performance requirements table
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APPENDIX APPENDIX FORMS PART 5962-00540 A.3.5 Marking. minimum, each unique die, loaded single multiple stack carriers, shipment customer, shall identified with wafer number, certification mark, manufacturer's identification listed A.1.2 herein. certification mark shall "QML" required MIL-PRF-38535. A.3.6 Certification compliance. device classes certificate compliance shall required from QML38535 listed manufacturer order supply requirements this drawing (see A.6.4 herein). certificate compliance submitted DSCC-VA prior listing approved source supply this appendix shall affirm that manufacturer's product meets, device classes requirements MIL-PRF-38535 requirements herein. A.3.7 Certificate conformance. certificate conformance required device classes MIL-PRF-38535 shall provided with each microcircuit delivered this drawing. VERIFICATION A.4.1 Sampling inspection. device classes sampling inspection procedures shall accordance with MIL-PRF-38535 modified device manufacturer's Quality Management (QM) plan. modifications plan shall effect form, function described herein. A.4.2 Screening. device classes screening shall accordance with MIL-PRF-38535, defined manufacturer's plan. minimum shall consist Wafer acceptance Class product using criteria defined MIL-STD-883 test method 5007. 100% wafer probe (see paragraph A.3.4 herein). 100% internal visual inspection applicable class criteria defined MIL-STD-883 test method 2010 alternate procedures allowed MIL-STD-883 test method 5004.
A.4.3 Conformance inspection. A.4.3.1 Group inspection. Group inspection required only parts intended identified radiation assured (see A.3.5 herein). levels device classes shall specified MIL-PRF-38535. point electrical testing packaged shall specified table herein. Group tests conditions specified paragraphs 4.4.4 herein. CARRIER A.5.1 carrier requirements. requirements carrier shall accordance with manufacturer's plan specified purchase order acquiring activity. carrier shall provide adequate physical, mechanical electrostatic protection. NOTES A.6.1 Intended use. Microcircuit conforming this drawing intended microcircuits built accordance with MIL-PRF-38535 MIL-PRF-38534 government microcircuit applications (original equipment), design applications logistics purposes. A.6.2 Comments. Comments this appendix should directed DSCC-VA, Columbus, Ohio, 43216-5000 telephone (614)-692-0547. A.6.3 Abbreviations, symbols definitions. abbreviations, symbols, definitions used herein defined MIL-PRF-38535 MIL-HDBK-1331. A.6.4 Sources supply device classes Sources supply device classes listed QML-38535. vendors listed within QML-38535 have submitted certificate compliance (see A.3.6 herein) DSCC-VA have agreed this drawing.
STANDARD MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
SIZE
REVISION LEVEL
5962-00540
SHEET
APPENDIX APPENDIX FORMS PART 5962-00540 complexity device, graphical representation locations available. This figure shall maintained available from device manufacturer. subsequent pages table locations.
bonding locations electrical functions Mask number 5186 physical dimensions. size: thickness: Interface materials. metallization: Backside metallization: Glassivation. Type: Thickness: Substrate: Assembly related information. Substrate potential: Special assembly instructions:
11,010 11,170 microns (with scribe line) microns (bare) Oxinitride Single crystal silicon connected None
FIGURE A-1. bonding locations electrical functions. SIZE
STANDARD MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
REVISION LEVEL
5962-00540
SHEET
APPENDIX APPENDIX FORMS PART 5962-00540 bonding locations. Center 4807.1 4655.1 4503.1 4351.1 4199.1 4047.1 3895.1 3743.1 3591.1 3439.1 3287.1 3135.1 2983.1 2831.1 2679.1 2527.1 2375.1 2223.1 2071.1 1919.1 1767.1 1615.1 1463.1 1311.1 1159.1 1007.1 855.1 703.1 551.1 399.1 247.1 95.1 Center 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 Center -75.8 -227.8 -379.8 -531.8 -683.8 -835.8 -987.8 -1139.8 -1291.8 -1443.8 -1595.8 -1747.8 -1899.8 -2051.8 -2203.8 -2355.8 -2507.8 -2659.8 -2811.8 -2963.8 -3115.8 -3267.8 -3419.8 -3571.8 -3723.8 -3875.8 -4027.8 -4179.8 -4331.8 -4483.8 -4635.8 -4787.8 Center 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 Center -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 Center 4807.1 4655.1 4503.1 4351.1 4199.1 4047.1 3895.1 3743.1 3591.1 3439.1 3287.1 3135.1 2983.1 2831.1 2679.1 2527.1 2375.1 2223.1 2071.1 1919.1 1767.1 1615.1 1463.1 1311.1 1159.1 1007.1 855.1 703.1 551.1 399.1 247.1 95.1 Center -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 Center -75.8 -227.8 -379.8 -531.8 -683.8 -835.8 -987.8 -1139.8 -1291.8 -1443.8 -1595.8 -1747.8 -1899.8 -2051.8 -2203.8 -2355.8 -2507.8 -2659.8 -2811.8 -2963.8 -3115.8 -3267.8 -3419.8 -3571.8 -3723.8 -3875.8 -4027.8 -4179.8 -4331.8 -4483.8 -4635.8 -4787.8
notes figure. FIGURE A-1. bonding locations electrical functions Continued.
STANDARD MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
SIZE
REVISION LEVEL
5962-00540
SHEET
APPENDIX APPENDIX FORMS PART 5962-00540 bonding locations Continued. Center -4807.1 -4655.1 -4503.1 -4351.1 -4199.1 -4047.1 -3895.1 -3743.1 -3591.1 -3439.1 -3287.1 -3135.1 -2983.1 -2831.1 -2679.1 -2527.1 -2375.1 -2223.1 -2071.1 -1919.1 -1767.1 -1615.1 -1463.1 -1311.1 -1159.1 -1007.1 -855.1 -703.1 -551.1 -399.1 -247.1 -95.1 Center -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 Center 75.8 227.8 379.8 531.8 683.8 835.8 987.8 1139.8 1291.8 1443.8 1595.8 1747.8 1899.8 2051.8 2203.8 2355.8 2507.8 2659.8 2811.8 2963.8 3115.8 3267.8 3419.8 3571.8 3723.8 3875.8 4027.8 4179.8 4331.8 4483.8 4635.8 4787.8 Center -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 -5101.8 Center 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 Center -4807.1 -4655.1 -4503.1 -4351.1 -4199.1 -4047.1 -3895.1 -3743.1 -3591.1 -3439.1 -3287.1 -3135.1 -2983.1 -2831.1 -2679.1 -2527.1 -2375.1 -2223.1 -2071.1 -1919.1 -1767.1 -1615.1 -1463.1 -1311.1 -1159.1 -1007.1 -855.1 -703.1 -551.1 -399.1 -247.1 -95.1 Center 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 5101.8 Center 75.8 227.8 379.8 531.8 683.8 835.8 987.8 1139.8 1291.8 1443.8 1595.8 1747.8 1899.8 2051.8 2203.8 2355.8 2507.8 2659.8 2811.8 2963.8 3115.8 3267.8 3419.8 3571.8 3723.8 3875.8 4027.8 4179.8 4331.8 4483.8 4635.8 4787.8
notes figure. FIGURE A-1. bonding locations electrical functions Continued.
STANDARD MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
SIZE
REVISION LEVEL
5962-00540
SHEET
APPENDIX APPENDIX FORMS PART 5962-00540 bonding locations Continued. Notes: center coordinate origin (0,0). Coordinates microns. Numbering numbering package pin. differs follows: Package Package Package Package
FIGURE A-1. bonding locations electrical functions Continued.
STANDARD MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
SIZE
REVISION LEVEL
5962-00540
SHEET
STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 04-11-22 Approved sources supply 5962-00540 listed below immediate acquisition information only shall added MIL-HDBK-103 QML-38535 during next revision. MIL-HDBK-103 QML-38535 will revised include addition deletion sources. vendors listed below have agreed this drawing certificate compliance been submitted accepted DSCC-VA. This information bulletin superseded next dated revision MIL-HDBK-103 QML-38535. DSCC maintains online database current sources supply
Standard microcircuit drawing 5962-0054001QXC 5962-0054001VXC 5962R0054001VXC 5962-0054001Q9A 5962-0054001V9
Vendor CAGE number F7400 F7400 F7400 F7400 F7400
Vendor similar TSC695F-25MAMQ TSC695F-25SASV TSC695F-25SASR TSC695F-25MBMQ TCS695F-25SBSV
lead finish shown each representing hermetic package most readily available from manufacturer listed that part. desired lead finish listed contact vendor determine availability. Caution. this number item acquisition. Items acquired this number satisfy performance requirements this drawing.
Vendor CAGE number F7400
Vendor name address Atmel Nantes BP70602 44306 NANTES CEDEX France
information contained herein disseminated convenience only Government assumes liability whatsoever inaccuracies information bulletin.

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