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ACT5028B 16-Bit Monolithic Tracking Hard Resolver-To-Digital Converter
www.aeroflex.com/RDC March 2005 FEATURES
Radiation Performance
Total Dose: 100Krad (Si) Immune: >100MeV-cm2/mg
+5VDC power only Programmable: using critical external resistors capacitors
Resolution: resolution Bandwidth Tracking rate
power: 30,000 carrier frequency range Accuracy Minutes Differential instrument amplifiers resolver input -55° +125°C Operating Temperature Digital interface logic voltage 3.3V Packaging Hermetic
Ceramic QUAD Flat Package (CQFP), .956" .10"Ht
Evaluation board (5028-480) available test evaluation. Aeroflex Application Note AN5028-1 Standard Microcircuit Drawing (SMD): 5962-0423501KXA/C
NOTE: Aeroflex Plainview does currently have DSCC Certified Radiation Hardened Assurance Program
APPLICATIONS
This single chip Resolver-to-Digital Converter (RDC) used shaft angle control systems, suitable space other radiation environments that require >100KRad total dose tolerance. part latchup free heavy environments (e.g., geosynchronous orbits) estimated experience induced errors less than minutes rate device years when operating dynamically.
THEORY OPERATION
ACT5028B converter single CMOS Type tracking resolver digital converter monolithic chip. implemented using precision analog circuitry digital logic. flexibility, converter bandwidth, dynamics velocity scaling externally with passive components. Refer Figure ACT5028B Block Diagram. converter powered from +5VDC. Analog signals referenced signal ground, which nominally converter consists three main sections; Analog Control Transformer (CT), Analog Error Processor (EP) Digital Logic Interface. analog resolver inputs (Sin Cos) that buffered high impedance input instrumentation type amplifiers digital word which represents output digital angle. performs ratiometric trigonometric computation SIN(A) sin(wt) COS(B) COS(A) sin(wt) SIN(B) SIN(A-B) sin(wt) Utilizing amplifiers, switches, logic resistors precision ratios. represents resolver angle, represents digital angle sin(wt) represents resolver reference carrier frequency. Error Processor configured critically damped Type loop. error, (A-B) (wt) full wave demodulated using reference squared drive. This error integrated analog integrator yielding velocity voltage which turn drives Voltage Controlled Oscillator (VCO). This incremental integrator (constant voltage input position rate output) which, together with velocity integrator, forms Type loop. lead inserted stabilize loop inserted higher frequency attenuate carrier frequency ripple. error processor drives digital output until nulls out. Then angle "B". digital output equals angle input accuracy precision control transformer. various error processor settings done with external resistors capacitors that converter loop dynamics easily controlled user. digital logic interface separate power line, that sets interface logic level. anywhere from power supply.
SCD5028-1
+VEL +2.5V
INT1
BPF2
BPF1
INTIN2
INTIN1
DEMOD1
-SIN DEMOD DIFFERENTIAL CONTROL TRANSFORMER
ERROR
DEMOD2
+SIN
HYSTERESIS
+COS
-COS
RIPPLE UP/DOWN COUNTER
TIMING
SIGNAL +2.25V OUTPUT DATA LATCH
VCOIN
COMP
INT2
SCD5028-1 +REF
-VEL
-REF
ACT5028B
INTERNAL ANALOG GROUND
CW/CCW
3,19,23
+5VA
+5VD
LOAD
DATA
ENABLE
BUSY
FIGURE ACT5028B BLOCK DIAGRAM
DESCRIPTIONS
SIGNAL +SIN -SIN +COS -COS +REF -REF (MSB) (LSB) DIRECTION INPUT INPUT INPUT SIGNAL DESCRIPTION Analog Sine input from Synchro Resolver. 1.3Vrms nominal Analog Cosine input from Synchro Resolver. 1.3Vrms nominal Analog Reference input Digital angle data. Parallel format. Natural binary positive logic. most significant 180°, 90°, mode, LSB. Bits 11-16 mode, LSB. Bits 13-16 mode, LSB. Bits 15-16 mode, LSB.
BIDIR
INPUT ENABLE* INH* DATALOAD* INPUT BUSY CW/CCW OUTPUT RIPPLE* OUTPUT BPF1 BPF2 DEMOD1 DEMOD2 INTIN1 INTIN2 INT1 VCOIN
SCD5028-1
Digital input. Sets resolution. Resolution Logic enables digital angle output. Otherwise high impedance. Logic freezes digital angle output that safely read. Logic enables digital angle lines inputs preset angle. Logic normal digital angle output. logic pulse when digital angle changes LSB. turns counting. Logic counting (CW), logic counting down (CCW). Ripple clock turns counting. logic pulse transition either direction. Differential error output Differential error input demodulator Differential error output Differential input differential velocity integrator Differential velocity output Input Voltage Controlled Oscillator Analog Power Digital Power Analog Power ground Digital Power ground Digital input/output power supply. Sets logic level.
INPUT INPUT
OUTPUT
OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT POWER POWER POWER
Indicates Active Signal
ABSOLUTE MAXIMUM RATINGS
PARAMETER Operating Temperature Storage Temperature Positive Power Supply Voltage (VCC VDD) Analog Output Current (Output Shorted GND) Digital Output Current (Output Shorted GND) Analog Input Voltage Range Digital Input Voltage Range Thermal Resistance Specification Maximum Junction Temperature VALUE -55°C +125°C -65°C +150°C -0.5 +7.0 18.6 -0.3 (VCC -0.3 (VDD 1.25°C/W 135°C
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. These stress ratings only; functional operation beyond these operating conditions recommended extended exposure beyond these operating conditions effect device reliability.
OPERATING CONDITIONS
-55°C +125°C)
POWER SUPPLY
PARAMETER Operating Voltage Operating Current Interface Voltage
3.3,
UNIT
ELECTRICAL CHARACTERISTICS 2,5,6
-55°C +125°C)
PARAMETER Accuracy4 Repeatability Resolution
CONDITIONS total Error
0.35 21.1 0.09 5.27 0.022 1.32 0.0055 0.33
UNITS Minutes Degrees Minutes Degrees Minutes Degrees Minutes Degrees Minutes
Mode Mode Mode Mode
Tracking Rate Mode Mode Mode Mode Frequency
SCD5028-1
Bits Used 1024 1.05
ELECTRICAL SPECIFICATIONS 2,5,6
-55°C +125°C)
ANALOG SIGNAL INPUTS SIN, COS, REF, VCOIN, INTIN1, INTIN2, BPF1, BPF2
VSIN, VCOS, VREF FREF
PARAMETER Voltage measurement made between inputs Frequency Impedance Capacitance Bias -Sin, -Cos Bias Current +25°C +125°C
UNITS VRMS
-100 -1000
+100 +1000
DIGITAL INPUTS ENABLE, DATALOAD SC2, SC1, Note Logic Logic High Leakage Current +25°C +125°C Impedance Capacitance3 DIGITAL OUTPUTS BUSY, RIPPLE CW/CCW DIGITAL Logic Logic High Logic 1.6mA Logic High -1.6mA Leakage Current +25°C +125°C High-Z Leakage Current +25°C +125°C -200 -2000 +200 +2000 -200 -2000 +200 +2000 Logic 1.6mA Logic High -1.6mA -200 -2000 +200 +2000
SCD5028-1
TIMING SPECIFICATIONS
25°C with 50pf Load)
DIGITAL OUTPUT Rise Time Fall Time Busy
COMMENTS Rise Time Fall Time Rise Time Fall Time
UNITS
CW/CCW, Ripple,
Busy Pulse Width Busy Data Stable Ripple Pulse Width Busy Ripple
tBPW tBDS tRPW
Enable
READ DATA Enable would normally tied together, Data Load Logic Enable Data Stable Enable High Data Hi-Z Data Stable High Data Change
tELDS tEHZ tILDS tIHZ
WRITING DATA Enable Logic Data Load Pulse Width Data Setup Data Load Data Hold
tDLPW tWDS tWDH
Transparent Trailing Edge Latch
Notes Bits, FREF BWCL Bits, FREF BWCL Bits, FREF BWCL Bits, FREF BWCL typical values measured +25°C. Characteristics guaranteed design, production tested. Accuracy apply over full operating Power Supply voltage range, Full operating Temperature range, Reference Frequency range, Signal Amplitude variation Reference Harmonic distortion. protection ACT5028B features limiting resistors series with diodes. Proper precautions strongly recommended avoid functional damage performance degradation. testing nominal voltage. unused inputs shall tied Ground. always MSB.
SCD5028-1
READ CYCLE
DATALOAD
ENABLE tELDS tILDS DATA
DATA
tEHZ tIHZ
WRITE CYCLE
ENABLE
tDLPW DATA LOAD tWDS DATA DATA tWDH
BUSY TIMING
tBPW BUSY RIPPLE tRPW
DATA
DATA tBDS
DATA
ACT5028B TIMING DIAGRAMS
SCD5028-1
+2.5V .1µf INT1 BPF2 BPF1 INT2
100K +REF -REF 100K
INTIN2
DEMOD1
DEMOD2
INTIN1
SCD5028-1 .1µf COMP +2.25V TIMING Cvco DEMOD G=0.9 ERROR HYSTERESIS 75nA UP/DOWN COUNTER DIGITAL OUTPUT Threshold 1.95V 20.5p G=14
RESOLVER
INPUT
RESOLVER INPUT [(S/T)+1] [(S/10T)+1]
FIGURE ACT5028B FUNCTIONAL BLOCK DIAGRAM
VELOCITY
DIGITAL OUTPUT
FIGURE ACT5028B TRANSFER FUNCTION DIAGRAM
-12dB/oct
Closed Loop Bandwidth (BWcl) (Hz) -G=4 -6dB/oct G/2) BWcl rad/sec
-12dB/oct
FIGURE ACT5028B OPEN LOOP BODE PLOT TRANSFER FUNCTION BODE PLOT
dynamic performance converter determined from Functional Block Diagram, Transfer Function Diagram Bode plots, shown Figures
PROCEDURE SELECTING BANDWIDTH COMPONENTS
Input: Carrier Frequency (Fc) 30,000 Input: Nominal Resolver Input Level Vrms [1Vrms min. 1.5Vrms max.] Input: Resolution bits; bits Input: Closed Loop Bandwidth (BWcl) bit; BWcl Fc/4 max.] bit; BWcl Fc/8 max.] bit; BWcl Fc/12 max.] bit; BWcl Fc/16 max. Input: Maximum Tracking Rate (RPS rotations second) bit; max.] bit, max.] bit; max.] bit, 1024 max.] Input: Hysteresis LSBs. Recommended bits LSBs bits. Nominal Resolver Input Level Nominal Resolver Input Level Nominal Resolver Input Level Nominal Resolver Input Level 2.22 BWcl 0.45 Hysteresis recommended values bit] bit] R1(ohms) Maximum Tracking Rate Maximum Tracking Rate Maximum Tracking Rate Maximum Tracking Rate R3(ohms) 109)/G2 G2/(EG
SCD5028-1
.0027 .011 .043
bit] bit] bit] bit]
bit] bit] bit] bit]
C2(farads) 1/(G1 C3(farads) C2/10 R2(ohms) 2/(G
ACT5028B EXAMPLE CALCULATIONS
Carrier Frequency Nominal Resolver Input Level 1.3Vrms Resolution bits Closed Loop Bandwidth (BWcl) Maximum Tracking Rate Hysteresis Nominal Resolver Input Level .011 bit] .011 .014 2.22 BWcl 2.22 44.4 bit] R1(ohms) .014 84K. closest standard resistor 84.5K Maximum Tracking Rate 8192 [213 bits] R3(ohms) 109)/G2 109)/8192 3,050K. closest standard resistor 3.01M 0.45 G2/(EG 44.42/(.014 8192) 38.2 C2(farads) 1/(G1 1/(38.2 84.5K) .31µF. closest standard capacitor .33µF C2/10(farads) C2/10 .33µ/10 .033µF R2(ohms) 2/(G 2/(44.4 .33µ) 136.5K. closest standard resistor 137K
SIGNAL REFERENCE INPUT CONDITIONING
Inputs converter should Vrms nominal, resolver format referenced nominal Figure shows various input configurations.
REFERENCE CONDITIONING
Most resolvers have LEADING input output phase shift. simple leading phase shift network (Figure Reference Conditioning) from resolver reference RDC's reference input will provide compensating phase shift required bring signals phase. resolver LAGGING input output phase shift lagging phase shift network (low pass network) would required. Note phase lead circuit input Demodulator (BPF1 BPF2) Figure should considered when calculating total system phase compensation. formula calculating phase shift network follows:
Phase angle ArcTan 6.28 FREF
Select convenient capacitor value perform following calculation determine proper resistor value.
(Tan (Phase Angle)) FREF 6.28
Software Program SW5028-2 available Aeroflex site.
SCD5028-1
+SIN +SIN +SIN -SIN -SIN +COS +COS +COS -COS -COS -COS -COS +COS -SIN -SIN
SCD5028-1 +SIN
+SIN
+SIN
+SIN
-SIN
-SIN
-SIN
+COS
+COS
+COS
-COS
-COS
-COS
DIRECT RESOLVER
SINGLE ENDED RESOLVER CONDITIONING
DIFFERENTIAL RESOLVER CONDITIONING
SYNCHRO CONDITIONING
+REF -REF +REF +REF
+REF
+REF -REF -REF
.1µF
4.7µF
2.5VDC
SINGLE ENDED REFERENCE CONDITIONING
DIFFERENTIAL REFERENCE CONDITIONING (FLOATING REFERENCE)
FIGURE ACT5028B RESOLVER, SYNCHRO REFERENCE INPUT CONFIGURATIONS
TABLE ACT5028B DESCRIPTIONS (CQFP PACKAGE)
FUNCTION DATA LOAD VCOIN INTIN2 INTIN1 INT1 INT2 +REF -REF BPF2 BPF1 DEMOD1 DEMOD2 FUNCTION -SIN +SIN -COS +COS (MSB) FUNCTION (LSB) ENABLE BUSY CW/CCW RIPPLE
SCD5028-1
+.02 .250
.956 .100
.600 ±.005
.017
.008
.023
.050
.005 .008 .063 ±.007
FIGURE CERAMIC QUAD FLAT PACKAGE (CQFP) OUTLINE
SCD5028-1
ERRATA INFORMATION
ACT5028-2-1-X
This Errata information represents known bugs, anomalies, work-arounds ACT5028 Resolver Digital Converter
DESCRIPTION ANOMALIES:
Anomaly Instability 360o 180o Input Angles Anomaly Correcting Integral Nonlinearity Error found Revision Silicon
EFFECTED PARTS:
ACT5028-2-1-X (revision silicon)
ANOMALY
PROBLEM DESCRIPTION:
This problem only occurs mode when rotating clockwise (CW) direction been observed 100% parts tested 25°C. occurs 100% time 360o approximately 180o. 360o problem occurs when counter passes from FFFF 0000 then reverse rotation (CCW) back FFFF. 180o problem occurs when counter passes from 7FFF 8000 then reverse rotation (CCW) back 7FFF. different failure modes have been observed: output latch locks value with inverted giving indication that chip 180o phase, chip exhibits zero error. This condition remains indefinitely until resolver rotates either direction count. which time chip responds 180o error which takes less than 150ms correct. chip sees immediate error 180o begins correct this error which takes less than 150ms. some cases been observed that next gets inverted which provides error. this case time required chip correct self less than
RECOMMENDED ACTIONS:
mode where this problem doesn't exist. Insure hysteresis least prevent this anomaly when rotating very slowly. Avoid reversing direction 360o 180o when rotating direction. resolver stops within counts 360o 180o wait 150ms after motion resumes before reading output.
SCD5028-1
ANOMALY
PROBLEM DESCRIPTION RECOMMENDED ACTION:
This Errata information address constant Integral Nonlinearity (INL) that exists each angle ACT5028B Resolver Digital Converter (RDC). This error repeatable from chip chip provides look Table offsets that must added output Resolver Digital Converter correct angle. Figure shows error Minutes that exists increments full 360o. Note that error from 180o basically same error between 180o 360o. Table angle correction factor Minutes) that must added zero error. simple calculation performed derive correction factor angles that fall between angles listed Table herein. Larger Angle Smaller Angle Correction Factor associated with larger Angle Correction Factor associated with smaller Angle Angle Correction Factor Formula: (((NA AS)) CS)) Example: Require correction factor 23.4009 (((15 14)) (24.0326 23.4009)) 23.4009 (((1) (2)) .6137) 23.4009 .6137) 23.4009 .31585 23.71675 minutes
SCD5028-1
Angle
Figure Anomaly Angle Error Chart
SCD5028-1
Minutes
Angle
Correction Factor 0.125244141 1.911621094 4.073730469 5.715087891 6.868652344 8.411132812 9.241699219 10.17114258 11.11376953 11.54882812 11.94433594 11.99707031 11.91137695 12.26733398 11.85205078 11.77954102 11.97070312 11.64770508 11.26538086 10.90942383 10.16455078 9.683349609 9.030761719 8.002441406 7.237792969 6.545654297 5.6953125 5.174560547 4.198974609 3.487060547 2.939941406 2.241210938 1.614990234 1.087646484 0.131835938 -0.547119141 -1.0546875 -1.549072266 -1.641357422 -1.977539063 -1.944580078 -1.766601563 -1.753417969 -1.0546875 -0.250488281
Angle
Correction Factor 0.415283203 1.153564453 1.977539062 2.537841797 2.814697266 3.071777344 2.735595703 2.656494141 2.478515625 1.885253906 1.285400391 0.837158203 -0.243896484 -0.626220703 -1.621582031 -2.168701172 -2.814697266 -3.460693359 -4.548339844 -4.871337891 -5.945800781 -6.842285156 -7.48828125 -8.582519531 -9.043945313 -9.887695313 -10.31616211 -10.73144531 -11.15332031 -11.43017578 -11.32470703 -11.64770508 -11.70043945 -11.71362305 -11.5949707 -11.58837891 -11.1862793 -10.79077148 -9.861328125 -8.971435547 -7.929931641 -6.512695313 -5.510742187 -3.697998047 -1.680908203
Angle
Correction Factor 0.145019531 1.997314453 3.981445312 5.754638672 6.822509766 8.411132813 9.221923828 10.19750977 11.09399414 11.44995117 11.97729492 12.01025391 11.88500977 12.19482422 12.10913086 11.82568359 11.92456055 11.64111328 11.22583008 10.89624023 10.13818359 9.650390625 8.984619141 7.969482422 7.218017578 6.492919922 5.682128906 5.174560547 4.185791016 3.520019531 2.887207031 2.181884766 1.588623047 1.114013672 0.171386719 -0.573486328 -1.074462891 -1.502929687 -1.628173828 -1.984130859 -1.957763672 -1.713867188 -1.694091797 -1.034912109 -0.283447266
Angle
Correction Factor 0.474609375 1.206298828 1.970947266 2.577392578 2.649902344 3.150878906 2.794921875 2.682861328 2.564208984 1.858886719 1.562255859 0.626220703 -0.171386719 -0.652587891 -1.496337891 -2.083007812 -2.649902344 -3.618896484 -4.403320313 -4.95703125 -5.879882812 -6.723632813 -7.461914063 -8.450683594 -8.918701172 -9.755859375 -10.29638672 -10.81054687 -11.29174805 -11.3972168 -11.44995117 -11.57519531 -11.65429688 -11.62792969 -11.62792969 -11.56201172 -11.12036133 -10.81713867 -9.834960938 -8.978027344 -7.883789063 -6.473144531 -5.444824219 -3.684814453 -1.654541016
Table Anomaly Correction Factor (Minutes)
SCD5028-1
ORDERING INFORMATION
AEROFLEX PART ACT5028-201-1S ACT5028-201-2S ACT5028-2-1-S ACT5028-2-1-7 ACT5028-2-1-I DESC 5962-0423501KXC 5962-0423501KXA SCREENING DSCC 5962-04235, Rev. Silicon Class Rev. Silicon Class Rev. Silicon Class Rev. Silicon PACKAGE CQFP
Notes first dash number indicates package style, CQFP. middle dash number indicates revision level, First four Part Numbers above initial release silicon, thus middle last dash number indicates testing level part: Class Commercial Flow, Commercial Temp. Range, +70oC testing Class Commercial Flow, Industrial Temp. Range, -40oC +85oC testing Class MIL-PRF-38534 Flow, -55oC +125oC testing (Rev. Silicon) Errata information Anomaly within this data sheet.
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Aeroflex Microelectronic Solutions reserves right change time without notice specifications, design, function, form products described herein. parameters must validated each customer's application engineering. liability assumed result this product. patent licenses implied.
SCD5028-1
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