16-Bit 24-Bit, 2/4/8-Channel ADCs with PGIA Input Current (100 pA
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CS5521/22/23/24/28
16-Bit 24-Bit, 2/4/8-Channel ADCs with PGIA
Input Current (100 pA), Chopper Stabilized Instrumentation Amplifier Scalable Input Span (Bipolar/Unipolar)
2.5V VREF: External:
General Description
CS5521/22/23/24/28 highly integrated Analog-to-Digital Converters (ADCs) which chargebalance techniques achieve 16-bit (CS5521/23) 24-bit (CS5522/24/28) performance. ADCs come either two-channel (CS5521/22), four-channel (CS5523/24), eight-channel (CS5528) devices, include input current, chopper-stabilized instrumentation amplifier. permit selectable input spans ADCs include (programmable gain amplifier). accommodate ground-based thermocouple applications, devices include Charge Pump Drive which provides negative bias voltage on-chip amplifiers. These devices also include fourth order modulator followed digital filter which provides eight selectable output word rates. digital filters designed settle full accuracy within conversion cycle when operated word rates below they reject both interference. These single supply products ideal solutions measuring isolated non-isolated, low-level signals process control applications.
Wide VREF Input Range Fourth Order Delta-Sigma Converter Easy Three-wire Serial Interface Port
Programmable/Auto Channel Sequencer with Conversion Data FIFO Accessible Calibration Registers Channel Compatible with SPIand Microwire
System Self-Calibration Eight Selectable Word Rates
(XIN kHz) Single Conversion Settling 50/60 Simultaneous Rejection
Single Power Supply Operation
Charge Pump Drive Negative Supply Digital Supply Operation
Power Consumption:
ORDERING INFORMATION page
AGND
VREF+ VREFX1
DGND
AIN1+ AIN1AIN2+ AIN2AIN3+ AIN3AIN4+ AIN4MUX
CS5524 Shown
Programmable Gain Differential Order Modulator Digital Filter
Data FIFO Calibration Register Control Register SCLK
Latch
Calibration Memory
Calibration
Clock Gen.
Output Register
XOUT
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS317F3
CS5521/22/23/24/28
TABLE CONTENTS
CHARACTERISTICS SPECIFICATIONS ANALOG CHARACTERISTICS TYPICAL NOISE, CS5521/23. TYPICAL NOISE FREE RESOLUTION (BITS), CS5521/23 TYPICAL NOISE, CS5522/24/28. TYPICAL NOISE FREE RESOLUTION (BITS), CS5522/24/28 DIGITAL CHARACTERISTICS. DIGITAL CHARACTERISTICS. DYNAMIC CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS SWITCHING CHARACTERISTICS GENERAL DESCRIPTION Analog Input 2.1.1 Instrumentation Amplifier 2.1.2 Coarse/Fine Charge Buffers 2.1.3 Analog Input Span Considerations 2.1.4 Measuring Voltages Higher than 2.1.5 Voltage Reference Overview Register Structure Operating Modes 2.2.1 System Initialization 2.2.2 Serial Port Initialization Sequence 2.2.3 Command Register Quick Reference 2.2.4 Command Register Descriptions 2.2.5 Serial Port Interface 2.2.6 Reading/Writing Offset, Gain, Configuration Registers 2.2.7 Reading/Writing Channel-Setup Registers 2.2.7.1 Latch Outputs 2.2.7.2 Channel Select Bits
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DS317F3
CS5521/22/23/24/28
2.2.7.3 Output Word Rate Selection 2.2.7.4 Gain Bits 2.2.7.5 Unipolar/Bipolar 2.2.8 Configuration Register 2.2.8.1 Chop Frequency Select 2.2.8.2 Conversion/Calibration Control Bits 2.2.8.3 Power Consumption Control Bits 2.2.8.4 Charge Pump Disable 2.2.8.5 Reset System Control Bits 2.2.8.6 Data Conversion Error Flags Calibration 2.3.1 Self Calibration 2.3.2 System Calibration 2.3.3 Calibration Tips 2.3.4 Limitations Calibration Range Performing Conversions Reading Data Conversion FIFO 2.4.1 Conversion Protocol 2.4.1.1 Single, One-Setup Conversion 2.4.1.2 Repeated One-Setup Conversions without Wait 2.4.1.3 Repeated One-Setup Conversions with Wait 2.4.1.4 Single, Multiple-Setup Conversions 2.4.1.5 Repeated Multiple-Setup Conversions without Wait 2.4.1.6 Repeated Multiple-Setup Conversions with Wait 2.4.2 Calibration Protocol 2.4.3 Example Using CSRs Perform Conversions Calibrations Conversion Output Coding 2.5.1 Conversion Data FIFO Descriptions Digital Filter Clock Generator Power Supply Arrangements 2.8.1 Charge Pump Drive Circuits Digital Gain Scaling 2.10 Getting Started 2.11 Layout DESCRIPTIONS Clock Generator Control Pins Serial Data Measurement Reference Inputs Power Supply Connections SPECIFICATION DEFINITIONS ORDERING GUIDE PACKAGE DIMENSION DRAWINGS
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LIST FIGURES
Figure Continuous Running SCLK Timing (Not Scale) Figure Write Timing (Not Scale) Figure Read Timing (Not Scale) Figure Multiplexer Configurations. Figure Input Models AIN+ AIN- pins, Input Ranges. Figure Input Models AIN+ AIN- pins, >100 input ranges Figure Input Ranges Greater than Figure Input Model VREF+ VREF- Pins. Figure CS5523/24 Register Diagram Figure Command Data Word Timing. Figure Self Calibration Offset (Low Ranges). Figure Self Calibration Offset (High Ranges) Figure Self Calibration Gain (All Ranges) Figure System Calibration Offset (Low Ranges) Figure System Calibration Offset (High Ranges) Figure System Calibration Gain (Low Ranges) Figure System Calibration Gain (High Ranges) Figure Filter Response (Normalized Output Word Rate Figure Typical Linearity Error CS5521/23 Figure Typical Linearity Error CS5522/24/28 Figure CS5522 Configured on-chip charge pump supply Figure CS5522 Configured ground-referenced Unipolar Signals. Figure CS5522 Configured Single Supply Bridge Measurement Figure Charge Pump Drive Circuit Figure Alternate Circuits
LIST TABLES
Table Relationship between Full Scale Input, Gain Factors, Internal Analog Signal Limitations Table Command Register Quick Reference. Table Channel-Setup Registers Table Configuration Register. Table Offset Gain Registers Table Output Coding 16-bit CS5521/23 24-bit CS5522/24/28
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CHARACTERISTICS SPECIFICATIONS
ANALOG CHARACTERISTICS VA+, ±5%; VREF+ VREF- AGND, -2.1 32.768 kHz, CFS1-CFS0 `00', (Output Word Rate) Bipolar Mode, Input Range ±100 Notes
CS5521/23 Parameter Accuracy Resolution Linearity Error Bipolar Offset Unipolar Offset Offset Drift Bipolar Gain Error Unipolar Gain Error Gain Drift Power Supplies Power Supply Currents (Normal Mode) (Note 5)ID+ INBV Power Consumption (Note Normal Mode Power Mode Standby Sleep Power Supply Rejection Positive Supplies (Note (Note (Note (Notes ±0.0015 ±0.003 Bits LSBN LSBN nV/°C ppm/°C ±0.0007 ±0.0015 CS5522/24/28 Unit
Notes: Applies after system calibration temperature within -40° +85° Specifications guaranteed design, characterization, and/or test. Specification applies device only does include effects external parasitic thermocouples. LSBN: CS5521/23 CS5522/24/28 Drift over specified temperature range after calibration power-up Measured with Charge Pump Drive off. outputs unloaded. input CMOS levels CS5521/23 have power mode.
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ANALOG CHARACTERISTICS (Continued)
Parameter Analog Input Common Mode Signal AIN+ AINBipolar/Unipolar Mode -1.8 -2.5 Range Range AGND Range (Note Range Current AIN+ AIN(Note Range Range Input Current Drift Range Input Leakage Multiplexer when Common Mode Rejection Input Capacitance Voltage Reference Input Range VREF+ VREFCVF Current Common Mode Rejection Input Capacitance System Calibration Specifications Full Scale Calibration Range (VREF 2.5V) Offset Calibration Range Bipolar/Unipolar Mode 0.40 Bipolar/Unipolar Mode ±12.5 ±27.5 ±0.5 ±1.25 ±2.50 32.5 71.5 1.30 3.25 (Note (VREF+) (VREF-)
(VREF-)+1
Unit
-0.150 1.85
0.950 2.65
(VREF+)-1
pA/°C
(Note
(Note
Notes: CS5528, ranges cannot used unless powered -1.8 -2.5 section data sheet which discusses input models. Chop clock (XIN/128) PGIA (programmable gain instrumentation amplifier). 32.768 kHz. maximum full scale signal limited saturation circuitry within internal signal path.
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TYPICAL NOISE, CS5521/23 (Notes
Output Rate Filter (Hz) Frequency 1.88 1.64 3.76 3.27 7.51 6.55 15.0 12.7 30.0 25.4 61.6 (Note 50.4 84.5 (Note 70.7 101.1 (Note 84.6 Input Range, (Bipolar/Unipolar Mode) 18.2 11.3 18.1
Notes: Wideband noise aliased into baseband. Referred input. Typical values shown estimate Peak-to-Peak Noise, multiply noise ranges output rates. input ranges <100 output rates 16.384 chopping frequency used.
TYPICAL NOISE FREE RESOLUTION (BITS), CS5521/23 (Note
Output Rate Filter (Hz) Frequency 1.88 1.64 3.76 3.27 7.51 6.55 15.0 12.7 30.0 25.4 61.6 (Note 50.4 84.5 (Note 70.7 101.1 (Note 84.6 Input Range, (Bipolar Mode)
Notes: bipolar mode, number bits Noise Free Resolution LOG((2XInput Range)/(6.6xRMS Noise))/LOG(2) rounded nearest bit. unipolar mode, number bits Noise Free Resolution LOG((Input Range)/(6.6xRMS Noise))/LOG(2) rounded nearest bit. Also, CS5521/23's output conversions bits. Noise free Resolution numbers based upon VREF 32.768 kHz. values will affected directly changes VREF, effects changes frequency will minor.
DS317F3
CS5521/22/23/24/28
TYPICAL NOISE, CS5522/24/28 (Notes
Output Rate Filter (Hz) Frequency 1.88 1.64 3.76 3.27 7.51 6.55 15.0 12.7 30.0 25.4 61.6 (Note 50.4 84.5 (Note 70.7 101.1 (Note 84.6 Input Range, (Bipolar/Unipolar Mode) 11.5
Notes: Wideband noise aliased into baseband. Referred input. Typical values shown estimate Peak-to-Peak Noise, multiply noise ranges output rates. input ranges <100 output rates 16.384 chopping frequency used.
TYPICAL NOISE FREE RESOLUTION (BITS), CS5522/24/28 (Note
Output Rate Filter (Hz) Frequency 1.88 1.64 3.76 3.27 7.51 6.55 15.0 12.7 30.0 25.4 61.6 (Note 50.4 84.5 (Note 70.7 101.1 (Note 84.6 Input Range, (Bipolar Mode)
Notes: bipolar mode, number bits Noise Free Resolution LOG((2XInput Range)/(6.6xRMS Noise))/LOG(2) rounded nearest bit. unipolar mode, number bits Noise Free Resolution LOG((Input Range)/(6.6xRMS Noise))/LOG(2) rounded nearest bit. Also, CS5522/24/28's output conversions bits. Noise free Resolution numbers based upon VREF 32.768 kHz. values will affected directly changes VREF, effects changes frequency will minor.
DS317F3
CS5521/22/23/24/28
DIGITAL CHARACTERISTICS VA+, ±5%;
Notes 18.)) Parameter High-Level Input Voltage Pins Except SCLK SCLK Pins Except SCLK SCLK Symbol (VD+)-0.5 (VD+) 0.45 (VA+) (VD+) (VD+) Cout Unit
Low-Level Input Voltage
High-Level Output Voltage Pins Except (Note CPD, Iout -4.0 SDO, Iout -5.0 Low-Level Output Voltage Pins Except SDO, Iout CPD, Iout SDO, Iout Input Leakage Current 3-State Leakage Current Digital Output Capacitance Notes: measurements performed under static conditions.
Iout -100 unless stated otherwise. (VOH Iout µA.)
DIGITAL CHARACTERISTICS ±5%; ±10%;
Notes 18.) Parameter High-Level Input Voltage Pins Except SCLK SCLK Pins Except SCLK SCLK Symbol (VD+)-0.5 (VD+) 0.45 (VA+) (VD+) (VD+) Cout 0.16 Unit
Low-Level Input Voltage
High-Level Output Voltage Pins Except SDO, Iout -400 CPD, Iout -4.0 SDO, Iout -5.0 Low-Level Output Voltage Pins Except SDO, Iout CPD, Iout SDO, Iout Input Leakage Current 3-State Leakage Current Digital Output Capacitance
DS317F3
CS5521/22/23/24/28
DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Frequency Filter Settling Time (Full Scale Step) Symbol Ratio XIN/4 1/fout Unit
RECOMMENDED OPERATING CONDITIONS (AGND, DGND Note 20.)
Parameter Power Supplies Analog Reference Voltage Negative Bias Voltage Notes: voltages with respect ground. Positive Digital Positive Analog (VREF+) (VREF-) Symbol VRefdiff 4.75 -1.8 -2.1 5.25 5.25 -2.5 Unit
ABSOLUTE MAXIMUM RATINGS (AGND, DGND Note 20.)
Parameter Power Supplies (Note Positive Digital Positive Analog Negative Potential (Note (Note VREF pins Pins Symbol IOUT VINR VINA VIND Tstg -0.3 -0.3 +0.3 -0.3 -0.3 -0.3 -2.1 +6.0 +6.0 -3.0 (VA+) (VA+) (VD+) Unit
Negative Bias Voltage Input Current, Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: should more negative than Applies pins including continuous overvoltage conditions analog input (AIN) pins. Transient current will cause latch-up. Maximum input current power supply Total power dissipation, including input currents output currents. WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
DS317F3
CS5521/22/23/24/28
SWITCHING CHARACTERISTICS ±5%; ±10% ±5%;
Levels: Logic Logic VD+; pF.)) Parameter Master Clock Frequency (Note External Clock Internal Oscillator (CS5522/24/28) (CS5521/23) Master Clock Duty Cycle Rise Times (Note Digital Input Except SCLK SCLK Digital Output (Note Digital Input Except SCLK SCLK Digital Output XTAL 32.768 (Note trise tfall tost tpor 2006 cycles Symbol 32.768 32.768 Unit
Fall Times
Start-up Oscillator Start-up Time Power-on Reset Period Serial Port Timing Serial Clock Frequency SCLK Falling Falling continuous running SCLK (Note Serial Clock Write Timing Enable Valid Latch Clock Data Set-up Time prior SCLK rising Data Hold Time After SCLK Rising SCLK Falling Prior Disable Read Timing Data Valid SCLK Falling Data Rising Hi-Z Pulse Width High Pulse Width SCLK
Notes: Device parameters specified with 32.768 clock; however, clocks (CS5522/24/28) (CS5521/23) used increased throughput. Specified using points waveform interest. Output loaded with Oscillator start-up time varies with crystal parameters. This specification does apply when using external clock source. Applicable when SCLK continuously running.
Specifications subject change without notice.
DS317F3
CS5521/22/23/24/28
SCLK
Figure Continuous Running SCLK Timing (Not Scale)
SCLK
Figure Write Timing (Not Scale)
SCLK
Figure Read Timing (Not Scale)
DS317F3
CS5521/22/23/24/28
GENERAL DESCRIPTION
CS5521/22/23/24/28 highly integrated Analog-to-Digital Converters (ADCs) which charge-balance techniques achieve 16-bit (CS5521/23) 24-bit (CS5522/24/28) performance. ADCs come either two-channel (CS5521/22), four-channel (CS5523/24), eightchannel (CS5528) devices, include input current, chopper-stabilized instrumentation amplifier. permit selectable input spans ADCs include (programmable gain amplifier). accommodate ground-based thermocouple applications, devices include (Charge Pump Drive) which provides negative bias voltage on-chip amplifiers. These devices also include fourth order modulator followed digital filter which provides eight selectable output word rates 1.88 3.76 7.51 61.6 84.5 101.1 (XIN 32.768 kHz). devices capable producing output update rates when clock used (CS5522/24/28) using clock (CS5521/23). Further note that digital filters designed settle full accuracy within conversion cycle simultaneously reject both interference when operated word rates below (assuming clock frequency 32.768 kHz). ease communication between ADCs micro-controller, converters include easy three-wire serial interface which SPIand Microwirecompatible.
Analog Input
Figure illustrates block diagram analog input signal path inside CS5521/22/23/24/28. front consists multiplexer (break before make configuration), chopper-stabilized instrumentation amplifier with fixed gain 20X, coarse/fine charge buffers, programmable gain section. input ranges, input signals amplified instrumentation amplifier. input ranges, instrumentation amplifier bypassed input signals connected Programmable Gain block coarse/fine charge buffers.
AIN2+ AIN2AIN1+ AIN1-
CS5522
VREF+ VREF-
AIN4+ AIN4* AIN1+ AIN1-
CS5524 ININCS5528 Programmable Gain Differential order delta-sigma modulator Digital Filter
AIN8+ AIN7+ AIN1+
also supplies negative supply voltage coarse/fine change buffers
Figure Multiplexer Configurations DS317F3
CS5521/22/23/24/28
2.1.1 Instrumentation Amplifier
instrumentation amplifier chopper stabilized activated time conversions performed with level input ranges, amplifier powered from from (Negative Bias Voltage) allowing CS5521/22/23/24/28 operated either analog input configurations. biased negative voltage between -1.8 tied AGND (for CS5528, between -1.8 -2.5 ranges below when amplifier engaged). common-mode plus signal range instrumentation amplifier 1.85 2.65 with grounded. common-mode plus signal range instrumentation amplifier -0.150 0.950 with between -1.8 -2.5 Whether tied between -1.8 -2.5 tied AGND, (Common Mode Signal) input AIN+ AIN- must stay between VA+. Figure illustrates analog input model ADCs when instrumentation amplifier engaged. (sampling) input current each analog input pins depends CFS1 CFS0 (Chop Frequency Select) bits configuration register (see Configuration Register details). Note that current lowest with
bits their default states (cleared logic 0s). Further note that current into instrumentation amplifier less than over -40°C +85°C. Note that Figure input current modeling only. physical input capacitance `Input Capacitance' specification under ANALOG CHARACTERISTICS. Also refer Applications Note AN30 "Switched-Capacitor Converter Input Structures" more details input models input sampling currents.
Note: Residual noise appears converter's baseband output word rates greater than 61.6 bits logic (chop clock Hz). word rates lower, chopping recommended, 61.6 84.5 101.1 filters, 4096 chopping recommended.
2.1.2 Coarse/Fine Charge Buffers
unity gain buffers activated time conversions performed with high level inputs ranges, unity gain buffers designed accommodate rail rail input signals. common-mode plus signal range unity gain buffer amplifier VA+. Typical (sampling) current unity gain buffer amplifiers about (XIN 32.768 kHz, Figure
anges
6.384
oars
2.768
Figure Input Models AIN+ AIN- pins, (100 Input Ranges
Figure Input Models AIN+ AIN- pins, >100 input ranges
DS317F3
CS5521/22/23/24/28
2.1.3 Analog Input Span Considerations
CS5521/22/23/24/28 designed measure full scale ranges Other full scale values accommodated performing system calibration within limits specified. Calibration section more details. Another change full scale range increase decrease voltage reference voltage other than Voltage Reference section more details. Three factors operating limits input span. They include: instrumentation amplifier saturation, modulator density, lower reference voltage. When range selected, input signal (including common mode voltage amplifier offset voltage) must cause amplifier saturate either input stage output stage. prevent saturation absolute voltages AIN+ AINmust stay within limits specified (refer Analog Input section). Additionally, differential output voltage amplifier must exceed equation ABS(VIN VOS) defines differential output limit, where (AIN+) (AIN-)
Input Range(1) Max. Differential Output Amplifier
differential input voltage absolute maximum offset voltage instrumentation amplifier (VOS will exceed mV). differential output voltage from amplifier exceeds amplifier saturate, which will cause measurement error. input voltage into modulator must cause modulator exceed percent high percent density. nominal full scale input span modulator (from percent percent density) determined VREF voltage divided Gain Factor. Table determine CS5521/22/23/24/28 being used properly. example, range, determine nominal input voltage modulator, divide VREF (2.5 Gain Factor (2.2727). When smaller voltage reference used, resulting code widths smaller causing converter output codes exhibit more changing codes fixed amount noise. Table based upon VREF other values VREF, values Table must scaled accordingly.
2.1.4 Measuring Voltages Higher than
Some systems require measurement voltages greater than input current instruVREF 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V Gain Factor 2.272727. 1.25 Nominal(1) Differential Input -(1) Max. Input 0.75 1.65
Table Relationship between Full Scale Input, Gain Factors, Internal Analog Signal Limitations Note: converter's actual input range, delta-sigma's nominal full scale input, delta-sigma's maximum full scale input scale directly with value voltage reference. values table assume VREF voltage. limit output amplifier differential output voltage.
DS317F3
CS5521/22/23/24/28
mentation amplifier, typically enough permit large external resistors divide down large external signal without significant loading. Figure illustrates example circuit. Refer Applications Note more details high voltage measurement.
Overview Register Structure Operating Modes
CS5521/22/23/24/28 ADCs have on-chip controller, which includes number user-accessible registers. registers used hold offset gain calibration results, configure chip's operating modes, hold conversion instructions, store conversion data words. Figure depicts block diagram on-chip controller's internal registers CS5523/24. Each converters 24-bit registers function offset gain calibration registers each channel. converters with channels have offset gain calibration registers, converters with four channels have four offset four gain calibration registers, eight channel converter eight offset eight gain calibration registers. These registers hold calibration results. contents these registers read written user. This allows calibration data off-loaded into external EEPROM. user also manipulate contents these registers modify offset gain slope converter. converters include 24-bit configuration register which bits used setting options such conversion mode, operating power options, setting chop clock rate instrumentation amplifier, providing number flags which indicate converter operation.
2.1.5 Voltage Reference
CS5521/22/23/24/28 specified operation with reference voltage between VREF+ VREF- pins device. singleended reference voltage, such LT1019-2.5, reference voltage input into VREF+ converter VREF- grounded. differential voltage between VREF+ VREF- voltage from VA+, however, VREF+ cannot above VREF- below NBV. Figure illustrates input models VREF pins. dynamic input current each pins determined from models shown.
VREF+ VREF1 ±10V Voltage Divider PGIA
PGIA chop clock
Charge Pump Regulator
32.768
-2.1 BAT85 1N4148 0.033
DGND
VREF
1N4148
Charge Pump Circuitry
Figure Input Ranges Greater than
Figure Input Model VREF+ VREF- Pins
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CS5521/22/23/24/28
group registers, called Channel Set-up Registers, also included converters. These registers used hold pre-loaded conversion instructions. Each channel set-up register bits long holds 12-bit conversion instructions (Setups). Upon power these registers initialized users' microcontroller with conversion instructions. user then bits configuration register choose conversion mode. Several conversion modes possible. Using single conversion mode, 8-bit command word written into serial port. command includes pointer bits which `point' 12-bit command Channel Setup Registers which executed. 12-bit commands setup perform conversion input channels converter. More than 12bit Setups used same analog input channel. This allows user convert same signal with either different conversion speed, different gain range, other options available Setup Register. user registers perform different conversion conditions each input channels. ADCs also include multiple channel conversion capability. User bits configuration register ADCs configured sequence through 12-bit command Setups, performing conversion according content each 12-bit Setup. This channel scanning capability configured continuously, scan through specified number Setup Registers stop until commanded continue. multiple channel scanning modes, conversion data words loaded into on-chip data FIFO. converter issues flag when scan cycle completed user read FIFO. More details given following pages. Instructions provided initialize converter, perform offset gain calibrations, configure converter various conversion modes. Each bits configuration register Channel Setup Registers described. list examples follows description section. Table used decode valid commands (the first 8-bits into serial port).
AIN1 AIN2 AIN3 AIN4
(24) Configuration
(24) Gain Gain Gain Gain
Setup Setup Setup Setup Setup Setup Setup Setup
DATA FIFO
Chop Frequency Multiple Conversions Depth Pointer Loop Read Convert Powerdown Modes Flags Etc.
Latch Outputs Channel Select Output Word Rate Selection Unipolar/Bipolar
Figure CS5523/24 Register Diagram
DS317F3
CS5521/22/23/24/28
2.2.1 System Initialization
When power CS5521/22/23/24/28 applied, chips held reset condition until 32.768 oscillator started countertimer elapses. high 32.768 crystal, oscillator takes 400-600 start. counter-timer counts 2006 oscillator clock cycles make sure oscillator fully stable. During this time-out period serial port logic reset (Reset Valid) configuration register indicate that valid reset occurred. After reset, on-chip registers initialized following states converter placed command mode where waits valid command.
configuration register: offset registers: gain registers: channel setup registers: 000040(H) 000000(H) 400000(H) 000000(H) Note: system reset initiated time writing logic (Reset System) configuration register. After reset, until configuration register read. user must then write logic take part reset mode. other bits written configuration register this time will lost. configuration register must written again once other bits.
2.2.2 Serial Port Initialization Sequence
serial port initialized command mode whenever power-on reset performed inside converter, when user transmits port initialization sequence. port initialization sequence involves clocking bytes 1's, followed byte with following contents `11111110'. This sequence places chip command mode where waits valid command written.
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CS5521/22/23/24/28
2.2.3 Command Register Quick Reference
D7(MSB) D6-D4 NAME Command Bit, Channel Select Bits, CSB2-CSB0 VALUE RSB2 RSB1 RSB0 FUNCTION Must logic these commands. table below. CS2-CS0 provide address eight physical channels. These bits used access calibration registers associated with respective channels. Note: These bits ignored when reading data register. Write selected register. Read from selected register. Reserved Offset Register Gain Register Configuration Register Channel Set-up Registers register 48-bits long CS5521/22 register 96-bits long CS5523/24 register 192-bits long CS5528 Reserved Reserved FUNCTION table above. Must logic these commands. These bits used pointers Setups. Note: bit, must logic these bits take effect. When these bits ignored. bits configuration register ignored during calibration. Normal Conversion Self-Offset Calibration Self-Gain Calibration Reserved Reserved System-Offset Calibration System-Gain Calibration Reserved
D2-D0
Read/Write, Register Select Bit, RSB2-RSB0
D7(MSB) D6-D3 CSRP3 CSRP2 NAME Command Bit, Channel Pointer Bits, CSRP3-CSRP0 CSRP1 CSRP0 VALUE 0000 1111
D2-D0
Conversion/Calibration Bits, CC2-CC0
Table Command Register Quick Reference
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CS5521/22/23/24/28
2.2.4 Command Register Descriptions
READ/WRITE INDIVIDUAL OFFSET CALIBRATION REGISTER
D7(MSB)
Function:
These commands used access each offset register separately. decode registers accessed.
Write selected register. Read from selected register.
(Read/Write)
CS[2:0] (Channel Select Bits)
Offset Register 1(All devices) Offset Register (All devices) Offset Register (CS5523/24/28 only) Offset Register (CS5523/24/28 only) Offset Register (CS5528 only) Offset Register (CS5528 only) Offset Register (CS5528 only) Offset Register (CS5528 only)
READ/WRITE INDIVIDUAL GAIN REGISTER
D7(MSB)
Function:
These commands used access each gain register separately. decode registers accessed.
Write selected register. Read from selected register.
(Read/Write)
CS[2:0] (Channel Select Bits)
Gain Register 1(All devices) Gain Register (All devices) Gain Register (CS5523/24/28 only) Gain Register (CS5523/24/28 only) Gain Register (CS5528 only) Gain Register (CS5528 only) Gain Register (CS5528 only) Gain Register (CS5528 only)
DS317F3
CS5521/22/23/24/28
READ/WRITE CONFIGURATION REGISTER
D7(MSB)
Function:
These commands used read from write configuration register.
Write selected register. Read from selected register.
(Read/Write)
READ/WRITE CHANNEL-SETUP REGISTER(S)
D7(MSB)
Function:
These commands used access channel-setup registers (CSRs). number CSRs accessed determined device being used number CSRs that being accessed (i.e. depth bits configuration register determine number levels accessed). This register 48-bits long Setups) CS5521/22, 96-bits long Setups) CS5523/24, 192-bits Setups) long CS5528.
Write selected register. Read from selected register.
(Read/Write)
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PERFORM CONVERSION
D7(MSB) CSRP3 CSRP2 CSRP1 CSRP0
Function:
These commands instruct perform conversions physical input channel pointed pointer bits (CSRP2 CSRP0) channel-setup registers. particular type conversion performed determined states conversion control bits (the multiple conversion bit, loop bit, read convert bit, depth pointer bits) configuration register.
Setup (All devices) Setup (All devices) Setup (All devices) Setup (All devices) Setup (CS5523/24/28) Setup (CS5523/24/28) Setup (CS5523/24/28) Setup (CS5523/24/28) Setup (CS5528 only) Setup (CS5528 only) Setup (CS5528 only) Setup (CS5528 only) Setup (CS5528 only) Setup (CS5528 only) Setup (CS5528 only) Setup (CS5528 only)
CSRP [3:0] (Channel Setup Register Pointer Bits)
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
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PERFORM CALIBRATION
D7(MSB) CSRP3 CSRP2 CSRP1 CSRP0
Function:
These commands instruct perform calibration physical input channel referenced which chosen command byte pointer bits (CSRP3 CRSP0).
Setup (All devices) Setup (All devices) Setup (All devices) Setup (All devices) Setup (CS5523/24/28 only) Setup (CS5523/24/28 only) Setup (CS5523/24/28 only) Setup (CS5523/24/28 only) Setup (CS5528 only) Setup (CS5528 only) Setup (CS5528 only) Setup (CS5528 only) Setup (CS5528 only) Setup (CS5528 only) Setup (CS5528 only) Setup (CS5528 only)
CSRP [3:0] (Channel Setup Register Pointer Bits)
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
[2:0] (Calibration Control Bits)
Reserved Self-Offset Calibration Self-Gain Calibration Reserved Reserved System-Offset Calibration System-Gain Calibration Reserved
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SYNC1
D7(MSB)
Function: SYNC0
D7(MSB)
Part serial port re-initialization sequence.
Function: NULL
D7(MSB)
serial port re-initialization sequence.
Function:
This command used clear port flag keep converter continuous conversion mode.
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2.2.5 Serial Port Interface
CS5521/22/23/24/28's serial interface consists four control lines: SCLK, SDI, SDO. Figure illustrates serial sequence necessary write read from serial port's registers. Chip Select, control line which enables access serial port. tied low, port function three wire interface. SDI, Serial Data data signal used transfer data converters. SDO, Serial Data Out, data signal used transfer output data from converters. output will held high impedance time logic SCLK, Serial Clock, serial bit-clock which controls shifting data from ADC's serial port. must held (logic before SCLK transitions recognized port logic. accommodate optoisolators SCLK designed with Schmitt-trigger input allow optoisolator with slower rise fall times directly drive pin. Additionally, capable sinking sourcing directly drive optoisolator LED. will have less than loss drive voltage when sinking sourcing
SCLK
Command Time SCLKs
Data Time SCLKs
Write Cycle
SCLK
Command Time SCLKs
Data Time SCLKs
Read Cycle
SCLK
Command Time SCLKs
XIN/OWR Clock Cycles SCLKs Clear Flag
XIN/OWR clock cycles each conversion except first conversion which will take XIN/OWR clock cycles
Data Time SCLKs
Figure Command Data Word Timing DS317F3
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2.2.6 Reading/Writing Offset, Gain, Configuration Registers
CS5521/22/23/24/28's offset, gain, configuration registers accessed individually read from written write offset, gain, configuration register, user must transmit appropriate write command which accesses particular register then follow that command bits data (refer Figure details). example, write 0x800000 (hexadecimal) physical channel one's gain register, user would transmit command byte 0x02 (hexadecimal) then follow that command byte with data 0x800000 (hexadecimal). Similarly, read physical channel one's gain register, user must first transmit command byte 0x0A (hexadecimal) then read bits data. Once offset, gain, configuration register written read from, serial port returns command mode. Once programmed they used determine mode (e.g. unipolar, range etc.) will operate when future conversions calibrations performed. access CSRs, user must first initialize depth pointer bits configuration register these bits determine number CSRs read from write example, write CSR1 (Setup1 Setup2), user would first program configuration register's depth pointer bits with `0001' binary. This notifies ADC's serial port that only first accessed. Then, user would transmit write command, 0x05 (hexadecimal) follow that command with 24bits data. Similarly, read CSR1, user must transmit command byte 0x0D (hexadecimal) then read bits data. write more than CSR, instance CSR1 CSR2 (Setup1, Setup2, Setup3 Setup4), user would first depth pointer bits configuration register `0011' binary. user would then transmit write command 0x05 (hexadecimal) follow that with information Setup1, Setup2, Setup Setup which 48-bits information. Note that while reading/writing CSRs, Setups accessed pairs single 24-bit register. Even Setups isn't used, must written read. Further note that CSRs accessed closed array, user access CSR2 without accessing CSR1. This requirement means that depth bits configuration register only following states when CSRs being read from written 0001, 0011, 0101, 0111, 1001, 1011, 1101, 1111. Examples detailing power CSRs provided Performing Conversions Reading Data Conversion FIFO section. Once CSRs written read from, serial port returns command mode.
2.2.7 Reading/Writing Channel-Setup Registers
CS5521/22 have 24-bit channel-setup registers (CSRs). CS5523/24 have four CSRs, CS5528 eight CSRs (refer Table more detail CSRs). These registers accessed conjunction with depth pointer bits configuration register. Each contains 12-bit Setups which programmed user contain data conversion calibration information such state output latch pins output word rate gain range polarity address physical input channel converted.
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(Channel-Setup Register) Setup Bits <47:36> Setup Bits <23:12> Setup Bits <35:24> Setup Bits <11:0>
Setup Setup Bits <95:84> Bits <83:72>
Setup Setup Bits <191:180> Bits <179:168>
CS5521/22
Setup Setup Bits <23:12> Bits <11:0> CS5523/24
Setup Bits <23:12> CS5528
Setup Bits <11:0>
D23(MSB)
NAME
FUNCTION
VALUE
D23-D22/ Latch Outputs, A1-A0 D11-D10 D21-D19/ Channel Select, CS2D9-D7
Latch Output Pins A1-A0 mimic D23/D11-D22/D10 register bits. Select physical channel (All devices) Select physical channel 2(All devices) Select physical channel (CS5523/24/28 only) Select physical channel (CS5523/24/28 only) Select physical channel (CS5528 only) Select physical channel (CS5528 only) Select physical channel (CS5528 only) Select physical channel (CS5528 only) 15.0 (2180 cycles). 30.0 (1092 cycles). 61.6 (532 cycles). 84.5 (388 cycles). 101.1 (324 cycles). 1.88 (17444 cycles). 3.76 (8724 cycles). 7.51 (4364 cycles). (assumes VREF Differential used. used. Bipolar measurement mode. Unipolar measurement mode.
D18-D16/ Word Rate, WR2-WR0 D6-D4
D15-D13/ Gain Bits, G2-G0 D3-D1
D12/D0
Unipolar/Bipolar,
indicates value after part reset
Table Channel-Setup Registers
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2.2.7.1 Latch Outputs
A1-A0 pins mimic latch output, D23/D11D22/D10, bits channel-setup registers. A1-A0 used control external multiplexers other logic functions outside converter. outputs sink source least recommended limit drive currents less than reduce self-heating chip. These outputs powered from VA+, hence, their output voltage logic will limited supply voltage.
2.2.8 Configuration Register
configuration register 24-bits long. following subsections detail bits configuration register. Table summarizes configuration register.
2.2.8.1 Chop Frequency Select
chop frequency select (CFS1-CFS0) bits used rate which instrumentation amplifier's chop switches modulate input signal. rate desirable provides lowest input (sampling) current, <300 over higher rates used eliminate modulation/aliasing effects frequency input signal increases.
2.2.7.2 Channel Select Bits
channel select, CS1-CS0, bits used determine which physical input channel will used when conversion performed with particular Setup.
2.2.8.2 Conversion/Calibration Control Bits
conversion/calibration control bits configuration register used control particular type conversion required users applications. short, depth pointer (DP3-DP0) bits determine number Setups that will referenced when conversions performed. multiple conversion (MC) instructs converter perform conversions number Setups channel-setup registers which referenced depth pointer bits. converter begins with Setup1 moves sequentially through Setups this mode. Loop (LP) instructs converter continuously perform conversions until stop command sent converter. read convert (RC) instructs converter wait until conversion data read before performing next conversion conversions.
2.2.7.3 Output Word Rate Selection
word rate, WR2-WR0, bits channel-setup registers output conversion word rate converter when conversion performed with particular Setup. word rates indicated Table assume master clock 32.768 kHz, scale linearly when using other master clock frequencies. Upon reset converter operate with output word rate 15.0
2.2.7.4 Gain Bits
gain bits, G2-G0, channel-setup registers full scale differential input range when conversion performed with particular Setup. input ranges table assume reference voltage, scale linearly when using other reference voltages.
2.2.7.5 Unipolar/Bipolar
unipolar/bipolar used determine type conversion, unipolar/bipolar, that will performed with particular Setup.
2.2.8.3 Power Consumption Control Bits
CS5522/24/28 accommodate four power consumption modes: normal, power, standby, sleep. CS5521/23 accommodate three power consumption modes: normal, standby, sleep. normal (default) mode entered after poweron-reset. normal mode, CS5522/24/28 typiDS317F3
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cally consume CS5521/23 typically consume power mode alternate mode CS5522/24/28 that reduces consumed power entered setting (the power mode bit) configuration register logic Slightly degraded noise linearity performance should expected power mode. Note that clock should exceed power mode. final modes accommodated devices referred power save modes. They power down most analog portion chip stop filter convolutions. power save modes entered whenever PS/R configuration register logic particular power save mode entered depends state (PSS, Power Save Select bit) configuration register. logic converters enters standby mode reducing power consumption standby mode leaves oscillator onchip bias generator running. This allows converter quickly return normal power mode once PS/R back logic PS/R configuration register logic sleep mode entered reducing consumed power around Since sleep mode disables oscillator, approximately 500ms oscillator start-up delay period required before returning normal power mode. configuration register. After system reset cycle complete, reset valid (RV) indicating that internal logic properly reset. remains until configuration register read. Note that user must write logic take part reset mode. other bits configuration register written this time. subsequent write configuration register necessary write other bits this register. Once reset, on-chip registers initialized following states.
configuration register: offset registers: gain registers: channel setup registers: 000040(H) 000000(H) 400000(H) 000000(H)
2.2.8.6 Data Conversion Error Flags
oscillation detect (OD) over flow (OF) bits configuration register flag bits used indicate that performed conversion input signal that within conversion range ADC. convenience, bits also data conversion word CS5521/23. logic when input signal more positive than full scale more negative than zero unipolar mode, more negative than negative full scale bipolar mode. flag cleared logic when conversion occurs which range. logic time that oscillatory condition detected modulator. This does occur under normal operating conditions, occur when input extremely overranged. flag will cleared logic when modulator becomes stable.
2.2.8.4 Charge Pump Disable
pump disable (PD) permits user turn charge pump drive thus enabling user reduce radiation digital interference from when charge pump being used.
2.2.8.5 Reset System Control Bits
reset system (RS) permits user perform system reset. system reset initiated time writing logic
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D23(MSB) D23-D22 D21-D20
CFS1 PS/R NAME
CFS0
FUNCTION
VALUE Must always logic
Used, Chop Frequency Select, CFS1-CFS0
Amplifier chop frequency. 4,096 Amplifier chop frequency. 16,384 Amplifier chop frequency. 1,024 Amplifier chop frequency. Must always logic
(XIN 32.768 kHz)
Used, Multiple Conversion,
Perform single-Setup conversions. ignored during calibrations. Perform multiple-Setup conversions Setups channel-setup register issuing only command with conversions single Setup multiple Setups performed only once. conversions single Setup multiple Setups continuously performed. Don't wait user finish reading data before starting conversions. used conjunction with when logic ignored. waits user read data conversion(s) before converting again. ignored during calibrations. Refer Calibration Protocol details. When writing reading CSRs, these bits (DP3-DP0) determine number CSR's accessed (0000=1). They also used determine many Setups converted when MC=1 command byte with issued. Note that CS5522 CSRS, CS5524 four CSRs, CS5528 CSRs. Standby Mode (Oscillator active, allows quick power-up). Sleep Mode (Oscillator inactive). Charge Pump Enabled. goes Hi-Z output state. Run. Power Save. Normal Mode (LPM only CS5522/24/28) Reduced Power Mode Normal Operation. Activate Reset cycle. return Normal Operation write zero. reset occurred been cleared (read only). after Valid Reset occurred. (Cleared when read.) clear when oscillation condition occurred (read only). when oscillatory condition detected modulator. clear when overrange condition occurred (read only). when input signal more positive than positive full scale, more negative than zero (unipolar mode), when input more negative than negative full scale (bipolar mode). Must always logic
Loop,
Read Convert,
D15-D12
Depth Pointer, DP3-DP0
0000 1111
Power Save Select, Pump Disable, Power Save/Run, PS/R Power Mode, Reset System, Reset Valid, Oscillation Detect, Overrange Flag,
D3-D0
Used,
0000
indicates value after part reset Table Configuration Register DS317F3
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Calibration
CS5521/22/23/24/28 offer four different calibration functions including self calibration system calibration. However, after devices reset, converter functional perform measurements without being calibrated. this case, converter will utilize initialized values on-chip registers (Gain 1.0, Offset 0.0) calculate output words ±100 range. initial offset gain errors internal circuitry chip will remain. gain offset registers, which used both self system calibration, used zero full-scale points converter's transfer function. offset register 2-24 proportion input span when gain register decimal (bipolar span times unipolar span). offset register determines offset trimmed positive negative positive, negative). converter typically trim percent input span. gain register spans from 2-22). decimal equivalent meaning gain register
where binary numbers have value either zero corresponds MSB-1, N=22). Refer Table details. offset gain calibration steps each take conversion cycle complete. calibration step, falls indicate that calibration finished.
2.3.1 Self Calibration
CS5521/22/23/24/28 offer both self offset self gain calibrations. self-calibration offset ranges, converters internally inputs instrumentation amplifier together route them AIN- shown Figure CS5528 they routed AGND). proper self-calibra-
Offset Register
Register
Reset
Sign
2-20 2-21 2-22 2-23 2-24
2-19
represents 2-24 proportion input span when gain register decimal (bipolar span times unipolar span) Offset data word bits align (bit MSB-4 offset register changes MSB-4 data)
Gain Register
Register
Reset
2-18 2-19 2-20 2-21 2-22
2-17
gain register span from (4-2-22). After Reset (MSB-1) other bits
Table Offset Gain Registers
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tion offset occur ranges, AIN- must proper common-mode-voltage specified `Common Mode +Signal AIN+/-' specification Analog Input section AIN- must between -1.8 -2.5 self-calibration offset ranges, inputs modulator connected together then routed VREF- shown Figure self-calibration gain, differential inputs modulator connected VREF+ VREF- shown Figure input range other than range, converter's gain error completely calibrated when using self-calibration. This lack accurate full scale voltage internal chips. range exception because external reference voltage nominal used full scale voltage. addition, when self-calibration gain performed input ranges, instrumentation amplifier's gain calibrated. These factors leave converters with gain error ±20% after self-calibration gain. Therefore, system gain calibration required better accuracy, except range.
2.3.2 System Calibration
system calibration functions, user must supply calibration signals converter which represent ground full scale. When system offset calibration performed, ground referenced signal must applied converters. Figures shown Figures user must input signal representing positive full scale point
OPEN AIN+ CLOSED AIN+
OPEN CLOSED OPEN CLOSED AIN+ AINVREF+
Figure Self Calibration Offset (Low Ranges)
Figure Self Calibration Offset (High Ranges)
OPEN AIN+ AINVREF+ Reference VREFCLOSED
External Connections AINAIN+
OPEN
CLOSED
Figure Self Calibration Gain (All Ranges)
Figure System Calibration Offset (Low Ranges)
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perform system gain calibration. either case, calibration signals must within specified calibration limits each specific calibration step (refer `System Calibration Specifications' ANALOG CHARACTERISTICS). system gain calibration performed following conditions must met:
External Connections AIN+ AINX20
density modulator must greater than percent (the input modulator must exceed maximum input which Table specifies). input must small relative range chosen that resulting gain register's content, decoded decimal, exceeds 3.9999998 (see discussion operating limits input span under Analog Input Limitations Calibration Range sections). This requires full scale input voltage modulator least percent nominal value. converter's input ranges were chosen guarantee gain calibration accuracy LSB16 LSB24 when system gain calibration performed. This useful when user wants manually scale full scale range converter maintain accuracy. example, gain calibration performed with full scale voltage 1.25 input range desired, user read contents gain register, shift register contents left bit, then write result back gain register. This multiples gain Assuming system provide known voltages, following equations allow user manually compute calibration register's values based uncalibrated conversions (see note). offset gain calibration registers used adjust typical conversion follows: 222. Calibration performed using following equations: (Rc0/G Ru0) where (Rc1 Rc0)/(Ru1-Ru0).
Note: Uncalibrated conversions imply that gain offset registers default {gain register 0x400000 (Hex) offset register 0x000000 (Hex)}.
Figure System Calibration Offset (High Ranges)
External Connections AIN+ Full Scale
AIN-
Figure System Calibration Gain (Low Ranges)
External Connections AIN+ Full Scale
AIN-
Figure System Calibration Gain (High Ranges)
Full-scale input must saturate instrumentation amplifier, calibration input range where instrumentation amplifier involved.
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variables defined below.
First calibration voltage Second calibration voltage (greater than Result uncalibrated conversion Result uncalibrated conversion (24-bit integer complement) Result uncalibrated conversion (24-bit integer complement) Result conversion Desired calibrated result converting (24-bit integer complement) Desired calibrated result converting (24-bit integer complement) Offset calibration register value (24-bit complement) Gain calibration register value (24-bit integer)
2.3.4 Limitations Calibration Range
System calibration limited signal headroom analog signal path inside chip discussed under Analog Input section this data sheet. gain calibration full scale input signal reduced point which gain register reaches upper limit (4-2-22 decimal) FFFFFF (hexadecimal). Under nominal conditions, this occurs with full scale input signal equal about nominal full scale. With converter's intrinsic gain error, this full scale input signal higher lower. defining minimum Full Scale Calibration Range (FSCR) under ANALOG CHARACTERISTICS, margin retained accommodate intrinsic gain error. Alternatively input full scale signal increased point which modulator reaches density limit percent, which under nominal condition occurs when full scale input signal times nominal full scale. With chip's intrinsic gain error, this full scale input signal higher lower. defining maximum FSCR, margin again incorporated accommodate intrinsic gain error. addition, full scale inputs greater than nominal full scale value range selected, there some voltage which various internal circuits saturate limited amplifier headroom. This most likely occur range.
2.3.3 Calibration Tips
Calibration steps performed output word rate selected WR2-WR0 bits configuration register. Since higher word rates result conversion words with more peak-to-peak noise, calibration should performed lower output word rates. Also, minimize digital noise near device, user should wait each calibration step completed before reading writing serial port. maximum accuracy, calibrations should performed offset gain (selected changing G2-G0 bits desired Setup). Note that only gain range calibrated physical channel. factory calibration user's system performed using system calibration capabilities CS5521/22/23/24/28, offset gain register contents read system microcontroller recorded EEPROM. These same calibration words then uploaded into offset gain registers converter when power first applied system, when gain range changed.
Performing Conversions Reading Data Conversion FIFO
CS5521/22/23/24/28 offers various modes performing conversions. sections that follow detail differences between conversion modes. sections also provide examples illustrating conversion modes with channel-setup registers acquire conversions further processing. While reading, note that CS5521/22 have FIFO which four words deep. CS5523/24 have FIFO which eight words deep CS5528 FIFO which sixteen
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conversion words deep. Further note that type conversion(s) performed access resulting data from FIFO determined (multiple conversion), (loop), (read convert), (depth pointer) bits configuration register. SCLKs then needed read conversion word from data register. first SCLKs used clear flag. During last SCLKs, data word will output from converter line. part returns command mode immediately after data word been read, where waits next command issued.
2.4.1 Conversion Protocol
CS552x offer different conversion modes, which categorized into main types conversions: one-Setup conversions, which reference only Setup, multiple-Setup conversions, which reference number Setups. converter instructed perform single conversions repeated conversions (with without wait) either these modes, using bits Configuration Register. controls whether part will one-Setup multiple-Setup conversions. controls whether part will perform single repeated conversion set. When doing repeated conversion sets, controls whether converter will wait data from current conversion read before beginning next conversion set. sections that follow further detail various conversion modes.
2.4.1.2 Repeated One-Setup Conversions without Wait
this conversion mode, will repeatedly perform conversions, referencing only Setup. 8-bit command word contains CSRP bits, which instruct converter which Setup when performing conversion. Note that this mode, part will continually perform conversions, user need read every conversion becomes available. Although conversions read whenever they needed, they must read within conversion cycle (defined referenced Setup), data word will overwritten when conversion data becomes available. line rises falls indicate availability conversion data. When data available, current conversion data will lost, case that user only read part conversion word, remainder conversion word will corrupted. perform repeated, one-Setup conversions with wait, must '0', must '1', must Configuration Register. Then, 8-bit command word that references desired Setup must sent converter. will then begin performing conversions referenced Setup, will fall indicate when conversion complete, data available. Thirty-two SCLKs then needed read conversion word from data register. first SCLKs used clear flag. During last SCLKs, data word will output from converter
2.4.1.1 Single, One-Setup Conversion
this conversion mode, will perform single conversion, referencing only Setup, return command mode after data word been fully read. 8-bit command word contains CSRP bits, which instruct converter which Setup when performing conversion. perform single, one-Setup conversion, bits Configuration Register must '0'. Then, 8-bit command word that references desired Setup must sent converter. will then perform single conversion referenced Setup, will fall indicate that conversion complete. Thirty-two
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line. during first SCLKs, "00000000" provided SDI, converter will remain this conversion mode, continue perform conversions selected Setup. exit this conversion mode, "11111111" must provided during first SCLKs. user decides exit, more SCLKs required read final conversion word from data register return command mode. quired read final conversion word from data register return command mode.
2.4.1.4 Single, Multiple-Setup Conversions
this conversion mode, will perform single conversions, referencing multiple Setups, return command mode after data conversions have been read. CSRP bits command word ignored this mode. Instead, Depth Pointer (DP3-DP0) bits Configuration Register accessed determine number Setups reference when collecting data. number Setups referenced will equal (DP3-DP0) will accessed order, beginning with Setup1. perform single, multiple-Setup conversions, must '1', must Configuration Register. Then, 8-bit command word start conversion must sent converter. Because CSRP bits command word ignored this mode, "start convert" command referencing available Setups will begin conversions. will then perform conversions using appropriate number Setups dictated bits Configuration Register), beginning with Setup1. line will fall after final conversion indicate that data ready. Eight SCLKs, plus SCLKs each Setup referenced required read conversion words from data FIFO. first SCLKs used clear flag. Every bits thereafter consist data words each Setup that referenced, until data been read from part. data word from Setup1 output first, followed data word from Setup2, appropriate number Setups. part returns command mode immediately after final data word been read, waits next command issued.
2.4.1.3 Repeated One-Setup Conversions with Wait
this conversion mode, will repeatedly perform conversions, referencing only Setup. 8-bit command word contains CSRP bits, which instruct converter which Setup when performing conversion. Note that this mode, every conversion word must read. part will wait current conversion word read before performing next conversion. perform repeated, one-Setup conversions with wait, must '0', must '1', must Configuration Register. Then, 8-bit command word that references desired Setup must sent converter. will then begin performing conversions referenced Setup, will fall indicate when conversion complete, data available. Thirty-two SCLKs then needed read conversion word from data register. first SCLKs used clear flag. During last SCLKs, data word will output from converter line. during first SCLKs, "00000000" provided SDI, converter will remain this conversion mode, continue perform conversions selected Setup after each data word read. exit this conversion mode, "11111111" must provided during first SCLKs. user decides exit, more SCLKs
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2.4.1.5 Repeated Multiple-Setup Conversions without Wait
this conversion mode, will repeatedly perform conversions, referencing multiple Setups. CSRP bits command word ignored this mode. Instead, Depth Pointer (DP3-DP0) bits Configuration Register accessed determine number Setups reference when collecting data. number Setups referenced will equal (DP3-DP0) will accessed order, beginning with Setup1. Note that this mode, part will continually perform conversions, looping back Setup1 when finished with each set, user need read every conversion becomes available. line rises falls indicate availability conversion data sets. When data available, current conversion data will lost, case that user only read part conversion set, remainder conversion will corrupted. perform repeated, multiple-Setup conversions with wait, must '1', must '1', must Configuration Register. Then, 8-bit command word start conversion must sent converter. Because CSRP bits command word ignored this mode, "start convert" command referencing available Setups will begin conversions. will then perform conversions using appropriate number Setups dictated bits Configuration Register), beginning with Setup1. line will fall after final conversion indicate that data ready. Eight SCLKs, plus SCLKs each Setup referenced required read conversion words from data FIFO. first SCLKs used clear flag. Every bits thereafter consist data words each Setup that referenced, until data been read from part. during first SCLKs, "00000000" provided SDI, converter will remain this conversion mode, continue perform conversions desired number Setups. exit this conversion mode, "11111111" must provided during first SCLKs. user decides exit, more SCLKs each referenced Setup required read final conversion data from FIFO return command mode.
2.4.1.6 Repeated Multiple-Setup Conversions with Wait
this conversion mode, will repeatedly perform conversions, referencing multiple Setups. CSRP bits command word ignored this mode. Instead, Depth Pointer (DP3-DP0) bits Configuration Register accessed determine number Setups reference when collecting data. number Setups referenced will equal (DP3-DP0) will accessed order, beginning with Setup1. Note that this mode, every conversion data must read. part will wait current conversion data read before performing next conversions. perform repeated, multiple-Setup conversions with wait, must '1', must '1', must Configuration Register. Then, 8-bit command word start conversion must sent converter. Because CSRP bits command word ignored this mode, "start convert" command referencing available Setups will begin conversions. will then perform conversions using appropriate number Setups dictated bits Configuration Register), beginning with Setup1. line will fall after final conversion indicate that data ready. Eight SCLKs, plus
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SCLKs each Setup referenced required read conversion words from data FIFO. first SCLKs used clear flag. Every bits thereafter consist data words each Setup that referenced, until data been read from part. during first SCLKs, "00000000" provided SDI, converter will remain this conversion mode, begin performing next conversions. exit this conversion mode, "11111111" must provided during first SCLKs. user decides exit, more SCLKs each referenced Setup required read final conversion data from FIFO return command mode.
2.4.3 Example Using CSRs Perform Conversions Calibrations
time calibration command issued (CB=1 proper CC2-CC0 bits set) time normal conversion command issued (CB=1, CC2=CC1=CC0=0, MC=0), bits D6-D3 CSRP3 CSRP0) command byte used pointers address Setups channel-setup registers (CSRs). Five example situations that user might encounter when acquiring conversion calibrating converter follow. These examples assume that user using CS5528 Setups) that CSRs programmed with following physical channel order: Example configuration register following bits shown: DP3-DP0 `XXXX', command issued `11110000'. These settings instruct converter convert 15th Setup once, CPB3 CPB0 `1110' (which happens physical channel this example). falls after physical channel converted. read conversion results, SCLKs then required. Once acquired, serial port returns command mode. Example configuration register following bits shown: DP3-DP0 `XXXX', command byte issued `10011000'. These settings instruct converter repeatedly convert fourth Setup CPB3-CPB0 `0011' (which happens physical channel this example). falls after physical channel converted. read conversion results SCLKs required. first SCLKs needed clear flag. `00000000' provided during first SCLKs, conversion performed again physical channel converter will remain data mode until `11111111' provided during first SCLKs following fall
DS317F3
2.4.2 Calibration Protocol
perform calibration, user must send command byte with MSB=1, pointer bits (CSRP3-CSRP0) address desired Setup calibrated, appropriate calibration bits (CC2-CC0) choose type calibration performed. Proper calibration assumes that CSRs have been previously initialized because information concerning physical channel, filter rate, gain range, polarity, comes from channel-setup register being addressed pointer bits command byte. Once CSRs initialized, future calibrations performed with command byte. Once calibration cycle complete, falls results stored either gain offset register physical channel being calibrated. Note that additional calibrations performed same physical channel referenced different Setup with different filter rates, gain ranges, conversion modes, last calibration results will replace effects from previous calibration only offset gain register available physical channel. final note that only calibration performed with each command byte. calibrate channels additional calibration commands necessary.
CS5521/22/23/24/28
SD0. After `11111111' provided, additional SCLKs required transfer last bytes conversion data before serial port will return command mode. Example configuration register following bits shown: DP3-DP `0101', command issued `1XXXX000'. These settings instruct converter perform single conversion Setups once. order which channels converted falls after physical channel converted. read conversion results SCLKs required clear flag. Then additional SCLKs required read conversion data from FIFO. Again, order which data provided same order which channels converted. After last bytes conversion data corresponding physical channel read, serial port automatically returns command mode where will remain until next valid command byte received. Example configuration register following bits shown: DP3-DP0 `1001', command byte issued `1XXXX000'. These settings instruct converter repeatedly perform multiple-setup conversions using Setups. order which channels converted falls after physical channel converted. read conversion results SCLKs with required clear flag. Then more SCLKs required read conversion data from FIFO. order which data provided same order which channels converted. first bytes data correspond first Setup which this example physical channel next bytes data correspond second Setup which this example physical channel and, last bytes data corresponds
DS317F3
10th Setup which here physical channel Since Setups converted background, while data being read, user must finish reading conversion data FIFO before updated with conversions. exit this conversion mode user must provide `11111111' during first SCLKs. byte provided, serial port returns command mode only after conversion data FIFO emptied this case conversions performed). Note that this example physical channel converted five times. Each conversion could with same different filter rates depending setting Setups Note that there only offset gain register physical channel. Therefore, physical channel only calibrated gain range selected during calibration. Specifying different gain range Setup other than range that calibrated will result gain error. Example configuration register following bits shown: DP3-DP0 `XXXX', command issued `10101101'. These settings instruct converter perform system offset calibration Setup (which physical channel this example). During calibration, serial port remains command mode. Once calibration completed, falls. perform additional calibrations, more commands have issued.
Notes: 1)The configuration register must written before channel-setup registers (CSRs) because depth information contained configuration register defines many CSRs use. CSRs need written irrespective single conversion multiple single conversion mode. When single-Setup conversions desired, channel address embedded command byte. multiple-Setup conversion mode channels selected preprogrammed order based information contained CSRs depth bits (DP3-DP0)
CS5521/22/23/24/28
configuration register. Once CSRs programmed, repeated conversions Setups performed issuing only command byte. single conversion mode also requires only command, whenever another different single conversion wanted, this command modified version issued again. NULL command used keep serial port command mode, once command mode.
conversions first. last byte conversion data word (CS5521/23 only) contains data monitoring flags. channel indicator (CI) bits keep track which physical channel converted, overrange flag (OF) oscillation detect (OD) bits monitor conversions determine valid conversion performed. Refer Conversion Data FIFO Descriptions section more details. CS5521/22/23/24/28 output data conversions binary format when operating unipolar mode two's complement when operating bipolar mode. Refer Conversion Data FIFO Descriptions section more details.
Conversion Output Coding
CS5521/22/23/24/28 devices output 16-bit (CS5521/23) 24-bit (CS5522/24/28) data conversion words. read conversion word, user must read conversion data FIFO. conversion data FIFO bits long outputs
CS5521/23 16-Bit Output Coding Unipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 Offset Binary FFFF FFFF -FFFE 8000 -7FFF 0001 -0000 0000 Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 Two's Complement 7FFF 7FFF -7FFE 0000 -FFFF 8001 -8000 8000
CS5522/24/28 24-Bit Output Coding Unipolar Input Voltage VFS-1.5 Offset Binary FFFFFF -FFFFFE 800000 -7FFFFF 000001 -000000 Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 Two's Complement 7FFFFF 7FFFFF -7FFFFE 000000 -FFFFFF 800001 -800000 800000
>(VFS-1.5 LSB) FFFFFF
VFS/2-0.5
VFS/2-0.5
-0.5
-0.5
+0.5
+0.5
-VFS+0.5 <(-VFS+0.5 LSB)
-VFS+0.5
<(+0.5 LSB)
<(+0.5 LSB)
000000 <(-VFS+0.5 LSB)
Note: table equals voltage between ground full scale unipolar gain ranges, voltage between full scale bipolar gain ranges. text about error flags under overrange conditions. Table Output Coding 16-bit CS5521/23 24-bit CS5522/24/28
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2.5.1 Conversion Data FIFO Descriptions
CS5521/23 (EACH 16-BIT CONVERSIONS)
CS5522/24/28 (EACH 24-BIT CONVERSION LEVELS)
Conversion Data Bits [23:8 CS5521/23; 23:0 CS5522/24/28]
These bits depict latest output conversion.
(Oscillation detect Flag Bit)
clear when oscillatory condition modulator does exist (bit read only). time oscillatory condition detected modulator. This does occur under normal operation conditions, occur when input extremely overranged. flag will cleared logic when modulator becomes stable.
(Over-range Flag Bit)
clear when over-range condition occurred (bit read only). when input signal more positive than positive full scale, more negative than zero (unipolar mode) when input more negative than negative full scale (bipolar mode).
(Channel Indicator Bits) [1:0]
These bits indicate which physical input channel converted. Physical Channel (CS5521/23 only) Physical Channel (CS5521/23 only) Physical Channel (CS5523 only) Physical Channel (CS5523 only)
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CS5521/22/23/24/28
Digital Filter
CS5521/22/23/24/28 have eight different linear phase digital filters which output word rates (OWRs) shown Table These rates assume that 32.768 kHz. Each filters magnitude response similar that shown Figure filters optimized settle full accuracy every conversion yield better than rejection both with output word rates below 15.0 converter's digital filters scale with XIN. example with output word rate filter's corner frequency typically 12.7 using 32.768 clock. increased 65.536 doubles filter's corner frequency moves 25.4 converters will operate with external (CMOS compatible) clock with frequencies (CS5521/23) (CS5522/24/28). Figures detail CS5521/23 CS5522/24/28's performance (respectively) increased clock rates. 32.768 crystal normally specified time-keeping crystal with tight specifications both initial frequency drift over temperature. maintain excellent frequency stability, these crystals specified only over limited operating temperature ranges (i.e. -10° +60° However, applications with CS5521/22/23/24/28 don't generally require such tight tolerances.
0.002 Linearity Error (%FS) 0.0018 0.0016 0.0014 0.0012 0.001 0.0008 0.0006 0.0004 (kHz)
Clock Generator
CS5521/22/23/24/28 include gate which connected with external crystal provide master clock chip. chips designed operate using low-cost 32.768 "tuning fork" type crystal. lead crystal should connected other XOUT. Lead lengths should minimized reduce stray capacitance. Note that oscillator circuit will also operate with "tuning fork" type crystal.
Figure Typical Linearity Error CS5521/23
0.0013 0.0012 Linearity Error (%FS) 0.0011 0.001 0.0009 0.0008 0.0007 0.0006 0.0005 0.0004 (kHz)
Figure Filter Response (Normalized Output Word Rate
Figure Typical Linearity Error CS5522/24/28
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CS5521/22/23/24/28
Power Supply Arrangements
CS5521/22/23/24/28 converters designed operate from single analog supply single digital supply. -2.1 supply usually generated from charge pump drive provide power instrumentation amplifier's (negative bias voltage) pin. Figure illustrates CS5522 connected with analog supply with external components required charge pump drive. This enables CS5522 measure ground referenced signals with magnitudes down ±100 Figure illustrates CS5522 connected measure ground referenced unipolar signals positive polarity using ranges converter. ranges, signals being digitized must have common mode between +1.85 +2.65 (NBV Although CS5521/22/23/24/28 optimized measurement thermocouple outputs, they also well suited measurement ratiometric bridge transducer outputs. Figure illustrates CS5522 connected measure output ratiometric differential bridge transducer while operating from single supply. Bridge outputs range from Digital Gain Scaling section about manipulating gain register achieve optimum gain scaling.
XOUT
VREF+ REF-
S5522 AGND SCLK
olute V301
DGND
itch
4148
4148
Figure CS5522 Configured on-chip charge pump supply
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CS5521/22/23/24/28
VREF+ VREF-
XOUT
ptio
CS5522
SCLK
erial Inte
Figure CS5522 Configured ground-referenced Unipolar Signals
XOUT
S5522 DGND
Figure CS5522 Configured Single Supply Bridge Measurement
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2.8.1 Charge Pump Drive Circuits
(Charge Pump Drive) converter used with external components (shown Figure develop appropriate negative bias voltage pin. When used generate NBV, voltage regulated with internal regulator loop referenced VA+. Therefore, change results proportional change NBV. With NBV's regulation proportional approximately -2.1 Figure illustrates charge pump circuit when converters powered from +3.0 digital supply. Alternatively, negative bias supply generated from negative supply voltage resistive divider illustrated Figure ground based signals with instrumentation amplifier engaged (when ranges), voltage should time less negative than -1.8 more negative than -2.5 prevent excessive voltage stress chip when instrumentation amplifier isn't engaged (when ranges) voltage should more negative than -2.5 components Figure preferred components filter. However, smaller capacitors used with acceptable results. ensures very ripple NBV. Intrinsic safety requirements prohibit electrolytic capacitors. this case, four 0.47 ceramic capacitors parallel used.
Note: charge pump designed nominally provide current instrumentation amplifier when 0.033 pumping capacitor used (XIN 32.768 kHz). When larger pumping capacitor used, charge pump source more current power external loads. Refer Applications Note "Using CS5521/23, CS5522/24/28, CS5525/26 Charge Pump Drive External Loads" more details using charge pump with external loads.
Digital Gain Scaling
CS5521/22/23/24 CS5528 feature gain register capable being scaled from 42-22 decimal. specified ranges converter defined with voltage reference gain register approximately 1.0. gain register manipulated scale input ranges other than those specified. example, when using voltage reference, input range setting, gain register changed from 1.000 2.000 (shift entire register contents left position) achieve input span 12.5 Under this condition full span converter codes will appear across 12.5 span. amount noise con-
BAT85
BAT85
Figure Charge Pump Drive Circuit
Figure Alternate Circuits
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CS5521/22/23/24/28
verter stays constant number codes affected doubled because code size been reduced half. converter input ranges specified with voltage reference device operated with reference tied directly supply. When this done, input span input ranges doubled; range actually becomes range. gain register (shift contents left bit) input range will scaled back Since gain register actually great 4-2-22 decimal, could scale input span range accept analog full scale span about 6.25 This useful ratiometric bridge measurement level differential outputs. gain register also scaled manually value lower than 1.0. recommended devices with gain register scaled lower than 0.6. This enable converter accept input signal range when using voltage reference Caution though scaling gain register below volt ranges analog signal path into converter saturate before expected full scale code output produced converter. Note that digital gain scaling will directly influence number digital output codes affected noise. effects analytically determined calculating size codes (V/Count) which result from given gain scaling condition relating amount noise converter relative determined code size. evaluation board converter useful tool assessment noise performance with various voltage reference values, input range settings, gain register settings. evaluation board supports noise analysis through data capture noise histogram analysis.
2.10 Getting Started
CS5521/22/23/24/28 have many features. From software programmer's perspective, what should done first? begin, 32.768 crystal takes approximately start-up. accommodate this, recommended that software delay approximately second precede processor's initialization code before registers accessed ADC. This delay time dependent start-up delay clock source. CMOS clock source with start-up delay being used drive ADC, then this delay necessary. converters include on-chip power reset circuit automatically reset ADCs shortly after power When power CS5521/22/23/24/28 applied, chips held reset condition until 32.768 oscillator started counter-timer elapses. counter-timer counts 2006 oscillator clock cycles make sure oscillator fully stable. During this time-out period serial port logic reset (Reset Valid) configuration register indicate that valid reset occurred. normal start-up conditions, this power-on-reset circuit should reset chip when power applied. your application experience abnormal power start-up conditions, following sequence instructions should performed guarantee converter begins proper operation: After power applied, initialize serial port using serial port synchronization sequence. Write reset (RS) configuration register reset converter. Read configuration register determine reset valid (RV) `1'. set, configuration register should read again. When been `1', reset back writing 0x000000
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configuration register. Note that while other register bits will reset their default state, must normal operation converters. Once been `0', placed command state were waits valid command execute. next step load configuration register then channel setup registers with conditions that have decided. need factory calibration, perform offset gain calibrations each channel that used. Then off-load offset gain register contents into EEPROM. These registers then initialized these conditions when instrument used normal operation. Once calibration ready, input command start conversions mode have selected configuration register bits. Monitor flag that data ready read conversion data.
2.11 Layout
CS5521/22/23/24/28 should placed entirely over analog ground plane with both AGND DGND pins device connected analog plane. Place analog-digital plane split immediately adjacent digital portion chip. separate digital (VD+) analog (VA+) supplies used, recommended that diode placed between them (the cathode diode should point VA+). digital supply comes before analog supply, start properly.
Note: CDB5521/22/23/24/28 data sheet suggested layout details Applications Note more detailed layout guidelines. Before layout, please call Free Schematic Review Service.
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DESCRIPTIONS
ANALOG GROUND POSITIVE ANALOG POWER DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT NEGATIVE BIAS VOLTAGE LOGIC OUTPUT
CHARGE PUMP DRIVE
AGND
AIN1+
VREF+
VREFAIN2+
VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT LOGIC OUTPUT SERIAL CLOCK INPUT
POSITIVE DIGITAL POWER
CS5521 CS5522
AIN1NBV
AIN2A1 SCLK DGND XOUT
SERIAL DATA INPUT CHIP SELECT CRYSTAL
DIGITAL GROUND SERIAL DATA CRYSTAL
ANALOG GROUND POSITIVE ANALOG POWER DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT
NEGATIVE BIAS VOLTAGE
AGND
AIN1+
VREF+
VREFAIN2+
VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT
LOGIC OUTPUT
CS5523 CS5524
AIN1AIN3+ AIN3NBV
AIN2AIN4+ AIN4A1 SCLK DGND
LOGIC OUTPUT CHARGE PUMP DRIVE SERIAL DATA INPUT CHIP SELECT CRYSTAL
SERIAL CLOCK INPUT POSITIVE DIGITAL POWER DIGITAL GROUND SERIAL DATA CRYSTAL
XOUT
ANALOG GROUND POSITIVE ANALOG POWER SINGLE-ENDED ANALOG INPUT SINGLE-ENDED ANALOG INPUT SINGLE-ENDED ANALOG INPUT SINGLE-ENDED ANALOG INPUT
NEGATIVE BIAS VOLTAGE
AGND
AIN1+
VREF+
VREFAIN3+
VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT SINGLE-ENDED ANALOG INPUT SINGLE-ENDED ANALOG INPUT SINGLE-ENDED ANALOG INPUT SINGLE-ENDED ANALOG INPUT
LOGIC OUTPUT
CS5528
AIN2+
AIN5+ AIN6+
AIN4+
AIN7+ AIN8+ SCLK DGND
LOGIC OUTPUT CHARGE PUMP DRIVE SERIAL DATA INPUT CHIP SELECT CRYSTAL
SERIAL CLOCK INPUT POSITIVE DIGITAL POWER DIGITAL GROUND SERIAL DATA CRYSTAL
XOUT
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CS5521/22/23/24/28
Clock Generator
XIN; XOUT Crystal Crystal Out. gate inside chip connected these pins used with crystal provide master clock device. Alternatively, external (CMOS compatible) clock supplied into provide master clock device.
Control Pins Serial Data
Chip Select. When active low, port will recognize SCLK. When high will output high impedance state. should changed when SCLK Serial Data Input. input serial input port. Data will input rate determined SCLK. Serial Data Output. serial data output. will output high impedance state SCLK Serial Clock Input. clock signal this determines input/output rate data SDI/SDO pins respectively. This input Schmitt trigger allow slow rise time signals. SCLK will recognize clocks only when low. Logic Outputs. logic states A0-A1 mimic states D22/D10-D23/D11 bits channel-setup register. Logic Output AGND, Logic Output VA+.
Measurement Reference Inputs
AIN1+, AIN1-, AIN2+, AIN2- AIN3+, AIN3-, AIN4+, AIN4- Differential Analog Input. Differential input pins into CS5522 CS5524 devices. AIN1+, AIN2+, AIN3+, AIN4+, AIN5+, AIN6+, AIN7+, AIN8+ Single-Ended Analog Input. Single-ended input pins into CS5528. VREF+, VREF- Voltage Reference Input. Fully differential inputs which establish voltage reference on-chip modulator.
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CS5521/22/23/24/28
Negative Bias Voltage. Input supply negative supply voltage gain instrumentation amplifier coarse/fine charge buffers. tied AGND AIN+ AIN- inputs centered around +2.5 tied negative supply voltage (-2.1 typical) allow amplifier handle level signals more negative than ground. When using CS5528 either range, analog inputs expected ground referenced; therefore, must between -1.8 -2.5 ensure proper operation. Charge Pump Drive. Square wave output used provide energy charge pump.
Power Supply Connections
Positive Analog Power. Positive analog supply voltage. Nominally Positive Digital Power. Positive digital supply voltage. Nominally +3.0 AGND Analog Ground. Analog Ground. DGND Digital Ground. Digital Ground.
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SPECIFICATION DEFINITIONS
Linearity Error deviation code from straight line which connects endpoints Converter transfer function. endpoint located below first code transition other endpoint located beyond code transition ones. Units percent full-scale. Differential Nonlinearity deviation code's width from ideal width. Units LSBs. Full Scale Error deviation last code transition from ideal [{(VREF+) (VREF-)} LSB]. Units LSBs. Unipolar Offset deviation first code transition from ideal (1/2 above voltage AIN- pin.). When unipolar mode (U/B Units LSBs. Bipolar Offset deviation mid-scale transition (111.111 000.000) from ideal (1/2 below voltage AIN- pin). When bipolar mode (U/B Units LSBs.
ORDERING GUIDE
Model Number CS5521-AS CS5522-AP CS5522-AS CS5523-AS CS5524-AP CS5524-AS CS5528-AS Bits Channels Linearity Error (Max) Temperature Range ±0.003% ±0.0015% ±0.0015% ±0.003% ±0.0015% ±0.0015% ±0.0015% -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C Package 20-pin 0.2" Plastic SSOP 20-pin 0.3" Plastic 20-pin 0.2" Plastic SSOP 24-pin 0.2" Plastic SSOP 24-pin 0.3" Plastic 24-pin 0.2" Plastic SSOP 24-pin 0.2" Plastic SSOP
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PACKAGE DIMENSION DRAWINGS
PLASTIC (PDIP) (300 MIL) PACKAGE DRAWING
SEATING PLANE
VIEW
BOTTOM VIEW
SIDE VIEW
0.000 0.015 0.115 0.014 0.045 0.008 0.980 0.300 0.240 0.090 0.280 0.300 0.000 0.115
INCHES -0.020 0.130 0.018 0.058 0.010 1.030 0.310 0.252 0.100 0.30 0.37 -0.130
0.210 0.025 0.195 0.022 0.070 0.014 1.060 0.325 0.280 0.110 0.320 0.430 0.060 0.150 JEDEC MS-001
0.00 0.38 2.92 0.36 1.14 0.20 24.89 7.62 6.10 2.29 7.11 7.62 0.00 2.92
MILLIMETERS -0.508 3.302 0.4572 1.46 0.25 26.162 7.874 6.40 2.54 7.62 9.40 -3.302
5.33 0.64 4.95 0.56 1.78 0.36 26.92 8.26 7.11 2.79 8.13 10.92 1.52 3.81
Controling Dimension Inches Notes: Positional tolerance leads shall within 0.25 (0.010 in.) maximum material condition, relation seating plane each other. Dimension center leads when formed parallel. Dimension does include mold flash.
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SKINNY PLASTIC (PDIP) (300 MIL) PACKAGE DRAWING
SEATING PLANE
VIEW
BOTTOM VIEW
SIDE VIEW
0.000 0.015 0.115 0.014 0.045 0.008 1.230 0.300 0.240 0.090 0.280 0.300 0.000 0.115
INCHES -0.020 0.130 0.018 0.058 0.010 1.255 0.310 0.252 0.100 0.30 0.37 -0.130
0.210 0.025 0.195 0.022 0.070 0.014 1.280 0.325 0.280 0.110 0.320 0.430 0.060 0.150 JEDEC MS-001
0.00 0.38 2.92 0.36 1.14 0.20 31.24 7.62 6.10 2.29 7.11 7.62 0.00 2.92
MILLIMETERS -0.51 3.30 0.46 1.46 0.25 31.88 7.87 6.40 2.54 7.62 9.40 -3.30
5.33 0.64 4.95 0.56 1.78 0.36 32.51 8.26 7.11 2.79 8.13 10.92 1.52 3.81
Controling Dimension Inches
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CS5521/22/23/24/28
SSOP PACKAGE DRAWING
SIDE VIEW
VIEW
SEATING PLANE
VIEW
-0.002 0.064 0.009 0.272 0.291 0.197 0.022 0.025
INCHES -0.006 0.068 -0.2834 0.307 0.209 0.026 0.03
0.084 0.010 0.074 0.015 0.295 0.323 0.220 0.030 0.041
-0.05 1.62 0.22 6.90 7.40 5.00 0.55 0.63
MILLIMETERS -0.13 1.73 -7.20 7.80 5.30 0.65 0.75
NOTE 2.13 0.25 1.88 0.38 7.50 8.20 5.60 0.75 1.03
JEDEC MO-150 Controling Dimension Millimeters. Notes: "E1" reference datums included mold flash protrusions, include mold mismatch measured parting line, mold flash protrusions shall exceed 0.20 side. Dimension does include dambar protrusion/intrusion. Allowable dambar protrusion shall 0.13 total excess dimension maximum material condition. Dambar intrusion shall reduce dimension more than 0.07 least material condition. These dimensions apply flat section lead between 0.10 0.25 from lead tips.
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CS5521/22/23/24/28
SSOP PACKAGE DRAWING
SIDE VIEW
VIEW
SEATING PLANE
VIEW
-0.002 0.064 0.009 0.311 0.291 0.197 0.022 0.025
INCHES -0.006 0.068 -0.323 0.307 0.209 0.026 0.03
0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.030 0.041
-0.05 1.62 0.22 7.90 7.40 5.00 0.55 0.63
MILLIMETERS -0.13 1.73 -8.20 7.80 5.30 0.65 0.75
NOTE 2.13 0.25 1.88 0.38 8.50 8.20 5.60 0.75 1.03
JEDEC MO-150 Controling Dimension Millimeters. Notes: "E1" reference datums included mold flash protrusions, include mold mismatch measured parting line, mold flash protrusions shall exceed 0.20 side. Dimension does include dambar protrusion/intrusion. Allowable dambar protrusion shall 0.13 total excess dimension maximum material condition. Dambar intrusion shall reduce dimension more than 0.07 least material condition. These dimensions apply flat section lead between 0.10 0.25 from lead tips.
DS317F3
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