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PEEL18CV8 -7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device
Multiple Speed Power, Temperature Options Volts ±10% Speeds ranging from Power 37mA 25MHz Commercial industrial versions available CMOS Electrically Erasable Technology Superior factory testing Reprogrammable plastic package Reduces retrofit development costs Development Programmer Support Third party software programmers WinPLACE Development Software PLD-to-PEELJEDEC file translator Architectural Flexibility Enhanced architecture fits more logic product terms input array inputs pins possible macrocell configurations Asynchronous clear Independent output enables DIP/SOIC/TSSOP PLCC Application Versatility Replaces random logic Super sets PLDs (PAL, GAL, EPLD) Enhanced Architecture fits more logic than ordinary PLDs
PEELTM18CV8 Programmable Electrically Erasable Logic (PEELTM) device providing attractive alternative ordinary PLDs. PEELTM18CV8 offers performance, flexibility, ease design production practicality needed logic designers today. PEELTM18CV8 available 20-pin DIP, PLCC, SOIC TSSOP packages with speeds ranging from 25ns with power consumption 37mA. EE-Reprogrammability provides convenience instant reprogramming development reusable production inventory minimizing impact programming changes errors. EE-Reprogrammability also improves factory testability, thus assuring highest quality possible. PEELTM18CV8 architecture allows replace over standard 20-pin PLDs (PAL, GAL, EPLD etc.). also provides additional architecture features more logic into every design. Anachip's JEDEC file translator instantly converts PEELTM18CV8 existing 20-pin PLDs without need rework existing design. Development programming support PEELTM18CV8 provided popular third-party program- mers development software.
Figure Block Diagram
Figure Configuration
I/CLK
TSSOP
PLCC
SOIC
This datasheet contains product information. Anachip Corp. reserves rights modify product specification without notice. liability assumed result this product. rights under patent accompany sale product.
Rev. 2004
Figure PEELTM18CV8 Logic Array Diagram
Anachip Corp. www.anachip.com.tw
Rev. 2004
Function Description
PEELTM18CV8 implements logic functions sum-of- products expressions programmable-AND/fixed-OR logic array. User-defined functions created programming connections input signals into array. User-configurable output structures form macrocells further increase logic flexibility.
effect output function).
Programmable Macrocell
unique twelve-configuration output macrocell provides complete control over architecture each output. ability configure each output independently permits users tailor configuration PEELTM18CV8 precise requirements their designs.
Architecture Overview
PEELTM18CV8 architecture illustrated block diagram Figure dedicated inputs I/Os provide inputs outputs creation logic functions. core device programmable electrically-erasable array which drives fixed array. With this structure, PEELTM18CV8 implement sum-of-products logic expressions. Associated with each functions macrocell which independently programmed different configurations. programmable macrocells allow each create sequential combinatorial logic functions active-high active-low polarity, while providing three different feedback paths into array.
Macrocell Architecture
Each macrocell, shown Figure consists D-type flip-flop signal-select multiplexers. configuration each macrocell determined four EEPROM bits controlling these multiplexers. These bits determine output polarity, output type (registered non-registered) input-feedback path (bidirectional I/O, combinatorial feedback). Refer Table details. Equivalent circuits twelve macrocell configurations illustrated Figure addition emulating four PAL-type output structures (configurations 3,4,9, 10), macrocell provides eight additional configurations. When creating PEELdevice design, desired macrocell configuration generally specified explicitly design file. When design assembled compiled, macrocell configuration bits defined last lines JEDEC programming file.
AND/OR LOGIC ARRAY
programmable array PEELTM18CV8 (shown Figure formed input lines intersecting product terms. input lines product terms used follows: Input Lines: input lines carry true complement signals applied input pins additional lines carry true complement values feedback input signals from I/Os product terms: product terms (arranged groups used form product functions output enable terms (one each I/O) global synchronous preset term global asynchronous clear term each input-line/product-term intersection, there EEPROM memory cell that determines whether there logical connection that intersection. Each product term essentially 36-input gate. product term that connected both true complement input signal will always FALSE thus will affect function that drives. When connections product term opened, "don't care" state exists that term will always TRUE. When programming PEELTM18CV8, device programmer first performs bulk erase remove previous pattern. erase cycle opens every logical connection array. device configured perform user-defined function pro- gramming selected connections array. (Note that PEELdevice programmers automatically program connections unused product terms that they will have
Anachip Corp. www.anachip.com.tw
Output Type
signal from array directly output (combinatorial function) latched D-type flip-flop (registered function). D-type flip-flop latches data rising edge clock controlled global preset clear terms. When synchronous preset term satisfied, output register will HIGH next rising edge clock input. Satisfying asynchronous clear will LOW, regardless clock state. both terms satisfied simultaneously, clear will override preset.
Output Polarity
Each macrocell configured implement active-high active-low logic. Programmable polarity eliminates need external inverters.
Output Enable
output each macrocell enabled disabled under control associated programmable output enable product term. When logical conditions programmed output enable term satisfied, output signal propagated pin. Otherwise, output buffer switched into high-impedance state. Under control output enable term, function dedicated input, dedicated output, bi-directional Opening every connection output enable term will permanently enable output buffer yield dedicated output. Conversely, every connection intact, enable term will
Rev. 2004
always logically false will function dedicated input.
Registered Feedback
Feedback also taken from register, regardless whether output function combinatorial registered. When implementing combinatorial output function, registered feedback allows internal latching states without giving external output.
Input/Feedback Select
PEELTM18CV8 macrocell also provides control over feedback path. input/feedback signal associated with each macrocell obtained from three different locations; from input pin, from output flip-flop (registered feedback), directly from gate (combinatorial feedback).
Design Security
PEELTM18CV8 provides special EEPROM security that prevents unauthorized reading copying designs programmed into device. security programmer, either conclusion programming cycle separate step, after device been programmed. Once security impossible verify (read) program PEELuntil entire device first been erased with bulk-erase function.
Bi-directional
input/feedback signal taken from when using dedicated input bi-directional I/O. (Note that possible create registered output function with bi-directional I/O.)
Combinatorial Feedback
signal-select multiplexer gives macrocell ability feedback output gate, bypassing output buffer, regardless whether output function registered combinatorial. This feature allows creation asynchronous latches, even when output must disabled. (Refer configurations 5,6,7 Figure
Programming Support
Anachip's JEDEC file translator allows easy conversion existing designs PEELTM18CV8, without need redesign. Anachip also offers (for free) proprietary WinPLACE software, easy-to-use entry level PC-based software development system. Programming support includes popular third party programmers: Microsystems, System General, Logical Devices, numerous others.
Figure Block Diagram PEELTM18CV8 Macrocell
Anachip Corp. www.anachip.com.tw
Rev. 2004
Figure Equivalent Circuits Twelve Configurations PEELTM18CV8 Macrocell
Anachip Corp. www.anachip.com.tw
Rev. 2004
Absolute Maximum Ratings
This device been designed tested specified operating ranges. Improper operation outside these levels guaran- teed. Exposure absolute maximum ratings cause permanent damage.
Operating Range
D.C. Electrical Characteristics Over operating range (Unless otherwise specified)
Anachip Corp. www.anachip.com.tw
Rev. 2004
A.C. Electrical Characteristics
Over operating range
Switching Waveforms
Inputs, I/O, Registered Feedback, Synchronous Preset Clock Asynchronous Reset Registered Outputs Combinatorial Outputs Notes:
Minimum input -0.5V, however, inputs undershoot -2.0V periods less than specified program/verify operation. Test Points Clock referenced levels. pins VCC. "Input" refers input signal. measured from input transition VREF±0.1V, measured from input transition VOH-0.1V VOL+0.1V; VREF=VL. Capacitances tested sample basis.
Anachip Corp. www.anachip.com.tw
Test conditions assume: signal transition times less from points, timing reference levels 1.5V (Unless otherwise specified). Test output time duration less than second. typical application: This parameter tested with device programmed 8-bit Counter. Parameters 100% tested. Specifications based initial characterization tested after design process modification that might affect operational frequency. Available only 18CV8 -15/I-15/-25/I-25 grades 24mA available 18CV8-5/-7. other speeds 16mA.
Rev. 2004
PEELDevice Array Test Loads
Ordering Information Part Number
PEEL18CV8P-7 PEEL18CV8J-7 PEEL18CV8S-7 PEEL18CV8P-10 PEEL18CV8PI-10 PEEL18CV8J-10 PEEL18CV8JI-10 PEEL18CV8S-10 PEEL18CV8SI-10 PEEL18CV8T-10 PEEL18CV8TI-10 PEEL18CV8P-15 PEEL18CV8PI-15 PEEL18CV8J-15 PEEL18CV8JI-15 PEEL18CV8S-15 PEEL18CV8SI-15 PEEL18CV8T-15 PEEL18CV8TI-15 PEEL18CV8P-25 PEEL18CV8PI-25 PEEL18CV8J-25 PEEL18CV8JI-25 PEEL18CV8S-25 PEEL18CV8SI-25 PEEL18CV8T-25 PEEL18CV8TI-25
Speed
15ns
Temperature
Commercial Commercial Commercial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
Package
20-pin Plastic 20-pin Plastic Leaded Chip Carrier (PLCC) 20-pin SOIC 20-pin Plastic 20-pin Plastic Leaded Chip Carrier (PLCC) 20-pin SOIC 20-pin TSSOP 20-pin Plastic 20-pin Plastic Leaded Chip Carrier (PLCC) 20-pin SOIC 20-TSSOP 20-pin Plastic 20-pin Plastic Leaded Chip Carrier (PLCC) 20-pin SOIC 20-pin TSSOP
Anachip Corp. www.anachip.com.tw
Rev. 2004
Part Number
Device Suffix
PEELTM18CV8
PI-25X Lead Free
Package
20-pin Plastic 300mil 20-pin Plastic Leaded Chip Carrier (PLCC) 20-pin SOIC Gullwing 20-pin TSSOP 170mil
Speed
7.5ns 10ns 15ns 25ns
Blank Normal Lead Free Package
Temperature Range
(Blank) Commercial +70oC Industrial +85oC
Anachip Corp. Head Office, 24-2, Industry Science-Based Industrial Park, Hsinchu, 300, Taiwan Tel: +886-3-5678234 Fax: +886-3-5678368 Email: sales_usa@anachip.com Website: http://www.anachip.com ©2004 Anachip Corp.
Anachip Montague Expressway, #201 Jose, 95131 Tel: (408) 321-9600 Fax: (408) 321-9696
Anachip reserves right make changes specifications time without notice. information furnished Anachip this publication believed accurate reliable. However, there responsibility assumed Anachip infringements patents other rights third parties resulting from use. license granted under patents patent rights Anachip. Anachip's products authorized critical components life support devices systems. Marks bearing registered trademarks trademarks Anachip Corp.
Anachip Corp. www.anachip.com.tw
Rev. 2004

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