EBD51RD8ABFA (64M words bits, Rank) EBD51RD8ABFA words bits, rank

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EBD51RD8ABFA (64M words bits, Rank) EBD51RD8ABFA words bits, rank

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512MB Registered SDRAM DIMM
EBD51RD8ABFA (64M words bits, Rank)
EBD51RD8ABFA words bits, rank Double Data Rate (DDR) SDRAM Module, mounting pieces SDRAM sealed TSOP package. Read write operations performed cross points /CK. This high-speed data transfer realized 2-bit prefetch-pipelined architecture. Data strobe (DQS) both read write available high speed reliable data design. setting extended mode register, on-chip Delay Locked Loop (DLL) enable disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors mounted beside each TSOP module board.
Features
184-pin socket type dual line memory module (DIMM) height: 30.48mm Lead pitch: 1.27mm 2.5V power supply Data rate: 333Mbps/266Mbps (max.) (SSTL_2 compatible) Double Data Rate architecture; data transfers clock cycle Bi-directional, data strobe (DQS) transmitted /received with data, used capturing data receiver Data inputs outputs synchronized with internal banks concurrent operation (Component) edge aligned with data READs; center aligned with data WRITEs Differential clock inputs /CK) aligns transitions with transitions Commands entered each positive edge; data referenced both edges Data mask (DM) write data Auto precharge option each burst access Programmable burst length: Programmable /CAS latency (CL): Refresh cycles: (8192 refresh cycles /64ms) 7.8µs maximum average periodic refresh interval variations refresh Auto refresh Self refresh piece clock driver, pieces register drivers piece serial EEPROM bits EEPROM) Presence Detect (PD)
Document E0376E10 (Ver. 1.0) Date Published April 2003 Japan URL: http://www.elpida.com
This product became March, 2004.
Elpida Memory,Inc. 2003
EBD51RD8ABFA
Ordering Information
Data rate Mbps (max.) Component JEDEC speed bin*1 (CL-tRCD-tRP) DDR333B (2.5-3-3) DDR266A (2-3-3) DDR266B (2.5-3-3) Contact Gold
Part number EBD51RD8ABFA-6B EBD51RD8ABFA-7A EBD51RD8ABFA-7B
Package 184-pin DIMM
Mounted devices EDD5108ABTA-6B EDD5108ABTA-6B, EDD5108ABTA-6B, -7A,
Notes: Module /CAS latency component
Configurations
Front side
name VREF DQS0 /RESET DQS1 DQ10 DQ11 CKE0 DQ16 DQ17 DQS2
Back side
name DQS8
name DM0/DQS9
name DM8/DQS17 DQ36 DQ37 DM4/DQS13 DQ38 DQ39 DQ44 /RAS DQ45 /CS0
Preliminary Data Sheet E0376E10 (Ver. 1.0)
DQ32 DQ33 DQS4 DQ34 DQ35 DQ40 DQ41 /CAS DQS5 DQ42 DQ43 DQ48 DQ49
DQ12 DQ13 DM1/DQS10 DQ14 DQ15 DQ20 DQ21 DM2/DQS11
DM5/DQS14 DQ46 DQ47 DQ52
EBD51RD8ABFA
name DQ18 DQ19 DQ24 DQ25 DQS3 name DQS6 DQ50 DQ51 VDDID DQ56 DQ57 DQS7 DQ58 DQ59 name DQ22 DQ23 DQ28 DQ29 DM3/DQS12 DQ30 DQ31 /CK0 name DQ53 DM6/DQS15 DQ54 DQ55 DQ60 DQ61 DM7/DQS16 DQ62 DQ63 VDDSPD
DQ26 DQ27
Preliminary Data Sheet E0376E10 (Ver. 1.0)
EBD51RD8ABFA
name BA0, DQ63 /RAS /CAS /CS0 Function Address input address Column address Data input/output Check (Data input/output) address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input output data strobe Input mask Clock input serial Data input/output serial Serial address input Power internal circuit Power serial EEPROM Input reference voltage Ground
Bank select address
CKE0 /CK0 DQS0 DQS8 VDDSPD VREF VDDID /RESET
DM8/DQS9 DQS17
Preliminary Data Sheet E0376E10 (Ver. 1.0)
identification flag connection
Reset (forces register inputs low)
EBD51RD8ABFA
Serial Matrix*
Byte
Function described Number bytes utilized module manufacturer Total number bytes serial device Memory type Number address Number column address Number DIMM ranks Module data width Module data width continuation
Bit7
Bit6
Bit5 Bit4
Bit3
Bit2
Bit1 Bit0
value
Comments byte SDRAM bits SSTL 2.5V 2.5*3
-7A, -7A, -7A, -7A,
Voltage interface level this assembly
SDRAM cycle time, SDRAM access from clock (tAC)
0.70ns*3 0.75ns*3 Self refresh Registered 0.2V
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number banks SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: latency SDRAM device attributes: latency SDRAM module attributes SDRAM device attributes: General
Minimum clock cycle time -6B, Maximum data access time (tAC) from clock Minimum clock cycle time
Maximum data access time (tAC) from clock Minimum precharge time (tRP)
Preliminary Data Sheet E0376E10 (Ver. 1.0)
0.70ns*3 0.75ns*3
18ns 20ns
EBD51RD8ABFA
Byte
Function described Minimum active active delay (tRRD) -7A, Minimum /RAS /CAS delay (tRCD) -7A, Minimum active precharge time (tRAS) -7A,
Bit7
Bit6
Bit5 Bit4
Bit3
Bit2
Bit1 Bit0
value
Comments 12ns 15ns 18ns 20ns 42ns 45ns rank 512MB 0.75ns*3 0.9ns*3 0.75ns*3 0.9ns*3 0.45ns*3 0.5ns*3 0.45ns*3 0.5ns*3 Future 60ns*3 65ns*3 72ns*3 75ns*3 12ns*3 0.45ns*3 0.5ns*3 0.55ns*3 0.75ns*3
Module rank density Address command setup time before clock (tIS) -7A,
-7A, -7A, -7A, -7A, -7A, -7A, -7A, revision
Address command hold time after clock (tIH) Data input setup time before clock (tDS)
Data input hold time after clock (tDH) Superset information
Active command period (tRC)
Auto refresh active/ Auto refresh command cycle (tRFC) SDRAM cycle max. (tCK max.) Dout skew Data hold skew (tQHS) Superset information Checksum bytes
Manufacturer's JEDEC code Manufacturer's JEDEC code Manufacturer's JEDEC code
Preliminary Data Sheet E0376E10 (Ver. 1.0)
Future Initial Elpida Memory
EBD51RD8ABFA
Byte Function described Manufacturing location Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments (ASCII-8bit code) (Space) Initial (Space) Year code (HEX) Week code (HEX)
-7A, -6B, Revision code Revision code
Module part number Module part number Module part number Module part number
Module part number
Manufacturing date Manufacturing date Module serial number
Manufacturer specific data
Notes: serial data protected. Serial data, "driven Low", Serial data, "driven High" Bytes through assembly serial number. These specifications defined based component specification, module.
Preliminary Data Sheet E0376E10 (Ver. 1.0)
EBD51RD8ABFA
Block Diagram
/RCS0 DM0/DQS9 DQS0 I/O0 I/O7 DM4/DQS13 DQ32 DQ39 I/O0 I/O7
DQS4
DM1/DQS10 DQS1 DQ15 I/O0 I/O7
DM5/DQS14
DQ40 DQ47 I/O0 I/O7
DQS5
VREF
DM2/DQS11 DQS2 DQ16 DQ23 I/O0 I/O7
DM6/DQS15
DQ48 DQ55 I/O0 I/O7
DQS6
DM3/DQS12 DQS3 I/O0 I/O7
DM7/DQS16
DQ56 DQ63 I/O0 I/O7
Preliminary Data Sheet E0376E10 (Ver. 1.0)
DQ24 DQ31 DM8/DQS17 DQS8
/CS0 /RAS /CAS CKE0
DQS7
I/O0 I/O7
/RCS0 /CS: SDRAMs
RBA0 RBA1 BA1: SDRAMs RA12 A12: SDRAMs /RRAS /RAS: SDRAMs /RCAS /CAS: SDRAMs
512M bits SDRAM bits EEPROM PLL: CDCV857 Register: SSTV16857 Serial
RCKE0 CKE: SDRAMs /RWE /WE: SDRAMs /RESET
/PCK
VDDID open CK0, /CK0 PLL* Note: Wire Clock loading table/Wiring diagrams.
Notes: pull-up resistor required open-drain/open-collector output. pull-up resistor recommended because normal line inacitve "high" state.
EBD51RD8ABFA
Differential Clock Wiring (CK0, /CK0)
(nominal)
OUT1
SDRAM
Capacitance
/CK0
Register1
OUT'N'
(Typically registers DIMM)
Feedback Register2
Notes: clock delay from input clock input SDRAM register will (nominal). Input, output feedback clock lines terminated from line line shown, from line ground. Only output shown output type. additional outputs will wired similar manner. Termination resistors feedback path clocks located after pins PLL. SDRAM clock pair inputs have parallel capacitor equal one-half nominal SDRAM input clock load.
Preliminary Data Sheet E0376E10 (Ver. 1.0)
EBD51RD8ABFA
Electrical Specifications
voltages referenced (GND). Absolute Maximum Ratings
Parameter Voltage relative Supply voltage relative Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol Tstg Value -1.0 +3.6 -1.0 +3.6 +125 Unit Note
Note: SDRAM component specification Caution Exposing device stress above those listed Absolute Maximum Ratings could cause permanent damage. device meant operated under conditions outside limits described operational section this specification. Exposure Absolute Maximum Rating conditions extended periods affect device reliability.
Parameter Supply voltage Input reference voltage Termination voltage Input high voltage Input voltage Input voltage level, inputs Input differential cross point voltage, inputs Input differential voltage, inputs
Operating Conditions +70°C) (DDR SDRAM component Specification)
Symbol VREF (DC) (DC) (DC) (DC) (DC)
0.49 VDDQ VREF 0.04 VREF 0.15
0.50 VDDQ VREF
0.51 VDDQ VREF 0.04 VDDQ VREF 0.15 VDDQ
Unit
Notes
VDD,VDDQ
-0.3 -0.3 VDDQ 0.2V 0.36
VDDQ
VDDQ 0.2V VDDQ
Notes:
VDDQ must lower than equal VDD. allowed exceed 3.6V period shorter than equal 5ns. allowed outreach below down -1.0V period shorter than equal 5ns. (DC) specifies allowable execution each differential input. (DC) specifies input differential voltage required switching. (CK) assumed over VREF 0.18V, (CK) assumed under VREF 0.18V measurement.
Preliminary Data Sheet E0376E10 (Ver. 1.0)
EBD51RD8ABFA
Characteristics +70°C, 2.5V 0.2V,
Parameter Operating current (ACTV-PRE) Operating current (ACTV-READ-PRE) Symbol IDD0 IDD1 Grade -7A, -7A, -7A, max. 1740 1605 2010 1830 -7A, -7A, -7A, -7A, 1020 2280 2010 2280 2010 3000 2820 -7A, 4260 3720 Unit Test condition VIH, (min.) VIH, 3.5, (min.) VIH, VIH, DQS, VREF VIH, VIH, DQS, VREF VIH, tRAS tRAS (max.) VIH, VIH, tRFC tRFC (min.), Input Input Input Notes
Idle power down standby current IDD2P Floating idle standby current Quiet idle standby current Active power down standby current IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7A
Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto refresh current Self refresh current Operating current banks interleaving) Parameter Input leakage current Output leakage current Output high current Output current
Notes. These data measured under condition that pins connected. bank operation. bank active. banks idle. Command/Address transition once cycle. transition twice cycle. banks active. Only bank running (min.) data this table measured with regard (min.) general. Command/Address transition once every clock cycles. Command/Address stable VIL.
Characteristics +70°C, VDD, VDDQ 2.5V 0.2V, (DDR SDRAM component Specification)
Symbol min. -15.2 15.2
Preliminary Data Sheet E0376E10 (Ver. 1.0)
max.
Unit
Test condition
Notes
VDDQ VOUT VOUT 1.95V
VOUT 0.35V
EBD51RD8ABFA
Capacitance 25°C, 2.5V 0.2V)
Parameter Input capacitance Input capacitance Data input/output capacitance Symbol Pins Address, /RAS, /CAS, /WE, /CS, DQS, max. Unit Notes
Notes: These parameters measured conditions: 100MHz, VOUT VDDQ/2, VOUT 0.2V. Dout circuits disabled. This parameter sampled 100% tested. Characteristics +70°C, VDD, VDDQ 2.5V 0.2V,
Parameter Clock cycle time 2.5) high-level width low-level width half period output access time from skew Data hold skew factor Read preamble Read postamble input setup time input hold time Write preamble setup time Write preamble Write postamble input high pulse width input pulse width
(DDR SDRAM component Specification)
Symbol min. 0.45 0.45 (tCH, tCL) -0.7 0.55 0.55 0.45 min. 0.45 0.45 (tCH, tCL) -0.75 -0.75 0.55 0.55 0.75 0.75 min. 0.45 0.45 (tCH, tCL) -0.75 -0.75 0.55 0.55 0.75 0.75 Unit Notes
output access time from tDQSCK -0.6 tDQSQ
DQ/DQS output hold time from
Data-out high-impedance time from Data-out low-impedance time from
input pulse width
Write command first latching transition falling edge setup time falling edge hold time from
Address control input setup time Address control input hold time
Preliminary Data Sheet E0376E10 (Ver. 1.0)
tQHS tRPRE tRPST tDIPW tWPRE tWPST tDQSS tDSS tDSH tDQSH tDQSL
tQHS 0.55 -0.7 -0.75 -0.7 0.45 0.45 1.75 -0.75 1.75 tWPRES 0.25 0.75 0.35 0.35 0.75 0.75 0.25 1.25 0.75 0.35 0.35
tQHS 0.75 0.75 0.75
tQHS -0.75 -0.75 0.75 0.75 0.75
1.75 0.25 1.25 0.75 0.35 0.35
1.25
EBD51RD8ABFA
Parameter Address control input pulse width Symbol tIPW min. tRCD min. 120000 min. tRCD min. 120000 min. tRCD min. 120000 Unit Notes
Mode register command cycle time tMRD Active Precharge command period tRAS Active Active/Auto refresh command period Auto refresh Active/Auto refresh tRFC command period Active Read/Write delay Precharge active command period Active auto precharge delay Active active command period Write recovery time Auto precharge write recovery precharge time Average periodic refresh interval tRCD tRAP tRRD tDAL
(tWR/tCK)+ (tRP/tCK)
(tWR/tCK)+ (tRP/tCK)
(tWR/tCK)+ (tRP/tCK)
Internal write Read command delay tWTR tREF
Notes: parameters listed this data sheet component specifications. testing conditions, refer corresponding component data sheet. This parameter defines signal transition delay from cross point /CK. signal transition defined occur when signal level crossing VTT. timing reference level VTT. Output valid window defined period between successive transition data (read) signals. signal transition defined occur when signal level crossing VTT. defined DOUT transition delay from Low-Z High-Z read burst operation. timing reference cross point /CK. This parameter referred specific DOUT voltage level, specify when device output stops driving. defined DOUT transition delay from High-Z Low-Z beginning read operation. This parameter referred specific DOUT voltage level, specify when device output begins driving. Input valid windows defined period between successive transition data input (write) signals. signal transition defined occur when signal level crossing VREF. timing reference level VREF. transition from Low-Z High-Z defined occur when device output stops driving. specific reference voltage judge this transition given. (max.) determined lock range DLL. Beyond this lock range, operation assured. (min.) when these parameters measured. Otherwise, absolute minimum values these values tCK. assumed 2.5V 0.2V. power supply variation cycle expected less than 0.4V/400 cycle. tDAL (tWR/tCK)+(tRP/tCK) each terms above, already integer, round next highest integer. Example: Speed 2.5, 7.5ns, 15ns tRP= 20ns, tDAL (15ns/7.5ns) (20ns/7.5ns) tDAL clocks
Preliminary Data Sheet E0376E10 (Ver. 1.0)
EBD51RD8ABFA
Timing Parameter Measured Clock Cycle Registered DIMM
Number clock cycle Parameter Write pre-charge command delay (same bank) Read pre-charge command delay (same bank) Write read command delay input data) Burst stop command write command delay Symbol tWPD tRPD tWRD tBSTW tBSTW tBSTZ tBSTZ tRWD tRWD tHZP tHZP min. BL/2 BL/2 BL/2 BL/2 max. 7.5ns min. BL/2 BL/2 BL/2 BL/2 BL/2 max. Unit
3.5) 3.5) 3.5) 3.5) Write recovery Power down entry
Burst stop command High-Z Read command write command delay output data) Pre-charge command High-Z
Write command data latency
Register command active register command Self refresh exit read command
Self refresh exit non-read command tSNR
Power down exit command input
Preliminary Data Sheet E0376E10 (Ver. 1.0)
tSRD
tWCD
tMRD
tPDEN tPDEX
EBD51RD8ABFA
Functions
(input pin) master clock inputs. inputs except DMs, DQSs referred cross point rising edge VREF level. When read operation, DQSs referred cross point /CK. When write operation, referred cross point VREF level. DQSs write operation referred cross point /CK. (input pin) When low, commands data input. When high, inputs ignored. However, internal operations (bank active, burst operations, etc.) held. /RAS, /CAS, (input pins) These pins define operating commands (read, write, etc.) depending combinations their voltage levels. "Command operation". (input pins) address (AX0 AX12) determined level cross point rising edge VREF level bank active command cycle. Column address (AY0 AY9, AY11) loaded cross point rising edge VREF level read write command cycle. This column address becomes starting address burst operation. (AP) (input pin) defines precharge mode when precharge command, read command write command issued. high when precharge command issued, banks precharged. when precharge command issued, only bank that selected BA1, precharged. high when read write command, auto-precharge function enabled. While low, auto-precharge function disabled. BA0, (input pin) BA0, bank select signals (BA). memory array divided into bank bank bank bank (See Bank Select Signal Table)
Bank Bank Bank Bank
[Bank Select Signal Table]
Remark: VIH. VIL.
(input pin) controls power down self-refresh. power down self-refresh commands entered when driven exited when resumes high. level must kept cycle least, that changes cross point rising edge VREF level with proper setup time tIS, next rising edge level must kept with proper hold time tIH. (input output pins) Data input output from these pins.
(input output pin) provide read data strobes output) write data strobes input).
Preliminary Data Sheet E0376E10 (Ver. 1.0)
EBD51RD8ABFA
(input pins): reference signal data input mask function. sampled cross point VREF (power supply pins) 2.5V applied. (VDD internal circuit.) VDDSPD (power supply pin) 2.5V applied (For serial EEPROM). (power supply pin) Ground connected. /RESET (input pin) LVCMOS reset input. When /RESET low, registers reset outputs low.
Detailed Operation Part Timing Waveforms
Refer EDD5104AB, EDD5108AB datasheet (E0237E). DIMM /CAS latency component registered type.
Preliminary Data Sheet E0376E10 (Ver. 1.0)
EBD51RD8ABFA
Physical Outline
Unit: 133.35 0.15 128.95 4.80 (64.48) (DATUM -A-)
2.30
Component area (Front)
49.53
64.77
1.27 0.10
2.50 0.10
10.00
4.00
4.00 0.10
2.50 0.20
0.20 0.15
3.80
2.00
Component area (Back)
3.00
Detail
Detail 1.27 6.62 2.175 0.90 (DATUM -A-)
6.35
1.00 0.05
1.80 0.10
Note: Tolerance dimensions 0.13 unless otherwise specified.
ECA-TS2-0058-01
Preliminary Data Sheet E0376E10 (Ver. 1.0)
30.48 0.15
17.80
EBD51RD8ABFA
CAUTION HANDLING MEMORY MODULES
When handling inserting memory modules, sure touch components modules, such memory ICs, chip capacitors chip resistors. necessary avoid undue mechanical stress these components prevent damaging them. particular, push module cover drop modules order protect from mechanical defects, which would electrical defects. When re-packing memory modules, sure modules touching each other. Modules contact with other modules cause excessive mechanical stress, which damage modules.
MDE0202
NOTES CMOS DEVICES
PRECAUTION AGAINST DEVICES
Exposing devices strong electric field cause destruction gate oxide ultimately degrade devices operation. Steps must taken stop generation static electricity much possible, quickly dissipate when once occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS DEVICES
connection CMOS devices input pins cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. unused pins must handled accordance with related specifications.
STATUS BEFORE INITIALIZATION DEVICES
Power-on does necessarily define initial status devices. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee output levels, settings contents registers. devices initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Preliminary Data Sheet E0376E10 (Ver. 1.0)
CME0107
EBD51RD8ABFA
information this document subject change without notice. Before using this document, confirm that this latest version.
part this document copied reproduced form means without prior written consent Elpida Memory, Inc. Elpida Memory, Inc. does assume liability infringement intellectual property rights (including limited patents, copyrights, circuit layout licenses) Elpida Memory, Inc. third parties arising from products information listed this document. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights Elpida Memory, Inc. others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. Elpida Memory, Inc. assumes responsibility losses incurred customers third parties arising from these circuits, software information. [Product applications] Elpida Memory, Inc. makes every attempt ensure that products high quality reliability. However, users instructed contact Elpida Memory's sales office before using product aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment life support, other such application which especially high quality reliability demanded where failure malfunction directly threaten human life cause risk bodily injury. [Product usage] Design your application that product used within ranges conditions guaranteed Elpida Memory, Inc., including maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions other related characteristics. Elpida Memory, Inc. bears responsibility failure damage when product used beyond guaranteed ranges conditions. Even within guaranteed ranges conditions, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Elpida Memory, Inc. products does cause bodily injury, fire other consequential damage operation Elpida Memory, Inc. product. [Usage environment] This product designed resistant electromagnetic waves radiation. This product must used non-condensing environment. export products technology described this document that controlled Foreign Exchange Foreign Trade Japan, must follow necessary procedures accordance with relevant laws regulations Japan. Also, export products/technology controlled U.S. export control regulations, another country's export control laws regulations, must follow necessary procedures accordance with such laws regulations. these products/technology sold, leased, transferred third party, third party granted license these products, that third party must made aware that they responsible compliance with relevant laws regulations.
Preliminary Data Sheet E0376E10 (Ver. 1.0)
M01E0107

EBD51RD8ABFA (64M words bits, Rank) EBD51RD8ABFA words bits, rank

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