EBD52UC8AARA (64M words bits, Ranks) EBD52UC8AARA words bits, ran
|
|
|
Top Searches for this datasheet
512MB SDRAM DIMM
EBD52UC8AARA (64M words bits, Ranks)
EBD52UC8AARA words bits, ranks Double Data Rate (DDR) SDRAM Small Outline Dual In-line Memory Module, mounting pieces 256M bits SDRAM sealed sTSOP package. Read write operations performed cross points /CK. This high-speed data transfer realized bits prefetch-pipelined architecture. Data strobe (DQS) both read write available high speed reliable data design. setting extended mode register, on-chip Delay Locked Loop (DLL) enable disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors mounted beside each sTSOP module board.
Features
200-pin socket type small outline dual line memory module DIMM) height: 31.75mm Lead pitch: 0.6mm 2.5V power supply Data rate: 333Mbps/266Mbps (max.) (SSTL_2 compatible) Double Data Rate architecture; data transfers clock cycle Bi-directional, data strobe (DQS) transmitted /received with data, used capturing data receiver Data inputs, outputs synchronized with internal banks concurrent operation (Component) edge aligned with data READs; center aligned with data WRITEs Differential clock inputs /CK) aligns transitions with transitions Commands entered each positive edge; data referenced both edges Data mask (DM) write data Auto precharge option each burst access Programmable burst length: Programmable /CAS latency (CL): Refresh cycles: (8192 refresh cycles /64ms) 7.8µs maximum average periodic refresh interval variations refresh Auto refresh Self refresh
Document E0341E40 (Ver. 4.0) Date Published June 2003 Japan URL: http://www.elpida.com Elpida Memory Inc. 2003
EBD52UC8AARA
Ordering Information
Data rate Mbps (max.) Component JEDEC speed (CL-tRCD-tRP) DDR333B (2.5-3-3) DDR266A (2-3-3) DDR266B (2.5-3-3) Contact
Part number EBD52UC8AARA-6B EBD52UC8AARA-7A EBD52UC8AARA-7B
Package
Mounted devices M2S56D30AKT-60 M2S56D30AKT-60, M2S56D30AKT-60, -75A,
200-pin DIMM Gold
Configurations
Front side
Back side
name VREF DQS0 DQS1 DQ10 DQ11 /CK0 DQ16 DQ17 DQS2 DQ18
name DQ19 DQ24 DQ25 DQS3 DQ26 DQ27 /CK2 CKE1
name VREF DQ12 DQ13 DQ14 DQ15 DQ20 DQ21 DQ22
name DQ23 DQ28 DQ29 DQ30 DQ31 CKE0
Preliminary Data Sheet E0341E40 (Ver. 4.0)
EBD52UC8AARA
name A10/AP /CS0 DQ32 DQ33 DQS4 DQ34 DQ35 DQ40 DQ41 DQS5
name DQ42 DQ43 DQ48 DQ49 DQS6 DQ50 DQ51 DQ56 DQ57 DQS7 DQ58 DQ59 VDDSPD VDDID
name /RAS /CAS /CS1 DQ36 DQ37 DQ38 DQ39 DQ44 DQ45
name DQ46 DQ47 /CK1 DQ52 DQ53 DQ54 DQ55 DQ60 DQ61 DQ62 DQ63
Preliminary Data Sheet E0341E40 (Ver. 4.0)
EBD52UC8AARA
name BA0, DQ63 /RAS /CAS /CS0, /CS1 CKE0, CKE1 /CK0 /CK2 DQS0 DQS7 VDDSPD VREF VDDID Function Address input address Column address Data input/output address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input output data strobe Input mask Clock input serial Data input/output serial Serial address input Power internal circuit Power serial EEPROM Input reference voltage Ground identification flag connection
Bank select address
Preliminary Data Sheet E0341E40 (Ver. 4.0)
EBD52UC8AARA
Serial Matrix
Byte Function described Number bytes utilized module manufacturer Total number bytes serial device Memory type Number address Number column address Number DIMM ranks Module data width Module data width continuation SDRAM cycle time, -7A, SDRAM access from clock (tAC) -7A, DIMM configuration type Refresh rate/type Primary SDRAM width Error checking SDRAM width SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number banks SDRAM device SDRAM device attributes: latency SDRAM device attributes: latency SDRAM module attributes SDRAM device attributes: General Minimum clock cycle time -0.5 -6B, Maximum data access time (tAC) from clock -0.5 -7A, Minimum precharge time (tRP) -7A, Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value 18ns 20ns 0.70ns*1 0.75ns*1 0.70ns*1 0.75ns*1 None 7.8µs Self refresh used 2,4,8 Unbuffered 0.2V Comments bytes bytes SDRAM bits SSTL2 2.5*1
Voltage interface level this assembly
SDRAM device attributes: /CAS latency
Preliminary Data Sheet E0341E40 (Ver. 4.0)
EBD52UC8AARA
Byte Function described
Bit7
Bit6
Bit5 Bit4
Bit3
Bit2
Bit1 Bit0
value
Comments 12ns 15ns 18ns 20ns 42ns 45ns 256M bytes 0.75ns*1 0.9ns*1 0.75ns*1 0.9ns*1 0.45ns*1 0.5ns*1 0.45ns*1 0.5ns*1 Future 60ns*1 65ns*1 72ns*1 75ns*1 15ns*1 0.45ns*1 0.5ns*1 0.55ns*1 0.75ns*1 Future
Minimum active active delay (tRRD) -7A, Minimum /RAS /CAS delay (tRCD) -7A, Minimum active precharge time (tRAS) -7A, Module rank density Address command setup time before clock (tIS) -7A, Address command hold time after clock (tIH) -7A,
Data input setup time before clock (tDS) -7A, Data input hold time after clock (tDH) -7A, Superset information Active command period (tRC) -7A, Auto refresh active/ Auto refresh command cycle (tRFC) -7A, SDRAM cycle max. (tCK max.) Dout skew -7A, Data hold skew (tQHS) -7A, Superset information Revision Checksum bytes
Manufacturer's JEDEC code Manufacturer's JEDEC code Manufacturer's JEDEC code
Continuation code Elpida Memory
Preliminary Data Sheet E0341E40 (Ver. 4.0)
EBD52UC8AARA
Byte Function described Manufacturing location Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number -7A, Module part number -6B, Module part number Revision code Revision code Manufacturing date Manufacturing date Module serial number Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments (ASCII-8bit code) (Space) Initial (Space) Year code (HEX) Week code (HEX)
Manufacture specific data
Note:
These specifications defined based component specification, module.
Preliminary Data Sheet E0341E40 (Ver. 4.0)
EBD52UC8AARA
Block Diagram
/CS0 /CS1 DQS0 DQS4
DQS1 DQ15 I/O0 I/O7
DQ32 DQ39
I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
I/O0 I/O7
DQS5 I/O0 I/O7 DQ40 DQ47 I/O0 I/O7 I/O0 I/O7
DQS2 DQ16 DQ23 DQS3 DQ24 DQ31 I/O0 I/O7 I/O0 I/O7 DQS7 I/O0 I/O7 I/O0 I/O7 DQS6
DQ48 DQ55 I/O0 I/O7
I/O0 I/O7
DQ56 DQ63 I/O0 I/O7
I/O0 I/O7
Serial /RAS /CAS CKE0 CKE1 VDDSPD VREF SDRAMs D15) SDRAMs D15) SDRAMs D15) SDRAMs D15) SDRAMs D15) SDRAMs SDRAMs D15) SDRAMs D15) SDRAMs D15) Notes VDDID SDRAMs D15) SDRAMs D15) wiring differ from that described this drawing; however DQ/DM/DQS relationships maintained shown. VDDID strap connections: 256M bits SDRAM EEPROM (for memory device VDD, VDDQ) Strap (open): VDDQ Strap (closed): VDDQ pull-up registor reguired open-drain/open-collector output. pull-up registor recommended, because normal lime inactive "high" state. /CK0 /CK1 /CK2 loads loads loads
Preliminary Data Sheet E0341E40 (Ver. 4.0)
EBD52UC8AARA
Electrical Specifications
voltages referenced (GND). Absolute Maximum Ratings
Parameter Voltage relative Supply voltage relative Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol Tstg Value -1.0 +3.6 -1.0 +3.6 +125 Unit Note
Note: SDRAM component specification. Caution Exposing device stress above those listed Absolute Maximum Ratings could cause permanent damage. device meant operated under conditions outside limits described operational section this specification Exposure Absolute Maximum Rating conditions extended periods affect device reliability.
Operating Conditions +70°C) (DDR SDRAM Component Specification)
Parameter Supply voltage Symbol VDD, VDDQ Input reference voltage Termination voltage Input high voltage Input voltage Input voltage level, inputs Input differential cross point voltage, inputs Input differential voltage, inputs VREF (DC) (DC) (DC) (DC) (DC) 0.49 VDDQ VREF 0.04 VREF 0.15 -0.3 -0.3 VDDQ 0.2V 0.36 0.50 VDDQ VREF VDDQ 0.51 VDDQ VREF 0.04 VDDQ VREF 0.15 VDDQ Unit Notes
VDDQ 0.2V VDDQ
Notes:
VDDQ must lower than equal VDD. allowed exceed 3.6V period shorter than equal 5ns. allowed outreach below down -1.0V period shorter than equal 5ns. (DC) specifies allowable execution each differential input. (DC) specifies input differential voltage required switching. (CK) assumed over VREF 0.18V, (CK) assumed under VREF 0.18V measurement.
Preliminary Data Sheet E0341E40 (Ver. 4.0)
EBD52UC8AARA
Characteristics +70°C, 2.5V 0.2V,
Parameter Operating current (ACTV-PRE) Operating current (ACTV-READ-PRE) Idle power down standby current Active power down standby current Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto refresh current Self refresh current Operating current banks interleaving) Symbol IDD0 IDD1 IDD2P IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7A -7A, Grade -7A, -7A, -7A, -7A, -7A, -7A, -7A, -7A, max. 1240 1040 1400 1160 1960 1560 1960 1480 1640 1480 2760 2240 Unit Test condition VIH, (min.) VIH, 2.5, (min.) VIH, tRAS tRAS (max.) VIH, VIH, tRFC tRFC (min.), Input Input Input Notes
Notes.
These data measured under condition that pins connected. bank operation. bank active. banks idle. Command/Address transition once cycle. transition twice clock cycle. banks active. Only bank running (min.) data this table measured with regard (min.) general. Command/Address transition once every clock cycles.
Characteristics +70°C, VDD, VDDQ 2.5V 0.2V,
Parameter Input leakage current Output leakage current Output high current Output current Symbol min. -16.8 16.8 max. Unit Test condition VOUT VOUT 0.84V VOUT 0.84V Notes
Note: SDRAM component specification.
Preliminary Data Sheet E0341E40 (Ver. 4.0)
EBD52UC8AARA
Capacitance 25°C, 2.5V 0.2V)
Parameter Input capacitance Input capacitance Data input/output capacitance Symbol Pins Address, /RAS, /CAS, /CK, CKE, DQS, max. Unit Notes
Characteristics +70°C, VDD, VDDQ 2.5V 0.2V, (DDR SDRAM Component Specification)
Parameter Clock cycle time 2.5) high-level width low-level width half period output access time from output access time from skew Symbol min. 0.45 0.45 0.55 0.55 min. 0.45 0.45 0.55 0.55 min. 0.45 0.45 0.55 0.55 Unit Notes
(tCH, tCL) -0.70 0.70 0.60 0.45
(tCH, tCL) -0.75 -0.75 0.75 0.75
(tCH, tCL) -0.75 -0.75 0.75 0.75
tDQSCK -0.60 tDQSQ
DQ/DQS output hold time from Data-out high-impedance time from Data-out low-impedance time from Read preamble Read postamble input setup time input hold time input pulse width Write preamble setup time Write preamble Write postamble Write command first latching transition falling edge setup time tRPRE tRPST tDIPW
0.55 -0.70 -0.70 0.45 0.45 1.75 0.70 0.70 1.25 120000
0.75 -0.75 -0.75 1.75 0.25 0.75 0.35 0.35 0.75 0.75 1.25 120000
0.75 -0.75 -0.75 1.75 0.25 0.75 0.35 0.35 0.75 0.75 1.25 120000
tWPRES tWPRE tWPST tDQSS tDSS 0.25 0.75 0.35 0.35 0.75 0.75
falling edge hold time from tDSH input high pulse width input pulse width Address control input setup time Mode register command cycle time Active Precharge command period tDQSH tDQSL
Address control input hold time tMRD tRAS
Preliminary Data Sheet E0341E40 (Ver. 4.0)
EBD52UC8AARA
Parameter Active Active/Auto refresh command period Auto refresh Active/Auto refresh command period Active Read/Write delay Precharge active command period Active active command period Write recovery time Auto precharge write recovery precharge time Internal write Read command delay Exit self refresh non-read command Exit self refresh read command Symbol tRFC tRCD tRRD tDAL tWTR tXSNR tXSRD min. min. min. Unit Notes
Exit power down non-read tXPNR command Exit precharge power down read tXPRD command Average periodic refresh interval tREF
Notes:
transitions occur same access time windows valid data transitions. These parameters referenced specific voltage level, specify when device output longer driving (HZ), begins driving (LZ). maximum limit this parameter device limit. device will operate with greater value this parameter, system performance (bus turnaround) will degrade accordingly. specific requirement that valid (High, Low, some point valid transition) before this edge. valid transition defined monotonic, meeting input slew rate specifications device. When writes were previously progress bus, will transitioning from High-Z logic Low. previous write progress, could High, Low, transitioning from High this time, depending tDQSS. maximum eight auto refresh commands posted given SDRAM device. tXPRD should condition unstable operation during power down mode. command/address slew rate 1.0V/ns.
Preliminary Data Sheet E0341E40 (Ver. 4.0)
EBD52UC8AARA
Functions
(input pin) master clock inputs. inputs except DMs, DQSs referred cross point rising edge VREF level. When read operation, DQSs referred cross point /CK. When write operation, referred cross point VREF level. DQSs write operation referred cross point /CK. (input pin) When low, commands data input. When high, inputs ignored. However, internal operations (bank active, burst operations, etc.) held. /RAS, /CAS, (input pins) These pins define operating commands (read, write, etc.) depending combinations their voltage levels. "Command operation". (input pins) address (AX0 AX12) determined level cross point rising edge VREF level bank active command cycle. Column address (AY0 AY9) loaded cross point rising edge VREF level read write command cycle. This column address becomes starting address burst operation. (AP) (input pin) defines precharge mode when precharge command, read command write command issued. high when precharge command issued, banks precharged. when precharge command issued, only bank that selected BA1, precharged. high when read write command, auto-precharge function enabled. While low, auto-precharge function disabled. BA0, (input pin) BA0, bank select signals (BA). memory array divided into bank bank bank bank (See Bank Select Signal Table) [Bank Select Signal Table]
Bank Bank Bank Bank
Remark: VIH. VIL. (input pin) controls power down self-refresh. power down self-refresh commands entered when driven exited when resumes high. level must kept cycle least, that changes cross point rising edge VREF level with proper setup time tIS, next rising edge level must kept with proper hold time tIH. (input output pins) Data input output from these pins. (input output pin) provide read data strobes output) write data strobes input).
Preliminary Data Sheet E0341E40 (Ver. 4.0)
EBD52UC8AARA
(input pins): reference signal data input mask function. sampled cross point VREF (power supply pins) 2.5V applied. (VDD internal circuit.) VDDSPD (power supply pin) 2.5V applied (For serial EEPROM). (power supply pin) Ground connected.
Detailed Operation Part Timing Waveforms
Refer M2S56D20/30/40AKT datasheet.
Preliminary Data Sheet E0341E40 (Ver. 4.0)
EBD52UC8AARA
Physical Outline
Unit: 67.60 63.60 11.55 18.45 3.80 (DATUM -A-)
Full Component area (Front)
31.75
6.00
2.15
11.40 4.20
47.40
2.45 1.00 0.10
4.20 1.50 2.45
11.40
47.40
2.15 R0.50 0.20
R0.50 0.20
1.80 Component area (Back) (DATUM -A-)
Detail
(DATUM -A-) FULL
4.00 0.10
Detail
4.00 0.10
2.00 Min.
20.0
0.60 1.80 1.00 0.10 0.45 0.03
ECA-TS2-0090-01
Preliminary Data Sheet E0341E40 (Ver. 4.0)
0.25
2.55
4.00
EBD52UC8AARA
CAUTION HANDLING MEMORY MODULES
When handling inserting memory modules, sure touch components modules, such memory ICs, chip capacitors chip resistors. necessary avoid undue mechanical stress these components prevent damaging them. particular, push module cover drop modules order protect from mechanical defects, which would electrical defects. When re-packing memory modules, sure modules touching each other. Modules contact with other modules cause excessive mechanical stress, which damage modules.
MDE0202
NOTES CMOS DEVICES
PRECAUTION AGAINST DEVICES
Exposing devices strong electric field cause destruction gate oxide ultimately degrade devices operation. Steps must taken stop generation static electricity much possible, quickly dissipate when once occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS DEVICES
connection CMOS devices input pins cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. unused pins must handled accordance with related specifications.
STATUS BEFORE INITIALIZATION DEVICES
Power-on does necessarily define initial status devices. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee output levels, settings contents registers. devices initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
CME0107
Preliminary Data Sheet E0341E40 (Ver. 4.0)
EBD52UC8AARA
information this document subject change without notice. Before using this document, confirm that this latest version.
part this document copied reproduced form means without prior written consent Elpida Memory, Inc. Elpida Memory, Inc. does assume liability infringement intellectual property rights (including limited patents, copyrights, circuit layout licenses) Elpida Memory, Inc. third parties arising from products information listed this document. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights Elpida Memory, Inc. others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. Elpida Memory, Inc. assumes responsibility losses incurred customers third parties arising from these circuits, software information. [Product applications] Elpida Memory, Inc. makes every attempt ensure that products high quality reliability. However, users instructed contact Elpida Memory's sales office before using product aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment life support, other such application which especially high quality reliability demanded where failure malfunction directly threaten human life cause risk bodily injury. [Product usage] Design your application that product used within ranges conditions guaranteed Elpida Memory, Inc., including maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions other related characteristics. Elpida Memory, Inc. bears responsibility failure damage when product used beyond guaranteed ranges conditions. Even within guaranteed ranges conditions, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Elpida Memory, Inc. products does cause bodily injury, fire other consequential damage operation Elpida Memory, Inc. product. [Usage environment] This product designed resistant electromagnetic waves radiation. This product must used non-condensing environment. export products technology described this document that controlled Foreign Exchange Foreign Trade Japan, must follow necessary procedures accordance with relevant laws regulations Japan. Also, export products/technology controlled U.S. export control regulations, another country's export control laws regulations, must follow necessary procedures accordance with such laws regulations. these products/technology sold, leased, transferred third party, third party granted license these products, that third party must made aware that they responsible compliance with relevant laws regulations.
M01E0107
Preliminary Data Sheet E0341E40 (Ver. 4.0)
Other recent searches
TEA0676T - TEA0676T TEA0676T Datasheet
SLLS352C - SLLS352C SLLS352C Datasheet
LM22678 - LM22678 LM22678 Datasheet
JDP2S04E - JDP2S04E JDP2S04E Datasheet
GVXO-525 - GVXO-525 GVXO-525 Datasheet
CGB191 - CGB191 CGB191 Datasheet
B41112 - B41112 B41112 Datasheet
2SD2167 - 2SD2167 2SD2167 Datasheet
2SC3338 - 2SC3338 2SC3338 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
