OVERVIEW MC92600 Quad high-speed, full-duplex, serializer/deseria

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OVERVIEW MC92600 Quad high-speed, full-duplex, serializer/deseria

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MC92600FACT/D Rev. 3/2003 Quad 1.25 Gbaud SERDES Transceiver
OVERVIEW
MC92600 Quad high-speed, full-duplex, serializer/deserializer (SERDES) data interface that used transmit data between chips across board, through backplane, through cabling. Four transceivers transmit receive coded data rate gigabit second (Gbps) through each 1.25 gigabaud link. rich feature makes easily adaptable many broadband applications. MC92600 carefully designed power consumption. 0.25 micron CMOS implementation nominally consumes less than with links operating full speed.
TYPICAL APPLICATIONS
High-speed data transfer applications high-bandwidth backplane chassis-to-chassis networking High-end router systems Backbone switches Storage Area Network equipment High-speed Automatic Test Equipment
PRODUCT HIGHLIGHTS
Four full-duplex differential data links Selectable speed range: 1.25 Gbaud 0.625 Gbaud power; approximately under typical conditions, while operating transceivers full speed Internal Fibre Channel 8B/10B encoder/decoder that bypassed Ten-Bit Interface mode Single double data rate, 8-bit 10-bit LVTTL parallel data interfaces On-chip 50-ohm series source termination parallel outputs Link-to-link synchronization supports aligned, 32-bit, word transfers. Synchronization mechanism tolerates 40-bit times link-to-link media delay Receivers have three alignment modes operation: Byte alignment with idle realignment Disparity word alignment aligned Received data clocked recovered clock reference clock frequencies Selectable serial link impedance; 50-ohm 75-ohm media (100- 150-ohm differential) Link inputs have on-chip receiver link termination "hot-swap" compatible Repeater mode configures MC92600 Quad into 4-link receive-transmit repeater Full-speed built-in self test mode test on-board diagnostics
More Information This Product, www.freescale.com
TECHNICAL SPECIFICATIONS
channels have: 8B/10B encoder/decoder that enabled bypassed Clock generation/recovery Idle/control character generation/detection Transceiver Links operate over 50-ohm 75-ohm media (100- 150-ohm differential) lengths meters FR-4 board/back-plane, meters coax
PARAMETRICS
Power Supply Core Power Supply: 0.15 Power Supply: Link Power Supply: 0.15 Power Dissipation Typical operation: <200 channel maximum speed
external loop filter termination components required System BIST test modes with error counters Loopback BIST isolated from link inputs outputs single-ended reference clock input (125 max) Frequency offset tolerance between transmitter receiver excess Technology: High-performance 0.25 CMOS Process, five-layer metal
PACKAGE
MAPBGA (15x15 body size, ball pitch) PBGA (23x23 body size, 1.27 ball pitch)
Four transceivers
XMIT_x _[7:0] XMIT_x XMIT_x _IDLE_B
Transmitter
BIST
Transmit Interface Unit
8B10B Encoder
XLINK_x_N
XLINK_x_P MEDIA
Interface Receiver
Receiver
MC92600 Quad SERDES Block Diagram
RECV_x_[7:0] RECV_x_K RECV_x_9 RECV_x_IDLE RECV_x_E RECV_x_CLK
8B10B Decoder
RLINK_x RLINK_x
RCCE WSE, WSE_GEN, HSE, DDRE, ADIE BSYNC_0, BSYNC_1, REPE LBE, LBOE, T_0, RESET, TNDBY
System
REF_CLK
System Configuration Unit
CONTACT INFORMATION
additional information this device, please contact Motorola SERDES Applications Phone: 480-814-2208 email: R4028C@ motorola.com
MOTOROLA Stylized Logo registered Patent Trademark Office. other product service names property their respective owners. Motorola Inc. 2003 MC92600FACT/D Rev. 03/2003
1PHX37195-0 Printed 03/03 Imperial Litho 56065 1,000 LITMOSCM
More Information This Product, www.freescale.com

OVERVIEW MC92600 Quad high-speed, full-duplex, serializer/deseria

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