Literature Number: SPRS197D August 2002 Revised August 2004 IMPOR
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OMAP5910 Dual-Core Processor
Literature Number: SPRS197D August 2002 Revised August 2004
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Revision History
REVISION HISTORY
This data sheet revision history highlights technical changes made SPRS197C device-specific data sheet make SPRS197D revision. Scope: This document been reviewed technical accuracy; technical content up-to-date specified release date includes following changes.
PAGE(S)
ADDITIONS/CHANGES/DELETIONS Removed references MMC/SD mode that longer supported. Table 2-1: Added footnote V12; "See Section 5.6.1 Section 5.6.2 special considerations with oscillator circuits." Changed from "USB0.DP" "USB.DP" Table 2-2: Added footnote "See Section 5.6.1 Section 5.6.2 special considerations with oscillator circuits." Changed from "USB0.DP" "USB.DP" Table 2-4: Added A11, A13, list Pins Changed column Changed USB1.TXEN column from Changed LCD.PCLK LCD.P[15:0] description from "LCD panels" "LCD panel" Changed SDRAM.CLK description include "SDRAM.CLK also configured input monitor skew control." Changed STAT_VAL/WKUP description remove "STAT_VAL/WKUP configured software function external wake-up signal OMAP5910 device request chip wake-up during sleep modes." Changed last bullet Section from: controller supporting monochrome panels color panels controller supporting monochrome panels (STN) color panels (STN TFT) Section 3.3.4, changed last sentence first paragraph from: Accessing registers with incorrect access width result unexpected results including Peripheral (TIPB) error associated TIPB interrupt. Accessing registers with incorrect access width cause unexpected results including Peripheral (TIPB) error associated TIPB interrupt. Combined bullets:
Selectable UART/autobauding modes (autobauding UART1 UART2) Auto bauding between 1200bits/s 115.2K bits/s Selectable UART/autobauding modes (autobauding UART1 UART2) with autobauding between 1200 bits/s 115.2K bits/s
read follows:
Revised Section 3.11 removed bulleted list replace with following: "The EMIFF Interface provides access 16-bit-wide access standard SDRAM memories IMIF provides access 192K bytes on-chip SRAM."
August 2002 Revised August 2004
SPRS197D
Revision History
PAGE(S)
ADDITIONS/CHANGES/DELETIONS Section 3.13, removed following bulleted items:
Quantization /Dequantization (useful JPEG, MPEG, H.26x Encoding/Decoding) Flexible 1D/2D Wavelet Processing (useful JPEG2000, MPEG4, other compression standards) Boundary Perimeter Computation (useful Machine Vision applications) Image Threshold Histogram Computations (useful various Image Analysis applications)
Revised Table 3-17 change access width from bit. Changed MPU_READ_TIM_WD address FFFE:C804 changed MPU_TIMER_MODE_WD address FFFE:C808. Revised Section added Figure 4-1, OMAP Device Nomenclature Changed Section 5.6.2, first paragraph, third line from internal oscillator used (configured software), external clock source must applied OSC1_IN OSC1_OUT must left unconnected." internal oscillator used (configured software using FUNC_MUX_CTRL_B register), external clock source must applied OSC1_IN OSC1_OUT must left unconnected." Revised Table 5-10 Revised Table 5-11 Changed footnote Table 5-14 from: 1/(Base frequency) McBSP1 1/(AMPER_CK clock frequency) nanoseconds (ns) McBSP 2.Base frequency 13MHz". "Regardless whether MCBSP.CLKS internally externally clocked, 1/(DSPXOR_CK) McBSP1 McBSP3, 1/(AMPER_CK) McBSP2. OMAP5910 Dual-Core Processor Clock Generation System Reset Management Reference Guide (literature number SPRU678) additional details."
SPRS197D
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Contents
Contents
Section OMAP5910 Features Introduction Description 2.1.1 TMS320C55x Core 2.1.2 TI-Enhanced TI925T RISC Processor Terminal Assignments Terminal Characteristics Multiplexing Signal Description Functional Overview Functional Block Diagram Features Memory Maps 3.2.1 Global Memory 3.2.2 Subsystem Registers Memory Memory Maps 3.3.1 Global Memory 3.3.2 On-Chip Dual-Access (DARAM) 3.3.3 On-Chip Single-Access (SARAM) 3.3.4 Space Memory External Memory (Managed MMU) Private Peripherals 3.5.1 Timers 3.5.2 Timer (MPU only) 3.5.3 Watchdog Timer 3.5.4 Interrupt Handlers 3.5.5 Controller Public Peripherals 3.6.1 Host Controller 3.6.2 Function Peripheral 3.6.3 Multichannel Buffered Serial Port (McBSP) 3.6.4 Master/Slave Interface 3.6.5 MICROWIRE Serial Interface 3.6.6 Multimedia Card/Secure Digital (MMC/SD) Interface 3.6.7 HDQ/1-Wire Interface 3.6.8 Camera Interface 3.6.9 MPUIO/Keyboard Interface 3.6.10 Pulse-Width Light (PWL) 3.6.11 Pulse-Width Tone (PWT) 3.6.12 Pulse Generator 3.6.13 Real-Time Clock 3.6.14 Frame Adjustment Counter Public Peripherals 3.7.1 Multichannel Buffered Serial Port (McBSP) 3.7.2 Multichannel Serial Interface (MCSI) Page
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Contents
Section Shared Peripherals 3.8.1 Universal Asynchronous Receiver/Transmitter (UART) 3.8.2 General-Purpose (GPIO) 3.8.3 Mailbox Registers System Controller Controller Traffic Controller (Memory Interfaces) Interprocessor Communication 3.12.1 MPU/DSP Mailbox Registers 3.12.2 Interface (MPUI) 3.12.3 MPU/DSP Shared Memory Hardware Accelerators 3.13.1 DCT/iDCT Accelerator 3.13.2 Motion Estimation Accelerator 3.13.3 Pixel Interpolation Accelerator Power Supply Connection Examples 3.14.1 Core Voltage Supply Connections 3.14.2 Core Voltage Noise Isolation Register Descriptions 3.15.1 Private Peripheral Registers 3.15.2 Public Peripheral Registers 3.15.3 Configuration Registers Register Descriptions 3.16.1 Private Peripheral Registers 3.16.2 Public Peripheral Registers 3.16.3 Configuration Registers 3.16.4 MPU/DSP Shared Peripheral Register Descriptions Interrupts System Request Mapping Event Mapping
Page
3.10 3.11 3.12
3.13
3.14
3.15
3.16
3.17 3.18 3.19
Documentation Support Device Development Tool Support Nomenclature Electrical Specifications Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics Over Recommended Operating Case Temperature Range (Unless Otherwise Noted) Package Thermal Resistance Characteristics Timing Parameter Symbology Clock Specifications 5.6.1 32-kHz Oscillator Input Clock 5.6.2 Base Oscillator MHz) Input Clock 5.6.3 Internal Clock Speed Limitations Reset Timings 5.7.1 OMAP5910 Device Reset 5.7.2 OMAP5910 Core Reset
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Contents
Section External Memory Interface Timing 5.8.1 EMIFS/Flash Interface Timing 5.8.2 EMIFF/SDRAM Interface Timing Multichannel Buffered Serial Port (McBSP) Timings 5.9.1 McBSP Transmit Receive Timings 5.9.2 McBSP Master Slave Timing Multichannel Serial Interface (MCSI) Camera Interface Timings Controller Timings Multimedia Card/Secure Digital (MMC/SD) Timings Timings Universal Serial (USB) Timings MICROWIRE Interface Timings HDQ/1-Wire Interface Timings
Page
5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17
Glossary Mechanical Data
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Contents
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Figures
List Figures
Figure 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 OMAP5910 MicroStar Package (Bottom View) OMAP5910 Package (Bottom View) OMAP5910 Functional Block Diagram Supply Connections Typical System Supply Connections System With 1.8-V SDRAM External Circuit DPLL CVDD Noise Isolation Tester Electronics 32-kHz Oscillator External Crystal 32-kHz Input Clock Internal System Oscillator External Crystal Device Reset Timings Core Reset Timings Asynchronous Memory Read Timing Asynchronous 32-Bit Read Asynchronous Read Page Mode Asynchronous Memory Write Timing Synchronous Burst Read 32-Bit 16-Bit) SDRAM (Read) Command (Active Row) 32-Bit 16-Bit) SDRAM (Write) Command (Active Row) SDRAM ACTV (Activate Row) Command SDRAM DCAB (Precharge/Deactivate Row) Command SDRAM REFR (Refresh) Command SDRAM (Mode Register Set) Command McBSP Receive Timings McBSP Transmit Timings McBSP Timing Master Slave: CLKSTP 10b, CLKXP McBSP Timing Master Slave: CLKSTP 11b, CLKXP McBSP Timing Master Slave: CLKSTP 10b, CLKXP McBSP Timing Master Slave: CLKSTP 11b, CLKXP MCSI Master Mode Timings MCSI Slave Mode Timings Camera Interface Timings Mode (LCD.HS/LCD.VS Falling LCD.Px Rising LCD.PCLK) Mode (LCD.HS/LCD.VS Rising LCD.Px Falling LCD.PCLK) MMC/SD Host Command Timings Page
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SPRS197D
Figures
5-30 5-31 5-32 5-33 5-34 5-35 5-36 5-37 5-38 5-39
MMC/SD Card Response Timings MMC/SD Host Write Timings MMC/SD Host Read Card Status Timings Timings Integrated Transceiver Interface Timings MICROWIRE Timings OMAP5910 Interface Reading From Slave Device OMAP5910 Interface Writing Slave Device Typical Communication Between OMAP5910 Slave HDQ/1-Wire Break (Reset) Timing
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Tables
List Tables
Table 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 3-33 3-34 3-35 3-36 3-37 3-38 3-39 3-40 3-41 Terminal Assignments Terminal Assignments Terminal Characteristics Multiplexing Signal Description OMAP5910 Global Memory Private Peripheral Registers Public Peripheral Registers MPU/DSP Shared Peripheral Registers Public Peripheral Registers (Accessible MPUI Port) Configuration Registers Global Memory DARAM Blocks SARAM Blocks Private Peripheral Registers Public Peripheral Registers DSP/MPU Shared Peripheral Registers Configuration Registers Timer Registers Timer Registers Timer Registers Watchdog Timer Registers Level Interrupt Handler Registers Level Interrupt Handler Registers System Controller Registers Controller Registers McBSP2 Registers MICROWIRE Registers Registers HDQ/1-Wire Interface Registers MMC/SD Registers Function Registers Host Controller Registers Camera Interface Registers I/O/Keyboard Registers Registers Registers Pulse Generator Registers Pulse Generator Registers Timer Registers Real-Time Clock Registers Frame Adjustment Counter Registers OMAP 5910 Configuration Registers Local Control Registers Local Registers Registers Page
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SPRS197D
Tables
Table 3-42 3-43 3-44 3-45 3-46 3-47 3-48 3-49 3-50 3-51 3-52 3-53 3-54 3-55 3-56 3-57 3-58 3-59 3-60 3-61 3-62 3-63 3-64 3-65 3-66 3-67 3-68 3-69 3-70 3-71 3-72 3-73 3-74 3-75 3-76 3-77 MPUI Registers TIPB (Private) Bridge Configuration Registers TIPB (Public) Bridge Configuration Registers UART TIPB Switch Registers Traffic Controller Registers Clock/Reset/Power Mode Control Registers DPLL1 Register Ultra Low-Power Device Module Registers Device Identification Registers JTAG Identification Code Register Controller Registers Timer Registers Timer Registers Timer Registers Watchdog Timer Registers Interrupt Interface Registers Level Interrupt Handler Registers McBSP1 Registers McBSP3 Registers MCSI1 Registers MCSI2 Registers Instruction Cache Registers EMIF Configuration Register TIPB Bridge Configuration Registers UART TIPB Switch Registers Clock Mode Registers UART1 Registers UART2 Registers UART3/IrDA Registers MPU/DSP Shared GPIO Registers MPU/DSP Shared Mailbox Registers Level Level Interrupt Mappings Level Interrupt Mappings Level Interrupt Mappings Request Mapping Mapping Thermal Resistance Characteristics 32-kHz Oscillator Switching Characteristics 32-kHz Input Clock Timing Requirements Base Oscillator Switching Characteristics Internal Clock Speed Limitations OMAP5910 Device Reset Timing Requirements OMAP5910 Device Reset Switching Characteristics MPU_RST Timing Requirements MPU_RST Switching Characteristics
Page
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Tables
Table 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34 5-35 EMIFS/Flash Interface Timing Requirements EMIFS/Flash Interface Switching Characteristics EMIFF/SDRAM Interface Timing Requirements EMIFF/SDRAM Interface Switching Characteristics McBSP Timing Requirements McBSP Switching Characteristics McBSP Master Slave Timing Requirements (CLKSTP 10b, CLKXP McBSP Master Slave Switching Characteristics (CLKSTP 10b, CLKXP McBSP Master Slave Timing Requirements (CLKSTP 11b, CLKXP McBSP Master Slave Switching Characteristics (CLKSTP 11b, CLKXP McBSP Master Slave Timing Requirements (CLKSTP 10b, CLKXP McBSP Master Slave Switching Characteristics (CLKSTP 10b, CLKXP McBSP Master Slave Timing Requirements (CLKSTP 11b, CLKXP McBSP Master Slave Switching Characteristics (CLKSTP 11b, CLKXP MCSI Timing Requirements MCSI Switching Characteristics Camera Interface Timing Requirements Controller Switching Characteristics MMC/SD Timing Requirements MMC/SD Switching Characteristics Signals (I2C.SDA I2C.SCL) Switching Characteristics Integrated Transceiver Interface Switching Characteristics MICROWIRE Timing Requirements MICROWIRE Switching Characteristics HDQ/1-Wire Timing Requirements HDQ/1-Wire Switching Characteristics
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Tables
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Features
OMAP5910 Features
Low-Power, High-Performance CMOS
Technology 0.13-µm Technology 1.6-V Core Voltage TI925T (MPU) ARM9TDMI Core Support 32-Bit 16-Bit (Thumb Mode) Instruction Sets 16K-Byte Instruction Cache 8K-Byte Data Cache Data Program Memory Management Units (MMUs) 64-Entry Translation Look-Aside Buffers (TLBs) MMUs 17-Word Write Buffer TMS320C55x (C55x) Core One/Two Instructions Executed Cycle Dual Multipliers (Two MultiplyAccumulates Cycle) Arithmetic/Logic Units Internal Program Five Internal Data/Operand Buses Read Buses Write Buses) 16-Bit On-Chip Dual-Access (DARAM) (64K Bytes) 16-Bit On-Chip Single-Access (SARAM) (96K Bytes) 16-Bit On-Chip (32K Bytes) Instruction Cache (24K Bytes) Video Hardware Accelerators DCT, iDCT, Pixel Interpolation, Motion Estimation Video Compression 192K Bytes Shared Internal SRAM Memory Traffic Controller (TC) 16-Bit EMIFS External Memory Interface Access 128M Bytes Flash, ROM, ASRAM 16-Bit EMIFF External Memory Interface Access Bytes SDRAM 9-Channel System Controller Memory Management Unit Endianism Conversion Logic Digital Phase-Locked Loop (DPLL) MPU/DSP/TC Clocking Control
Peripherals
TMS320C55x C55x trademarks Texas Instruments. ARM9TDMI trademark Limited. Thumb registered trademark Limited. MICROWIRE trademark National Semiconductor Corporation. 1-Wire registered trademark Dallas Semiconductor Corporation. IEEE Standard 1149.1-1990 Standard Test-Access Port Boundary Scan Architecture. August 2002 Revised August 2004
Three 32-Bit Timers Watchdog Timer Level1/Level2 Interrupt Handlers Six-Channel Controller Multichannel Buffered Serial Ports (McBSP) Multichannel Serial Interfaces (MCSI) TI925T Peripherals Three 32-Bit Timers Watchdog Timer 32-kHz Timer Level1/Level2 Interrupt Handlers (Full/Low Speed) Host Interface With Ports (Full Speed) Function Interface Integrated Transceiver Either Host Function Multichannel Buffered Serial Port Inter-Integrated Circuit (I2C) Master Slave Interface MICROWIRE Serial Interface Multimedia Card (MMC) Secure Digital (SD) Interface HDQ/1-Wire Interface Camera Interface CMOS Sensors ETM9 Trace Module TI925T Debug Keyboard Matrix Interface General-Purpose I/Os Pulse-Width Tone (PWT) Interface Pulse-Width Light (PWL) Interface Pulse Generators (LPGs) Real-Time Clock (RTC) Controller With Dedicated System Channel Shared Peripherals Three Universal Asynchronous Receiver/Transmitters (UARTs) (One Supporting Mode IrDA) Four Interprocessor Mailboxes Shared General-Purpose I/Os Individual Power-Saving Modes MPU/DSP/TC On-Chip Scan-Based Emulation Logic IEEE 1149.1 (JTAG) Boundary Scan Logic 289-Ball Ball Grid Array Package Options (GZG Suffixes)
SPRS197D
Introduction
Introduction
This section describes main features OMAP5910 device, lists terminal assignments, describes function each terminal. This data manual also provides detailed description section, electrical specifications, parameter measurement information, mechanical data about available packaging.
Description
OMAP5910 highly integrated hardware software platform, designed meet application processing needs next-generation embedded devices. OMAP platform enables OEMs ODMs quickly bring market devices featuring rich user interfaces, high processing performance, long battery life through maximum flexibility fully integrated mixed processor solution. dual-core architecture provides benefits both RISC technologies, incorporating TMS320C55x core high-performance TI925T core. OMAP5910 device designed leading open embedded RISC-based operating systems, well Texas Instruments (TI) DSP/BIOS software kernel foundation, available 289-ball MicroStar package. OMAP5910 targeted following applications: Applications processing devices Mobile communications 802.11 Bluetooth wireless technology (including GPRS EDGE) CDMA Proprietary government other
Video image processing (MPEG4, JPEG, Windows Media Video, etc.) Advanced speech applications (text-to-speech, speech recognition) Audio processing (MPEG-1 Audio Layer3 [MP3], AMR, WMA, AAC, other speech codecs) Graphics video acceleration Generalized access Data processing (fax, encryption/decryption, authentication, signature verification watermarking)
2.1.1 TMS320C55x Core
core OMAP5910 device based TMS320C55x generation processor core. C55x architecture achieves high performance power through increased parallelism total focus reduction power dissipation. supports internal structure composed program bus, three data read buses, data write buses, additional buses dedicated peripheral activity. These buses provide ability perform three data reads data writes single cycle. parallel, controller perform data transfers cycle independent activity.
OMAP, DSP/BIOS, MicroStar trademarks Texas Instruments. Bluetooth trademark owned Bluetooth SIG, Inc. Windows registered trademark Microsoft Corporation. Other trademarks property their respective owners. SPRS197D August 2002 Revised August 2004
Introduction
C55x provides multiply-accumulate (MAC) units, each capable 17-bit 17-bit multiplication single cycle. central 40-bit arithmetic/logic unit (ALU) supported additional 16-bit ALU. ALUs under instruction control, providing ability optimize parallel activity power consumption. These resources managed address unit (AU) data unit (DU) C55x CPU. C55x generation supports variable byte width instruction improved code density. instruction unit (IU) performs 32-bit program fetches from internal external memory queues instructions program unit (PU). program unit decodes instructions, directs tasks resources, manages fully protected pipeline. Predictive branching capability avoids pipeline flushes execution conditional instructions. OMAP5910 core also includes 24K-byte instruction cache minimize external memory accesses, improving data throughput conserving system power.
2.1.1.1
Tools Support
core supported industry's leading eXpressDSP software environment including Code Composer Studio integrated development environment, DSP/BIOS software kernel foundation, TMS320 Algorithm Standard, industry's largest third-party network. Code Composer Studio features code generation tools including C-Compiler, Visual Linker, simulator, Real-Time Data Exchange (RTDX), XDS510 emulation device drivers, Chip Support Libraries (CSL). DSP/BIOS scalable real-time software foundation available cost users Texas Instruments' products providing preemptive task scheduler real-time analysis capabilities with very memory megahertz overhead. TMS320 Algorithm Standard specification coding conventions allowing fast integration algorithms from different teams, sites, third parties into application framework. Texas Instruments' extensive third-party network over providers brings focused competencies complete solutions customers.
2.1.1.2
Software Support
Texas Instruments also developed foundation software available core. C55x Library (DSPLIB) features over C-callable software kernels (FIR/IIR filters, Fast Fourier Transforms (FFTs), various computational functions). Image/Video Processing Library (IMGLIB) contains over software kernels highly optimized C55x DSPs compiled with latest revision C55x code generation tools. These imaging functions support wide range applications that include compression, video processing, machine vision, medical imaging.
2.1.2 TI-Enhanced TI925T RISC Processor
core TI925T reduced instruction computer (RISC) processor. TI925T 32-bit processor core that performs 32-bit 16-bit instructions processes 32-bit, 16-bit, 8-bit data. core uses pipelining that parts processor memory system operate continuously. core incorporates: coprocessor (CP15) protection module Data program Memory Management Units (MMUs) with table look-aside buffers. separate 16K-byte instruction cache 8K-byte data cache. Both two-way associative with virtual index virtual (VIVT). 17-word write buffer (WB)
OMAP5910 device uses TI925T core little endian mode only. reduce effective memory access time, TI925T instruction cache, data cache, write buffer. general, these transparent program execution.
eXpressDSP, Code Composer Studio, TMS320, RTDX, XDS510 trademarks Texas Instruments. August 2002 Revised August 2004 SPRS197D
Introduction
Terminal Assignments
Figure illustrates ball locations 289-ball ball grid array (BGA) package used conjunction with Table locate signal names ball grid numbers. ball numbers Table read from left-to-right, top-to-bottom.
Figure 2-1. OMAP5910 MicroStar Package (Bottom View) Table 2-1, signals with multiplexed functions separated with forward slashes follows: signal1/signal2/signal3 (for example, GPIO11/HDQ)
Signals which associated with specific peripherals denoted using peripheral name, followed period, then signal name; follows:
BALL
peripheral1.signal1 (for example, MCBSP1.DR) Table 2-1. Terminal Assignments
SIGNAL DVDD4 DVDD4 DVDD1 SDRAM.D[13] SDRAM.D[4] CVDD3 LCD.P[11] LCD.P[1] SDRAM.D[14] SDRAM.D[2] SDRAM.A[7] BALL SIGNAL SDRAM.RAS CVDD LCD.P[13] SDRAM.D[0] SDRAM.A[0] FLASH.A[3] SDRAM.D[11] SDRAM.CLK SDRAM.A[4] BALL SIGNAL CVDD1 DVDD1 SDRAM.D[8] DVDD4 LCD.AC LCD.P[6] DVDD5 SDRAM.D[9] SDRAM.BA[0] SDRAM.A[1] BALL SIGNAL DVDD4 LCD.P[5] SDRAM.DQML DVDD4 CVDD3 SDRAM.WE SDRAM.D[6] SDRAM.A[10] LCD.PCLK
Section 5.6.1 Section 5.6.2 special considerations with ocillator circuits.
MicroStar trademark Texas Instruments. SPRS197D August 2002 Revised August 2004
Introduction
Table 2-1. Terminal Assignments (Continued)
BALL SIGNAL LCD.P[14] KB.C[5] SDRAM.DQMU SDRAM.D[5] SDRAM.A[6] LCD.P[9] KB.C[1] FLASH.A[4] KB.R[3] FLASH.A[6] SDRAM.D[3] SDRAM.A[2] PWRON_RESET FLASH.A[15] SDRAM.CAS LCD.P[4] CAM.EXCLK/ ETM.SYNC/ UWIRE.SDO FLASH.A[19] CAM.D[5]/ ETM.D[5]/ UWIRE.SDI FLASH.A[22] CAM.D[2]/ ETM.D[2]/ UART3.CTS DVDD5 FLASH.A[21] CAM.D[0]/ ETM.D[0]/ MPUIO12 FLASH.CS2/ FLASH.BAA GPIO7/ MMC.DAT2 FLASH.D[2] GPIO12/ MCBSP3.FSX FLASH.D[3] BALL SIGNAL LCD.P[10] KB.C[4] SDRAM.D[15] SDRAM.CKE SDRAM.A[3] LCD.P[8] DVDD5 RSVD DVDD1 KB.C[0] FLASH.A[12] SDRAM.D[1] LCD.P[12] MCBSP1.CLKS FLASH.A[14] SDRAM.A[11] KB.R[2] MCBSP1.DR FLASH.A[18] CAM.LCLK/ ETM.CLK/ UWIRE.SCLK CVDD3 FLASH.A[16] CAM.D[4]/ ETM.D[4]/ UART3.TX FLASH.BE[0] UART3.RX/PWL/ UART2.RX DVDD1 FLASH.CS0 UART3.TX/ PWT/ UART2.TX FLASH.D[1] FLASH.CS3 GPIO13/ KB.R[5] DVDD5 BALL SIGNAL LCD.P[7] FLASH.A[5] SDRAM.D[12] SDRAM.BA[1] LCD.VS LCD.P[0] KB.C[3] CVDD KB.R[1] FLASH.A[11] SDRAM.A[12] LCD.P[3] MCBSP1.CLKX FLASH.RDY SDRAM.A[5] MCBSP1.FSX/ MCBSP1.DX FLASH.A[20] FLASH.A[8] CAM.D[7]/ ETM.D[7]/ UWIRE.CS0 FLASH.A[13] CAM.D[3]/ ETM.D[3]/ UART3.RX FLASH.ADV CAM.HS/ ETM.PSTAT[1]/ UART2.CTS CVDD4 FLASH.BE[1] CAM.RSTZ/ ETM.PSTAT[0]/ UART2.RTS FLASH.CLK UWIRE.CS0/ MCBSP3.CLKX GPIO11/ FLASH.D[4] BALL SIGNAL LCD.P[2] FLASH.A[2] SDRAM.D[7] SDRAM.A[9] LCD.P[15] KB.C[2] FLASH.A[7] KB.R[4] FLASH.A[9] FLASH.A[10] SDRAM.A[8] KB.R[0] DVDD5 SDRAM.D[10] LCD.HS MCBSP1.DX/ MCBSP1.FSX FLASH.A[17] FLASH.A[1] CAM.D[6]/ ETM.D[6]/ UWIRE.CS3 FLASH.A[23] CAM.D[1]/ETM.D[1]/ UART3.RTS FLASH.A[24] CAM.VS/ ETM.PSTAT[2] FLASH.CS1 GPIO2/ SPI.CLK GPIO15/ KB.R[7] FLASH.D[0] MPUIO2/ EXT_DMA_REQ0 GPIO14/ KB.R[6] FLASH.D[5]
Section 5.6.1 Section 5.6.2 special considerations with ocillator circuits.
August 2002 Revised August 2004
SPRS197D
Introduction
Table 2-1. Terminal Assignments (Continued)
BALL SIGNAL FLASH.D[11] CVDD GPIO3/ SPI.CS3/ MCBSP3.FSX/LED1 FLASH.D[6] UART2.RX/ USB2.VM BCLKREQ/ UART3.CTS/ UART1.DSR CVDD3 FLASH.D[14] FLASH.D[12] UWIRE.SDI/ UART3.DSR/ UART1.DSR/ MCBSP3.DR DVDD5 UART2.TX/ USB2.TXD MMC.DAT1/ MPUIO7 UART1.RX CONF FLASH.WE MCBSP2.FSR/ GPIO12 MMC.DAT2/ MPUIO11 MCSI1.DOUT/ USB1.TXD CVDD2 UART2.CTS/ USB2.RCV/ GPIO7 MCLK UART1.TX BALL SIGNAL USB.DP CLK32K_IN GPIO6/ SPI.CS1/ MCBSP3.FSX FLASH.D[7] MCLKREQ/EXT_ MASTER_REQ UART1.CTS I2C.SCL MPUIO1 FLASH.D[15] MCBSP2.CLKR/ GPIO11 MMC.CLK MPU_RST UWIRE.SCLK/ KB.C[7] OSC1_OUT MCBSP2.FSX MMC.DAT3/ MPUIO6 RST_OUT BFAIL/ EXT_FIQ OSC1_IN MCBSP2.CLKX MCSI2.CLK/ USB2.SUSP BALL SIGNAL MCBSP2.DR/ MCBSP2.DX RST_HOST_OUT/ MCBSP3.DX/ USB1.SE0 GPIO4/ SPI.CS2/ MCBSP3.FSX FLASH.D[8] MMC.DAT0/SPI.DI GPIO0/ SPI.RDY/ USB.VBUS FLASH.D[9] MPUIO4/ EXT_DMA_REQ1/ LED2 FLASH.D[13] FLASH.WP MPUIO3 EMU0 I2C.SDA USB.PUEN/ USB.CLKO GPIO9 OSC32K_IN MCBSP3.CLKX/ USB1.TXEN DVDD3 CLK32K_OUT/ MPUIO0/ USB1.SPEED DVDD1 BALL SIGNAL MMC.CMD/SPI.DO UWIRE.CS3/ KB.C[6] DVDD5 USB.DM OSC32K_OUT GPIO1/ UART3.RTS FLASH.D[10] MPUIO5/ LOW_PWR FLASH.OE DVDD1 MCSI2.SYNC/ GPIO7 MCSI1.SYNC/ USB1.VP FLASH.RP UART2.RTS/ USB2.SE0/ MPUIO5 MCSI2.DOUT/ USB2.TXEN MCSI1.DIN/ USB1.RCV EMU1 UWIRE.SDO/ UART3.DTR/ UART1.DTR/ MCBSP3.DX UART2.BCLK GPIO8 BCLK/ UART3.RTS/ UART1.DTR STAT_VAL/ WKUP
Section 5.6.1 Section 5.6.2 special considerations with ocillator circuits.
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Introduction
Table 2-1. Terminal Assignments (Continued)
BALL AA15 AA21
SIGNAL TRST UART1.RTS
BALL AA17
SIGNAL DVDD2 MCSI2.DIN/ USB2.VP MPU_BOOT/ MCBSP3.DR/ USB1.SUSP
BALL AA11 AA19
SIGNAL CVDD CVDD2 DVDD1
BALL AA13 AA20
SIGNAL CVDDA MCBSP2.DX/ MCBSP2.DR MCSI1.CLK/ USB1.VM CLK32K_CTRL
Section 5.6.1 Section 5.6.2 special considerations with ocillator circuits.
Figure illustrates ball locations 289-ball ball grid array (BGA) package used conjunction with Table locate signal names ball grid numbers. ball numbers Figure read from left-to-right, top-to-bottom.
Bottom View
Figure 2-2. OMAP5910 Package (Bottom View) Table 2-2, signals with multiplexed functions separated with forward slashes follows: signal1/signal2/signal3 (for example, GPIO11/HDQ)
Signals which associated with specific peripherals denoted using peripheral name, followed period, then signal name; follows: peripheral1.signal1 (for example, MCBSP1.DR)
August 2002 Revised August 2004
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Introduction
Table 2-2. Terminal Assignments
BALL SIGNAL SDRAM.WE DVDD4 SDRAM.A[5] LCD.P[9] KB.C[5] SDRAM.D[12] SDRAM.BA[0] LCD.P[13] LCD.P[0] FLASH.RDY SDRAM.D[3] SDRAM.A[3] LCD.P[5] FLASH.A[7] SDRAM.D[7] SDRAM.A[4] KB.R[1] FLASH.A[12] SDRAM.A[10] KB.R[3] FLASH.A[10] SDRAM.CAS MCBSP1.FSX/ MCBSP1.DX FLASH.A[14] BALL SIGNAL SDRAM.DQMU SDRAM.D[0] SDRAM.A[1] DVDD1 FLASH.A[1] SDRAM.D[11] SDRAM.A[11] LCD.P[11] KB.C[3] SDRAM.RAS SDRAM.A[12] DVDD1 LCD.P[1] DVDD4 SDRAM.CKE LCD.VS LCD.P[2] CVDD SDRAM.D[8] DVDD4 DVDD1 DVDD5 FLASH.A[8] SDRAM.A[7] MCBSP1.CLKS MCBSP1.DX/ MCBSP1.FSX FLASH.A[13] SDRAM.D[13] CAM.D[6]/ ETM.D[6]/ UWIRE.CS3 MCBSP1.DR FLASH.A[18] DVDD5 CVDD3 CAM.LCLK/ ETM.CLK/ UWIRE.SCLK FLASH.CS0 BALL SIGNAL SDRAM.D[9] SDRAM.CLK LCD.AC LCD.P[6] SDRAM.DQML SDRAM.D[5] SDRAM.A[2] LCD.P[7] FLASH.A[3] SDRAM.D[14] SDRAM.BA[1] LCD.P[14] KB.C[0] SDRAM.D[15] DVDD4 LCD.P[15] KB.C[4] FLASH.A[5] SDRAM.D[1] LCD.HS KB.C[2] FLASH.A[11] CVDD3 PWRON_RESET FLASH.A[16] FLASH.A[15] CAM.EXCLK/ ETM.SYNC/ UWIRE.SDO CAM.D[3]/ ETM.D[3]/ UART3.RX FLASH.A[19] UART3.RX/PWL/ UART2.RX CAM.D[5]/ ETM.D[5]/ UWIRE.SDI FLASH.A[24] BALL SIGNAL SDRAM.D[6] SDRAM.A[9] LCD.PCLK LCD.P[3] CVDD1 SDRAM.D[2] SDRAM.A[0] LCD.P[4] FLASH.A[4] SDRAM.D[10] SDRAM.A[8] LCD.P[8] DVDD5 DVDD4 SDRAM.A[6] KB.R[0] KB.R[4] FLASH.A[6] CVDD LCD.P[10] KB.C[1] FLASH.A[9] SDRAM.D[4] LCD.P[12] KB.R[2] FLASH.A[17] FLASH.A[2] CVDD3 CAM.D[7]/ ETM.D[7]/ UWIRE.CS0 FLASH.ADV FLASH.A[21] DVDD1 CAM.D[2]/ ETM.D[2]/ UART3.CTS FLASH.A[23]
MCBSP1.CLKX FLASH.A[20] FLASH.A[22] CAM.D[1]/ETM.D[1]/ UART3.RTS FLASH.BE[1] FLASH.BE[0]
Section 5.6.1 Section 5.6.2 special considerations with ocillator circuits.
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August 2002 Revised August 2004
Introduction
Table 2-2. Terminal Assignments (Continued)
BALL SIGNAL UART3.TX/ PWT/ UART2.TX CAM.VS/ ETM.PSTAT[2] FLASH.CLK GPIO3/ SPI.CS3/ MCBSP3.FSX/LED1 GPIO15/ KB.R[7] DVDD5 BALL SIGNAL CAM.RSTZ/ ETM.PSTAT[0]/ UART2.RTS FLASH.CS1 FLASH.CS2/ FLASH.BAA GPIO6/ SPI.CS1/ MCBSP3.FSX GPIO14/ KB.R[6] FLASH.D[2] CVDD2 UWIRE.CS3/ KB.C[6] GPIO11/ FLASH.D[11] UART2.RX/ USB2.VM RST_OUT GPIO2/ SPI.CLK FLASH.D[13] UART2.CTS/ USB2.RCV/ GPIO7 CLK32K_OUT/ MPUIO0/ USB1.SPEED I2C.SDA FLASH.D[10] USB.DP DVDD1 UART1.TX BALL SIGNAL CAM.D[4]/ ETM.D[4]/ UART3.TX CVDD4 DVDD5 GPIO13/ KB.R[5] FLASH.CS3 FLASH.D[0] MPUIO5/ LOW_PWR GPIO7/ MMC.DAT2 FLASH.D[6] GPIO9 GPIO0/ SPI.RDY/ USB.VBUS FLASH.OE DVDD3 BALL SIGNAL CAM.D[0]/ ETM.D[0]/ MPUIO12 FLASH.D[1] CVDD2 CVDD3 CAM.HS/ ETM.PSTAT[1]/ UART2.CTS DVDD5 FLASH.D[3] BCLKREQ/ UART3.CTS/ UART1.DSR GPIO4/ SPI.CS2/ MCBSP3.FSX FLASH.D[4] FLASH.D[7] MMC.DAT1/ MPUIO7 UWIRE.SCLK/ KB.C[7] GPIO1/ UART3.RTS FLASH.D[8] MCLKREQ/ EXT_MASTER_REQ MCSI1.DOUT/ USB1.TXD DVDD1 OSC1_OUT MPUIO3 BCLK/ UART3.RTS/ UART1.DTR I2C.SCL
GPIO12/ MCBSP3.FSX FLASH.D[5] UART1.CTS MPUIO1 FLASH.D[9]
CLK32K_IN
RSVD MPUIO4/ EXT_DMA_REQ1/ LED2 FLASH.WE MCBSP2.FSR/ GPIO12 CVDD MCBSP3.CLKX/ USB1.TXEN
MPUIO2/ EXT_DMA_REQ0 USB.DM MCSI2.DIN/ USB2.VP MPU_RST
Section 5.6.1 Section 5.6.2 special considerations with ocillator circuits.
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SPRS197D
Introduction
Table 2-2. Terminal Assignments (Continued)
BALL SIGNAL UWIRE.SDO/ UART3.DTR/ UART1.DTR/ MCBSP3.DX FLASH.WP MCSI2.SYNC/ GPIO7 UART1.RX CVDDA FLASH.RP MCBSP2.FSX OSC32K_IN DVDD5 MCBSP2.CLKX MMC.DAT0/SPI.DI RST_HOST_OUT/ MCBSP3.DX/ USB1.SE0 BALL SIGNAL UWIRE.SDI/ UART3.DSR/ UART1.DSR/ MCBSP3.DR UART2.TX/ USB2.TXD MMC.DAT2/ MPUIO11 MPU_BOOT/ MCBSP3.DR/ USB1.SUSP UWIRE.CS0/ MCBSP3.CLKX USB.PUEN/ USB.CLKO MCSI2.DOUT/ USB2.TXEN MCSI1.SYNC/ USB1.VP CLK32K_CTRL FLASH.D[15] GPIO8 MMC.CLK STAT_VAL/ WKUP BALL SIGNAL BALL SIGNAL
FLASH.D[12] MCBSP2.DX/ MCBSP2.DR MMC.DAT3/ MPUIO6 EMU0 UART2.BCLK MCSI2.CLK/ USB2.SUSP DVDD1 CONF DVDD2 MCLK MCSI1.CLK/ USB1.VM TRST
OSC1_IN MCBSP2.DR/ MCBSP2.DX MCSI1.DIN/ USB1.RCV BFAIL/ EXT_FIQ FLASH.D[14] MCBSP2.CLKR/ GPIO11 OSC32K_OUT EMU1 CVDD UART2.RTS/ USB2.SE0/ MPUIO5 MMC.CMD/SPI.DO UART1.RTS
Section 5.6.1 Section 5.6.2 special considerations with ocillator circuits.
Terminal Characteristics Multiplexing
Table describes terminal characteristics signals multiplexed each ball. table column headers explained below: SIGNAL NAME: names signals that multiplexed each ball. TYPE: terminal type when particular signal multiplexed terminal. CTRL SETTING: register field that controls multiplexing terminal proper register field setting necessary select signal multiplexed terminal. reset values these register fields indicated bold type. DESELECTED INPUT STATE: logic level internally driven signal when selected multiplexed corresponding terminal. PULLUP/PULLDN: Denotes presence internal pullup pulldown. Pullups pulldowns enabled disabled software. BUFFER STRENGTH: Drive strength associated output buffer.
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Introduction
OTHER: Contains various terminal information, such buffer type, boundary scan capability, gating/inhibit functionality. Certain terminals gated 3-stated based state other terminals and/or software configuration register settings. RESET STATE: state terminal reset. SUPPLY: voltage supply which powers terminal's buffers. NOTE: extensive multiplexing options which available OMAP5910 device, software utility available ease process configuring pins based peripheral required specific application. 5910 OMAP Configuration Utility currently available from Texas Instruments. NOTE: Configuring pins same input signal supported yield unexpected results. This easily avoided with proper software configuration. Table 2-3. Terminal Characteristics Multiplexing
BALL
BALL
SIGNAL NAME SDRAM.WE SDRAM.RAS SDRAM.DQMU SDRAM.DQML SDRAM.D[15:0]
TYPE I/O/Z
CTRL SETTING
DESELECTED INPUT STATE
BUFFER STRENGTH
RESET STATE#
SUPPLY DVDD4 DVDD4 DVDD4 DVDD4 DVDD4
SDRAM.CKE SDRAM.CLK SDRAM.CAS SDRAM.BA[1:0]
I/O/Z
DVDD4 DVDD4 DVDD4 DVDD4
Input, Output, High-Impedance 'regx' denotes terminal multiplexing register that controls specified terminal where regx FUNC_MUX_CTRL_x PD20 20-µA internal pulldown, PD100 100-µA pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup Standard LVCMOS input/output Terminal gated BFAIL Fail-safe LVCMOS input/output Terminal gated GPIO9 MPUIO3 transceiver input/output Terminal gated BFAIL PWRON_RESET input/output buffers Terminal 3-stated BFAIL input Fail-safe LVCMOS input Standard LVCMOS output Boundary-scannable terminal analog oscillator terminals High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven
UART1 signals multiplexed this additional multiplexing module.
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Introduction
Table 2-3. Terminal Characteristics Multiplexing (Continued)
BALL
BALL
SIGNAL NAME SDRAM.A[12:0]
TYPE
CTRL SETTING
DESELECTED INPUT STATE
BUFFER STRENGTH
RESET STATE#
SUPPLY DVDD4
LCD.VS LCD.HS LCD.AC LCD.PCLK LCD.P[15:0]
DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
KB.C[5:0]
DVDD1
KB.R[4:0]
input
DVDD1
PWRON_RESET MCBSP1.CLKS MCBSP1.CLKX MCBSP1.FSX MCBSP1.DX
I/O/Z I/O/Z
reg4[14:12] reg4[14:12]
input input
DVDD1 DVDD1 DVDD1 DVDD1
Input, Output, High-Impedance 'regx' denotes terminal multiplexing register that controls specified terminal where regx FUNC_MUX_CTRL_x PD20 20-µA internal pulldown, PD100 100-µA pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup Standard LVCMOS input/output Terminal gated BFAIL Fail-safe LVCMOS input/output Terminal gated GPIO9 MPUIO3 transceiver input/output Terminal gated BFAIL PWRON_RESET input/output buffers Terminal 3-stated BFAIL input Fail-safe LVCMOS input Standard LVCMOS output Boundary-scannable terminal analog oscillator terminals High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven
UART1 signals multiplexed this additional multiplexing module.
SPRS197D
August 2002 Revised August 2004
Introduction
Table 2-3. Terminal Characteristics Multiplexing (Continued)
BALL BALL SIGNAL NAME MCBSP1.DX MCBSP1.FSX MCBSP1.DR CAM.EXCLK ETM.SYNC UWIRE.SDO CAM.LCLK ETM.CLK UWIRE.SCLK CAM.D[7] ETM.D[7] UWIRE.CS0 CAM.D[6] ETM.D[6] UWIRE.CS3 CAM.D[5] ETM.D[5] UWIRE.SDI CAM.D[4] ETM.D[4] UART3.TX CAM.D[3] ETM.D[3] UART3.RX CAM.D[2] ETM.D[2] UART3.CTS CAM.D[1] ETM.D[1] UART3.RTS CAM.D[0] ETM.D[0] MPUIO12 CAM.VS ETM.PSTAT[2] CAM.HS ETM.PSTAT[1] UART2.CTS
TYPE I/O/Z I/O/Z
CTRL SETTING reg4[17:15] reg4[17:15] reg4[23:21] reg4[23:21] reg4[23:21] reg4[26:24] reg4[26:24] reg4[26:24] reg4[29:27] reg4[29:27] reg4[29:27] reg5[2:0] reg5[2:0] reg5[2:0] reg5[5:3] reg5[5:3] reg5[5:3] reg5[8:6] reg5[8:6] reg5[8:6] reg5[11:9] reg5[11:9] reg5[11:9] reg5[14:12] reg5[14:12] reg5[14:12] reg5[17:15] reg5[17:15] reg5[17:15] reg5[20:18] reg5[20:18] reg5[20:18] reg5[23:21] reg5[23:21] reg5[26:24] reg5[26:24] reg5[26:24]
DESELECTED INPUT STATE
BUFFER STRENGTH
RESET STATE# input
SUPPLY DVDD1 DVDD1 DVDD1
PD20
input
DVDD1
input
DVDD1
input
DVDD1
PD20
input
DVDD1
input
DVDD8
PD20 PD20
input
DVDD1
input
DVDD1
input
DVDD1
input
DVDD1
PD20
input input
DVDD1 DVDD1
Input, Output, High-Impedance 'regx' denotes terminal multiplexing register that controls specified terminal where regx FUNC_MUX_CTRL_x PD20 20-µA internal pulldown, PD100 100-µA pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup Standard LVCMOS input/output Terminal gated BFAIL Fail-safe LVCMOS input/output Terminal gated GPIO9 MPUIO3 transceiver input/output Terminal gated BFAIL PWRON_RESET input/output buffers Terminal 3-stated BFAIL input Fail-safe LVCMOS input Standard LVCMOS output Boundary-scannable terminal analog oscillator terminals High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven
UART1 signals multiplexed this additional multiplexing module.
August 2002 Revised August 2004
SPRS197D
Introduction
Table 2-3. Terminal Characteristics Multiplexing (Continued)
BALL BALL SIGNAL NAME CAM.RSTZ ETM.PSTAT[0] UART2.RTS forced drive UART3.TX IRQ_OBS UART2.TX UART3.RX DMA_REQ_OBS UART2.RX GPIO15 KB.R[7] GPIO14 KB.R[6] GPIO13 KB.R[5] GPIO12 MCBSP3.FSX GPIO11 GPIO7 MMC.DAT2 GPIO6 SPI.CS1 MCBSP3.FSX GPIO4 SPI.CS2 MCBSP3.FSX GPIO3 SPI.CS3 MCBSP3.FSX LED1
TYPE I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
CTRL SETTING reg5[29:27] reg5[29:27] reg5[29:27] reg6[2:0] reg6[2:0] reg6[2:0] reg6[2:0] reg6[2:0] reg6[5:3] reg6[5:3] reg6[5:3] reg6[5:3] reg6[8:6] reg6[8:6] reg6[11:9] reg6[11:9] reg6[14:12] reg6[14:12] reg6[17:15] reg6[17:15] reg6[20:18] reg6[20:18] reg6[23:21] reg6[23:21] reg6[26:24] reg6[26:24] reg6[26:24] reg6[29:27] reg6[29:27] reg6[29:27] reg7[2:0] reg7[2:0] reg7[2:0] reg7[2:0] reg7[5:3] reg7[5:3]
DESELECTED INPUT STATE
BUFFER STRENGTH
RESET STATE#
SUPPLY DVDD1
DVDD1
input
DVDD1
PD20
input
DVDD1
PD20
input
DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
PD20
input
PD20 PD20 PD20 PD20 PD20
input
input
input
PD20 PD20 PD20 PD20 PD20 PD20
input
input
DVDD1
input
DVDD1
GPIO2 SPI.CLK
PD20
input
DVDD1
Input, Output, High-Impedance 'regx' denotes terminal multiplexing register that controls specified terminal where regx FUNC_MUX_CTRL_x PD20 20-µA internal pulldown, PD100 100-µA pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup Standard LVCMOS input/output Terminal gated BFAIL Fail-safe LVCMOS input/output Terminal gated GPIO9 MPUIO3 transceiver input/output Terminal gated BFAIL PWRON_RESET input/output buffers Terminal 3-stated BFAIL input Fail-safe LVCMOS input Standard LVCMOS output Boundary-scannable terminal analog oscillator terminals High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven
UART1 signals multiplexed this additional multiplexing module.
SPRS197D
August 2002 Revised August 2004
Introduction
Table 2-3. Terminal Characteristics Multiplexing (Continued)
BALL BALL SIGNAL NAME GPIO1 UART3.RTS GPIO0 SPI.RDY USB.VBUS MPUIO5 LOW_PWR MPUIO4 EXT_DMA_REQ1 LED2 MPUIO2 EXT_DMA_REQ0 MPUIO1 I2C.SCL I2C.SDA UWIRE.SDI UART3.DSR UART1.DSR MCBSP3.DR UWIRE.SDO UART3.DTR UART1.DTR MCBSP3.DX UWIRE.SCLK KB.C[7] forced high-z UWIRE.CS0 MCBSP3.CLKX forced high-z UWIRE.CS3 KB.C[6] AA20 AA19
TYPE I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
CTRL SETTING reg7[8:6] reg7[8:6] reg7[11:9] reg7[11:9] reg7[11:9] reg7[14:12] reg7[14:12] reg7[17:15] reg7[17:15] reg7[17:15] reg7[20:18] reg7[20:18] reg8[2:0] reg8[2:0] reg8[2:0] reg8[2:0] reg8[5:3] reg8[5:3] reg8[5:3] reg8[5:3] reg8[8:6] reg8[8:6] reg8[11:9] reg8[11:9] reg8[11:9] reg8[14:12] reg8[14:12] reg8[14:12]
DESELECTED INPUT STATE
PD20 PD20 PD20 PD20 PD20
BUFFER STRENGTH
RESET STATE# input input
SUPPLY DVDD1 DVDD1
input input
DVDD1 DVDD1
PD20
input input input
DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
PD20 PD20 PD20 PD20
DVDD1
DVDD1 DVDD1
DVDD1
BFAIL/EXT_FIQ CLK32K_CTRL CONF
PD10 PD20 PD20
input input input input input
DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
Input, Output, High-Impedance 'regx' denotes terminal multiplexing register that controls specified terminal where regx FUNC_MUX_CTRL_x PD20 20-µA internal pulldown, PD100 100-µA pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup Standard LVCMOS input/output Terminal gated BFAIL Fail-safe LVCMOS input/output Terminal gated GPIO9 MPUIO3 transceiver input/output Terminal gated BFAIL PWRON_RESET input/output buffers Terminal 3-stated BFAIL input Fail-safe LVCMOS input Standard LVCMOS output Boundary-scannable terminal analog oscillator terminals High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven
UART1 signals multiplexed this additional multiplexing module.
August 2002 Revised August 2004
SPRS197D
Introduction
Table 2-3. Terminal Characteristics Multiplexing (Continued)
BALL AA17 BALL SIGNAL NAME TRST EMU0 EMU1 STAT_VAL/WKUP MPU_BOOT MCBSP3_DR USB1_SUSP RST_HOST_OUT MCBSP3.DX USB1.SE0 forced high-z MCBSP3.CLKX USB1.TXEN AA15 MPU_RST RST_OUT forced drive UART1.RTS UART1.CTS UART1.RX forced drive UART1.TX MCSI1.DOUT USB1.TXD UART1.TX BCLKREQ UART3.CTS UART1.DSR BCLK UART3.RTS UART1.DTR
TYPE I/O/Z I/O/Z I/O/Z I/O/Z
CTRL SETTING reg8[29:27] reg8[29:27] reg8[29:27] reg9[2:0] reg9[2:0] reg9[2:0] reg9[5:3] reg9[5:3] reg9[5:3] reg9[14:12] reg9[14:12] reg9[23:21] reg9[23:21] reg9[26:24] reg9[26:24] reg9[26:24] 001|| reg9[29:27] reg9[29:27] reg9[29:27] regA[2:0] regA[2:0] regA[2:0] regA[5:3] regA[5:3]
DESELECTED INPUT STATE
PD20 PD10 PU10 PU10 PD20 PD20
BUFFER STRENGTH
RESET STATE# input input input input
SUPPLY DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
DVDD1
PD20 PD20
DVDD1
PD20 PD20
input input input
DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
PD20 PD20 PD20
input
DVDD1
DVDD1
MCSI1.SYNC USB1.VP
PD20 PD20
input
DVDD1
Input, Output, High-Impedance 'regx' denotes terminal multiplexing register that controls specified terminal where regx FUNC_MUX_CTRL_x PD20 20-µA internal pulldown, PD100 100-µA pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup Standard LVCMOS input/output Terminal gated BFAIL Fail-safe LVCMOS input/output Terminal gated GPIO9 MPUIO3 transceiver input/output Terminal gated BFAIL PWRON_RESET input/output buffers Terminal 3-stated BFAIL input Fail-safe LVCMOS input Standard LVCMOS output Boundary-scannable terminal analog oscillator terminals High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven
UART1 signals multiplexed this additional multiplexing module.
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Introduction
Table 2-3. Terminal Characteristics Multiplexing (Continued)
BALL AA13 BALL SIGNAL NAME MCSI1.CLK USB1.VM UART1.RX MCSI1.DIN USB1.RCV UART1.CTS CLK32K_OUT MPUIO0 USB1.SPEED CLK32K_IN OSC32K_IN OSC32K_OUT MMC.DAT3 Reserved MPUIO6 MMC.CLK MMC.DAT0/SPI.DI MMC.DAT2 forced hi-z MPUIO11 MMC.DAT1 Reserved MPUIO7
TYPE I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
CTRL SETTING regA[8:6] regA[8:6] regA[8:6] 001|| regA[11:9] regA[11:9] regA[11:9] 001|| regA[14:12] regA[14:12] regA[14:12] regD[14:12] regD[14:12] regD[14:12] regA[20:18] regA[20:18] regA[20:18] regA[26:24] regA[26:24] regA[26:24] regB[5:3] regB[5:3] regB[8:6] regB[8:6] regB[11:9] regB[11:9] regB[14:12] regB[14:12] regB[20:18] regB[20:18]
DESELECTED INPUT STATE
PD20 PD20 PD20 PD20 PD20 PD20
BUFFER STRENGTH
RESET STATE# input
SUPPLY DVDD1
input
DVDD1
DVDD1
PU20 PU20 PU20 PU20 PU20 PU20 PU20 PU10 PD20 PD20 PD20 PD20 PD20 PD20 PD20 PD20
input input
DVDD1 DVDD1
input input
DVDD1 DVDD1 DVDD1
input
DVDD1
MMC.CMD/SPI.DO MCSI2.CLK USB2.SUSP MCSI2.DIN USB2.VP MCSI2.DOUT USB2.TXEN MCSI2.SYNC GPIO7 MCLK MCLKREQ
EXT_MASTER_REQ
input input input input input input input
DVDD1 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3
GPIO9 GPIO8
Input, Output, High-Impedance 'regx' denotes terminal multiplexing register that controls specified terminal where regx FUNC_MUX_CTRL_x PD20 20-µA internal pulldown, PD100 100-µA pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup Standard LVCMOS input/output Terminal gated BFAIL Fail-safe LVCMOS input/output Terminal gated GPIO9 MPUIO3 transceiver input/output Terminal gated BFAIL PWRON_RESET input/output buffers Terminal 3-stated BFAIL input Fail-safe LVCMOS input Standard LVCMOS output Boundary-scannable terminal analog oscillator terminals High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven
UART1 signals multiplexed this additional multiplexing module.
August 2002 Revised August 2004
SPRS197D
Introduction
Table 2-3. Terminal Characteristics Multiplexing (Continued)
BALL BALL SIGNAL NAME MPUIO3 MCBSP2.DR MCBSP2.DX MCBSP2.FSX MCBSP2.CLKR GPIO11 MCBSP2.CLKX MCBSP2.FSR GPIO12 MCBSP2.DX MCBSP2.DR UART2.RX USB2.VM UART2.CTS USB2.RCV GPIO7 forced drive UART2.RTS USB2.SE0 MPUIO5 forced drive UART2.TX USB2.TXD
TYPE I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
CTRL SETTING regC[2:0] regC[2:0] regC[8:6] regC[8:6] regC[14:12] regC[14:12] regC[17:15] regC[17:15] regC[20:18] regC[20:18] regC[23:21] regC[23:21] regC[23:21] regC[26:24] regC[26:24] regC[26:24] regC[26:24] regC[29:27] regC[29:27] regC[29:27] regD[5:3] regD[5:3]
DESELECTED INPUT STATE
PD20 PD20 PD20 PD20 PD20 PD20
BUFFER STRENGTH
RESET STATE# input input input input input input
SUPPLY DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3
PD20 PD20 PD20 PD20 PD20 PD20
DVDD3
DVDD3
UART2.BCLK USB.PUEN USB.CLKO USB.DP USB.DM OSC1_IN OSC1_OUT FLASH.WP FLASH.WE FLASH.RP FLASH.OE
18.3 18.3
DVDD3 DVDD2 DVDD2 DVDD2 DVDD5 DVDD5 DVDD5 DVDD5
Input, Output, High-Impedance 'regx' denotes terminal multiplexing register that controls specified terminal where regx FUNC_MUX_CTRL_x PD20 20-µA internal pulldown, PD100 100-µA pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup Standard LVCMOS input/output Terminal gated BFAIL Fail-safe LVCMOS input/output Terminal gated GPIO9 MPUIO3 transceiver input/output Terminal gated BFAIL PWRON_RESET input/output buffers Terminal 3-stated BFAIL input Fail-safe LVCMOS input Standard LVCMOS output Boundary-scannable terminal analog oscillator terminals High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven
UART1 signals multiplexed this additional multiplexing module.
SPRS197D
August 2002 Revised August 2004
Introduction
Table 2-3. Terminal Characteristics Multiplexing (Continued)
BALL
BALL
SIGNAL NAME FLASH.D[15:0]
TYPE I/O/Z
CTRL SETTING
DESELECTED INPUT STATE
BUFFER STRENGTH
RESET STATE#
SUPPLY DVDD5
FLASH.CLK FLASH.CS3 FLASH.CS2 FLASH.BAA FLASH.CS1 FLASH.CS0 FLASH.BE[1:0] FLASH.ADV FLASH.A[24:1]
regD[8:6] regD[8:6]
DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5
FLASH.RDY RSVD
input
DVDD5
Input, Output, High-Impedance 'regx' denotes terminal multiplexing register that controls specified terminal where regx FUNC_MUX_CTRL_x PD20 20-µA internal pulldown, PD100 100-µA pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup Standard LVCMOS input/output Terminal gated BFAIL Fail-safe LVCMOS input/output Terminal gated GPIO9 MPUIO3 transceiver input/output Terminal gated BFAIL PWRON_RESET input/output buffers Terminal 3-stated BFAIL input Fail-safe LVCMOS input Standard LVCMOS output Boundary-scannable terminal analog oscillator terminals High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven
UART1 signals multiplexed this additional multiplexing module.
August 2002 Revised August 2004
SPRS197D
Introduction
Signal Description
Table provides description signals OMAP5910. Many signals available multiple pins depending upon software configuration multiplexing options. Ball numbers which italicized indicate default muxings reset. Ball numbers busses listed from (left right, bottom). Table 2-4. Signal Description
SIGNAL BALL BALL DESCRIPTION TYPE
EMIFF SDRAM Interface SDRAM.WE SDRAM.RAS SDRAM.DQMU SDRAM write enable. SDRAM.WE active (low) during writes, DCAB, commands SDRAM memory. SDRAM address strobe. SDRAM.RAS active (low) during ACTV, DCAB, REFR, commands SDRAM memory. SDRAM upper data mask. Active-low data mask upper byte SDRAM data (SDRAM.D[15:8]). data mask outputs allow both 16-bit-wide 8-bit-wide accesses SDRAM memories. SDRAM lower data mask. Active-low data mask lower byte SDRAM data (SDRAM.D[7:0]). data mask outputs allow both 16-bit-wide 8-bit-wide accesses SDRAM memories. SDRAM data bus. SDRAM.D[15:0] provides data exchange between Traffic Controller SDRAM memory.
SDRAM.DQML
SDRAM.D[15:0]
I/O/Z
SDRAM.CKE
SDRAM clock enable. Active-high output which enables SDRAM clock during normal operation; SDRAM.CKE driven inactive memory into low-power mode. SDRAM clock. Clock synchronization SDRAM memory commands/accesses. minimize voltage undershoot overshoot effects, recommended place series resistor (typically close SDRAM.CLK driver pin. SDRAM.CLK also configured input monitor skew control. SDRAM column address strobe. SDRAM.CAS active (low) during reads, writes, REFR commands SDRAM memory. SDRAM bank address bus. Provides bank address SDRAM memories.
SDRAM.CLK
I/O/Z
SDRAM.CAS SDRAM.BA[1:0]
D10,
Input, Output, High-Impedance core voltage supplies should tied same voltage level (within During system prototyping phases, useful maintain capability independent measurement core supply currents facilitate power optimization experiments. Sections 5.6.1 5.6.2 special considerations with oscillator circuits.
SPRS197D
August 2002 Revised August 2004
Introduction
Table 2-4. Signal Description (Continued)
SIGNAL BALL G10, H10, C11, D11, G11, C12, D12, H11, C13, D13, G12, C14, BALL C10, D10, C11, B10, A10, DESCRIPTION TYPE
EMIFF SDRAM Interface (Continued) SDRAM.A[12:0] SDRAM address bus. Provides column address information SDRAM memory well command data. SDRAM.A[10] also serves control signal define specific commands SDRAM memory.
EMIFS FLASH Asynchronous Memory Interface FLASH.WP FLASH.WE FLASH.RP FLASH.OE FLASH.D[15:0] EMIFS byte enables. Active-low byte enable signals used perform byte-wide accesses memories devices that support byte enables. EMIFS address valid. Active-low control signal used indicate valid address present FLASH.A[24:1] bus. EMIFS burst advance acknowledge. Active-low control signal used with Advanced Micro Devices burst Flash. FLASH.BAA multiplexed with FLASH.CS2. EMIFS write protect. Active-low output hardware write protection feature standard memory devices. EMIFS write enable. Active-low write enable output Flash SRAM memories asynchronous devices. EMIFS power down reset output (Intel flash devices) EMIFS output enable. Active-low output enable output Flash SRAM memories asynchronous devices. EMIFS data bus. Bidirectional 16-bit data used transfer read write data during EMIFS accesses. I/O/Z
FLASH.CLK FLASH.CS3 FLASH.CS2 FLASH.CS1 FLASH.CS0 FLASH.BE[1:0] FLASH.ADV FLASH.BAA
EMIFS clock. Clock output that active during synchronous modes EMIFS operation synchronous burst Flash memories. EMIFS chip selects. Active-low chip-select outputs that become active when appropriate address decoded internal device. Each chip select decodes 32M-byte region memory space space.
Input, Output, High-Impedance core voltage supplies should tied same voltage level (within During system prototyping phases, useful maintain capability independent measurement core supply currents facilitate power optimization experiments. Sections 5.6.1 5.6.2 special considerations with oscillator circuits. Intel registered trademark Intel Corporation. Advanced Micro Devices trademark Advanced Micro Devices, Inc. August 2002 Revised August 2004 SPRS197D
Introduction
Table 2-4. Signal Description (Continued)
SIGNAL BALL BALL DESCRIPTION TYPE
EMIFS FLASH Asynchronous Memory Interface (Continued) FLASH.A[24:1] EMIFS address bus. Address output EMIFS accesses. FLASH.A[24:1] provides upper bits 25-bit byte address. byte enables must used implement 8-bit accesses.
FLASH.RDY
EMIFS ready. Active-high ready input used suspend EMIFS interface when external memory asynchronous device ready continue current cycle. recommended that this should pulled high externally unused. OMAP5910 Dual-Core Processor Silicon Errata (literature number SPRZ016) more details. vertical sync output. LCD.VS frame clock which signals start frame pixels panel. mode, LCD.VS vertical synchronization signal. horizontal sync. LCD.HS line clock which signals line pixels panel. mode, LCD.HS horizontal synchronization signal. AC-bias. LCD.AC used signal switch polarity column power supplies counteract charge buildup causing offset. mode, LCD.AC used output enable latch pixel data using pixel clock. pixel clock output. Clock output provided synchronize pixel data panel. passive mode, LCD.PCLK only transitions when LCD.P[15:0] valid. active mode, LCD.PCLK transitions continuously LCD.AC used output enable when LCD.P[15:0] valid.
Interface LCD.VS
LCD.HS
LCD.AC
LCD.PCLK
Input, Output, High-Impedance core voltage supplies should tied same voltage level (within During system prototyping phases, useful maintain capability independent measurement core supply currents facilitate power optimization experiments. Sections 5.6.1 5.6.2 special considerations with oscillator circuits.
SPRS197D
August 2002 Revised August 2004
Introduction
Table 2-4. Signal Description (Continued)
SIGNAL Interface (Continued) LCD.P[15:0] D15, C16, A17, G13, B17, C17, D16, D17, C18, B19, A20, H13, G14, C19, B21, V19, P15, C20, C21, E18, D19, D20, M20, N21, N19, E19, E20, H14, F19, W16, H15, N18, P18, P19, D12, C13, B12, F11, B13, E12, A13, C14, B14, A15, C15, B15, A16, D15, C16, M13, L12, A17, D16, B17, E15, E16, K16, K17, K14, D17, E17, F15, D14, P14, F17, L15, K12, K13, pixel data bus. Pixel data transferred this output panel. BALL BALL DESCRIPTION TYPE
Keyboard Matrix Interface KB.C[7:0] Keyboard matrix column outputs. KB.Cx column outputs used conjunction with KB.Rx inputs implement keyboard matrix.
KB.R[7:0]
Keyboard matrix inputs. KB.Rx inputs used conjunction with KB.Cx column outputs implement keyboard matrix.
Multichannel Buffered Serial Ports (McBSPs) MCBSP1.CLKS MCBSP1.CLKX MCBSP2.CLKX MCBSP3.CLKX MCBSP1.FSX MCBSP2.FSX MCBSP3.FSX McBSP1 clock source. Provides external clock reference with transmitter reciever. CLKS only present McBSP1. McBSP transmit clock. Serial shift clock reference transmitter. CLKX present McBSPs. case McBSP1 McBSP3, clock input BSP1 BSP3 McBSP receiver also provided this terminal internal loop-back connection between transmitter receiver clocks. McBSP transmit frame sync. Frame synchronization transmitter. present McBSPs. case McBSP1 McBSP3, frame sync input McBSP receiver also provided this terminal internal loop-back connection between transmitter receiver frame syncs syncs. I/O/Z
I/O/Z
Input, Output, High-Impedance core voltage supplies should tied same voltage level (within During system prototyping phases, useful maintain capability independent measurement core supply currents facilitate power optimization experiments. Sections 5.6.1 5.6.2 special considerations with oscillator circuits.
August 2002 Revised August 2004
SPRS197D
Introduction
Table 2-4. Signal Description (Continued)
SIGNAL BALL H18, AA5, P14, P10, AA17, BALL F16, U13, R12, McBSP2 receive clock. Serial shift clock reference receiver. CLKR only present McBSP2. McBSP2 receive frame sync. Frame synchronization receiver. only present McBSP2. McBSP receive data. Serial receive data input. present McBSPs. I/O/Z I/O/Z DESCRIPTION TYPE
Multichannel Buffered Serial Ports (McBSPs) (Continued) MCBSP1.DX MCBSP2.DX MCBSP3.DX MCBSP2.CLKR MCBSP2.FSR MCBSP1.DR MCBSP2.DR MCBSP3.DR Camera Interface CAM.EXCLK CAM.LCLK CAM.VS CAM.HS CAM.D[7:0] J18, J19, J14, K18, K19, K15, K14, G14, G12, H16, J15, G17, H17, H14, Camera interface external clock. Output clock used provide timing reference camera sensor. Camera interface line clock. Input clock provide external timing reference from camera sensor logic. Camera interface vertical sync. Vertical synchronization input from external camera sensor. Camera interface horizontal sync. Horizontal synchronization input from external camera sensor. Camera interface data. Data input receive image data from external camera sensor. McBSP transmit data. Serial transmit data output. present McBSPs.
CAM.RSTZ ETM9 Trace Macro Interface ETM.CLK ETM.SYNC ETM.D[7:0]
Camera interface reset. Reset output used reset Initialize external camera sensor logic.
J18, J19, J14, K18, K19, K15, K14,
G14, G12, H16, J15, G17, H17, H14,
ETM9 Trace Clock. Clock output standard ETM9 test/debug equipment. ETM9 Trace Synchronization. Trace Sync output standard ETM9 test/debug equipment. ETM9 Trace Packet data. Trace Packet outputs standard ETM9 test/debug equipment.
Input, Output, High-Impedance core voltage supplies should tied same voltage level (within During system prototyping phases, useful maintain capability independent measurement core supply currents facilitate power optimization experiments. Sections 5.6.1 5.6.2 special considerations with oscillator circuits.
SPRS197D
August 2002 Revised August 2004
Introduction
Table 2-4. Signal Description (Continued)
SIGNAL BALL L18, L15, V19, W21, U18, N14, P15, BALL J17, K15, M13, P16, P17, R16, L12, DESCRIPTION TYPE
ETM9 Trace Macro Interface (Continued) ETM.PSTAT[2:0] ETM9 Trace Pipe State 2-0. Pipeline status outputs standard ETM9 test/debug equipment.
MICROWIRE Interface UWIRE.SCLK UWIRE.SDO UWIRE.SDI UWIRE.CS0 UWIRE.CS3 HDQ/1-Wire Interface HDQ/1-wire interface. optionally implements serial protocols: 1-Wire. Shared General-Purpose I/O. Each GPIO used either core core. Control each GPIO between cores selected control registers Each GPIO also configured cause registers. interrupt respective core processor. GPIO5 GPIO10 available OMAP5910 device. device MICROWIRE serial clock. This drives clock MICROWIRE device. active edge software configurable. MICROWIRE serial data out. Write data transferred MICROWIRE device this pin. MICROWIRE serial data Read data transferred from MICROWIRE device this pin. MICROWIRE chip select output selects single MICROWIRE device (configurable active high active low). MICROWIRE chip select output selects single MICROWIRE device (configurable active high active low).
General-Purpose (GPIO) (MPUIO) GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO9 GPIO8 GPIO7 N18, N20, M15, L15, L16, L17, I/O/Z
GPIO6 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
Input, Output, High-Impedance core voltage supplies should tied same voltage level (within During system prototyping phases, useful maintain capability independent measurement core supply currents facilitate power optimization experiments. Sections 5.6.1 5.6.2 special considerations with oscillator circuits.
August 2002 Revised August 2004
SPRS197D
Introduction
Table 2-4. Signal Description (Continued)
SIGNAL BALL T20, BALL L13, Pulse Width Tone output. output provides modulated output with external buzzer. Pulse Width Light output. output provides pseudo-random modulated voltage output used keypad backlighting. MMC/SD clock. Clock output MMC/SD card. MMC/SD command output. MMC/SD commands transferred to/from this pin. card data Data used 4-bit Secure Digital mode. card data Data used 4-bit Secure Digital mode. card data Data used -bit Secure Digital mode. MMC/SD dat0 input. MMC.DAT0 functions data during Secure Digital operation. functions data input generic mode. DESCRIPTION TYPE
General-Purpose (GPIO) (MPUIO) (Continued) MPUIO12 MPUIO11 MPUIO7 MPUIO6 MPUIO5 MPUIO4 MPUIO3 MPUIO2 MPUIO1 MPUIO0 General-Purpose I/O. MPUIO pins only used core. MPUIO8, MPUIO9 MPUIO10 available OMAP5910 device device. MPUIO8 MPUIO9, I/O/Z
Pulse-Width Tone Pulse-Width Light Interface
Multimedia Card/Secure Digital Interface (MMC/SD) MMC.CLK MMC.CMD MMC.DAT3 MMC.DAT2 MMC.DAT1 MMC.DAT0
W10,
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
Input, Output, High-Impedance core voltage supplies should tied same voltage level (within During system prototyping phases, useful maintain capability independent measurement core supply currents facilitate power optimization experiments. Sections 5.6.1 5.6.2 special considerations with oscillator circuits.
SPRS197D
August 2002 Revised August 2004
Introduction
Table 2-4. Signal Description (Continued)
SIGNAL BALL M18, L14, R13, AA15 Y13, R19, W21, U18, BALL J13, H12, L10, P11, M17, P16, P17, UART baud clock output. clock UART2 baud rate driven onto this pin. This feature only implemented UART2. serial clock. I2C.SCL provides timing reference transfers. serial data. I2C.SDA provides control data transfers. UART data-set-ready. only present UART1 UART3. UART data-terminal-ready. only present UART1 UART3. UART request-to-send. present UARTs. UART3 IrDA mode, this SD_MODE. MODE UART clear-to-send. present UARTs. UART receive. Receive data input. present UARTs. UART3, implements RXIR function during mode operation. DESCRIPTION TYPE
Universal Asynchronous Receiver/Transmitter Interfaces UART1.TX UART2.TX UART3.TX UART1.RX UART2.RX UART3.RX UART1.CTS UART2.CTS UART3.CTS UART1.RTS UART2.RTS UART3.RTS UART transmit. Transmit data output. present UARTs. UART3, implements TXIR function during mode operation.
UART1.DTR UART3.DTR UART1.DSR UART3.DSR UART2.BCLK
Inter-Integrated Circuit Master Slave Interface I2C.SCL I2C.SDA LED1 LED2 I/O/Z I/O/Z
Pulse Generator Interface Pulse Generator output LED1 produces static pulsing output used drive external indicator. Pulse Generator output LED2 produces static pulsing output used drive external indicator. MCSI clock. Multichannel Serial Interface clock reference. clock driven master mode external clock driven this signal slave mode. MCSI sync. Multichannel Serial Interface frame synchronization signal. frame sync driven master mode external clock driven this signal slave mode. MCSIx.SYNC configured active-low active-high sync.
Multichannel Serial Interfaces (MCSIs) MCSI1.CLK MCSI2.CLK MCSI1.SYNC MCSI2.SYNC
AA13
I/O/Z I/O/Z
Input, Output, High-Impedance core voltage supplies should tied same voltage level (within During system prototyping phases, useful maintain capability independent measurement core supply currents facilitate power optimization experiments. Sections 5.6.1 5.6.2 special considerations with oscillator circuits.
August 2002 Revised August 2004
SPRS197D
Introduction
Table 2-4. Signal Description (Continued)
SIGNAL BALL BALL internal transceiver positive side integrated transceiver's differential bus. series resistor tolerance) required USB.DP pin. internal transceiver negative side integrated transceiver's differential bus. series resistor tolerance) required USB.DM pin. transmit enable. Driven active (low) when host Function peripheral driving data onto output. transmit data. Single-ended logic output used transmit data transmit input external transceiver. USBx.TXD also used transceiverless connection between OMAP5910 another transceiverless device. vplus data. Single-ended input used monitor logical state line USBx should driven external transceiver based bus. USBx.VP state vminus data. Single-ended input used monitor logical state line USBx should driven external transceiver bus. USBx.VM based state receive data. Single-ended logic input used receive data from receive output external transceiver. USBx.RCV also used transceiverless connection between OMAP5910 another transceiverless device. segment suspend control. Active-high output indicates detection IDLE condition greater than USBx SUSP implemented USBx.SUSP both ports single-ended zero. Active-high output indicates detection single-ended zero state bus. USBx.SE0 implemented both ports segment speed control. Static control output used external transceiver determine whether port operating full-speed low-speed mode. USB1.SPEED only implemented port I/O/Z MCSI data out. Multichannel Serial Interface data output pin. DESCRIPTION TYPE
Multichannel Serial Interfaces (MCSIs) (Continued) MCSI1.DIN MCSI2.DIN MCSI1.DOUT MCSI2.DOUT USB.DP MCSI data Multichannel Serial Interface data input pin.
(Integrated Transceiver Interface, used with Host Function)
USB.DM
I/O/Z
Group (Utilizing External Transceivers, used with Host Function) USB1.TXEN USB2.TXEN USB1.TXD USB2.TXD USB1.VP USB2.VP USB1.VM USB2.VM USB1.RCV USB2.RCV USB1.SUSP USB2.SUSP USB1.SE0 USB2.SE0 USB1.SPEED AA13 AA17
Input, Output, High-Impedance core voltage supplies should tied same voltage level (within During system prototyping phases, useful maintain capability independent measurement core supply currents facilitate power optimization experiments. Sections 5.6.1 5.6.2 special considerations with oscillator circuits.
SPRS197D
August 2002 Revised August 2004
Introduction
Table 2-4. Signal Description (Continued)
SIGNAL Miscellaneous Signals USB.CLKO USB.PUEN clock output. 6-MHz divided clock output internal DPLL provided reference. Common host Function peripherals. pullup enable. Control output used conjunction with external pullup resistor implement device connect disconnect software. USB.PUEN used with Function peripheral. voltage enable. USB.VBUS used provide logic-high voltage level which used enable pullup resistors indicate connection disconnection status OMAP5910 device Function device. IEEE Standard 1149.1 test clock. normally free-running clock signal with duty cycle. changes test access port (TAP) input signals clocked into controller, instruction register, selected test data register rising edge TCK. Changes output signal occur falling edge TCK. IEEE Standard 1149.1 test data input. clocked into selected register (instruction data) rising edge TCK. IEEE Standard 1149.1 test data output. contents selected register (instruction data) shifted falling edge TCK. high-impedance state except when scanning data progress. IEEE Standard 1149.1 test mode select. This serial control input clocked into controller rising edge TCK. IEEE Standard 1149.1 test reset. TRST, when high, gives IEEE standard 1149.1 scan system control operations device. TRST connected, driven low, device operates functional mode, IEEE standard 1149.1 signals ignored. Emulation When TRST driven high, EMU0 used interrupt from emulator system defined input/output IEEE standard 1149.1 scan system. Emulation When TRST driven high, EMU1 used interrupt from emulator system defined input/output IEEE standard 1149.1 scan system. BALL BALL DESCRIPTION TYPE
USB.VBUS
JTAG/Emulation Interface
AA19
TRST
EMU0
EMU1
Device Clock Pins CLK32K_IN CLK32K_OUT CLK32K_CTRL AA20 32-kHz clock input. Digital CMOS 32-kHz clock input driven external 32-kHz oscillator internal 32-kHz oscillator used. 32-kHz clock output. Clock output reflecting internal 32-kHz clock. 32-kHz clock selection control input. CLK32K_CTRL selects whether internal 32-kHz oscillator used 32-kHz clock provided externally CLK32K_IN input. CLK32K_CTRL high, 32-kHz internal oscillator used; CLK32K_CTRL low, CMOS input CLK32K_IN used 32-kHz clock source. 32-kHz crystal connection. Analog clock input 32-kHz oscillator with external crystal. 32-kHz crystal connection. Analog output from 32-kHz oscillator with external crystal. Base crystal connection. Analog input base oscillator with external crystal driven external 13-MHz oscillator.
OSC32K_IN OSC32K_OUT OSC1_IN
analog analog analog
Input, Output, High-Impedance core voltage supplies should tied same voltage level (within During system prototyping phases, useful maintain capability independent measurement core supply currents facilitate power optimization experiments. Sections 5.6.1 5.6.2 special considerations with oscillator circuits.
August 2002 Revised August 2004
SPRS197D
Introduction
Table 2-4. Signal Description (Continued)
SIGNAL BALL BALL DESCRIPTION TYPE
Device Clock Pins (Continued) OSC1_OUT MCLK Base crystal connection. Analog output from base oscillator with external 13-MHz crystal. M-Clock. General-purpose clock output which configured MHz. MCLK configured drive constantly only when MCLKREQ signal asserted active high. B-Clock. General purpose clock output which configured MHz. BCLK configured drive constantly only when BCLKREQ signal asserted active high. M-Clock Request. Active high request input which allows external device request that MCLK driven. B-Clock Request. Active high request input which allows external device request that BCLK driven. analog
BCLK
MCLKREQ BCLKREQ Reset Logic Pins PWRON_RESET MPU_RST RST_OUT
Reset input device. Active-low asynchronous reset input resets entire OMAP5910 device. reset input. Active-low asynchronous reset input resets core. Reset output. Active-low output asserted when MPUST active (after synchronization.)
Interrupts Miscellaneous Control Configuration Pins MPU_BOOT AA17 boot mode. When MPU_BOOT low, boots from chip select EMIFS (Flash) interface. When MPU_BOOT high, boots from chip select EMIFS. request external observation output. external observation output. External requests. EXT_DMA_REQ0 EXT_DMA_REQ1 provide request inputs which external devices trigger System transfers. System must configured software respond these external requests. Battery power failure external interrupt input. BFAIL/EXT_FIQ used gate certain input pins when battery power failing. pins which gated configured software. This also optionally used external interrupt source MPU. function this configurable software. External master request. 12-MHz clock provided external device instead using on-chip oscillator, high level this output indicates external device that clock must driven. level indicates that OMAP5910 device sleep mode 12-MHz clock necessary. Low-power request output. This active-high output indicates that OMAP5910 device low-power sleep mode. During reset functional modes, LOW_PWR driven low. This signal used indicate low-power state external power management devices system used chip select external SDRAM memory minimize current consumption while SDRAM self-refresh OMAP5910 device sleep mode. Configuration input. CONF selects reserved factory test modes. CONF should always pulled during device operation.
DMA_REQ_OBS IRQ_OBS EXT_DMA_REQ1 EXT_DMA_REQ0 BFAIL/EXT_FIQ
EXT_MASTER_REQ
LOW_PWR
CONF
Input, Output, High-Impedance core voltage supplies should tied same voltage level (within During system prototyping phases, useful maintain capability independent measurement core supply currents facilitate power optimization experiments. Sections 5.6.1 5.6.2 special considerations with oscillator circuits.
SPRS197D
August 2002 Revised August 2004
Introduction
Table 2-4. Signal Description (Continued)
SIGNAL BALL BALL DESCRIPTION TYPE
Interrupts Miscellaneous Control Configuration Pins (Continued) STAT_VAL/WKUP Static Valid Chip wake-up input. STAT_VAL/WKUP also sampled reset select MMC/SD port. MMC/SD peripheral used, this must pulled high during reset. recommended that this pulled high during reset regardless whether MMC/SD will used. Reset Host output. software controllable Reset Shutdown output external device. Reserved pin. This must left unconnected.
RST_HOST_OUT RSVD Power Supplies
A11, A13, A21, B16, B18, F20, J20, K20, R21, U20, V12, W20, Y15, AA1, AA7, AA21 P12, B13, B20, J21,
G11, L11, J12, J10, K10, H10, F12, M12, E13, J11, T17, F10, G10, H11,
Ground. Common ground return core voltage supplies.
power
CVDD
Core supply voltage. Supplies power OMAP5910 core logic low-voltage sections I/O.
power
CVDD1 CVDD2 CVDD3
Core Supply Voltage Supplies power on-chip shared SRAM memory (192k-Bytes). Core Supply Voltage Supplies power subsystem logic memory. Core Supply Voltage Supplies power subsystem logic memory.
power power power
CVDD4
Core Supply Voltage Supplies power DPLL which provides internal clocks core peripherals (excluding peripherals). NOTE: voltage this supply should kept clean possible maximize performance.
power
Input, Output, High-Impedance core voltage supplies should tied same voltage level (within During system prototyping phases, useful maintain capability independent measurement core supply currents facilitate power optimization experiments. Sections 5.6.1 5.6.2 special considerations with oscillator circuits.
August 2002 Revised August 2004
SPRS197D
Introduction
Table 2-4. Signal Description (Continued)
SIGNAL Power Supplies (Continued) CVDDA Analog supply voltage. Supplies power ULPD DPLL which provides internal clock peripherals. NOTE: voltage this supply should kept clean possible maximize performance. Supply Voltage Supplies power majority peripheral buffers. DVDD1 connected common with other DVDD supplies same operating voltage desired. power BALL BALL DESCRIPTION TYPE
DVDD1
A15, A19, E21, L21, U21, AA11,
C12, A14, E14, H13, N16,
power
DVDD2
Supply Voltage Supplies power internal transceiver buffers. DVDD2 optionally used connect disconnect detection connecting DVDD2 power from system. DVDD2 connected common with other DVDD supplies same operating voltage desired. Supply Voltage Supplies power MCSI2 McBSP2 peripheral buffers well GPIO[9:8] buffers. DVDD3 supply operate within high-voltage low-voltage range (see Section operating conditions). DVDD3 connected common with other DVDD supplies same operating voltage desired. Supply Voltage Supplies power SDRAM interface buffers. DVDD4 supply operate within high-voltage low-voltage range (see Section operating conditions). DVDD4 connected common with other DVDD supplies same operating voltage desired. Supply Voltage Supplies power FLASH interface buffers. DVDD5 supply operate within high-voltage low-voltage range (see Section operating conditions). DVDD5 connected common with other DVDD supplies same operating voltage desired.
power
DVDD3
power
DVDD4
B10,
power
DVDD5
power
Input, Output, High-Impedance core voltage supplies should tied same voltage level (within During system prototyping phases, useful maintain capability independent measurement core supply currents facilitate power optimization experiments. Sections 5.6.1 5.6.2 special considerations with oscillator circuits.
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OMAP5910 (289-Ball Package) Timers Watchdog Timer Level Interrupt Handlers Public Peripherals McBSP1 MCSI1 MCSI2 Public (Shared) Peripheral McBSP3 Private Peripherals
Private Peripheral
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TMS320C55x (Instruction Cache, SARAM, DARAM, DMA, Accelerators) Interface MPU/DSP Shared Peripherals Mailboxes GPIO UART1, UART2, UART3 System Controller Bridge Public Peripheral Peripheral Public Peripherals McBSP2 Function Host Private Peripheral Local MICROWIRE
Functional Overview
Flash SRAM Memories
SDRAM Memories
Memory Interface Traffic Controller (TC)
SRAM 192K Bytes Core (TI925T) (Instruction Cache, Data Cache, MMUs) ETM9
following functional overview based block diagram Figure 3-1.
Figure 3-1. OMAP5910 Functional Block Diagram
Private Peripherals Clock/Reset/Power Management Timers Watchdog Timer Level Interrupt Handlers Configuration Registers Clock Reset External Clock Requests
Camera MPUIO HDQ/1-Wire Keyboard MMC/SD 32-kHz Timer
JTAG/ Emulation
Functional Overview
SPRS197D
ETM9 pins shared with Camera Interface.
Functional Overview
Functional Block Diagram Features
OMAP5910 device includes following functional blocks: ARM9TDMI-based core 16K-byte instruction cache 8K-byte data cache Memory Management Units (MMUs) Instruction Data 64-entry Translation Look-Aside Buffers (TLBs) MMUs 17-word write buffer 48K-word single-access (SARAM) (96K bytes) 32K-word dual-access (DARAM) (64K bytes) 16K-word (32K bytes) 24K-byte instruction cache Six-channel controller Hardware Accelerators DCT, iDCT, pixel interpolation, motion estimation
C55x subsystem
Nine-channel system controller Traffic controller providing shared access three memory interfaces: EMIFF External Memory Interface providing 16-bit interface bytes standard SDRAM EMIFS External Memory Interface providing 16-bit interface 128M bytes Flash, ROM, asynchronous memories Internal Memory Interface (IMIF) providing 32-bit interface 192K bytes internal SRAM
Memory Management Unit (MMU) configured Interface (MPUI) allowing System access subsystem memory public peripherals Local Interface (with MMU) allowing host peripheral direct access system memories. Private Peripherals (accessible only DSP) Three 32-bit general-purpose timers Watchdog timer Level 1/Level interrupt handlers Multichannel Buffered Serial Ports (McBSPs) Multichannel Serial Interfaces (MCSIs) ideal voice data Three 32-bit general-purpose timers Watchdog Timer Level 1/Level interrupt handlers Configuration Registers pin-multiplexing other device-level configurations controller supporting monochrome panels (STN) color panels (STN TFT)
Public Peripherals (accessible DSP, DMA, interface)
Private Peripherals (accessible only MPU)
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Functional Overview
Public Peripherals (accessible System DMA) Multichannel Buffered Serial Port (McBSP) Function interface (optional internal transceiver shared with Host interface) Host interface with three ports (optional internal transceiver shared with Function interface) integrated transceiver either host Function Inter-Integrated Circuit (I2C) Multi-mode master slave interface MICROWIRE serial interface Camera interface providing connectivity CMOS image sensors general-purpose I/Os (MPUIOs) 32-kHz timer with Pulse-Width Tone (PWT) module tone generation Pulse-Width Light (PWL) module backlight control Keyboard interface matrix) Multimedia Card Secure Digital interface (MMC/SD) Pulse Generator modules (LPG) Real-Time Clock module (RTC) 1-Wire Master interface serial communication battery management devices Frame Adjustment Counter (FAC) Four Mailboxes interprocessor communications General-Purpose pins with interrupt capability either processor Three UARTs (UART3 mode IrDA functionality) Configurable Digital Phase-Locked Loop (DPLL) providing clocks MPU, DSP, Dedicated DPLL with input clock, dedicated APLL with input clock providing clocking peripherals Integrated base (12- 13-MHz) 32-kHz oscillators utilizing external crystals Reset, clocking idle/sleep controls power management
MPU/DSP Shared Peripherals (Controlling processor selected MPU)
Clock/Reset/Power Management modules
JTAG ETM9 interfaces emulation debug
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Functional Overview
Memory Maps
unified address space. Therefore, internal external memories program data well peripheral registers configuration registers accessed within same address space. space always addressed using byte addressing. Table provides high level illustration entire addressable space. Further detail regarding peripheral configuration registers provided Sections 3.2.2, 3.15, 3.17. Table 3-1. OMAP5910 Global Memory
BYTE ADDRESS RANGE 0x0000 0000 0x01FF FFFF 0x0200 0000 0x03FF FFFF 0x0400 0000 0x05FF FFFF 0x0600 0000 0x07FF FFFF 0x0800 0000 0x09FF FFFF 0x0A00 0000 0x0BFF FFFF 0x0C00 0000 0x0DFF FFFF 0x0E00 0000 0x0FFF FFFF 0x1000 0000 0x13FF FFFF 0x1400 0000 0x1FFF FFFF 0x2000 0000 0x2002 FFFF 0x2003 0000 0x2FFF FFFF 0x3000 0000 0x5FFF FFFF 0x6000 0000 0xDFFF FFFF public memory space 0xE000 0000 0xE0FF FFFF (accessible MPUI) bytes 0xE100 0000 0xEFFF FFFF 0xF000 0000 0xFFFA FFFF 0xFFFB 0000 0xFFFB FFFF 0xFFFC 0000 0xFFFC FFFF 0xFFFD 0000 0xFFFE FFFF 0xFFFF 0000 0xFFFF FFFF public peripherals MPU/DSP shared peripherals private peripherals Reserved public peripherals (accessible MPUI) Reserved Local space Host Reserved IMIF Internal SRAM 192K bytes Reserved Reserved Reserved EMIFF (SDRAM) bytes Reserved EMIFS (Flash CS3) bytes Reserved EMIFS (Flash CS2) bytes Reserved EMIFS (Flash CS1) bytes ON-CHIP EXTERNAL INTERFACE EMIFS (Flash CS0) bytes
3.2.1 Global Memory
Some peripherals within this memory region actually shared peripherals (UART 1,2,3).
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Functional Overview
3.2.2 Subsystem Registers Memory
accesses peripheral configuration registers same that internal external memory accessed. following tables specify base addresses where each registers accessed. accesses these registers must utilize appropriate access width (8-, 16-, 32-bit-wide accesses) indicated tables. Accessing registers with incorrect access width cause unexpected results including Peripheral (TIPB) error associated TIPB interrupt. Refer Sections 3.15, 3.16, 3.17 more detail about each these register sets including individual register addresses, register names, descriptions, supported access types (read, write read/write) reset values. Table 3-2. Private Peripheral Registers
BASE ADDRESS 0xFFFE 0000 0xFFFE C000 0xFFFE C500 0xFFFE C600 0xFFFE C700 0xFFFE C800 0xFFFE CB00 0xFFFE D800 REGISTER Level Interrupt Handler Registers Controller Registers Timer1 Registers Timer2 Registers Timer3 Registers Watchdog Timer Registers Level Interrupt Handler Registers System Controller Registers ACCESS WIDTH ACCESS WIDTH ACCESS WIDTH
Table 3-3. Public Peripheral Registers
BASE ADDRESS 0xFFFB 1000 0xFFFB 3000 0xFFFB 3800 0xFFFB 4000 0xFFFB 4800 0xFFFB 5000 0xFFFB 5800 0xFFFB 6000 0xFFFB 6800 0xFFFB 7800 0xFFFB 9000 0xFFFB A000 0xFFFB A800 0xFFFB C000 0xFFFB D000 0xFFFB D800 REGISTER McBSP2 Registers MICROWIRE Registers Registers Function Registers Registers MPUIO/Keyboard Registers Pulse Width Light (PWL) Registers Pulse Width Tone (PWT) Registers Camera Interface Registers MMC/SD Registers Timer Registers Host Registers Frame Adjustment Counter (FAC) Registers HDQ/1-Wire Registers Pulse Generator (LPG1) Registers Pulse Generator (LPG2) Registers
Table 3-4. MPU/DSP Shared Peripheral Registers
BASE ADDRESS 0xFFFB 0000 0xFFFB 0800 0xFFFB 9800 0xFFFC E000 0xFFFC F000 REGISTER UART1 Registers UART2 Registers UART3 Registers GPIO Interface Registers Mailbox Registers
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Functional Overview
Table 3-5. Public Peripheral Registers (Accessible MPUI Port)
BASE ADDRESS 0xE101 1800 0xE101 2000 0xE101 2800 0xE101 7000 REGISTER McBSP1 Registers MCSI2 Registers MCSI1 Registers McBSP3 Registers ACCESS WIDTH
Table 3-6. Configuration Registers
BASE ADDRESS 0xFFFB C800 0xFFFE 0800 0xFFFE 1000 0xFFFE 1800 0xFFFE C100 0xFFFE C200 0xFFFE C900 0xFFFE CA00 0xFFFE CC00 0xFFFE CE00 0xFFFE CF00 0xFFFE D200 0xFFFE D300 0xFFFE D400 REGISTER UART TIPB Switch Registers Ultra Low-Power Device (ULPD) Registers OMAP5910 Configuration Registers Device Identification Registers Local Control Registers Local Registers Interface (MPUI) Registers TIPB (Private) Bridge Configuration Registers Traffic Controller Registers Clock/Reset/Power Control Registers DPLL1 Configuration Registers Registers TIPB (Public) Bridge Configuration Registers JTAG Identification Registers ACCESS WIDTH
Memory Maps
supports unified program/data memory (program data accesses made same physical space), however peripheral registers located separate space which accessed DSP's port instructions.
3.3.1 Global Memory
Subsystem contains 160K bytes on-chip SRAM (64K bytes DARAM bytes SARAM). also access these memories MPUI (MPU Interface) port. also access shared system SRAM (192K bytes) both EMIF spaces (EMIFF EMIFS) Memory Management Unit (MMU) which configured MPU. Table shows high-level program/data memory subsystem. data accesses utilize 16-bit word addresses while program fetches utilize byte addressing. Table 3-7. Global Memory
BYTE ADDRESS RANGE 0x00 0000 0x00 FFFF 0x01 0000 0x02 7FFF 0x02 8000 0x04 FFFF 0x05 0000 0xFF 7FFF 0xFF 8000 0xFF FFFF
WORD ADDRESS RANGE 0x00 0000 0x00 7FFF 0x00 8000 0x01 3FFF 0x01 4000 0x02 7FFF 0x02 8000 0x7F BFFF 0x7F C000 0x7F FFFF
INTERNAL MEMORY DARAM bytes SARAM bytes Reserved
EXTERNAL MEMORY
Managed PDROM (MPNMC Managed (MPNMC
This space could external memory internal shared system memory depending configuration.
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Functional Overview
3.3.2 On-Chip Dual-Access (DARAM)
DARAM located byte address range 000000h-00FFFFh composed eight blocks bytes each (see Table 3-8). Each DARAM block perform accesses cycle (two reads, writes, read write). Table 3-8. DARAM Blocks
BYTE ADDRESS RANGE 0x00 0000 0x00 1FFF 0x00 2000 0x00 3FFF 0x00 4000 0x00 5FFF 0x00 6000 0x00 7FFF 0x00 8000 0x00 9FFF 0x00 A000 0x00 BFFF 0x00 C000 0x00 DFFF 0x00 E000 0x00 FFFF WORD ADDRESS RANGE 0x00 0000 0x00 0FFF 0x00 1000 0x001FFF 0x00 2000 0x00 2FFF 0x00 3000 0x00 3FFF 0x00 4000 0x00 4FFF 0x00 5000 0x00 5FFF 0x00 6000 0x00 6FFF 0x00 7000 0x00 7FFF MEMORY BLOCK DARAM DARAM DARAM DARAM DARAM DARAM DARAM DARAM
3.3.3 On-Chip Single-Access (SARAM)
SARAM located byte address range 010000h-03FFFFh composed blocks bytes each (see Table 3-9). Each SARAM block perform access cycle (one read write). Table 3-9. SARAM Blocks
BYTE ADDRESS RANGE 0x01 0000 0x01 1FFF 0x01 2000 0x01 3FFF 0x01 4000 0x01 5FFF 0x01 6000 0x01 7FFF 0x01 8000 0x01 9FFF 0x01 A000 0x01 BFFF 0x01 C000 0x01 DFFF 0x01 E000 0x01 FFFF 0x02 0000 0x02 1FFF 0x02 2000 0x02 3FFF 0x02 4000 0x02 5FFF 0x02 6000 0x02 7FFF WORD ADDRESS RANGE 0x00 8000 0x00 8FFF 0x00 9000 0x00 9FFF 0x00 A000 0x00 AFFF 0x00 B000 0x00 BFFF 0x00 C000 0x00 CFFF 0x00 D000 0x00 DFFF 0x00 E000 0x00 EFFF 0x00 F000 0x00 FFFF 0x01 0000 0x01 0FFF 0x01 1000 0x01 1FFF 0x01 2000 0x01 2FFF 0x01 3000 0x01 3FFF MEMORY BLOCK SARAM SARAM SARAM SARAM SARAM SARAM SARAM SARAM SARAM SARAM SARAM SARAM
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Functional Overview
3.3.4 Space Memory
space separate address space from data/program memory space. space accessed DSP's port instructions. Public Shared peripheral registers also accessible through MPUI (MPU Interface) port. space accessed using 16-bit word addresses. following tables specify base addresses where each registers accessed. accesses these registers must utilize appropriate access width indicated tables. Accessing registers with incorrect access width cause unexpected results including Peripheral (TIPB) error associated TIPB interrupt. Refer Sections 3.16 3.17 more detail about each these register sets including individual register addresses, register names, descriptions, supported access types (read, write read/write) reset values. Table 3-10. Private Peripheral Registers
BASE ADDRESS 0x00 0C00 0x00 2800 0x00 2C00 0x00 3000 0x00 3400 0x00 3800 0x00 4800 REGISTER Controller Registers Timer1 Registers Timer2 Registers Timer3 Registers Watchdog Timer Registers Interrupt Interface Registers Level2 Interrupt Handler Registers ACCESS WIDTH
Table 3-11. Public Peripheral Registers
BASE ADDRESS 0x00 8C00 0x00 9000 0x00 9400 0x00 B800 REGISTER McBSP1 Registers MCSI2 Registers MCSI1 Registers McBSP3 Registers ACCESS WIDTH
Table 3-12. DSP/MPU Shared Peripheral Registers
BASE ADDRESS 0x00 8000 0x00 8400 0x00 CC00 0x00 F000 0x00 F800 REGISTER UART1 Registers UART2 Registers UART3 Registers GPIO Interface Registers Mailbox Registers ACCESS WIDTH
Table 3-13. Configuration Registers
BASE ADDRESS 0x00 0000 0x00 0800 0x00 1400 0x00 4000 0x00 E400 REGISTER TIPB Bridge Configuration Registers EMIF Configuration Registers I-Cache Registers Clock Mode Registers UART TIPB Switch Registers ACCESS WIDTH
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Functional Overview
External Memory (Managed MMU)
When off, address lines directly copied traffic controller without modification. There virtual-to-physical address translation. addresses between 0x05 0000 0x00FF F800 (0x00FF FFFF MP/MC redirected first sector flash (CS0) shared memory space (shared DSP).
Byte Address 0x00 0000 0x05 0000 Memory Internal Shared Memory EMIFS (FLASH CS0) Reserved EMIFS (FLASH CS1) Reserved EMIFS (FLASH CS2) 0xFF 8000 0xFF FFFF Reserved EMIFS (FLASH CS3) Reserved EMIFF (SDRAM) Reserved IMIF (Internal SRAM) 0x2000 0000 0x2002 FFFF 0x1000 0000 0x13FF FFFF 0x0C00 0000 0x0DFF FFFF 0x0800 0000 0x09FF FFFF 0x0400 0000 0x05FF FFFF Byte Address 0x0000 0000 0x01FF FFFF
Figure 3-2.
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Functional Overview
When address lines (virtual address) relocated within physical 32-bit address MMU. controlled MPU.
Byte Address 0x00 0000 0x05 0000 Shared Memory EMIFS (FLASH CS0) Reserved EMIFS (FLASH CS1) Reserved EMIFS (FLASH CS2) Reserved EMIFS (FLASH CS3) Reserved EMIFF (SDRAM) Reserved IMIF (Internal SRAM) 0x2000 0000 0x2002 FFFF 0x1000 0000 0x13FF FFFF 0x0C00 0000 0x0DFF FFFF 0x0800 0000 0x09FF FFFF 0x0400 0000 0x05FF FFFF Byte Address 0x0000 0000 0x01FF FFFF
Memory Internal
FLASH 0xFF 8000 0xFF FFFF
Figure 3-3.
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Functional Overview
Private Peripherals
each have their separate private peripheral bus. Peripherals each these private buses only accessed their respective processors. instance, timers private peripheral accessible System controller.
3.5.1 Timers
each have their three 32-bit timers available their respective private Peripheral (TIPB). These timers used operating systems provide general-purpose housekeeping functions, case DSP, also provide synchronization real-time processing functions. These timers configured either auto-reload one-shot mode with on-the-fly read capability. timers generate interrupt respective processor (MPU DSP) when timer's down-counter equal zero.
3.5.2 Timer (MPU only)
Timer that runs 32-kHz clock opposed subsystem domain clock. subsystem operating system (OS) requires interrupts regular time intervals scheduling purpose (typically ms). These time intervals generated using MPU's three 32-bit general-purpose timers. However, these timers cannot used sleep modes when system clock operating. Therefore, 32-kHz clock-based timer needed provide required timing interval.
3.5.3 Watchdog Timer
each have single Watchdog Timer. Each watchdog timer configured either watchdog timer general-purpose timer. watchdog timer requires that software periodically write appropriate count register before counter underflows. counter underflows, generates reset appropriate processor (MPU DSP). resets only processor while resets both processors (MPU DSP). watchdog timers useful detecting user programs that stuck infinite loop, resulting loss program control runaway condition. When used general-purpose timer, 16-bit timer configurable either autoreload one-shot mode with on-the-fly read capability. timer generates interrupt respective processor (MPU DSP) when timer's down-counter equal zero.
3.5.4 Interrupt Handlers
each have levels interrupt handling, allowing interrupts interrupts MPU.
3.5.5 Controller
OMAP5910 device includes Controller that interfaces with most industry-standard LCDs. Controller configured utilizes dedicated channel System transfer data from frame buffer. frame buffer implemented using internal shared SRAM (192K bytes) optionally using external SDRAM EMIFF. Using frame buffer data source, System must provide data FIFO front controller data path rate sufficient support chosen display mode resolution. Optimal performance achieved when using internal SRAM frame buffer. panel size programmable, width (line length) from 1024 pixels 16-pixel increments. number lines programming total number pixels LCD. total frame size programmable 1024 1024. However, frame sizes frame rates supported specific applications will depend upon available memory bandwidth allowed specific application well maximum configurable pixel clock rate.
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Functional Overview
screen intended mapped frame buffer contiguous block where each horizontal line pixels mapped consecutive bytes words frame memory. principle features controller are: Dedicated 64-entry 16-bit FIFO Dedicated channel Programmable display including support 12-, 16-bit graphics modes Programmable display resolutions 1024 pixels 1024 lines (assuming sufficient system bandwidth) Support passive monochrome (STN) displays Support passive color (STN) displays Support active color (TFT) displays Patented dithering algorithm, providing: grayscale levels monochrome passive displays 3375 colors color passive displays 65536 colors active color displays 256-entry 12-bit palette Programmable pixel rate Pixel clock plus horizontal vertical synchronization signals ac-bias drive signal Active display enable signal 256-entry 12-bit palette Dual-frame buffers
Public Peripherals
Peripherals Public Peripheral only accessed System Controller, which configured MPU. This called public because accessible System controller. cannot access peripherals this bus.
3.6.1 Host Controller
OMAP5910 host controller communicates with devices low-speed (1.5M-bit/s maximum) full-speed (12M-bit/s maximum) data rates. controller compliant. additional information, Universal Serial Specification, Revision OpenHCI Open Host Controller Interface Specification USB, Release 1.0a, hereafter called OHCI Specification USB. OMAP5910 host controller implements register makes memory data structures which defined OHCI Specification USB. These registers data structures mechanism which host controller driver software package control OMAP5910 host controller. host controller connected public peripheral access registers. host controller gains access data structures system memory internal Local interface. OMAP5910 device implements variety signal multiplexing options that allows host controller with three available interfaces device. these interfaces utilizes integrated transceiver, while other require external transceivers. host controller support three downstream ports. OMAP5910 host controller implementation does implement every aspect functionality defined OHCI Specification USB. differences focus power switching, overcurrent reporting, OHCI ownership change interrupt. Other restrictions imposed OMAP5910 system memory addressing mechanisms effects OMAP5910 pin-multiplexing options.
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Functional Overview
3.6.2 Function Peripheral
Function peripheral provides full-speed Function interface between wire. module handles transactions with minimal intervention fully compliant standard. Function module supports control endpoint (EP0), endpoints, endpoints. exact endpoint configuration software-programmable. specific items configuration each endpoint are: size bytes, direction (IN, OUT), type (bulk/interrupt isochronous), associated endpoint number. Function module also supports three System channels endpoints three System channels endpoints either bulk/interrupt isochronous transactions. OMAP5910 device implements variety signal-multiplexing options that allow Function peripheral with three available interfaces device. these interfaces utilizes integrated transceiver, while other require external transceivers. Function only utilize these ports time. other ports used simultaneously Host controller peripheral.
3.6.3 Multichannel Buffered Serial Port (McBSP)
Multichannel Buffered Serial Port (McBSP) provides high-speed, full-duplex serial port that allow direct interface audio codecs, various other system devices. public peripheral access McBSP, which McBSP2. McBSP provides: Full-duplex communication Double-buffer data registers, which allow continuous data stream Independent framing clocking receive transmit Direct interface T1/E1 framers MVIP switching-compatible ST-BUS compliant devices IOM-2 compliant device AC97-compliant device I2S-compliant device Serial peripheral interface (SPI) Multichannel transmit receive channels wide selection data sizes, including: bits µ-law A-law companding Programmable polarity both frame synchronization data clocks Programmable internal clock frame generation NOTE: standard McBSP pins necessarily available every McBSP OMAP5910 device. case MPU's McBSP2, following pins available: CLKX CLKR (transmit receive clocks) (transmit receive frame syncs) (transmit receive data)
addition, McBSP following capabilities:
functional clock McBSP2 peripheral configurable DPLL clock rate with divider McBSP2 does have CLKS external clock reference pin. Therefore, McBSP2 Sample Rate Generator (SRG) used, only reference clock available Sample Rate Generator programmable clock from domain.
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Functional Overview
3.6.4 Master/Slave Interface
Master/Slave Interface compliant Philips 2C-Bus Specification Version master bus. controller supports multimaster mode, which allows more than device capable controlling connected Including OMAP5910 device, each device recognized unique address operate either transmitter receiver, depending function device. addition being transmitter receiver, device connected also considered master slave when performing data transfers. Interface supports following features: Compliant Philips 2C-Bus Specification Version Support standard mode 100K bits/s) Fast mode 400K bits/s) 7-bit 10-bit device addressing modes General call Start/Restart/Stop Multimaster transmitter/slave receiver mode Multimaster receiver/slave transmitter mode Combined master transmit/receive receive/transmit mode Built-in FIFO buffered read write Module enable/disable capability Programmable clock generation Supports channels
Interface does support following features: High-speed (HS) mode transfer rates 3.4M bits C-bus compatibility mode
3.6.5 MICROWIRE Serial Interface
MICROWIRE interface serial synchronous interface that drive four serial external components. interface compatible with MICROWIRE standard seen master. MICROWIRE typically used transmit control status information external peripheral devices transmit data from small nonvolatile memories such serial EEPROMs serial Flash devices.
3.6.6 Multimedia Card/Secure Digital (MMC/SD) Interface
MMC/SD Interface controller provides interface memory cards. controller handles MMC/SD transactions with minimal intervention, allowing optional system channels transfer data. following combination external devices supported: more memory cards sharing same bus. single memory card. NOTE: Other combinations such cards card with card supported. software must manage transaction semantics, while MMC/SD controller deals with MMC/SD protocol transmission level: packing data, adding CRC, generating start/end checking syntactical correctness. mode wide width also supported.
trademark Philips Electronics N.V. SPRS197D August 2002 Revised August 2004
Functional Overview
3.6.7 HDQ/1-Wire Interface
This module allows implementation both 1-Wire protocols. These protocols single wire communicate between master slave. HDQ/1-Wire open-drain requires external pullup resistor. 1-Wire interfaces found commercially available battery management power management devices. interface used send command status information between OMAP5910 such battery power management device.
3.6.8 Camera Interface
camera interface 8-bit external port which used accept data from external camera sensor. interface handles multiple image formats synchronized vertical horizontal synchronization signals. Data transfer camera interface done synchronously asynchronously. camera interface module converts 8-bit data transfers into 32-bit words utilizes 128-word buffer facilitate efficient data transfer memory. Data transferred from camera interface buffer internal memory system controller directly MPU. interface utilize externally driven clock rates optionally provide output reference clock rates MHz, MHz, when camera interface configured clocking from internal MHz. When camera interface configured obtain clocking from base oscillator frequency MHz), camera interface clock configurable operate base frequency half base frequency MHz).
3.6.9 MPUIO/Keyboard Interface
MPUIO pins used either general-purpose Keyboard Interface keypad array. keypad array implemented, unused MPUIO pins used GPIO. When used GPIO, each configured individually either output input, they individually configured generate interrupts based level change (falling rising) after debouncing process. These MPUIO interrupts used wake device from deep-sleep mode using 32-kHz clock. MPUIO pins also used keyboard interface. keyboard interface provides following pins: KB.R[7:0] input pins lines KB.C[7:0] output pins column lines
allow key-press detection, input pins (KB.Rx) pulled DVDD output pins (KB.Cx) driven level. KB.R[7:0] KB.C[7:0] pins should connected external keyboard matrix such that when matrix pressed, corresponding column lines shorted together. action generates interrupt MPU, which then scans column lines particular sequence determine which keys have been pressed.
3.6.10
Pulse-Width Light (PWL)
Pulse-Width Light (PWL) module provides control keypad backlighting employing random sequence generator. This voltage-level control technique decreases spectral power modulator harmonic frequencies. module uses switchable 32-kHz clock.
3.6.11
Pulse-Width Tone (PWT)
Pulse-Width Tone (PWT) module generates modulated frequency signal with external buzzer. frequency programmable between 5276 with half-tone frequencies octave. volume level output also programmable.
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Functional Overview
3.6.12
Pulse Generator
There separate Pulse Generator (LPG) modules. Each module provides output indication LED. blinking period programmable between switched permanently.
3.6.13
Real-Time Clock
Real-Time Clock (RTC) module provides embedded applications which need track real time. This peripheral ultra-low-power module-meaning that module cannot powered independently without powering OMAP5910 core. Therefore, ultra-low-power desired system application, external should used. module following features: Time information (seconds/minutes/hours) directly code Calendar information (day/month/year/day week) directly code year 2099 Interrupts generation, periodically (1s/1m/1h/1d period) precise time (alarm function) 30-s time correction Oscillator frequency calibration
3.6.14
Frame Adjustment Counter
frame adjustment counter (FAC) simple peripheral that counts number rising edges signal (start frame interrupt Function) during programmable number rising edges second signal (transmit frame synchronization McBSP2). only used with these specific Function McBSP2 signals. count value used system-level software adjust duration time domains with respect each other reduce overflow underflow. data being transferred audio data, this module part solution that reduces pops clicks. module generates second-level interrupt MPU.
Public Peripherals
Peripherals Public Peripheral directly accessible DMA. These peripherals also accessed System Controller MPUI interface. MPUI interface must properly configured allow this access.
3.7.1 Multichannel Buffered Serial Port (McBSP)
Multichannel Buffered Serial Port (McBSP) provides high-speed, full-duplex serial port that allow direct interface audio codecs various other system devices. Refer Section 3.6.3 list features provided McBSP. public peripheral access McBSPs: McBSP1 McBSP3. NOTE: standard McBSP pins necessarily available every McBSP OMAP5910 device. case McBSPs, following pins available: McBSP1 pins: CLKX (transmit clock) (transmit frame sync) (transmit receive data) CLKS (external reference Sample Rate Generator) CLKX (transmit clock) (transmit frame sync) (transmit receive data)
McBSP3 pins:
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Functional Overview
Because McBSP1 McBSP3 have CLKR pins available, transmit clock frame sync pins (CLKX FSX) must used clock frame synchronization both transmit receive channels these McBSPs. functional clock McBSP1 McBSP3 fixed OMAP5910 base operating frequency MHz). bit-clock rate these McBSPs therefore limited (one half base frequency). Only McBSP1 CLKS available. sample rate generator (SRG) used McBSP1, reference clock configured either external reference provided CLKS pin, internal base (12- 13-MHz) device clock. However, used McBSP3, only reference clock available this base device clock clock reference.
3.7.2 Multichannel Serial Interface (MCSI)
multichannel serial interface (MCSI) provides flexible serial interface with multichannel transmission capability. MCSI allows access variety external devices, such audio codecs other types analog converters. public peripheral access MCSIs: MCSI1 MCSI2. These MCSIs provide full-duplex transmission master slave clock control. transmission parameters configurable cover maximum number operating conditions. MCSIs have following features: Master slave clock control (transmission clock frame synchronization pulse) Programmable transmission clock frequency (master mode) half OMAP5910 base frequency MHz) Reception clock frequency (slave mode) base frequency MHz) Single-channel multichannel (x16) frame structure Programmable word length: bits Full-duplex transmiss
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