Data Sheet August, 2002 FEATURES 400.0 Mbps jitter fully differen
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UT54LVDM228 Quad Mbps Crosspoint Switch
Data Sheet August, 2002
FEATURES 400.0 Mbps jitter fully differential data path 200MHz clock channel power supply 10mA LVDS output drivers Input receiver fail-safe Cold sparing pins Output channel-to-channel skew 120ps Configurable quad mux, demux, repeater or1:2 signal splitter Fast propagation delay 3.5ns Receiver input threshold Radiation-hardened design; total dose irradiation testing MIL-STD-883 Method 1019 Total-dose: krad(Si) Mrad(Si) Latchup immune (LET MeV-cm2/mg) Packaging options: 64-lead flatpack Standard Microcircuit Drawing 5962-01537 compliant part Compatible with ANSI/TIA/EIA 644-1995 LVDS Standard
INTRODUCTION UT54LVDM228 quad crosspoint switch utilizing Voltage Differential Signaling (LVDS) technology power, high speed operation. Data paths fully differential from input output noise generation pulse width distortion. non-blocking design allows connection input output outputs each switch. LVDS enable high speed data transmission point-to point multidrop interconnects. This device used high speed differential crosspoint, mux, demux, repeater signal splitter. demux functions useful switching between primary backup circuits fault tolerant systems. signal splitter functions useful distribution across several rack-mounted backplanes. individual LVDS outputs into Tri-State enable pins. pins have Cold Spare buffers. These buffers will high impedance when tied VSS.
In1+ In1Sel1 In2+ In2Sel2 Figure UT54LVDM228 Crosspoint Switch Block Diagram (Partial Page complete diagram)
Out1+ Out1-
In1+ In1Sel1 In2+ In2Sel2 In3+ In3Sel3 In4+ In4Sel4 In5+ In5Sel5 In6+ In6Sel6 In7+ In7Sel7 In8+ In8Sel8 ENCK
Out1+ Out1-
Out3+ Out3-
Out4+ Out4-
Out5+ Out5-
Out6+ Out6-
Out7+ Out7-
Out8+ Out8-
Out+
Skew Match
Out-
Figure UT54LVDM228 Crosspoint Switch Block Diagram
In1+ In1En2 In2+ In2V In3+ In3En3 In4+ In4En4 ENCK InVSS In5+ In5En6 In6+ In6V In7+ In7En7 In8+ In8En8
UT54LVDM228 Crosspoint Switch
Sel1 Out1+ Out1Sel2 Out2+ Out2V Sel3 Out3+ Out3Sel4 Out4+ Out4V Out+ OutVSS Sel5 Out5+ Out5Sel6 Out6+ Out6V Sel7 Out7+ Out7Sel8 Out8+ Out8-
TRUTH TABLE Sel1 Sel2 Out1 Out2 Mode splitter Repeater Switch splitter
DESCRIPTION Name InOut+ OutEn Pins Description Non-inverting LVDS input Inverting LVDS input Non-inverting LVDS output Inverting LVDS Output logic enable puts LVDS output into Tri-State reduces supply current logic enable puts LVDS output into Tri-State reduces supply current input select Ground Power supply Non-Inverting Clock LVDS Input Inverting clock LVDS Input Non-Inverting Clock LVDS Output Inverting Clock LVDS Output
ENCK
InCLK Out+ Out-
Figure UT54LVDS228 Pinout
APPLICATIONS INFORMATION UT54LVDM228 provides three modes operation. splitter mode, outputs copies same single input. This useful distribution fan-out applications. repeater mode, device operates 9channel LVDS buffer. Repeating signal restores LVDS amplitude, allowing drive another media segment. This allows isolation segments long distance applications buffers standard LVDS 10mA multi-op drivers.The switch mode provides crosspoint function. This used system when primary redundant paths supported fault tolerant application. intended application these devices signaling technique both point-to-point baseband (single termination) multipoint (double termination) data transmissions over controlled impedance media. transmission media printed-circuit board traces, backplanes, cables. (Note: ultimate rate distance data transfer dependent upon attenuation characteristics media, noise coupling environment, other application specific characteristics.
outer layers flooded with additional ground plane. These planes will improve shielding isolation, well increase intrinsic capacitance power supply plane system. Naturally, effective, these planes must tied ground supply plane frequent intervals with vias. Frequent placement also improves signal integrity signal transmission lines providing short paths image currents which reduces signal distortion. planes should pulled back from transmission lines component mounting pads distance equal width widest transmission line from internal power ground plane(s) whichever greater. Doing minimizes effects transmission line impedances reduces unwanted parasitic capacitances component mounting pads. Compatibility with LVDS standard: backplane multidrop configurations, with closely spaced loads, effective differential impedance line reduced. mainline been designed differential impedance, loading effects reduce this range depending upon spacing capacitance load. Terminating line with load better match than with reflections reduced.
Input Fail-Safe: UT54LVDM228 also supports OPEN, shorted terminated input fail-safe. Receiver output will HIGH fail-safe conditions.
layout Power System Bypass: Circuit board layout stack-up UT54LVDM228 should designed provide noise-free power device. Good layout practice also will separate high frequency high level inputs outputs minimize unwanted stray noise pickup, feedback interference. Power system performance greatly improved using thin dielectrics mils) power/ground sandwiches. This increases intrinsic capacitance power system which improves power supply filtering, especially high frequencies, makes value placement external bypass capacitors less critical. External bypass capacitors should include both ceramic tantalum electrolytic types. capacitors values range 0.01µF 0.1µ Tantalum capacitors range 2.2µF 10µF. Voltage rating tantalum capacitors should least power supply voltage being used. recommended practice vias each power UT54LVDM228, well bypass capacitor terminals. Dual vias reduce interconnect inductance extends effective frequency range bypass components.
ABSOLUTE MAXIMUM RATINGS1 (Referenced SYMBOL I/O4 PARAMETER supply voltage Voltage Storage temperature Maximum power dissipation Maximum junction temperature Thermal resistance, junction-to-case3 input current LIMITS -0.3 4.0V -0.3 0.3V) +150°C 800mW +150°C 22°C/W
±10mA
Notes: Stresses outside listed absolute maximum ratings cause permanent damage device. This stress rating only, functional operation device these other conditions beyond limits indicated operational sections this specification recommended. Exposure absolute maximum rating conditions extended periods affect device reliability performance. Maximum junction temperature increased +175°C during burn-in life test Test MIL-STD-883, Method 1012. Cold Spare mode SS), -0.3V maximum recommended operating 0.3V.
RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER Positive supply voltage Case temperature range input voltage, receiver inputs input voltage, logic inputs LIMITS 3.6V +125°C 2.4V
ELECTRICAL CHARACTERISTICS (VDD 3.3V 0.3V; -55°C +125°C) SYMBOL PARAMETER CONDITION UNIT
CMOS/TTL SPECIFICATIONS (EN, SEL) High-level input voltage Low-level input voltage High-level input current Low-level input current Input clamp voltage Cold Spare Leakage IN=3.6V; 3.6V IN=0V; 3.6V =-18mA IN=3.6V, =VSS -1.5
LVDS OUTPUT SPECIFICATIONS (OUT+, OUT-) Differential Output Voltage Change between complimentary output states Offset Voltage (see Figure OS=(V +VOL (see Figure 1.055 1.550
Change between complimentary RL=35 output states Output Tri-State Current Tri-State output, 3.6V OUT=V
ICSOUT
Cold Sparing Leakage Current Output Short Circuit Current
OUT=3.6V, VDD=V OUT+ OUT-
LVDS RECEIVER SPECIFICATIONS (IN+, IN-) Differential Input High Threshold Differential Input Threshold Common Mode Voltage Range Input Current +1.2V +1.2V ID=200mV +2.4V, 3.6V 3.6V CSIN Cold Sparing Leakage Current IN=3.6V, =VSS -100 2.00 +100
Supply Current Total Supply Current EN8, ENCK ICCZ Tri-State Supply Current EN8, ENCK
Notes: Current into device pins defined positive. Current device pins defined negative. voltages referenced ground. Output short circuit current (IOS specified magnitude only, minus sign indicates direction only. Only output should shorted time, excee maximum junction temperature specification. Guaranteed characterization.
SWITCHING CHARACTERISTICS +3.3V 0.3V, +125 SYMBOL tSET1, tHOLD1,2 tSWITCH tPHZ tPLZ tPZH tPZL tLHT tHLT tPLHD TPHLD TSKEW TCCS PARAMETER Input Setup Time (Figure Input Hold Time (Figure Switched Output (Figure Disable Time (Active Tri-State) High (Figure Disable Time (Active Tri-State) (Figure Enable Time (Tri-State Active) High (Figure Enable Time (Tri-State Active) (Figure Output Low-to-High Transition Time, (Figure Output High-to-Low Transition Time, (Figure Propagation High Delay (Figure Propagation High Delay (Figure Pulse Skew TPHLD TPLHD (Figure Output Channel-to-Channel Skew (Figure Conditions =35, CL=10pf =35, CL=10pf =35, CL=10pf =35, CL=10pf =35, CL=10pf =35, CL=10pf other channels =35, CL=10pf other channels =35, CL=10pf =35, CL=10pf =35, CL=10pf =35, CL=10pf 11.0 11.0 UNIT
Notes: Guaranteed characterization. HOLD time specify that data must stable state before after transition. Guaranteed design. 4.5ns when ENCL another channel.
TIMING DIAGRAMS
THOLD
TSWITCH
Figure Input-to-Select Rising Edge Setup Hold Times Switch Time
THOLD
SWITCH
Figure Input-to-Select Falling Edge Setup Hold Times Switch Time
Pulse Generator
Figure LVDS Output Load
Vdiff=(OUT+) (OUT-)
tLHT tHLT
Figure LVDS Output Transition Time
Vdiff
tPLHD Vdiff
tPHLD
Figure Propagation Delay Low-to-High High-to-Low
tPHZ
tPZH
Diff Diff tPLZ tPZL
Figure Output active TRI-STATE TRI-STATE active
Vdiff
TCCS
Vdiff
Figure Output Channel-to-Channel Skew splitter mode
DOUT+ 20pF Generator
Driver Enabled
20pF
OUT-
Figure Driver Test Circuit Equivalent Circuit
PACKAGING
Notes: exposed metalized areas gold plated over electroplated nickel MIL-PRF-38535. electrically connected VSS. Lead finishes accordance MIL-PRF-38535. Package dimensions symbols similar MIL-STD-1835 Requirement 101, Configuration Lead position coplanarity measured. mark symbol vendor option. With solder, increase maximum 0.003.
Figure 64-pin Flatpack
ORDERING INFORMATION UT54LVDM228 Crosspoint Switch:
54LVDM228
Lead Finish: solder dipped Gold Factory option (gold solder)
Screening: Military Temperature Range flow Prototype flow
Package Type: 64-lead Flatpack (dual-in-line)
Access Time: applicable
Device Type: UT54LVDM228 Crosspoint Switch
Notes: Lead finish (A,C, must specified. specified when ordering, then part marking will match lead finish will either (solder) (gold). Prototype flow UTMC Manufacturing Flows Document. Tested 25°C only. Lead finish GOLD ONLY. Radiation neither tested guaranteed. Military Temperature Range flow UTMC Manufacturing Flows Document. Devices tested -55°C, room temp, Radiation neither tested guaranteed.
UT54LVDM228 Crosspoint Switch:
5962 01537
Lead Finish: solder dipped Gold Factory Option (gold solder) Case Outline: 64-lead Flatpack (dual-in-line) Class Designator: Class Class
Device Type LVDS Crosspoint Switch
Drawing Number: 01537 Total Dose rad(Si) rad(Si) rad(Si) rad(Si) Federal Stock Class Designator: Options
Notes: 1.Lead finish (A,C, must specified. 2.If specified when ordering, part marking will match lead finish will either (solder) (gold). 3.Total dose radiation must specified when ordering. available without radiation hardening.
NOTES
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