FEATURES 71M6511 highly integrated with core, RTC, FLASH driver.

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FEATURES 71M6511 highly integrated with core, RTC, FLASH driver.

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71M6511/71M6511H Power Meter
FEATURES
71M6511 highly integrated with core, RTC, FLASH driver. TDK's patent pending Single Converter Technology with 22-bit delta-sigma ADC, analog inputs, digital temperature compensation, precision voltage reference 32-bit computation engine support wide range residential metering applications with very cost external components. 32kHz crystal timebase entire system Internal battery backup support further reduce system cost. Maximum design flexibility supported with multiple UARTs, I2C, power fail comparator, charge pump, pins system programmable FLASH which updated with data application code operation. Easy conversion offers unprecedented cost structure high volume applications. complete array development tools, programming libraries reference designs enable rapid development certification TOU, Prepay meters that meet world wide electricity metering standards.
0.1% accuracy over 2000:1 range (71M6511H version), 0.5% accuracy over 2000:1 range (71M6511 version) Exceeds IEC62053 ANSIC12.20 standards Voltage reference 10ppm/°C spec (71M6511H version), 50ppm/°C (71M6511 version) Three sensor inputs-VDD referenced Digital temperature compensation 22-bit delta-sigma Independent 32-bit compute engine jitter VARh pulse outputs 40-70Hz line frequency range Phase compensation (±7°) Battery backup 29mW @3.3V, 7.2µW battery backup
LIVE
CT/SHUNT POWER SUPPLY LOAD
NEUT
Flash memory option with security 8-bit microcontroller (80515) Integrated debug High speed serial output time functions event counter/timers
BATTERY
CONVERTER
V3.3A V3.3D GNDA GNDD BOOST
71M6511
TEMP SENSOR
VDRV REGULATOR VBAT V2.5 DRIVER DIO, PULSE VLCD COM0.3 SEG0.19 24.32 0.11 32.41 12.21
Watchdog timer, power fail monitor driver pixels) general purpose pins 32kHz timebase RTC, 64kB FLASH ROM, total UARTs Third software UART pins 64-lead LQFP package Lead Free package option
VOLTAGE VREF VBIAS SERIAL PORTS
FLASH/ COMPUTE ENGINE
3/5V
88.88.8888
EEPROM TEST PULSES
SENSE DRIVE
POWER FAULT
COMPARATOR OSC/PLL XOUT
TIMERS
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71M6511/71M6511H Power Meter
Table Contents
GENERAL DESCRIPTION FEATURES. FUNCTIONAL DESCRIPTION. Meter Equations. Digital Computation Engine (CE) 80515 Core Internal Resources. Memory. Peripherals Digital EEPROM Interface Drivers Optical Interface. Synchronous Serial Interface (SSI). SIGNAL. System Timing Summary. Fault Reset Behavior Battery Operation/Power Save Modes Watchdog Timer Program Security Voltage Reference Meter Calibration. DESCRIPTION Alphabetical Order Ordered Function. Data Memory Data Memory (XRAM).
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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RECOMMENDED EXTERNAL COMPONENTS RECOMMENDED OPERATING CONDITIONS PERFORMANCE SPECIFICATIONS LOGIC LEVELS. SUPPLY CURRENT VREF, VBIAS 2.5V VOLTAGE REGULATOR COMPARATORS FLASH MEMORY TIMING CONVERTER, REFERENCED CRYSTAL OSCILLATOR OPTICAL INTERFACE. TEMPERATURE SENSOR BOOST. DRIVERS FOOTNOTES PACKAGE OUTLINE PINOUT: DESCRIPTIONS Power/Ground Pins:. Analog Pins: Digital Pins:. ORDERING INFORMATION
List Figures
Figure Functional BLOCK DIAGRAM.5 Figure ROutput Format.9 Figure MPU/CE Communication Figure Timing, (SSI_FPOL SSI_RDYPOL Figure Timing, field example. External device delays SRDY. Figure Timing relationship between MUX, Serial Transfers.20 Figure 71M6511H accuracy performance Figure Meter Accuracy over Harmonics 240V,
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SEPTEMBER 2004 List Tables
Table Standard Meter Equations Table Locations Results Table Outputs. Table Data Memory Space Table External Interrupts.11 Table Interrupt Control Bits Table EECTRL status bits.16 Table Liquid Crystal Display Segment Table(typical) Table Pins Table Power Saving Measures
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SEPTEMBER 2004 Figure Functional BLOCK DIAGRAM
VREF VBIAS V3P3A GNDA GNDA
CONVERTER VBIAS V3P3A VREF TEMP CTRL MUX_ALT MUX_DIV CHOP_EN VREF_DIS CK32 VREF FIR_LEN V2P5NV FILTER LCD_IBST LCD_BSTEN VOLTAGE BOOST
VDRV
GNDD
VOLT
V3P3D VBAT
XOUT CKTEST
CKOUT_EN
(32KHz) OSC_DIS
V2P5NV RTCLK (32KHz)
0.1V
GNDD
V2P5
V2P5 VLCD
CK_EN 4.9MHz CK_GEN ECK_DIS MPU_DIV CK_2X CKMPU_2X MUX_SYNC CKCE <4.9MHz WPULSE VARPULSE RDATA 00-FF
CKFIR 4.9MHz (1KB)
2.5V logic
CTRL
LCD_MODE LCD_FS LCD_EN VLC0 VLC1 VLC2
STRT Compute Engine
DISPLAY DRIVER MEMORY SHARE
TEST
TEST MODE
SCALE_TAGS HW_TAGS CONTROL
COM0.3
SEG0.SEG2
PROG 000-7FF
1000-13FF
PRE_SAMPS SUM_CYCLES
RTM_EN CE_EN XFER BUSY CE_BUSY CE_RUN PROG (4KB) CE_LOAD
WPULSE VARPULSE
3000-3FFF
LCD_NUM LCD_MODE LCD_CLK LCD_EN DIGITAL DIO_EEX PULSEV/W DIO_IN DIO_OUT LCD_NUM DIO_GP RTC_HOLD RTC_SET RTCLK V2P5NV CONFIGURATION PARAMETERS
SEG8.SEG19 SEG24/DIO4 SEG31/DIO11 SEG34/DIO14 SEG37/DIO17 SEG3/SCLK SEG4/SSDATA SEG5/SFR SEG6/SRDY SEG7/ MUX_SYNC
CKMPU <4.9MHz SDCK SDOUT SDIN EEPROM INTERFACE 2000-20FF DATA 0000-FFFF 0000-07FF V2PNV5
CONFIG XFER_BUSY CE_BUSY RTCLK PULSE_OUT CK_MPU CK_10M MUX_SYNC OPTRX V3_OK V2_OK WDTR_EN RVBIAS PLL_2.5V IBIAS DGND
UART
(8051)
XRAM (2KB)
DMUX
DIGITAL
OPT_TX
OPTICAL
PROG 0000-FFFF VREF
0000-FFFF
FLASH (64KB) EERDSLOW EEWRSLOW
OPT_RX
OPT_TXDIS
POWER FAULT
WAKE FAULTZ
MPU_RSTZ V3P3
EMULATOR PORT
COMP_STAT COMP_INT
TMUX
ANALOG
TMUXOUT
RESETZ
E_RXTX E_TCLK E_RST (Open Drain)
September 2004
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SEPTEMBER 2004 FUNCTIONAL DESCRIPTION 71M6511 single chip power meter integrates primary functional blocks required implement solidstate electricity meter. Included chip analog front (AFE), digital computation engine, 8051compatible microprocessor, voltage reference, temperature sensor, drivers, RAM, Flash memory, real time clock, variety pins. typical application, 71M6511 sequentially samples voltage inputs pins performs calculations measure active power (Wh), reactive power (VARh), A2h, V2h. These other measurement functions which primarily executed internal 32-bit Compute Engine provided part TDK's standard library. standard ANSI 80515 application programming interface library available help reduce design cycle. addition advanced measurement functions, real time clock function allows device record time metering information multi-rate time-of-use (TOU) applications. Measurements displayed either commonly used temperature environments. Flexible mapping display segments will facilitate integration exisiting custom LCD. Design trade-off between number segments pins implemented software accommodate various requirements. internal UARTs adapted support Infrared with internal drive sense amplification also function standard UART. addition hardware UART modules, customers implement third UART function using Bit-Bang scheme through pins. This flexibility makes possible implement meters with ports plus third Infrared interface. detailed describtion various functions follows:
Meter Equations Compute Engine (CE) implements equations Table Compute Engine (CE) firmware industrial configurations implements equations Table register (located RAM) specifies equation used based number phases used metering. Table Standard Meter Equations Channels used from
Formula Sequence States element, VA(IA-IB)/2 element,
Channels used from alternative Sequence
States TEMP
TEMP
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SEPTEMBER 2004 Analog Front (AFE) 71M6511 comprised input multiplexer, delta-sigma converter voltage reference. Input multiplexer: input multiplexer supports three input signals that applied pins device. Alternatively, ability select temperature (TEMP),VA some cases, selection intended commanded infrequently (every second MPU. order prevent disruption voltage tracking voltage allpass networks, replaced selections. Table details regular alternative sequences. typical application, connected current transformers that sense current each phase line voltage. typically connected voltage sensors through resistor divider.
Control: advance, filter initiation, VREF chopping (using CROSS signal described below) controlled MUX_CTRL circuit. Additionally, MUX_CTRL launches each pass through program. MUX_CTRL clocked CK32, 32768Hz clock from block. behavior MUX_CTRL governed MUX_ALT, EQU, MUX_DIV. MUX_ALT requests alternative multiplexer frame. asserted cycle subsequently deasserted cycle including next one. rising edge MUX_ALT will cause MUX_CTRL wait until next multiplexer frame implement single alternate frame. Another control input multiplexer MUX_DIV. This signal request multiplexer states frame. Delta-sigma Converter: single delta-sigma converter digitizes power inputs device. resolution programmable using FIR_LEN register shown section. resolution selected bits (FIR_LEN=0), bits (FIR_LEN=1). Conversion time cycles CK32 with FIR_LEN three cycles with FIR_LEN Accuracy timing specifications inthis data sheet based FIR_LEN Initiation each conversion controlled MUX_CTRL described previously. each conversion filter output data stored into location determined multiplexer selection. Table details locations. Table Locations Results ADDRESS (HEX) NAME TEMP -DESCRIPTION Phase current Phase voltage Phase current Reserved Reserved Reserved Temperature Reserved
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SEPTEMBER 2004 Voltage Reference: device includes on-chip precision bandgap voltage reference that incorporates autozero techniques well production trims minimize errors caused component mismatch drift. result voltage output with predictable temperature coefficient. Rather than internally compensating temperature variation, digital output corresponding bandgap temperature provided embedded microcontroller which then digitally compensates power outputs. This permits system wide temperature correction over entire system than local chip. This effective thermal coefficients include current sensors, voltage sensors, crystal frequency. Since band chopper stabilized CHOP_EN bits, most significant long term drift mechanism voltage reference removed. CHOP_EN states: Positive, reverse, chop. Digital Computation Engine (CE) dedicated 32-bit performs precision computations necessary accurately measure power. calculations include frequency insensitive offset cancellation channels frequency insensitive phase shifter calculations. Table Outputs. Output TEMP FREQ W0SUM, W1SUM VAR0SUM, VAR1SUM I0SQSUM, I1SQSUM V0SQSUM Description Resolution (LSB size) bandgap temperature with respect calibration 0.1° temperature. information. frequency actual value 232F0/FS. 0.5869 measured fundamental frequency frame rate, typically 2.5kHz. 216.99 output samples selected power (250mVpk Current =200A RMS, equation. 250mVpk Voltage 450V RMS) 216.99 output samples selected power (250mVpk Current =200A RMS, equation, with voltage inputs lagging degrees. 250mVpk Voltage 450V RMS) square samples each 9.644x10-5 current. (250mVpk Current =200A) 4.8823x10-4 squared samples each voltage. (250mVpk Voltage 450V RMS)
number samples summed controlled bits PRE_SAMPS SUM_CYCLES. integration time each energy output PRE_SAMPS SUM_CYCLES/2520.6. contains Real Time Monitor (RTM) which programmed through UART monitor four selectable locations full sample rate. four monitored locations serially output TMUXOUT digital output multiplexer beginning each code pass. Rcan enabled disabled with RTM_EN. Routput clocked CKTEST. Each Rword clocked cycles contains leading flag bit. Figure illustrates Routput format. when
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SEPTEMBER 2004 Figure ROutput Format
CK32 MUX_SYNC
CKTEST TMUXOUT/R
RDATA0 bits) RDATA1 bits) RDATA2 bits) RDATA3 bits)
Clock Generator: clock frequency always CK32 150. clock frequency determined MPU_DIV CE*2-MPU_DIV where MPU_DIV varies from This makes clock scalable from 4.9152MHz down 38.4kHz. CK32 32kHz clock. circuit also generates clock emulator. This clock generated when ECK_DIS asserted emulator. RAM: data accessed filter block, RTM, MPU. Assigned time slots reserved FIR, RTM, MPU, respectively, such that memory accesses collide. Holding registers used convert 8-bit wide data to/from 32-bit wide data, wait states inserted needed, depending frequency CKMPU. Rdata read from locations specified RTM0, RTM1, RTM2, RTM3 after rise MUX_SYNC. PRAM: program loaded boot time then accessed necessary Each instruction word bytes long. PRAM memory size 2048 words. program counter begins pass through code each time state begins. code pass ends when HALT instruction executed. proper operation, code pass must completed before muxstate begins. Communication with MPU: outputs signals MPU: CE_BUSY XFER_BUSY. These connected interrupt service inputs. CE_BUSY indicates that actively processing data. This signal will occur once every multiplexer frame. XFER_BUSY indicates that updating Output region RAM. This will occur whenever finished generating sum. interrupts occur falling edges these signals. power-up loads code into CEPRAM. executes code, generating results storing them RAM. Once, control CEDRAM transferred MPU, then access CEDRAM data.
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FLAG
FLAG
FLAG
FLAG
71M6511/ 71M6511H Power Meter
PRAM
FLASH
TRANSFER CTRL
COMPUTATION ENGINE
DRAM
Figure MPU/CE Communication
Pulse Generator: chip contains pulse generators which create jitter pulses rate APULSEW*WRATE APULSER*WRATE EXT_PULSE EXT_PULSE APULSEW replaced with WSUM_X APULSER replaced with VARSUM_X. DIO_PV DIO_PW described Digital section programmed route WPULSE VARPULSE output pins DIO_7 DIO_6 respectively. LCD_NUM lets user configure number dual purpose pins configured pins. maximum time jitter frame period (normally 400µs) independent number pulses measured. Thus, errors jitter attenuated number pulses averaged, rather than square root number pulses averaged. actual pulse rate, using WSUM example, RATE WRATE WSUM (246 TMUX), measured
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SEPTEMBER 2004 80515 Core device includes 80515 microcontroller (8-bit, 8051 compatible) that processes instruction each clock cycle. Using 5MHz clock, fastest operations processed MIPS. Actual processor clocking speed adjusted total processing demand metering calculations, management, memory management, driver management, management. peripheral 80515, without timer addressable memory space bytes. Data address space allocated on-chip memory follows: Table Data Memory Space ADDRESS (hex) 0000-07FF 1000-13FF 2000-20FF 3000-3FFF MEMORY TYPE Data Data Misc Prog MEMORY SIZE
Interrupts: 71M6511 allows seven external interrupts. These connected shown table direction interrupts programmable MPU. Interrupts should programmed falling sensitivity. generic 8051 literature states that interrupt through defined rising edge sensitive. Thus, hardware signals attached interrupts inverted achieve edge polarity shown Table Table External Interrupts INTERRUPT CONNECTION Digital High Priority Digital Priority Comparator (falling) CE_BUSY (falling) Comparator (rising) EEPROM busy (falling) XFER_BUSY (falling), RTC_1SEC
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SEPTEMBER 2004 Table Interrupt Control Bits NAME EX_XFER EX_RTC IEX2 IEX3 IEX4 IEX5 IEX6 IE_XFER IE_RTC DESCRIPTION Enable external interrupt Enable external interrupt Enable external interrupt Enable external interrupt Enable external interrupt Enable external interrupt Enable external interrupt Enable XFER_BUSY interrupt Enable RTC_1SEC interrupt External interrupt flag External interrupt flag External interrupt flag External interrupt flag External interrupt flag External interrupt flag External interrupt flag XFER_BUSY interrupt flag RTC_1SEC interrupt flag
(special function register) enable bits must permit these interrupts occur. Likewise, each interrupt flag which interrupt hardware must reset interrupt handler. Note that XFER_BUSY RTC_1SEC have their enable flag bits addition interrupt enable flag bits.
Internal Resources Oscillator: oscillator drives standard 32.768kHz watch crystal. These crystals accurate require high current oscillator circuit. 71M6511 oscillator been designed specifically handle these crystals compatible with their high impedance limited power handling capability. oscillator power dissipation very maximize lifetime battery backup device attached VBAT pin. PLL: internal clocks based clock generated on-chip which multiplies watch crystal frequency (32,768Hz). multiplies this frequency yield 4.9152MHz. This frequency supplied ADC, which then supplies clock filter (CKFIR), clock test output (CKTEST), clock generator. clock generator provides clocks, (CKMPU) (CKCE). Clock/Timers: Timing device derived from 32.768kHz watch crystal. On-chip timing functions include 80515 master clock, real time clock (RTC), delta-sigma sample clock, 80515 general counter/timers, timer timer
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SEPTEMBER 2004 Real-Time Clock (RTC): driven directly crystal oscillator. powered V2P5NV net, which battery-backed supply. consists counter chain output registers. counter chain consists seconds, minutes, hours, week, month, month, year. Each counter output register. Whenever reads seconds register, other registers automatically updated. Since clock coherent clock, must read seconds register until consecutive reads same (requires either reads). this point, registers will have correct time. Regardless clock speed, reads require wait state. time writing registers. Each byte written must delayed least clock cycles from previous byte written RTC. time correction bits, RTC_DEC_SEC RTC_INC_SEC provided adjust time. pulse these bits causes time decremented incremented additional second next update RTC_SEC register. crystal temperature coefficient known, integrate temperature correct time necessary discussed temperature compensation. Temperature Sensor: device includes on-chip temperature sensor determining temperature bandgap reference. request alternate frame containing temperature sensor output asserting MUX_ALT. primary temperature data determine magnitude compensation required offset thermal drift system (see section titled "Temperature Compensation"). secondary temperature data monitor ambient temperature meter. user characterize temperature 71M6511 compared ambient temperature within meter. Based this characterization data, user determine over-temperature value. on-chip temperature also monitored determine ambient approaching unsafe level. event that temperature exceeds level, firmware generate interrupt. This interrupt used trigger functions that disable power supplies, contact utility through port, measure duration over-temp condition, etc.
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SEPTEMBER 2004 Memory Flash Memory: 71M6511 includes 64KB on-chip flash memory. flash memory primarily contains program code. also contains images program code, coefficients, RAM, CONFIG RAM. power-up, before enabling copies these images their respective memory locations. Flash66Z (see table) defines speed accessing flash. With this flag being high flash 33ns read pulse used otherwise 66ns read pulse required. minimize supply current draw, this should Flash erasure initiated writing specific data pattern specific registers proper sequence. These special pattern/sequence requirements prevent inadevertent erasure flash memory. mass erase sequence Write FLSH_MEEN (SFR address 0xB2[1]. Write pattern 0xAA FLSH_ERASE (SFR address 0x94) Note: mass erase cycle only initiated when port enabled. page erase sequence Write page address FLSH_PGADR (SFR address 0xB7[7:1] Write pattern 0x55 FLSH_ERASE (SFR address 0x94) write flash memory. This non-volatile storage options available user. other option, battery backed-up RAM, lower supply current option non-volatile storage. FLSH_PWE (flash program write enable) differentiates 80515 data store instructions (MOVX@DPTR,A) between Flash writes. RAM: 71M6511 includes 2k-bytes static memory on-chip plus 256-bytes internal core. 2k-bytes used data storage during normal operations. RAM: working memory read write primary means data communication between processors.
Peripherals 71M6511 includes several peripheral functions that improve functionality device reduce component count most meter applications. peripherals include UARTs, digital I/O, comparator inputs, display drivers, interface interface. Note: Clock stretching multi-master operation supported interface. UART: device includes UART that programmed communicate with variety modules. UART also provides mechanism programming on-chip flash memory. second UART connected optical port, described optical port description.
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SEPTEMBER 2004 UART dedicated wire serial interface which communicate with external host processor. operation each follows: serial input data. transfers inputs contents block internal registers memory. bytes input first. serial output data. Outputs contents block internal registers memory. bytes output first. 71M6511 several on-chip registers which read written. UART transfers programmable parity enable, parity, stop bits/1 stop XON/XOFF options variable communication baud rates from 38400 bps. UART Memory Operations: addition registers, program data memory read written. This accomplished program data address registers. After write memory address register with start address, subsequent reads/writes program register will read/write succesive program memory locations. Similarly, subsequent reads/writes data register will read/write successive data memory locations.
Digital device includes pins general purpose digital I/O. These pins dual function alternatively used drivers. pins configured registers five bits LCD_NUM register (located RAM). Each configured independently input output with DIO_DIR bits. configured input, each configuration word, DIO_Rx, that indicates whether connected resource such interrupt timer control. Additionally, DIO6 DIO7 configured WPULSE VARPULSE outputs using DIO_PW DIO_PV registers. EEPROM interface multiplexed onto DIO4 DIO5.
Analog Digital Output Multiplexer: digital analog signals selected output TMUXOUT pin. function multiplexer controled with TMUX bits (located RAM).
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SEPTEMBER 2004 EEPROM Interface
dedicated serial interface communicates with external EEPROM devices. interface multiplexed onto DIO4 DIO5. DIO_EEX table. communicates with interface through registers: EEDATA EECTRL. wishes write byte data EEPROM, places data EEDATA then writes `Transmit' code EECTRL. write EECTRL initiates transmit. transmit finished when Busy falls. Interrupt also asserted when BUSY falls. then check RX_ACK EEPROM acknowledged transmission. byte read writing `Receive' command EECTRL waiting Busy fall. Upon completion, received data EEDATA. serial transmit receive clock 78kHz during each transmission, then holds high state until next transmission. bits EECTRL shown table below:
Table EECTRL status bits Statu Name Error Busy RX_ACK TX_ACK Read/Writ Polarity High High High High Description Asserted when illegal command received. Asserted when serial data busy. Indicates EEPROM sent bit. Indicates when been sent EEPROM Others Operation No-op Receive byte from EEPROM send ACK. Transmit byte EEPROM Issue `STOP' sequence Receive last byte from EEPROM don't send ACK. Issue `START' sequence Operation, assert Error
CMD[3:0]
Table
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SEPTEMBER 2004 Drivers device contains dedicated segment drivers multi-purpose pins which configured additional segment drivers. device capable driving between pixels display with duty cycle. pixels digit, designed digits display. Since each pixel addressed individually, display combination alphanumeric digits enunciator symbols. drivers grouped into commons (COM0 COM3) segments. typical shown below. charge pump suitable driving VLCD included. This circuit creates from 3.3v supply. contrast provided that permits full scale adjusted between VLCD VLCD. LCD_NUM defines number dual purpose pins used segment interface. Table Liquid Crystal Display Segment Table (typical) Seg0 Com0 Com1 Com2 Com3 Seg1 Seg2 Seg3 Seg4 Seg5 Seg31 P124 P125 P126 P127
Note: Represent pixel numbers LCD.
Optical Interface device includes interface implement optical port. OPT_Tx designed directly drive external transmitting data optical link. OPT_Rx designed sense input from external photo detector used receiver optical link. These pins connected dedicated UART port. OPT_Tx tristated desired multiplex another OPT_Tx output. This control OPT_TXDIS.
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SEPTEMBER 2004 Synchronous Serial Interface (SSI) high speed, handshake, serial interface available send contiguous block data external data logger DSP. block data, configurable location size, sent starting cycle 32kHz before each code pass begins. block data enough that transmission completed when code pass begins, will complete during code pass with timing impact serial data. this case, care must taken that transmitted data modified unexpectedly interface enabled SSI_EN consists SCLK, SSDATA, outputs and, optionally, SRDY input. interface compatible with 16bit 32bit processors. operation each follows: SCLK serial clock. clock 5MHz 10MHz, specified SSI_10M bit. SSI_CKGATE controls whether SCLK runs continuously gated when activity occurring. SCLK gated, will begin cycles before rises will persist cycles after last data output. SSDATA serial output data. SSDATA changes rising edge SCLK outputs contents block words starting with address SSI_STRT ending with SSI_END. words output first. Figure Timing, (SSI_FPOL SSI_RDYPOL
SSI_CKGATE 16bit fields 32bit fields SSI_CKGATE
(Output) SRDY (Input) SCLK (Output) SSDATA (Output) MUX_SYNC SSI_END
SSI_BEG
SSI_BEG+1
Figure Timing, field example. External device delays SRDY.
Next field delayed while SRDY (Output) SRDY (Input) SCLK (Output) SSDATA (Output)
framing pulse. Although words always bits, interface will frame entire data block single field, multiple fields, multiple 32-bit fields. pulse clock cycle wide,
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SEPTEMBER 2004 changes state rising edge SCLK preceeds first each field. field size with SSI_FSIZE: entire data block, fields, 2-16 fields, 3-32 fields. polarity pulse inverted with SSI_FPOL. SRDY does delay first pulse frame will rise third SCLK after MUX_SYNC (fourth SCLK 10MHz). MUX_SYNC used synchronize fields arriving data logger DSP. pins used multiplexed with segment outputs, shown table Table Pins SIGNAL SCLK SSDATA SRDY SEGMENT OUTPUT SEG3 SEG4 SEG5 SEG6
SRDY optional handshake input that indicates that data logging device ready receive data. SRDY must high enable rise initiate transfer next field. expected that SRDY changes state rising edges SCLK. SRDY high when port ready transmit next field, transmission will delayed until SRDY ignored except beginning field transmission. SRDY enabled SSI_RDYEN), port will behave SRDY always one.
System Timing Summary Figure summarizes timing relationships between input states, CE_BUSY signal, serial output streams. this example, MUX_DIV=6 FIR_LEN 288. Since filter conversions required three CK32 cycles, duration each frame MUX_DIV FIR_LEN 288, MUX_DIV FIRLEN 384. Followed conversions single CK32 cycle. Each program pass begins when MUX_SYNC falls. Depending length program, continue running until ADC5 conversion. opcodes constructed ensure that code passes consume exactly same number cycles. result each conversion inserted into DRAM when conversion complete. code must written tolerate sudden changes data. exact count when each value loaded into DRAM shown Figure Figure also shows that serial data streams, Rand SSI, begin transmitting beginning MUX_SYNC. RTM, consisting cycles, will always finish before next code pass starts. port begins transmitting same time RTM, significantly overrun next code pass large block data required. Neither port will affected this overlap.
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SEPTEMBER 2004 Figure Timing relationship between MUX, Serial Transfers.
Frame
TIMING
CK32 MUX_SYNC STATE EXECUTION ADC0
MUX_DIV Conversions (MUX_DIV=6 shown)
Settle
ADC1
ADC2
ADC3 1200
ADC4 1500
ADC5 1800
TIMING
CE_EXECUTION CE_BUSY XFER_BUSY
COUNT CE_CYCLES floor(CE_CYCLES
COUNT
INITIATED OPCODE INTERVAL
Rand TIMING
RSSI LAST TRANSFER DIMENSIONS 5MHZ COUNTS. PRECISE FREQUENCY 150*CRYSTAL FREQUENCY 4.9152MHz. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS SUM_CYCLES) CODE PASSES.
NOTES:
BEGIN TRANSFER
Fault Reset Behavior Reset Mode: When RESETZ pulled low, digital activity chip stops. exceptions oscillator module which continue run. Additionally, bits cleared. long VBIAS, internal 2.5v regulator will continue provide power digital section. Once initiated, reset mode will persist until reset timer times out, signified WAKE rising. This will occur 4100 cycles real time clock, which time will begin executing preboot boot sequences from address security section more description preboot boot.
Power Fault Circuit: input connected power fault detection circuitry. output power fault detection circuit controls WAKE FAULTZ signals. Upon power fault, WAKE FAULTZ both lowered immediately stop engage battery backup circuit DRAM. When power fault ends, FAULTZ rises immediately disengages battery backup. remains reset will start until 4100 clocks later, when WAKE rises. delay before asserting WAKE permits settle.
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SEPTEMBER 2004 Battery Operation/Power Save Modes With V3P3 down, external battery will power following parts 71M6511 V2P5 internal voltage:
Crystal oscillator circuitry XRAM WD_OVF
normal mode operation, running 3.3V supply, various resources device shut down firmware order reduce power consumption while other essential resources such UARTs remain active. following list outlines these resources their typical current consumption: Table Power Saving Measures Power Saving Measure Disable Disable Disable clock test output CKTEST Disable emulator clock flash read pulse timing Disable voltage boost circuitry Disable Routputs Disable output Select DGND multiplexer input Disable reference voltage output Reduce clock Software Control CE_EN ADC_DIS CKOUTDIS ECK_DIS FLASH66Z LCD_BSTEN RTM_EN SSI_EN TMUX[3:0] VREF_DIS MPU_DIV 0.4mA Typical Savings 0.16mA 1.8mA 0.6mA 0.1mA 0.04mA 0.9mA 0.01mA
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SEPTEMBER 2004 Watchdog Timer addition basic watchdog timer included 80515, independent, robust, fixed duration, watchdog timer (WD) included device. uses crystal oscillator timebase requires firmware reset every seconds. When overflow occurs, part momentarily reset RESETZ were pulled half crystal oscillator cycle. Thus, 4100 cycles later, will launched from address status bit, WD_OVF, when overflow occurs. This powered supply read when WAKE rises determine part initializing after overflow event after power After read, firmware must clear WD_OVF. WD_OVF cleared RESETZ watchdog timer also includes oscillator check. crystal oscillator stops slows down, WD_OVF system reset will performed when crystal oscillator resumes. There internal digital state that deactivates debug purposes, however, disabled tying V3P3. course, this also deactivates power fault detection. Since there firmware disable crystal oscillator guaranteed that whatever state part might find itself upon watchdog overflow, part will reset known state. normal operation, reset periodically writing WDT_RST bit. watchdog timer also reset when WAKE=0 when command received from ICE.
Program Security When enabled, security feature limits global flash erase only. other operations blocked. This guarantees security user's program code. Security enabled code that executed cycle preboot interval before primary boot sequence begins. Once security enabled, only disable perform global erase flash, followed chip reset. Global flash erase also clears program RAM. first cycles boot code called preboot because happens while inhibited. read-only status bit, PREBOOT, identifies these cycles MPU. Upon completion preboot, enabled permitted take control MPU. SECURE, security enable bit, reset whenever chip reset. Hardware associated with permits only ones written Thus, preboot code SECURE enable security feature reset Once SECURE set, preboot code protected external read program code possible Specifically, when SECURE set: limited bulk flash erase only. Page zero flash memory, preferred location user's preboot code, page-erased either ICE. Page zero only erased with global flash erase. Note that global flash erase erases program whether SECURE not. Writes page zero, whether inhibited.
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SEPTEMBER 2004 Voltage Reference Initial Calibration: internal voltage reference calibrated during device manufacture. Trim data stored on-chip fuses accessible user. Temperature Compensation: internal voltage reference predictable temperature dependency that, compensated, result measurement errors. fuse registers, TRIMBGA TRIMBGB used implement temperature compensation. VREF calculated from where (TRIMBGB TRIMBGA)/10. TRIMBGA TRIMBGB read first writing either TRIMSEL (20FD) then reading value TRIM (20FF). compensates temperature variation reference, along with other system components such crystal input attenuators, reading temperature output modifying gain constants accordingly.
Meter Calibration TDK71M6511 power meter device calibrated current sensors, voltage dividers signal conditioning component tolerances. device calibrated using gain phase adjustment factors. gain adjustment used compensate tolerances components used signal conditioning, especially resistive components. Phase adjustment provided compensate phase shifts introduced current sensors. readings (Reading1 Reading below directly available on-chip 80515 through used perform calibration. Alternatively, readings obtained from pulse generator described procedure below. Calibration Procedure: Typically, meter calibrator used apply calibrated load, e.g. 240V 30A, while interfacing voltage current sensors 71M6511. This load should result observable pulse rate WPULSE output depending selected energy pulse. example, 7.2kW will result pulse rate corresponding 7200Wh/3600s 2Wh/s. Apply load rated voltage, test current phase angle record instantaneous values (reading Apply load rated voltage, test current phase angle record instantaneous values (reading Apply load rated voltage, test current phase angle lead record instantaneous values (reading Apply load rated voltage, test current phase angle 1800 lead record instantaneous values (reading Calibration Calculations: accuracy performance each step above calculated. Desired performance always assumed 100%. corresponding terms ERR60, ERR300, ERR0 ERR180 derived percentage error from desired accuracy 100%. spreadsheet provided site ease calibration. Alternatively, calibration coefficients determined using formulae below.
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SEPTEMBER 2004 Formulae Phase Gain Adjust: calibration constants CAL_I CAL_V determined G_CORR CAL_ADJ P_CORR ANG_ERR P_ADJ CAL_I CAL_V P_ADJ CAL_I -0.5 (ERR0 ERR180) 16384 SQRT GCORR_x/100) -0.5 ((ERR60 ERR300) 0.005 (ERR0 ERR180))) ACOS(0.5 (P_CORR/100))) RADIANS(60) 0.02229 TAN(-ANG_ERR) (0.1487 0.0131 TAN(-ANG_ERR)) 16384 SQRT(1 (G_CORR/100)) 0.0155 TAN(-ANG_ERR) (0.1241 0.009695 TAN(-ANG_ERR)) CAL_ADJ SQRT(1 (18.5 P_ADJ 0.91
60Hz
CAL_ADJ SQRT(1 (2.5 10-8 P_ADJ 0.91 10-12 P_ADJ2) 0.0223) 60Hz 50Hz
P_ADJ 0.0155) 50Hz
Calibration Example: meter performed test degree phase angle with accuracy 98.15%. Therefore, ERR60 (98.15 100) -1.85. Assume, tests were repeated other angles yielded errors ERR300 -1.55, ERR0 -1.69, ERR180 -1.71. applying these values obtain: Calibration Example: 60Hz meter performed test degree phase angle with accuracy 98.15%. Therefore, ERR60 (98.15 100) -1.85. Assume, tests were repeated other angles yielded errors ERR300 -1.55, ERR0 -1.69, ERR180 -1.71. applying these values obtain: G_CORR CAL_ADJ P_CORR ANG_ERR P_ADJ CAL_I CAL_V -0.5 (-1.69 -1.71) 16384 SQRT 1.7/100) 16522.7 -0.5 (-1.85 (-1.55)) 0.005 (-1.69 (-1.71))) 0.152594 ACOS(0.5 (-0.2134/100))) 1.047198 0.000881 (0.02229 TAN(-0.000881)) (0.1487 (0.0131 TAN(-0.000881))) -138 CAL_ADJ SQRT(1 (2.5 10-8 (-138) 10-13 (-138)2) 0.0223) 16523.95 16384*(SQRT(1+(1.7 100))) 16522.7
CAL_I, CAL_V P_ADJ rounded nearest integer values, 16524, 16523, -138. calibration factors first loaded test accuracy meter. permanent calibration, calibration factors written Flash memory external EEPROM.
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SEPTEMBER 2004 DESCRIPTION Alphabetical Order Bits with (write) direction written into configuration RAM. Typically, they initially stored flash memory copied configuration MPU. Some more frequently programmed bits mapped memory space. remaining bits mapped 2xxx. Bits with (read) direction read MPU. power bits cleared zero unless otherwise stated. NAME ADC_DIS CE_EN CHOP_EN[1:0] RESERVED CKOUT_DIS RESERVED DIO_R4[2:0] DIO_R5[2:0] DIO_R6[2:0] DIO_R7[2:0] DIO_R8[2:0] DIO_R9[2:0] DIO_R10[2:0] DIO_R11[2:0] LOCATIO 2005[3] 2000[4] 2002[5:4] 2004[5] 2004[4] 2003[4:3] 200B[2:0] 200B[6:4] 200C[2:0] 200C[6:4] 200D[2:0] 200D[6:4] 200E[2:0] 200E[6:4] DESCRIPTION Disables removes bias current enable. Chop enable reference band circuit. 00-enabled Must CKOUT Disable. When zero, CKTEST active output. Must Connects dedicated pins internal resources. more than input connected same resource, `MULTIPLE' column below specifies they combined.
DIO_GP Resource MULTIPLE
01-disabled
10-disabled
11-enabled
NONE Reserved (Timer0 clock gate) (Timer1 clock gate) High priority interrupt (int0 rising) priority interrupt (int1 rising) High priority interrupt (int0 falling) priority interrupt (int1 falling)
RESERVED RESERVED
2009.200A SFRA2[3:0]
Must 0000. Must 1111.
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DIO_DIR0[7:4]
SFRA2[7:4]
Programs direction pins through indicates output. Ignored configured I/O. DIO_PV DIO_PW special option DIO_6 DIO_7 outputs. DIO_EEX special option DIO_4 DIO_5. Note: must Programs direction pins through indicates output. Ignored configured I/O. Note: must Programs direction pins indicates output. Ignored configured I/O. Note: must value pins. Pins configured will read zero. When written, changes data pins configured outputs. Pins configured input will ignore writes.
DIO_DIR1[7:6] DIO_DIR1[3:0] DIO_DIR2[1:0]
SFR91
SFRA1[5:0]
DIO_0[7:4] DIO_1[7:6], DIO_1[3:0] DIO_2[1:0] DIO_EEX
SFR80 SFR90
SFRA0[1:0] 2008[4] When set, converts DIO_4 DIO_5 interface with external EEPROM. DIO_4 becomes SDCK DIO_5 becomes bidirectional SDATA. LCD_NUM must less than Causes VARPULSE output DIO_7, DIO_7 configured output. LCD_NUM must less than Causes WPULSE output DIO_6, DIO_6 configured output. LCD_NUM must less than Serial EEPROM interface data Serial EEPROM interface control Emulator clock disable. When one, emulator clock disabled. Specifies power equation. Interrupt enable bits. These bits enable XFER_BUSY RTC_1SEC interrupts. Note that either interrupt enabled, 80515 must also set. length decimation filter. bits/3 CK32 cycles bits/2 CK32 cycles
DIO_PV DIO_PW EEDATA[7:0] EECTRL[7:0] ECK_DIS EQU[2:0] EX_XFR EX_RTC FIR_LEN
2008[2] 2008[3] SFR9E SFR9F 2005[5] 2000[7:5] 2002[0] 2002[1] 2005[4]
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FLASH66Z FLSH_ERASE
2005[1] SFR94
Should minimize power supply current. Flash Erase Initiate FLSH_ERASE used initiate either Flash Mass Erase cycle Flash Page Erase cycle. Specific patterns expected FLSH_ERASE order initiate appropriate Erase cycle. (default 0x00). 0x55 Initiate Flash Page Erase cycle. Must proceeded write FLSH_PGADR 0xB7. 0xAA Initiate Flash Mass Erase cycle. Must proceeded write FLSH_MEEN 0xB2 debug (CC) port must enabled. other pattern written FLSH_ERASE will have effect.
FLSH_MEEN
SFRB2[1]
Mass Erase Enable Mass Erase disabled (default). Mass Erase enabled. Must re-written each Mass Erase cycle.
FLSH_PGADR
SFRB7[7:1]
Flash Page Erase Address FLSH_PGADR[6:0] Flash Page Address (page thru 127) that will erased during Page Erase cycle. (default 0x00). Must re-written each Page Erase cycle.
FLSH_PWE
SFRB2[0]
Program Write Enable MOVX commands refer External Space, normal operation (default). MOVX @DPTR,A moves External Program Space (Flash) DPTR. This automatically reset after each byte written flash. Writes this inhibited when interrupts enabled.
IE_XFER IE_RTC
SFRE8[0] SFRE8[1]
Interrupt flags. These flags monitor XFER_BUSY interrupt RTC_1SEC interrupt. flags hardware must cleared interrupt handler. Note that IE6, interrupt flag 80515 must also cleared when either these interrupts occur. Interrupt inputs. read these bits input external interrupts INT0, INT1, INT6. These bits have memory primarily intended debug use. Enables voltage boost circuit.
INTBITS
SFRF8[6:0]
LCD_BSTEN
2020[7]
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SEPTEMBER 2004 LCD_CLK[1:0] 2021[1:0] Sets clock frequency. Note: CKADC/128 00-fw/2^9, 01-fw/2^8, 10-fw/2^7, 11-fw/2^6 LCD_EN LCD_FS[4:0] LCD_MODE[2:0] 2021[5] 2022[4:0] 2021[4:2] Enables display. When disabled, VLC2, VLC1, VLC0 ground outputs. full scale voltage, VLC2. (0.7 VLCD) VLCD bias mode: 000-4 states, bias 001-3 states, bias 010-2 states, bias 011-3 states, bias 100-static display LCD_NUM[4:0] 2020[4:0] Controls number dual-purpose LCD/DIO pins configured LCD. LCD_NUM will between first dual-purpose allocated SEG37/DIO17. table below lists which functions selected each LCD_NUM value. LCD_NUM 8-10 None SEG37 SEG36-37 SEG35-37 SEG34-37 SEG34-37, SEG31 SEG34-37, SEG30-31 SEG34-37, SEG29-31 SEG34-37, SEG28-31 SEG34-37, SEG27-31 SEG34-37, SEG26-31 SEG34-37, SEG25-31 SEG34-37, SEG24-31 DIO4-11, DIO14-17 DIO4-11, DIO14-16 DIO4-11, DIO14-15 DIO4-11, DIO14 DIO4-11 DIO4-10 DIO4-9 DIO4-8 DIO4-7 DIO4-6 DIO4-5 DIO4 None
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SEPTEMBER 2004 LCD_SEG0[3:0]LCD_SEG19[3:0], LCD_SEG24[3:0]LCD_SEG31[3:0], LCD_SEG34[3:0]LCD_SEG37[3:0], MPU_DIV[2:0] 2030[3:0]2043[3:0], 2048[3:0]204f[3:0], 2052[3:0]2055[3:0] 2004[2:0] clock divider (from CKCE). These bits programmed without risk losing control. 000-CKCE, 001-CKCE/2, 111-CKCE/27 MUX_ALT MUX_DIV[1:0] MUX_E OPT_TXDIS PREBOOT PRE_SAMPS[1:0] 2005[2] 2002[7:6] 2005[0] 2008[5] SFRB2[7] 2001[7:6] asserts this when wishes perform conversions alternate inputs. number states input mux. 00-6 states 10-3 states 11-2 states 01-4 states Segment Data. Each word contains information from time divisions each segment. each word, corresponds COM0, COM3.
MUX_SYNC enable. When high, converts SEG7 into MUX_SYNC output. Tristates OPT_TX output. Indicates that preboot sequence active. Together SUM_CYCLES, this value determines number samples cycle between XFER interrupts. Number cycles PRE_SAMPS*SUM_CYCLES. 00-42, 01-50, 10-84, 11-100 interface. These `year', `month', `day', `hour', `minute' `second' parameters RTC. writing these registers. Year defined leap year. (00=Midnight) (01=Sunday)
RTC_SEC[5:0] RTC_MINI[5:0] RTC_HR[4:0] RTC_DAY[2:0] RTC_DATE[4:0] RTC_MO[3:0] RTC_YR[7:0]
2015 2016 2017 2018 2019 201A 201B
DATE
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RTC_DEC_SEC RTC_INC_SEC
201C[1] 201C[0]
time correction bits. Only pulsed time. When pulsed, causes time value incremented decremented) additional second next time RTC_SEC register clocked. pulse width value. additional correction desired, must wait seconds before pulsing bits again. Real Time Monitor enable. When `0', Routput low. This enables wire version RFour Rprobes. Before each code pass, values these registers serially output Rpin. Rregisters ignored when RTM_EN=0.
RTM_EN RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] SECURE
2002[3] 2060 2061 2062 2063 SFRB2[6]
Enables security provisions that prevent external reading flash memory program RAM. This reset chip reset only set. Attempts write zero ignored. Enables Synchronous Serial Interface (SSI) SEG3, SEG4, SEG5 pins. SSI_RDYEN set, SEG6 enabled also. pins take functions SCLK, SSDATA, SFR, SRDY, respectively. When SSI_EN high LCD_EN low, these pins converted function, regardless LCDEN LCD_NUM. proper operation, SSI_EN must high when LCD_EN high. clock speed: 0-5MHz 1-10MHz gated clock enable. When low, SCLK continuous. When high, clock held when data being transferred. frame pulse format: 0-once beginning sequence. 1-every bits. 2-every bits. 3-every bits. pulse polarity: 0-positive 1-negative SRDY enable. SSI_RDYEN SSI_EN high, SEG6 configured SRDY. Otherwise, driver. SRDY polarity: 0-positive 1-negative beginning ending address transfer region data memory. Synchronous Serial Interface enabled, block words starting with SSI_BEG ending with SSI_END will sent. SSI_END must equal larger than SSI_BEG. maximum number output words limited number clocks code pass-see FIR_LEN, MUX_DIV, SSI_10M.
SSI_EN
2070[7]
SSI_10M SSI_CKGATE
2070[6] 2070[5]
SSI_FSIZE[1:0] SSI_FPOL SSI_RDYEN SSI_RDYPOL SSI_BEG[7:0] SSI_END[7:0]
2070[4:3] 2070[2] 2070[1] 2070[0] 2071[7:0] 2072[7:0]
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SEPTEMBER 2004 SUM_CYCLES [5:0] TMUX[3:0] 2001[5:0] Together PRE_SAMPS, this value determines number samples cycle between XFER interrupts. Number cycles PRE_SAMPS*SUM_CYCLES. Selects inputs TMUXOUT. DGND (analog) IBIAS (analog) PLL_2.5v (analog) VBIAS (analog) R(Real time output from WDTR_EN (Comparator Output V1LT3) Reserved Reserved (from Optical interface) MUX_SYNC (from MUX_CTRL) CK_10M CK_MPU PULSE_OUT RTCLK CE_BUSY XFER_BUSY RESERVED VERSION[7:0] VREF_CAL VREF_DIS WD_RST WD_OVF 2005[7] 2006 2004[7] 2004[3] SFRE8[7] 2002[2] Must Zero. silicon revision number. This data sheet does apply revisions 0010. Makes voltgae reference available VREF pin. This feature disabled when VREF_DIS=1. Disables internal voltage reference. Reset timer. reset when written this bit. overflow status bit. This when timer overflows. powered supply bootup will indicate part recovering from overflow power fault. This should cleared bootup. also automatically cleared when RESETZ low.
2000[3:0]
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SEPTEMBER 2004 Ordered Function `Not Used' bits blacked-out following table, contain memory read zero. RESERVED bits should changed.
Name
Addr
Configuration: 2000 EQU[2:0] CE_EN TMUX[3:0] 2001 PRE_SAMPS[1:0] SUM_CYCLES[5:0] 2002 MUX_DIV[1:0] CHOP_EN[1:0] RTM_EN WD_OVF EX_RTC EX_XFR COMP0 2003 RESERVED RESERVED CONFIG0 2004 VREF_CAL RESERVED CKOUT_DIS VREF_DIS MPU_DIV CONFIG1 2005 RESERVED ECK_DIS FIR_LEN ADC_DIS MUX_ALT FLSH66Z MUX_E VERSION 2006 VERSION[7:0] Digital I/O: DIO0 2008 OPT_TXDIS DIO_EEX DIO_PW DIO_PV DIO1 2009 RESERVED RESERVED DIO2 200A RESERVED RESERVED DIO3 200B DIO_R5[2:0] DIO_R4[2:0] DIO4 200C DIO_R7[2:0] DIO_R6[2:0] DIO5 200D DIO_R9[2:0] DIO_R8[2:0] DIO6 200E DIO_R11[2:0] DIO_R10[2:0] DIO7 SFR80 DIO_0[7:4] RESERVED DIO8 SFRA2 DIO_DIR0[7:4] 1111 DIO9 SFR90 DIO_1[7:6] RESERVED DIO_1[3:0] DIO10 SFR91 DIO_DIR1[7:6] DIO_DIR1[3:0] DIO11 SFRA0 RESERVED DIO_2[1:0] DIO12 SFRA1 1111 DIO_DIR2[1:0] Interrupts Timer: INTBITS SFRF8 INT6 INT5 INT4 INT3 INT2 INT1 INT0 SFRE8 WD_RST IE_RTC IE_XFER Flash: ERASE SFR94 FLSH_ERASE[7:0] FLSHCTL SFRB2 PREBOOT SECURE FLSH_MEEN FLSH_PWE PGADR SFRB7 FLSH_PGADR[6:0] Real Time Clock: RTC0 2015 RTC_SEC[5:0] RTC1 2016 RTC_MIN[5:0] RTC2 2017 RTC_HR[4:0] RTC3 2018 RTC_DAY[2:0] RTC4 2019 RTC_DATE[2:0] RTC5 201A RTC_MO[3:0] RTC6 201B RTC_YR[7:0] RTC_DEC_SEC RTC_INC_SEC RTC7 201C Display Interface: LCDX 2020 LCD_BSTEN LCD_NUM[4:0] LCDY 2021 LCD_EN LCD_MODE[2:0] LCD_CLK[1:0] LCDZ 2022 LCD_FS[4:0] RESERVED:SEG20-23,32-33,38-41
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LCD0 LCD1 LCD19 LCD20 LCD21 LCD22 LCD23 LCD24 LCD25 LCD26 LCD27 LCD28 LCD29 LCD30 LCD31 LCD32 LCD33 LCD34 LCD35 LCD36 LCD37 LCD38 LCD39 LCD40 LCD41 RTM0 RTM1 RTM2 RTM3 2030 2031 2043 2044 2045 2046 2047 2048 2049 204A 204B 204C 204D 204E 204F 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 SSI_EN LCD_SEG0[3:0] LCD_SEG1[3:0] LCD_SEG19[3:0] RESERVED RESERVED RESERVED RESERVED LCD_SEG24[3:0] LCD_SEG25[3:0] LCD_SEG26[3:0] LCD_SEG27[3:0] LCD_SEG28[3:0] LCD_SEG29[3:0] LCD_SEG30[3:0] LCD_SEG31[3:0] RESERVED RESERVED LCD_SEG34[3:0] LCD_SEG35[3:0] LCD_SEG36[3:0] LCD_SEG37[3:0] RESERVED RESERVED RESERVED RESERVED
2070 SSI_BEG 2071 SSI_END 2072 EEDATA SFR9E EECTRL SFR9F
RProbes: RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] Synchronous Serial Interface: SSI_10M SSI_CKGATE SSI_FSIZE[1:0] SSI_BEG[7:0] SSI_END[7:0] Serial EEPROM: EEDATA[7:0] EECTRL[7:0]
SSI_FPOL
SSI_RDYEN
SSI_RDYPOL
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SEPTEMBER 2004 Data Memory words bytes. Unless specified otherwise, they 32-bit two's complement. `Calibration' parameters defined flash memory copied memory before enabling `Internal' variables used internal calculations. `Input' variables allow control behavior code. `Output' variables outputs calculations. data memory mapped address space shown column. address most significant byte. Constants used Data Memory table are: 32768 2520.6 fundamental frequency. IMAX external current corresponding 250mV inputs VMAX external voltage corresponding 250mV input Accumulation time energy measurements PRE_SAMPS*SUM_CYCLES/FS. ADDRESS
NAME
DESCRIPTION
Input Data: I_RAW 1000 V_RAW 1004 I1_RAW3 1008 Input data from ADC, valid frame. These addresses RESERVED 100C hard-wired converter circuit. RESERVED 1010 RESERVED 1014 TEMP 1018 RESERVED 101C Calibration Parameters: (Assignments address higher describe code hardwired) CAL_I0 1020 These constants control gain their respective channels. CAL_V0 1024 nominal value each parameters 214=16384. gain CAL_I1 1028 each channel directly proportional parameter. Thus, RESERVED 102C gain channel slow, should increased RESERVED 1030 RESERVED PHADJ_0 PHADJ_1 RESERVED TEMP_NOM 1034 1038 103C 1040 1044 These constants control phase compensation. compensation occurs when PHADJ=0. PHADJ increased, more compensation introduced. TEMP_RAWX reading calibration temperature
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SEPTEMBER 2004 Input Data: I0SHUNT I1SHUNT WRATE RESERVED QUANT RESERVED SAG_THR SAG_CNT RESERVED QUANT_VAR QUANT_I SUMPRE EXT_PULSE RESERVED RESERVED RESERVED RESERVED APULSEW
10AC 10B0 10B4 10B8 10BC 10C0 10C4 10C8 10CC 10D0 10D4 10D8 10DC 10E0 10E4 10E8 10E8 116C
When positive, gain applied channel When positive, gain applied channel IMAX*VMAX*0.018706/WRATE Wh/pulse. Default 16384. Compensation truncation code. Default inputs must above this threshold prevent alarms. 2.35*10-9 VMAX Volts. Default 26000. Number consecutive voltage samples below SAG_THR before alarm declared. Default Compensation truncation calculation. Default Compensation truncation calculation. Product PRE_SAMPS SUM_CYCLE. Default 2520. Should When zero, causes pulse generators respond WSUM_X VARSUM_X. Otherwise, they respond values host places APULSEW APULSER. Default (host driven).
APULSER
1170
Watt pulse generator input (see DIO_PW bit). Output pulse rate APULSEW*FS*2-32*WRATE*2-14. This input buffered loaded during computation interval will take effect beginning next interval. Default value pulse generator input (see DIO_PV bit). Output pulse rate APULSER*FS*2-32*WRATE*2-14. This input buffered loaded during computation interval will take effect beginning next interval. Default value
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SEPTEMBER 2004 Outputs: TEMP_X FREQ_X RESERVED W0SUM_X W1SUM_X RESERVED VARSUM_X VAR0SUM_X VAR1SUM RESERVED I0SQSUM_X I1SQSUM_X RESERVED RESERVED V0SQSUM_X RESERVED RESERVED RESERVED RESERVED TEMP_RAW_X
1100 1104 1108 110C 1110 1114 1118 111C 1120 1124 1128 112C 1130 1134 1138 113C 1140 1148 114C 1168
Deviation from Calibration temperature. Fundamental frequency.
0.587
Watt samples from each wattmeter element. 6.6972*10-13 VMAX IMAX signed sum: VAR0SUM_X samples from each wattmeter element. 6.6972*10-13 VMAX IMAX squared current samples from each element. 6.697210-13 IMAX2 squared voltage samples from each element. LSB= 6.6972*10-13 VMAX2
Filtered, unscaled reading from temperature sensor. This value should written TEMP_NOM during meter calibration.
Status: Status Word
1144
This word contains warnings phase well derived clock operating fundamental input frequency. STATUS Word contains information about events that occurred during immediately preceding code pass.
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SEPTEMBER 2004 Internal Data: First Address Last Address Status Word: Status Word minimizes computation required interrupt handler (CE_BUSY interrupt occurs 2520.6Hz). contains warnings phase well derived clock operating fundamental input frequency. STATUS word contains information about events that occured during immediately preceding code pass.
1174 13FC
First memory location Last memory location
31-29 24-0
NAME Used RESERVED RESERVED SAG_A Used
DESCRIPTION These unused bits will always zero. square wave exact fundamental input frequency.
Normally zero. Becomes when remains below SAGTHR SAGCNT samples. Will return zero until rises above SAG_THR. These unused bits will always zero.
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SEPTEMBER 2004 Data Memory (XRAM) NAME First Address Last Address ADDRESS 0000 0xxx 07FF TYPE DESCRIPTION First XRAM location Last internal XRAM location
Certain XRAM parameters have been given fixed addresses order permit easy external modification meter behavior. These parameters loaded startup should need adjustment during meter calibration. These parameters defined implemented code.
Input Parameters: Word Name Address Address
Description each element, WSUM_X VARSUM_X that element exceeds CREEP_THR, sample values that element zeroed. Otherwise, accumulators VARh, updated instantaneous value IRMS that element zeroed. 6.69722*10-13 VMAX IMAX Sets calculation mode.
CREEP_THR
CONFIG
0-VRMS*ARMS
Clears accumulators VARh, VAh. This need reset. PK_VTHR When voltage exceeds this value, might choose warning. Event logs implemented `demo' code. LSB=0.1VRMS When current exceeds this value, might choose warning. Event logs implemented `demo' code. LSB=0.1ARMS values these locations implement trim using following formula:
PK_ITHR Y_CAL Y_CALC Y_CALC2
CORRECTION( ppm)
CALC CALC 1000
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SEPTEMBER 2004 PULSEW source PULSER source. Values are: WSUM W0SUM W1SUM W2SUM VARSUM VAR0SUM VAR1SUM VAR2SUM I0SQSUM I1SQSUM I2SQSUM INSQSUM V0SQSUM V1SQSUM V2SQSUM VASUM VA0SUM VA1SUM VA2SUM
PULSEW_SRC PULSER_SRC
VMAX
nominal external voltage that corresponds 250mV input. meter uses this value convert internal quantities external. LSB=0.1V nominal external current that corresponds 250mv input. meter uses this value convert internal quantities external. LSB=0.1A PPM/C*26.84. Linear temperature compensation. positive value will cause meter faster when hot. This applied both will therefore have double effect products. Default PPM/C2*1374. Square compensation. positive value will cause meter faster when hot. This applied both will therefore have double effect products. Default Scale factor TEMP_X. TEMP_NOM). Default 9879.
IMAX
PPMC
PPMC2
DEGSCALE
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SEPTEMBER 2004 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Supplies Ground Pins: V3P3D, V3P3A VLCD VBAT GNDD Analog Output Pins: VREF, VBIAS V2P5 Analog Input Pins: XIN, XOUT OPT_RX Other Pins: other pins Operating junction temperature (peak, 100ms) Operating junction temperature (continuous) Storage temperature Solder temperature second duration -0.5V 4.6V -0.5V -0.5V 4.6V -0.5V +0.5V -1mA 1mA, -0.5V V3P3A+0.5V -1mA 1mA, -0.5V 3.0V -0.5V V3P3A+0.5 -0.5V 3.0V -1mA -0.5V V3P3D+0.5V
Stresses beyond Absolute Maximum Ratings cause permanent damage device. These stress ratings only functional operation these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. voltages with respect GNDA. RECOMMENDED EXTERNAL COMPONENTS NAME XTAL CBIAS CBST1 CBST2 FROM V3P3A V3P3D XOUT VBIAS VDRV VLCD AGND DGND XOUT AGND AGND AGND external DGND FUNCTION Bypass capacitor 3.3V supply Bypass capacitor 3.3V supply 32.768kHz crystal. Electrically similar Ecliptek (www.ecliptek.com) ECPSM310T series Load capacitor crystal (depends crystal specs board parasitics). Load capacitor crystal (depends crystal specs board parasitics). Bypass capacitor VBIAS Boost charging capacitor Boost bypass capacitor VALUE 0.1±20% 0.1±20% 32.768 10±10% 10±10% 1000±20% 33±20% 0.22±20% UNIT
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SEPTEMBER 2004 RECOMMENDED OPERATING CONDITIONS PARAMETER 3.3V Supply Voltage (V3P3A, V3P3D) VLCD VBAT Operating Temperature Battery Battery Backup CONDITION Normal Operation Battery Backup UNIT 3.45 Externally Connect V3P3D
PERFORMANCE SPECIFICATIONS LOGIC LEVELS PARAMETER Digital high-level input voltage, Digital low-level input voltage, Digital high-level output voltage Digital low-level output voltage Input pull-up current, RESETZ E_RXTX, CKTEST E_RST Other digital inputs Input pull down current, TEST Other digital inputs CONDITION -0.3 V3P3D -0.4 V3P3D -0.6 V3P3D V3P3D UNIT
ILOAD ILOAD 15mA ILOAD ILOAD 15mA VIN=0V
VIN=V3P3D
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SEPTEMBER 2004 SUPPLY CURRENT PARAMETER V3P3A V3P3D VLCD current V3P3A current V3P3D current VLCD current VBAT current V3P3A V3P3D current V3P3D current, Write Flash VBAT current, VBAT=3.6V VREF, VBIAS Unless otherwise specified, VREF_DIS=0 PARAMETER CONDITION 1.193 1.195 1.197 VREF output voltage, VNOM(25) VREF chop step VREF output impedance ILOAD 10µA, -10µA VNOM(T) VREF(22) (T-22)TC1 (T-22) VNOM definition TRIMBGA TRIMBGB available (6511H) -VREF temperature coefficients TRIMBGB- TRIMBGA 14.95x 0.0174x 0.307 VREF(T) deviation from VNOM(T) VREF(T VNOM VNOM max(| |,40) (For 71M6511H version only) TRIMBGA TRIMBGB available (6511) -VREF temperature coefficients -6.68 -0.341 VREF(T) deviation from VNOM(T) VREF(T VNOM VNOM max(| |,40) (For 71M6511H version only) (-1%) (+1%) VBIAS output voltage (-2%) (+2%) ILOAD 1mA, -1mA VBIAS output impedance This relationship describes nominal behavior VREF different temperatures. UNIT CONDITION Normal Operation, V3P3A=V3P3D=VLCD=3.3V CKMPU=614kHz VBAT=3.6V Flash memory write Power save/sleep mode V3P3A=V3P3D=VLCD=3.3V Normal Operation above, except write Flash maximum rate. Battery backup, V3P3A=V3P3D=VLCD=0V 7.89 0.04 -300 8.74 4.79 0.05 10.4 UNIT
ppm/°C2
ppm/°C
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SEPTEMBER 2004 2.5V VOLTAGE REGULATOR Unless otherwise specified, load PARAMETER Voltage overhead V3P3-V2P5 PSSR V2P5/V3P3 COMPARATORS PARAMETER Offset Voltage V1-VBIAS Hysteresis Current Response Time Disable Threshold (V1-V3P3A) FLASH MEMORY TIMING PARAMETER Write Time Byte Read Time: wait states Page Erase (512 bytes) Mass Erase CONDITION UNIT CONDITION VBIAS 100mV +100mV overdrive -400 UNIT CONDITION Reduce V3P3 until V2P5 drops 200mV ResetZ=1, iload=0 UNIT mV/V
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SEPTEMBER 2004 CONVERTER, REFERENCED FIR_LEN=0, VREF_DIS=0, VDDREFZ=0 PARAMETER Recommended Input Range (Vin-V3P3A) Voltage Current Crosstalk: CONDITION -250 200mV peak, 65Hz, µV/V UNIT peak
*Vcrosstalk cos(Vin Vcrosstalk Vcrosstalk largest measurement (First harmonics) Vin=65Hz, 250mV-pk 64kpts FFT, Blackman20mV-pk Harris window Input Impedance Vin=65Hz size Digital Full Scale Gain Error %Power Supply Variation Vin=200mV 65Hz Nout V3P3A=3.0V, 3.6V
+884736
nV/LSB ppm/
Input Offset (Vin-V3P3A) CRYSTAL OSCILLATOR Crystal disconnected. Test load series 200pF, 100k connected between DGND XOUT. PARAMETER CONDITION UNIT Vin=32.8kHz, 10mV-pp sin, (µmho) Transconductance measure voltage mV-pp across 100k Vin=0V 0.1V step Bias Settling Time, 0.05 CL20pF I(XOUT) when 0.25 Peak Output Source Current XOUT=0V Vin=0.2V-pp wave, Maximum Output Voltage 32.8kHz, test load Maximum Output Power Crystal4 Crystal connected Xout Capacitance1 Capacitance DGND1 Xout Watchdog RTC_OK threshold
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SEPTEMBER 2004 OPTICAL INTERFACE PARAMETER OPT_TX (V3P3D-OPT_TX) OPT_TX OPT_RX Threshold (VinRISING+VinFALLING)/2 OPT_RX Hysteresis (VinRISING-VinFALLING) OPT_RX input impedance CONDITION ISOURCE=1mA ISINK=20mA UNIT
|Vin|300mV
TEMPERATURE SENSOR PARAMETER Nominal Sensitivity (Sn)4 Nominal Offset (Nn) Temperature Error
CONDITION Nominal relationship: N(T)= Sn*T+Nn
-923 428500
UNIT
(25))
BOOST PARAMETER VDRV Frequency VDRV Sink Current VDRV Source Current VLCD Target Voltage VLCD Input Current CONDITION Vol=1.5V Voh=1.5V VLCD=5.0V, LCD_FS=1F, LCD_MODE=0,1,2,3 OSC/2 UNIT
DRIVERS Applies pins. Unless otherwise stated, VLCD=5.0V, LCD_FS=1F CONDITION PARAMETER VLC0 Voltage (LCD_FS =1F) With respect VLCD -0.2 VLC0 Voltage (LCD_FS =00) With respect VLCD*0.7 -0.2 UNIT
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SEPTEMBER 2004 FOOTNOTES
This spec guaranteed, been verified production samples, measured production. This spec guaranteed, been verified production samples, measured production only This spec measured production limits specified operating temperature.
This spec defines nominal relationship rather than measured parameter. Correct circuit operation verified with other specs that this nominal relationship reference.
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SEPTEMBER 2004 Figure 71M6511H accuracy performance
Test Time when I>3.0A Test Time when I>1.0A
100.6 100.4 100.2 99.8 Must 99.6 99.4 0.01 Light Test 200A
Accuracy
62053-22, ANSI C12.20-1998, class
PH=0 PH=60 PH=0 upper PH=0 lower
Current
1000
Figure Meter Accuracy over Harmonics 240V,
Meter Performance over Harmonics %Error
50Hz Harmonic data 60Hz Harmonic Data
Measured current distortion amplitude voltage distortion amplitude 10%.
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PACKAGE OUTLINE
11.7 12.3
11.7 12.3
Indicator 10.2 0.00 0.20
0.60 Typ.
0.50 Typ.
0.14 0.28
1.40 1.60
NOTE:
CONTROLLING DIMENSIONS
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SEPTEMBER 2004 PINOUT:
E_TCLK
OPT_RX
E_RST
GNDA
V3P3A
VBIAS
GNDD E_RXTX OPT_TX TMUXOUT SEG3/SCLK VDRV CKTEST V3P3D SEG4/SSDATA SEG5/SFR SEG37/DIO17 COM0 COM1 COM2 COM3
GNDA
XOUT
VLCD
TEST
VREF
RESETZ V2P5 VBAT SEG31/DIO11 SEG30/DIO10 SEG29/DIO9 SEG28/DIO8 SEG27/DIO7 SEG26/DIO6 SEG25/DIO5 SEG24/DIO4 SEG19 SEG18 SEG17 SEG16
71M6511-IGT
SEG1
SEG36/DIO16
SEG6/SRDY
SEG7/MUX_SYNC
SEG34/DIO14
SEG35/DIO15
SEG9 SEG10
SEG11
SEG0
SEG2
SEG8
SEG13
SEG12
SEG14
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SEG15
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71M6511/ 71M6511H Power Meter
SEPTEMBER 2004 DESCRIPTIONS Power/Ground Pins: Name GNDA GNDD V3P3A V3P3D VBAT V2P5 VLCD Type Description Analog ground: This should connected directly ground plane. Digital ground: This should connected directly ground plane. Analog power supply: 3.3V power supply should connected this pin. Digital power supply: 3.3V power supply should connected this pin. Battery backup power supply. battery super-capacitor connected between VBAT GNDD. battery used, connect VBAT V3P3D. Output internal 2.5v regulator. connection should made this pin. power supply.
Analog Pins: Name Type Description Line Current Sense Input: This voltage input internal converter. Typically, connected output current transformer. Line Voltage Sense Input: This voltage input internal converter. Typically, connected output resistor divider. Line Current Sense Input: This voltage input internal converter. Typically, connected output current transformer. Comparator Input: This voltage input internal comparator. voltage applied compared internal reference voltage 1.5V. input voltage above reference, comparator output will high (1). comparator output maintained Register Voltage Reference reference voltage used power fault detection circuit. Crystal Inputs: 32kHz style crystal should connected across these pins. Typically, 10pf capacitor also connected from each GNDA. important minimize capacitance between these pins. crystal manufacturer datasheet details. Voltage boost output.
VREF VBIAS XOUT VDRV
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SEPTEMBER 2004 Digital Pins: Name COM3, COM2, COM1, COM0 SEG19.SEG8, SEG2.SEG0 SEG24/DIO4. SEG31/DIO11, SEG34/DIO14. SEG37/DIO17 SEG7/ MUX_SYNC SEG6/SRDY SEG5/SFR SEG4/SDATA SEG3/SCLK CKTEST TMUXOUT OPT_RX OPT_TX pinout pinout Type Description Common Outputs: These pins provide select signals display. Dedicated Segment Output. Multi-use pin, configurable either driver DIO. Multi-use-pin Segment Output/ MUX_SYNC output Synchronous serial interface Multi-use-pin, Segment Outputs/ SRDY input Synchronous serial interface. Multi-use-pin, Segment Output/ output Synchronous serial interface. Multi-use-pin, Segment Output/ SDATA output Synchronous serial interface. Multi-use-pin, Segment Output/ SCLK output Synchronous serial interface. Clock output. enabled disabled CKOUT_EN. Digital output test multiplexor. Controlled DMUX[3:0]. Receive Input: This receives signal from external photo-detect diode used serial interface. Transmit Output: This designed directly drive transmitting data serial interface. tristated with OPT_TXDIS multiplexed with other GPIO pins. Chip reset: This input used reset chip into known state. normal operation, this reset chip, this driven This internal 30µA (nom.) current source pull UART input. UART output. Emulator serial data. Emulator clock. Emulator reset. Enables Production Test. Must grounded normal operation.
RESETZ E_RXTX E_TCLK E_RST TEST
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ORDERING INFORMATION
PART DESCRIPTION 71M6511 LQFP, 0.5% accuracy 71M6511 LQFP Lead Free, 0.5% accuracy 71M6511H LQFP, 0.1% accuracy 71M6511H LQFP Lead Free, 0.1% accuracy
ORDERING NUMBER 71M6511-IGT
PACKAGE MARKING 71M6511-IGT
71M6511-IGT/F
71M6511-IGT/F
71M6511H-IGT
71M6511H-IGT 71M6511HIGT/F
71M6511H-IGT/F
Preliminary Data Sheet: This Preliminary Data Sheet proprietary Semiconductor Corporation (TSC) sets forth design goals described product. data sheet subject change. assumes obligation regarding future manufacture, unless agreed writing. when manufactured sold, this product sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, patent infringement limitation liability. Semiconductor Corporation (TSC) reserves right make changes specifications time without notice. Accordingly, reader cautioned verify that data sheet current before placing orders. assumes liability applications assistance.
Semiconductor Corp., 6440 Canyon, Irvine, 92618 (714) 508-8800, (714) 508-8877, http://www.tdksemiconductor.com
2004 Semiconductor Corporation
9/23/2004
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FEATURES 71M6511 highly integrated with core, RTC, FLASH driver.

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