6-Port JTAG Gateway AS91L1006BU 6-port JTAG gateway. partitions s

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6-Port JTAG Gateway AS91L1006BU 6-port JTAG gateway. partitions s

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AS91L1006BU
6-Port JTAG Gateway
AS91L1006BU 6-port JTAG gateway. partitions single JTAG chain into separate chains. These separate chains optionally configured operate single chain. AS91L1006BU device used provide enhanced capabilities standard IEEE1149.1. enables IEEE1149.1 interface used true Multi-Drop environment without additional signals. This Multi-Drop capability enables standard IEEE1149.1 interface used just stand alone (Printed Circuit Board) testing, also complete system testing including PCBs within system back plane environment. AS91L1006BU provides capability partitioning PCB, into multiple smaller IEEE1149.1 scan chains totally under software control. Partitioning IEEE1149.1 chains several benefits which include easier fault diagnostics capabilities fault IEEE1149.1 Local Scan Ports (LSPs) does render untestable, faster flash programming PCBs, removal IEEE1149.1 signal loading issues. protocols required addressing AS91L1006BU device Multi-Drop capability protocols configuring which IEEE1149.1 LSPs AS91L1006BU used, handled party ATPG tools from vendors like AssetIntertech JTAG Technologies. Multi-Drop environment also possible perform interconnect tests between multiple PCBs within system thus extending interconnect tests back plane itself.
Features
Device Multi-Drop addressable IEEE 1149.1 protocol Support local scan chains addressable IEEE 1149.1 interface Support Pass-ThroughSupport IEEE 1149.1 USERCODE instruction Support Status instruction enabling nonintrusive monitoring system card Local Scan Port (LSP) enable signal provides ability IEEE 1149.1 compliant devices that require JTAG enable signal Provides ability initiate Self-Test remote standard IEEE 1149.1 command Support JTAG Technologies AutoWRfeature Pinout feature compatible (complete second source) with Firecron JTS06BU device Available 100-pin LQFP 100-pin FPBGA lead free package
Device Block Diagram
LSP2 LSP1
LSP3
LSP4
LSP5
LSP6
Figure AS91L1006BU Device Block Diagram
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AS91L1006BU
AS91L1006BU Gateway Functional basic structure AS91L1006BU device shown Figure-1. core device 16-state IEEE1149.1 controller state machine. accesses internal registers AS91L1006BU device controlled this state machine during normal operation IEEE1149.1 standard. address selection logic enables AS91L1006BU operate MultiDrop environment within system backplane. address selection logic compares scanned address slot address value presented AS91L1006BU device. park/unpark logic provides control through instructions scanned under IEEE1149.1 protocol, select, which will placed into active, scan chain. passthrough connection logic selects signal paths IEEE1149.1 signals. device also supports Pass-Through mode which enables primary IEEE1149.1 signals routed LSPs. This signal routing selectable pins AS91L1006BU device. Figure-2 shows device selection state machine. AS91L1006BU will perform address compare slot address presented value scanned IEEE1149.1. value matches then AS91L1006BU becomes selected ready normal access IEEE1149.1 commands. address does match then device will proceed unselected mode, where will remain until AS91L1006BU issued GOTOWAIT instruction reset occurs TRST LSP_RESET pin.
Selected Single Device
Device Unselected
Parked-RTI
Wait Selection
Parked-TLR
ParkedPauseDR
UnParked
Select Group Devices
Select Devices
ParkedPauseIR
Figure AS91L1006BU Selection Logic State machine
Figure Park/Unpark State Machine
Park/Unpark State Machine controls insertion LSPs into current active scan chain. ability park certain IEEE1149.1 states, enable AS91L1006BU perform several functions including backplane interconnect testing BIST.
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AS91L1006BU
AS91L1006BU Detailed Mode Operation
Addressing AS91L1006BU device After Test-Logic-Reset power-up, AS91L1006BU device will Wait-forSelection state with tri-stated, thus avoiding contention Multi-Drop environment. AS91L1006BU device will respond device-select sequence particular address that auto generated third party test tools with respect address that pre-loaded S(5.0). Once this sequence been completed, AS91L1006BU device will respond normal IEEE 1149.1 instructions. Note that addresses 6063 have been reserved AS91L1006BU device will respond user selects these addresses. AS91L1006BU device should Wait-for-Selection mode, which entered into issuing asynchronous reset (through deassertion TRST) issuing synchronous reset (through assertion five cycles TCK). After device been selected, issued GOTOWAIT instruction. internal IEEE1149.1 state machine AS91L1006BU device taken Shift-IR phase required Device-ID shifted into Instruction register. IEEE1149.1 state machine passes through Update-IR phase, address matched value S(5-0) pins AS91L1006BU device; values match, then AS91L1006BU device selected ready receive normal IEEE1149.1 command.
S(5-0) value decimal Table AS91L1006BU
value XXVVVVVV Device Selection Table
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AS91L1006BU
Table AS91L1006BU Multi Cast Group Selection Table Selection Mode Single Address Mode Binary Function Address XX000000 Single AS91L1006BU XX111010 selected device will active accessible AS91L1006BU devices selected operation. devices will HighZ Access AS91L1006BU devices that have been placed GRP0 their MCGR contents Access AS91L1006BU devices that have been placed GRP1 their MCGR contents Access AS91L1006BU devices that have been placed GRP2 their MCGR contents Access AS91L1006BU devices that have been placed GRP3 their MCGR contents
Table AS91L1006BU Device Register Description Register Name Instruction Register Description AS91L1006BU device addressing instructiondecode IEEE Std. 1149.1 required register IEEE Std. 1149.1 required register IEEE Std. 1149.1 required register IEEE Std. 1149.1 optional register IEEE Std. 1149.1 optional register AS91L1006BU device intrusive 8-bit register load able from pins AS91L1006BU device specific single register initiating self testing AS91L1006BU device local-port configuration control bits AS91L1006BU device Auto Write feature enable register AS91L1006BU device Async reset register LSPs
Broad XX111011 Cast Mode
Multi-Cast XX111100 Group
Multi-Cast XX111101 Group
BoundaryScan Register Bypass Register Device Identification Register User Code Register Status Register Self Test Register Mode Register Auto Write Register Async Reset Register
Multi-Cast XX111110 Group
Multi-Cast XX111111 Group
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AS91L1006BU
OpCode Binary Data Register Code 11111111 Bypass Register 00000000 10000001 10101010 11100111 11000101 10000100 11000110 11000011 10001110 00000011 10001000 10010111 10011000 10011001 Boundary-Scan Register Boundary-Scan Register Device Identification Register Device Identification Register Device Identification Register Device Identification Register Device Identification Register Device Identification Register Mode Register Multi-Cast Group Register. Device Identification Register User Programmable Identification Register Auto Write Feature Enable Register Single pulse, used initiate function (SELF_TEST pin) User programmable status byte (USER_STATUS_DATA pins) Toggles TRST while maintaining AS91L1006BU selected state. Device Identification Register
Instructions BYPASS EXTEST SAMPLE/PRELOAD IDCODE UNPARK PARKTLR PARKRTI PARKPAUSE GOTOWAIT* MODESELECT MCGRSELECT SOFTRESET USERCODE AUTOWR STEST_PCB
STATUS_BYTE LSP_ASYNC_RESET
10011010 10011011
Other Undefined
Table AS91L1006BU Device Instruction Register OpCodes
Note: instructions single selected AS91L1006BU device only. This instruction causes AS91L1006BU become unselected revert Wait-forSelection state.
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AS91L1006BU
AS91L1006BU device Register descriptions
Bypass Register
mandatory single register that connected between PRIM_TDI PRIM_TDO AS91L1006BU device.
Multi-Cast Group Register
This 2-bit data register enables host system place AS91L1006BU into four distinct addressable groups.
MCGR Register Bits [1.0]
Binary Selection Address XX111100 XX111101 XX111110 XX111111
MCGR GROUP GRP0 GRP1 GRP2 GRP3
Table Multicast Group Register Mapping Note: MCGR reset upon receiving TRST entering Test-Logic-Reset state.
IDCODE Register
optional 32-bit register that connected between PRIM_TDI PRIM_TDO AS91L1006BU device. contents IDCODE register will loaded with following data when AS91L1006BU enters Test-LogicReset passes through Capture-IR: Bits indicate ALSC Jedec value "001101101111"
Bits indicate part number device: "0000000000010000" Bits indicate revision device: "0000"
USERCODE Register
USERCODE 8-bit register that addressed standard IEEE1149.1 commands, which automatically generated third party test tools. AS91L1006BU returns zeroes read from this registerUSERUSER does have ability write into this register.
AS91L1006BU complete second source replacement Firecron JTS06BU device.
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AS91L1006BU
internal registers reset. order enable async reset tests LSPs, test tool should instruct device toggle reset pins while maintaining information AS91L1006BU. When instruction loaded into AS91L1006BU instruction register, single data register connected data register which always reset logic zero when state machine enters Capture-DR. This will cause TRST pins pulse cycle, during Update-DR phase.
SELF_TEST Register
AS91L1006BU device supports single output that controlled IEEE1149.1 interface. When instruction loaded into AS91L1006BU instruction register, single data register connected which always reset logic zero when state machine enters Capture-DR. This will cause SELF_TEST pulse cycle TCK, during Update-DR phase. This going pulse used initiate self-tests PCB's rack JTAG interface.
AUTOWR Register LSP_ASYNC_RST Register
AS91L1006BU device supports async reset tests devices connected LSPs. standard method performing these tests utilizing primary TRST cannot used will cause AS91L1006BU deselect This 6-bit register that controls passthrough JTAG Technologies AutoWRsignal LSP. register reset zeros when entering Test-Logic-Reset state.
Note: MCGR reset upon receiving TRST entering Test-Logic-Reset state AutoWr Register (Bit AutoWr Signal High High High Active Active Active Active AutoWr Signal High High Active High High Active Active AutoWr Signal High Active Active High Active High Active AutoWr Register (Bit AutoWr Signal High High High Active Active Active Active AutoWr Signal High High Active High High Active Active AutoWr Signal High Active Active High Active High Active
Table AUTOWR Register Mapping
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AS91L1006BU
parked stable state, i.e.: Pause-DR, Pause-IR, Run-Test-Idle TestLogic-Reset, will connected into active scan chain. LSPs parked stable state, then AS91L1006BU will perform bypass 6-LSP chain section. this both sections bypass mode then AS91L1006BU performing loopback TDI>Register->TDO host device. Mode_Select Register (Bit XXX0X000 XXX0X001 XXX0X010 XXX0X011 Configuration Port Unparked) LSP_Data ->TDO LSP_Data ->LSP4->PAD>TDO LSP_Data ->LSP5->PAD>TDO LSP_Data ->LSP4->PAD>LSP5->PAD->TDO LSP_Data ->LSP6->PAD>TDO LSP_Data ->LSP4->PAD>LSP6->PAD->TDO LSP_Data ->LSP5->PAD>LSP6->PAD->TDO LSP_Data
MODE_SELECT Register
Mode_Select register allows AS91L1006BU connected various different configurations. selected connection within scan chain contents Mode_Select register.
Mode_Select Register (Bit XXX0X000 XXX0X001 XXX0X010 XXX0X011
Configuration Port Unparked) ->Register->LSP_Data ->Register->LSP1->PAD-> LSP_Data ->Register->LSP2->PAD-> LSP_Data LSP_Data ->Register->LSP3->PAD-> LSP_Data LSP_Data LSP_Data LSP_Data
XXX0X100 XXX0X101
XXX0X100 XXX0X101
XXX0X110
XXX0X110
XXX0X111
XXX0X111
Table Mode Select Register Mapping Don't care Register AS91L1006BU device instruction register AS91L1006BU device test data registers. Insertion 1-bit register data synchronization. Upon entering Test-Logic-Reset, register bits will loaded with "0000000".
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AS91L1006BU
Pass Through Support within AS91L1006BU Device
AS91L1006BU device supports Pass-Through mode where primary master IEEE1149.1 JTAG signals routed LSPs. When this mode activated, "Debug Enable" signal that will active, which used place processor such MPC8260 into (Background Debug mode), required. processors present LSP, Pass-Through mode used assist generation test vectors memory tests devices that linked into selected LSP. pass-through feature effect simplifying test vector generation LSP, also effect removing AS91L1006BU device from test vector generation process.
PASS_THRU_Enable PASS_THRU_SEL(2) PASS_THRU_SEL(1) PASS_THRU_SEL(0) Active High High High High High High High High Normal Operation LSP1 LSP2 LSP3 LSP4 LSP5 LSP6
Table Pass through mode AS91L1006BU Note: When PASS_THRU_ENABLE deasserted (logic "1"), then LSPs under control AS91L1006BU device logic.
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AS91L1006BU
Signal NAME LSP1_TCK TYPE NUMBER LQFP DESCRIPTION NUMBER FPBGA IEEE1149.1 Test Clock when PASS_THRU_ENABLE HIGH. Stable state after port/reset Buffered version signal present primary
LSP1_TMS
Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 000. This tri-stated other combinations. IEEE1149.1 Test Mode Select Logic when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 000. This tri-stated other combinations. IEEE1149.1 Test Data Logic when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 000. This tri-stated other combinations. IEEE1149.1 Test Data when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 000. IEEE1149.1 Test Reset when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 000.
LSP1_TDO
LSP1_TDI
LSP1_TRST
Buffered version signal present primary TRST
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AS91L1006BU
NUMBER LQFP Stable state DESCRIPTION NUMBER after port/reset FPBGA Flash, Memory Auto-Write Logic when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 000; PRIM_AutoWR routed output. This tri-stated other combinations. Pass-Through Debug Enable Output Logic Local Scan Port Active output when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 000. This high other combinations. IEEE1149.1 Test Clock when PASS_THRU_ENABLE HIGH.
NAME LSP1_AutoWR
TYPE
LSP1_DE
LSP2_TCK
Buffered version signal present primary
LSP2_TMS
Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 001. This tri-stated other combinations. IEEE1149.1 Test Mode Select Logic when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 001. This tri-stated other combinations. IEEE1149.1 Test Data Logic when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 001. This tri-stated other combinations.
LSP2_TDO
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AS91L1006BU
NUMBER LQFP DESCRIPTION NUMBER FPBGA IEEE1149.1 Test Data when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 001. IEEE1149.1 Test Reset when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 001.
NAME LSP2_TDI
TYPE
Stable state after port/reset
LSP2_TRST
Buffered version signal present primary TRST
LSP2_AutoWR
Flash, Memory Auto-Write Logic when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 001; PRIM_AutoWR routed output. This tri-stated other combinations. PASS_THRU Debug Enable Output Logic Active output when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 001. This high other combinations. IEEE1149.1 Test Clock when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 010. This tri-stated other combinations.
LSP2_DE
LSP3_TCK
Buffered version signal present primary
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AS91L1006BU
NUMBER LQFP Stable state DESCRIPTION NUMBER after port/reset FPBGA IEEE1149.1 Test Mode Select Logic when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 010. This tri-stated other combinations. IEEE1149.1 Test Data Logic when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 010. This tri-stated other combinations. IEEE1149.1 Test Data when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 010. IEEE1149.1 Test Reset when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 010.
NAME LSP3_TMS
TYPE
LSP3_TDO
LSP3_TDI
LSP3_TRST
Buffered version signal present primary TRST
LSP3_LSP_ AutoWR
Flash, Memory Auto-Write Logic when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 010; PRIM_AutoWR routed output. This tri-stated other combinations.
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AS91L1006BU
NUMBER LQFP Stable state DESCRIPTION NUMBER after port/reset FPBGA PASS_THRU Debug Enable Output Logic Active output when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 010. This high other combinations. IEEE1149.1 Test Clock when PASS_THRU_ENABLE HIGH.
NAME LSP3_DE
TYPE
LSP4_TCK
Buffered version signal present primary
LSP4_TMS
Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 011. This tri-stated other combinations. IEEE1149.1 Test Mode Select Logic when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 011. This tri-stated other combinations. IEEE1149.1 Test Data Logic when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 011. This tri-stated other combinations. IEEE1149.1 Test Data when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 011. IEEE1149.1 Test Reset when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 011.
LSP4_TDO
LSP4_TDI
LSP4_TRST
Buffered version signal present primary TRST
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AS91L1006BU
NUMBER LQFP Stable state DESCRIPTION NUMBER after port/reset FPBGA Flash, Memory Auto-Write Logic when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 011; PRIM_AutoWR routed output. This tri-stated other combinations. PASS_THRU Debug Enable Output Logic Active output when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 011. This high other combinations. IEEE1149.1 Test Clock when PASS_THRU_ENABLE HIGH.
NAME LSP4_AutoWR
TYPE
LSP4_DE
LSP5_TCK
Buffered version signal present primary
LSP5_TMS
Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 100. This tri-stated other combinations. IEEE1149.1 Test Mode Select Logic when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 100. This tri-stated other combinations. IEEE1149.1 Test Data Logic when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 100. This tri-stated other combinations.
LSP5_TDO
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AS91L1006BU
NUMBER LQFP DESCRIPTION NUMBER FPBGA IEEE1149.1 Test Data when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 100. IEEE1149.1 Test Reset when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 100.
NAME LSP5_TDI
TYPE
Stable state after port/reset
LSP5_TRST
Buffered version signal present primary TRST
LSP5_AutoWR
Flash, Memory Auto-Write Logic when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 100; PRIM_AutoWR routed output. This tri-stated other combinations. PASS_THRU Debug Enable Output Logic Active output when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 100. This high other combinations. IEEE1149.1 Test Clock when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 101. This tri-stated other combinations.
LSP5_DE
LSP6_TCK
Buffered version signal present primary
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AS91L1006BU
NUMBER LQFP Stable state DESCRIPTION NUMBER after port/reset FPBGA IEEE1149.1 Test Mode Select Logic when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 101. This tri-stated other combinations. IEEE1149.1 Test Data Logic when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 101. This tri-stated other combinations. IEEE1149.1 Test Data when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 101. IEEE1149.1 Test Reset when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 101.
NAME LSP6_TMS
TYPE
LSP6_TDO
LSP6_TDI
LSP6_TRST
Buffered version signal present primary TRST
LSP6_AutoWR
Flash, Memory Auto-Write Logic when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 101; PRIM_AutoWR routed output. This tri-stated other combinations.
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AS91L1006BU
NUMBER LQFP Stable state DESCRIPTION NUMBER after port/reset FPBGA PASS_THRU Debug Enable Output Logic Active output when PASS_THRU_ENABLE PASS_THRU_SEL[2:0] 101. This high other combinations. IEEE1149.1 Primary Test Clock Input. IEEE1149.1 Primary Test Mode Select Input. IEEE1149.1 Primary Test Data Output. This tri-stated when AS91L1006BUis selected. IEEE1149.1 Primary Test Data Input IEEE1149.1 Primary Test Reset Input.
NAME LSP6_DE
TYPE
PRIM_TCK PRIM_TMS PRIM_TDO
HighZ
PRIM_TDI PRIM_TRST
PRIM_AutoWR
S[5:0]
This active asynchronous reset input signal places AS91L1006U Wait-for-Selection state. Primary Auto-Write Input controlled test equipment shorten Flash memory programming. 8,7,6,5,100, D2,D1,D3,C AS91L1006BU Slot Address[5:0] 2,B2,A2 Inputs. Used address which AS91L1006BU will respond; typically hardwired connection backplane. Test Output Enable Input. Tri-states LSPs, when asserted low. Reset Input. Active resets AS91L1006BU "Wait-for-Selection" state pulses TRST output pins low. This resets devices with TRST function; typically this signal would connected power-on-reset function.
*TOE
LSP_RESET_n
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AS91L1006BU
NUMBER LQFP DESCRIPTION NUMBER FPBGA AS91L1006BU_Selected Output.
NAME AS91L1006BU_ SELECTED
TYPE
Stable state after port/reset Logic
LSP_ENABLE
Active when AS91L1006BU selected; typically used control board buffering. Enabled Output. Logic
USER_STATUS _BYTE[7:0]
SELF_TEST
PASS_THRU_ ENABLE
Active when AS91L1006BU selected; typically used IEEE1149.1 compliance enable pins devices. C7,C6,C5,C AS91L1006BU Status_Byte Inputs. 4,B4,A4,B3, A3(MSB- Used provide status information (MSB-LSB) LSB) under test back test master IEEE1149.1 bus. Eight signals levels monitored then reported IEEE1149.1 intrusive manner. Provides going output pulse Logic under command from IEEE1149.1 bus, which used start self-test functions PCB. PASS_THRU Enable Input. Active high disables Pass-Through mode. Active enables Pass-Through mode. 13,12,10 E2,E1,E3 PASS_THRU Select Inputs. (MSB-LSB) (MSB-LSB) Used select active routing PassThrough ports enabled active PASS_THRU_ENABLE pin. LSP1 LSP2 LSP3 LSP4 LSP5 LSP6 Ground pins. G4,H8, J9,B1,
PASS_THRU_ SEL12:0]
POWER
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AS91L1006BU
DESCRIPTION NUMBER NUMBER LQFP FPBGA pins. 82,23,56 H3,G9,H1 Factory Test_Enable Input. This should left unconnected. IEEE1149.1 ASIC Test Clock Input. IEEE1149.1 ASIC Test Mode Select. Input IEEE1149.1 ASIC Test Clock Output. IEEE1149.1 ASIC Test Clock Input.
NAME
TYPE POWER
Stable state after port/reset
ASIC_TEST_ ASIC_TCK ASIC_TMS ASIC_TDO ASIC_TDI Connects
Table AS91L0006BU Signal
Absolute Maximum Ratings
Parameter Supply Voltage (Vcc) Input Voltage (Vi) sink current when -0.5V source current when 0.5V Junction Temperature with power applied Storage temperature Maximum Range -0.3V 5.5V -0.5V +0.5V -20mA +20mA +125 degrees +150 degree
Table Absolute Maximum Ratings Note: Stress above stated maximum values cause irreparable damage device. Correct operation device these values guaranteed.
Recommended Operating Conditions
Parameter Supply Voltage (Vcc) Operating Range 3.0V 3.6V
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AS91L1006BU
Input Voltage (Vi) Output Voltage (Vo) Operating Temperature (Ta) Commercial Industrial (Ta)
3.00V 3.6V
Table Recommended Operating Conditions
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AS91L1006BU
Electrical Characteristics
Signal High High
Figure AS91L1006BU Timing Diagram SYMBOL Parameter clock pulse width pulse width high pulse width Setup time Hold time Edge valid data enable Edge valid data Pass through Mode Primary/Lsp Delay UNITS
Table AS91L1006BU Timing Information
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AS91L1006BU
Electrical Characteristics
Symbol Symbol Iccd Parameter Minimum High Input Voltage Maximum Input Voltage Parameter Minimum High Output Voltage Minimum LowOutput Voltage 5.25 0.8V Value 2.4V 0.4V -0.3V Condition Ioh=24mA defined Iol=24mA defined Condition
Tristate output leakage Maximum quiecennt supply current Maximum dynamic supply current 80mA freq equal
Table AS91L1006BU Electrical Characteristics
Timing Information
From Prim_TCK Prim_TCK Prim inputs Prim inputs Type Setup Hold Setup Hold Value
LSP[1:6]_TCK inputs LSP[1:6]_TCK inputs Prim inputs inputs Prim_TCK Prim_TCK LSP_TCK Prim_TCK outputs
Comb Delay 11ns
Prim outputs Comb Delay 11ns LSP_TCK Comb Delay 10ns 11ns 40MHz
Prim outputs Delay outputs Delay Freq
Table AS91L1006BU timing information
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AS91L1006BU
Packaging Information
AS91L1006BU available 100-pin LQFP 100-pin FPBGA lead free package.
Square
Square
NOTES ENSIO ILLIM PLAS FLAS TUSIO ALLO ABLE 0.25 SIDE. LEAD PRESENTATIVE CTUAL PACKAG
-C0.09/0.20
0.25
LEAD COPLANARITY
Figure LQFP-100
REV.
Revisions DESCRIPTION Initial document release. Updated ball coplanarity limits from 0.20mm 0.15mm.
91253
DATE 12-04-01
0.15
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AS91L1006BU
SYMBOL PACKAGE NUMBER JEDEC
DIMENSIONS MIN. -0.30 0.25 0.50
NOM. -0.60 11.00 9.00 11.00 9.00 1.00 FBGA0100-11F MO-192 VAR. AAC-1
MAX. 1.70 -1.10 0.70
0.25 0.25
Figure FPBGA-100
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AS91L1006BU
Device Selector Guide Ordering Information
AS91L
Aliance Semiconductor system solution
XXXX
TEMP
Blank leaded lead free green Commercial degrees Industrial (-40 degrees Package L100 LQFP F100 FPBGA Clock speed Frequency High Frequency
Device family 1001 1002 1003 1006 Product version standard 16-bit user code 8-bit status/user code enhanced
Figure Part Numbering Guide
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AS91L1006BU
Part Number AS91L1006BU 10L100-C AS91L1006BU 10L100-I AS91L1006BU 10F100-C
Description JTAG 6-Port Gateway, 100-pin LQFP package, commercial JTAG 6-Port Gateway, 100-pin LQFP package, industrial JTAG 6-Port Gateway 100-pin FPBGA package, commercial JTAG 6-Port Gateway 100-pin FPBGA package, industrial JTAG 6-Port Gateway, 100-pin LQFP package, commercial, High Frequency JTAG 6-Port Gateway, 100-pin LQFP package, commercial, lead free, High Frequency JTAG 6-Port Gateway, 100-pin LQFP package, industrial, High Frequency JTAG 6-Port Gateway, 100-pin LQFP package, industrial, lead free, High Frequency JTAG 6-Port Gateway 100-pin FPBGA, commercial, High Frequency JTAG 6-Port Gateway 100-pin FPBGA, commercial, green package, High Frequency JTAG 6-Port Gateway 100-pin FPBGA, industrial, High Frequency JTAG 6-Port Gateway 100-pin FPBGA, industrial, green package, High Frequency Table Valid Part Number Combinations
Availability Please Contact Alliance Semiconductor Please Contact Alliance Semiconductor Please Contact Alliance Semiconductor
AS91L1006BU 10F100-I
AS91L1006BU 40L100-C
AS91L1006BU 40L100-CF
AS91L1006BU 40L100-I
Please Contact Alliance Semiconductor
AS91L1006BU 40L100-IF
AS91L1006BU 40F100-C
Please Contact Alliance Semiconductor Please Contact Alliance Semiconductor Please Contact Alliance Semiconductor Please Contact Alliance Semiconductor
AS91L1006BU 40F100-CG
AS91L1006BU 40F100-I
AS91L1006BU 40F100-IG
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AS91L1006BU
Device Master AS91L1001 AS91L1002 AS91L1003U AS91L1006BU
FPBGA-100 (1mm pitch)
Package Options
LQFP-100
JTAG Test Controller JTAG Test Sequencer 3-Port Gateway 6-Port Gateway
Table JTAG Controller Product Family
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1006BU
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.

6-Port JTAG Gateway AS91L1006BU 6-port JTAG gateway. partitions s

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