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3-Port JTAG Gateway AS91L1003U 3-port JTAG gateway. partitions si


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AS91L1003U
3-Port JTAG Gateway
AS91L1003U 3-port JTAG gateway. partitions single JTAG chain into three separate chains. These separate chains optionally configured operate single chain. AS91L1003U device used provide enhanced capabilities standard IEEE1149.1. enables IEEE1149.1 interface used true Multi-Drop environment without additional signals. This Multi-Drop capability enables standard IEEE1149.1 interface used just stand alone Printed Circuit Board (PCB) testing, complete system testing including PCBs within system back plane environment. AS91L1003U provides capability partitioning into multiple smaller IEEE1149.1 scan chains totally under software control. Partitioning IEEE1149.1 chains several benefits, which include easier fault diagnostics capabilities, fault IEEE1149.1 Local Scan Ports (LSPs) does render un-testable, faster flash programming PCB's removal IEEE1149.1 signal loading issues. protocols required addressing AS91L1003U device MultiDrop capability protocols configuring which three IEEE1149.1 LSPs AS91L1003U used, handled party ATPG tools from vendors like AssetIntertech JTAG Technologies. Multi-Drop environment, also possible perform interconnect tests between multiple PCBs within system thus extending interconnect tests back plane itself.
Features
Device Multi-Drop addressable IEEE 1149.1 protocol Support local scan chains addressable IEEE 1149.1 interface Support Pass-ThroughSupport IEEE 1149.1 USERCODE instruction Support Status instruction enabling nonintrusive monitoring system card Local Scan Port (LSP) enable signal provides ability IEEE 1149.1 compliant devices that require JTAG enable signal Provides ability initiate Self-Test remote standard IEEE 1149.1 command Support JTAG Technologies AutoWRfeature Pinout feature compatible (complete second source) with Firecron JTS03U device Available 100-pin LQFP 100-pin FPBGA lead free package
Device Block Diagram
LSP1
Pass Local
LSP2
LSP3
Figure AS91L1003U Device Block Diagram
Alliance Semiconductor
2575 Augustine Drive Santa Clara, 95054 408-855-4900 408-855-4999 www.alsc.com
AS91L1003U
AS91L1003U Gateway Functional basic structure AS91L1003U device shown Figure core device 16-state IEEE1149.1 controller state machine. accesses internal registers AS91L1003U device controlled this state machine during normal operation IEEE1149.1 standard. address selection logic enables AS91L1003U operate MultiDrop environment within system backplane. address selection logic compares scanned address slot address value presented AS91L1003U device. park/unpark logic provides control through instructions scanned under IEEE1149.1 protocol, select which will placed into active scan chain. passthrough connection logic selects signal paths IEEE1149.1 signals. device also supports Pass-Through mode which enables primary IEEE1149.1 signals routed LSPs. This signal routing selectable pins AS91L0003U device. AS91L1003U operation controlled core blocks through three closely coupled state machines. Figure-2 shows device selection state machine. AS91L1003U will perform address compare slot address presented value scanned IEEE1149.1. value matches, then AS91L1003U becomes selected ready normal access IEEE1149.1 commands. address does match then device will proceed unselected mode, where will remain until AS91L1003U issued GOTOWAIT instruction reset occurs either TRST LSP_RESET pin.
Selected Single Device
Device Unselected
Parked-RTI
Wait Selection
Parked-TLR
ParkedPauseDR
UnParked
Select Group Devices
Select Devices
ParkedPauseIR
Figure AS91L1003U Selection Logic State machine
Figure Park/Unpark State Machine
Park/Unpark state machine controls insertion LSPs into current active scan chain. ability park certain IEEE1149.1 states, enable AS91L1003U perform several functions including backplane interconnect testing BIST.
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
AS91L1003U Detailed Mode Operation
Addressing AS91L1003U device After Test-Logic-Reset power-up, AS91L1003U device will Wait-forSelection state with tri-stated, thus avoiding contention Multi-Drop environment. AS91L1003U device will respond deviceselect sequence particular address that auto generated third party test tools with respect address that pre-loaded S(5.0) pins. Once this sequence been completed, AS91L1003U device will respond normal IEEE 1149.1 instructions. Note that addresses 60-63 have been reserved AS91L1003U device will respond user selects these addresses. selected, AS91L1003U device should Wait-for-Selection mode which entered into issuing asynchronous reset (through deassertion TRST) issuing synchronous reset (through assertion five cycles TCK). After device been selected, issued GOTOWAIT instruction reset AS91L1003U device. internal IEEE1149.1 state machine AS91L1003U device taken Shift-IR phase required Device-ID shifted into Instruction register. IEEE1149.1 state machine passes through Update-IR phase, address matched value S(5-0) pins AS91L1003U device; values match then AS91L1003U device selected ready receive normal IEEE1149.1 command.
S(5-0) value decimal
value XXVVVVVV
Table AS91L1003U Device Selection Table
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
Table AS91L1003U Multi Cast Group Selection Table Selection Mode Single Address Mode Binary Function Address XX000000 Single AS91L1003U XX111010 selected device will active accessible AS91L1003U devices selected operation. devices will HighZ Access AS91L1003U device that have been placed GRP0 their MCGR contents Access AS91L1003U device that have been placed GRP1 their MCGR contents Access AS91L1003U device that have been placed GRP2 their MCGR contents Access AS91L1003U device that have been placed GRP3 their MCGR contents
Table AS91L1003U Device Register Description Register Name Instruction Register Description AS91L1003U device addressing instruction-decode IEEE Std. 1149.1 required register IEEE Std. 1149.1 required register IEEE Std. 1149.1 required register IEEE Std. 1149.1 optional register IEEE Std. 1149.1 optional register AS91L1003U device intrusive 8-bit register load able from pins AS91L1003U device specific single register initiating self testing AS91L1003U device local-port configuration control bits AS91L1003U device Auto Write feature enable register AS91L1003U device Async reset register LSPs
BroadXX111011 Cast Mode
Multi-Cast XX111100 Group
Multi-Cast XX111101 Group
BoundaryScan Register Bypass Register Device Identification Register User Code Register Status Register Self Test Register Mode Register Auto Write Register Local Scan Port Async Reset Register
Multi-Cast XX111110 Group
Multi-Cast XX111111 Group
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2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
OpCode Binary Data Register Code 11111111 Bypass Register 00000000 10000001 10101010 11100111 11000101 10000100 11000110 11000011 10001110 00000011 10001000 10010111 10011000 10011001 Boundary-Scan Register Boundary-Scan Register Device Identification Register Device Identification Register Device Identification Register Device Identification Register Device Identification Register Device Identification Register Mode Register Multi-Cast Group Register. Device Identification Register User Programmable Identification Register Auto Write Feature Enable Register Single pulse used initiate function (SELF_TEST pin) User programmable status byte (USER_STATUS_DATA pins) Toggles TRST while maintaining AS91L1003U selected state. Device Identification Register
Instructions BYPASS EXTEST SAMPLE/PRELOAD IDCODE UNPARK PARKTLR PARKRTI PARKPAUSE GOTOWAIT* MODESELECT MCGRSELECT SOFTRESET USERCODE AUTOWR STEST_PCB
STATUS_BYTE LSP_ASYNC_RESET
10011010 10011011
Other Undefined
Table AS91L1003U Device Instruction Register OpCodes
Note: instructions single selected AS91L1003U device only. This instruction causes AS91L1003U become unselected revert Wait-forSelection state.
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
AS91L1003U device Register descriptions
Bypass Register
mandatory single register that connected between PRIM_TDI PRIM_TDO AS91L1003U device.
Multi-Cast Group Register
This 2-bit data register enables host system place AS91L1003U into four distinct addressable groups.
MCGR Register Bits [1.0]
Binary Selection Address XX111100 XX111101 XX111110 XX111111
MCGR GROUP GRP0 GRP1 GRP2 GRP3
Table Multicast Group Register Mapping Note: MCGR reset upon receiving TRST entering Test-Logic-Reset state.
IDCODE Register
optional 32-bit register that connected between PRIM_TDI PRIM_TDO AS91L1003U device. contents IDCODE register will loaded with following data when AS91L1003U enters Test-LogicReset passes through Capture-IR: Bits indicate ALSC Jedec value "001101101111" Bits indicate part number device: "0000000000010000"
Bits indicate revision device: "0000"
USERCODE Register
USERCODE 32-bit register that addressed standard IEEE1149.1 commands, which automatically generated third party test tools. user ability program binary value that will transmitted back host USERCODE command; setting binary pattern USERCODE pins AS91L1003U device.
AS91L1003U complete second source replacement Firecron JTS03U device.
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
STATUS_BYTE Register
STATUS_BYTE register AS91L1003U device provides means sense value USER_STATUS_DATA pins AS91L1003U device. This 8-bit field where user non-intrusively monitor signals printed circuit card IEEE1149.1 interface. data register loaded each time state machine passes through Capture-DR phase. Note: Value positive logic.
LSP_ASYNC_RST Register
AS91L1003U device supports async reset tests devices connected LSPs. standard method performing these tests utilizing PRIM_TRST cannot used will cause AS91L1003U deselect internal registers reset. order enable async reset tests LSP, test tool should instruct device toggle local scan port reset pins while maintaining information AS91L1003U. When instruction loaded into AS91L1003U instruction register, single data register connected which always zero when state machine enters Capture-DR. This will cause TRST pins pulse cycle, during Update-DR phase.
SELF_TEST Register
AS91L1003U device supports single output that controlled IEEE1149.1 interface. When instruction loaded into AS91L1003U instruction register, single data register connected which zero when state machine enters CaptureDR. This will cause SELF_TEST pulse cycle TCK, during Update-DR phase. This going pulse used initiate self-tests PCB's rack JTAG interface. AutoWr Register (Bit AutoWr Signal High High High Active Active Active Active
AUTOWR Register
This 3-bit register that controls passthrough JTAG Technologies AutoWRsignal Local Scan Port. register reset zeros when entering Test-LogicReset state. AutoWr Signal High High Active High High Active Active AutoWr Signal High Active Active High Active High Active
Table AUTOWR Register Mapping
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2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
Local Scan Port parked stable state, i.e.: Pause-DR, Pause-IR, Run-TestIdle Test-Logic-Reset, will connected into active scan chain. LSPs parked stable state, then AS91L1003U will perform loopback TDI->Register->TDO.
MODE_SELECT Register
Mode_Select register allows Local Scan Port AS91L1003U connected various different configurations. selected connection within scan chain contents Mode_Select register.
Mode_Select Register Configuration Port Unparked) (Bit XXX0X000 TDI->Register->TDO XXX0X001 XXX0X010 XXX0X011 XXX0X100 XXX0X101 XXX0X110 XXX0X111 TDI->Register->LSP1->PAD->TDO TDI->Register->LSP2->PAD->TDO TDI->Register->LSP3->PAD->TDO
Table Mode Select Register Mapping don't care Register AS91L1003U device instruction register AS91L1003U device test data registers. Insertion 1-bit register data synchronization. Upon entering Test-Logic-Reset, register bits will loaded with "0000000".
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
Pass-Through Support within AS91L1003U Device
AS91L1003U device supports PassThrough mode where primary master IEEE1149.1 JTAG signals routed LSPs. When this mode activated, "Debug Enable" signal that will active, which used place processor such MPC8260 into (Background Debug Mode) required. processors present LSP, Pass-Through mode used assist generation test vectors memory tests devices that linked into selected LSP. pass-through feature effect simplifying test vector generation LSP, also effect removing AS91L1003U device from test vector generation process.
PASS_THRU_ENABLE High
PASS_THRU_SEL(1) High
PASS_THRU_SEL(0) High
Active Normal Operation LSP1 LSP2 LSP3
Table Pass-Through mode AS91L1003U Note: When PASS_THRU_ENABLE enable deasserted (logic "1"), then LSPs under control AS91L1003U device logic.
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2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
Signal NUMBER LQFP NUMBER FPBGA Stable signals states, with device unselected active outputs device Buffered version signal present primary
NAME
TYPE
DESCRIPTION
LSP1_TCK
IEEE1149.1 Test Clock Local Scan Port when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[1:0] This tri-stated other combinations. IEEE1149.1 Test Mode Select Local Scan Port when PASS_THRU_ENABLE HIGH.
LSP1_TMS
Logic
LSP1_TDO
Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[1:0] This tri-stated other combinations. IEEE1149.1 Test Data Local Logic Scan Port when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[1:0] This tri-stated other combinations. IEEE1149.1 Test Data Local Scan Port when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[1:0] IEEE1149.1 Test Reset Local Scan Port when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[1:0]
LSP1_TDI
LSP1_TRST
Buffered version signal present primary TRST
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2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
Stable signals states, with device unselected active outputs device Logic
NAME
TYPE
NUMBER LQFP
NUMBER FPBGA
DESCRIPTION
LSP1_AutoWR
Flash, Memory Auto-Write Local Scan Port when PASS_THRU_ENABLE HIGH.
LSP1_DE
Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[1:0] This tri-stated other combinations. Pass-Through Debug Enable Output Logic Local Scan Port Active output when PASS_THRU_ENABLE PASS_THRU_SEL[1:0] =00. This high other combinations. IEEE1149.1 Test Clock Local Scan Port when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[1:0] This tri-stated other combinations. IEEE1149.1 Test Mode Select Local Scan Port when PASS_THRU_ENABLE HIGH.
LSP2_TCK
Buffered version signal present primary
LSP2_TMS
Logic
LSP2_TDO
Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[1:0] This tri-stated other combinations. IEEE1149.1 Test Data Local Logic Scan Port when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[1:0] This tri-stated other combinations.
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
Stable signals states, with device unselected active outputs device
NAME
TYPE
NUMBER LQFP
NUMBER FPBGA
DESCRIPTION
LSP2_TDI
IEEE1149.1 Test Data Local Scan Port when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[1:0] IEEE1149.1 Test Reset Local Scan Port when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[1:0]
LSP2_TRST
Buffered version signal present primary TRST
LSP2_AutoWR
Flash, Memory Auto-Write Local Scan Port when PASS_THRU_ENABLE HIGH.
Logic
LSP2_DE
Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[1:0] This tri-stated other combinations. Pass-Through Debug Enable Output Logic Local Scan Port Active output when PASS_THRU_ENABLE PASS_THRU_SEL[1:0] =01. This high other combinations. IEEE1149.1 Test Clock Local Scan Port when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[1:0] This tri-stated other combinations.
LSP3_TCK
Buffered version signal present primary
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2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
Stable signals states, with device unselected active outputs device Logic
NAME
TYPE
NUMBER LQFP
NUMBER FPBGA
DESCRIPTION
LSP3_TMS
IEEE1149.1 Test Mode Select Local Scan Port when PASS_THRU_ENABLE HIGH.
LSP3_TDO
Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[1:0] This tri-stated other combinations. IEEE1149.1 Test Data Local Logic Scan Port when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[1:0] This tri-stated other combinations. IEEE1149.1 Test Data Local Scan Port when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[1:0] IEEE1149.1 Test Reset Local Scan Port when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[1:0]
LSP3_TDI
LSP3_TRST
Buffered version signal present primary TRST
LSP3_LSP_ AutoWR
Flash, Memory Auto-Write Local Scan Port when PASS_THRU_ENABLE HIGH. Pass-Through mode when PASS_THRU_ENABLE PASS_THRU_SEL[1:0] This tri-stated other combinations.
Logic
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2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
Stable signals states, with device DESCRIPTION unselected active outputs device Pass-Through Debug Enable Output Logic Local Scan Port Active output when PASS_THRU_ENABLE PASS_THRU_SEL[1:0] =10. This high other combinations. IEEE1149.1 Primary Test Clock Input. IEEE1149.1 Primary Test Mode Select Input. IEEE1149.1 Primary Test Data HighZ Output. This tri-stated when AS91L1003 selected. IEEE1149.1 Primary Test Data Input IEEE1149.1 Primary Test Reset Input.
NAME
TYPE
NUMBER LQFP
NUMBER FPBGA
LSP3_DE
PRIM_TCK PRIM_TMS PRIM_TDO
PRIM_TDI PRIM_TRST
PRIM_AutoWR
S[5:0]
*TOE
This active asynchronous reset input signal places AS91L1003U Wait-for-Selection state. Primary Auto-Write Input controlled test equipment shorten Flash memory programming. 8,7,6,5,100, D2,D1,D3,C2, Slot Address (5:0) Inputs. B2,A2 Used address which AS91L1003U will respond; typically hardwired connection backplane. Test Output Enable Input. Tri-states LSPs, when asserted low. Local Scan Port Reset Input. Active resets AS91L1003U "Wait-for-Selection" state pulses TRST output pins low. This resets devices with TRST function; typically this signal would connected power-on-reset function.
LSP_RESET_n
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2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
Stable signals states, with device unselected active outputs device
NAME
TYPE
NUMBER LQFP
NUMBER FPBGA
DESCRIPTION
AS91L1003U_ SELECTED
AS91L1003U_Selected Output. Active when AS91L1003U selected; typically used control board buffering. Local Scan Port Enable Output.
LSP_ENABLE
USERCODE [15:0]
USER_STATUS _BYTE[7:0]
SELF_TEST
PASS_THRU_ ENABLE
Active output when AS91L1003U selected; typically used IEEE1149.1 compliance enable pins devices. 64,65,67,68 E9,E10,E8,E7 User/Board Identification Inputs. ,69,70,71,7 ,D9,D10,D8,C 2,75,76,77, 9,C10,B10,B9 Used establish board type 78,79,80,81 ,A9,A8,B8,A7, revision ensure correct (MSBB7 (MSB- IEEE1149.1 test vector sets LSB) LSB) applied. C7,C6,C5,C4, USER_Status_Byte Inputs. B4,A4,B3,A3( MSB-LSB) Used provide status information (MSB-LSB) under test back test master IEEE1149.1 bus. Eight signals levels monitored then reported IEEE1149.1 intrusive manner. Provides going output pulse Logic under command from IEEE1149.1 bus, which used start self-test functions PCB. PASS_THRU Enable Input. Active high disables Pass-Through mode. Active enables Pass-Through mode. PASS_THRU Select Inputs. Used select active routing PassThrough ports enabled active PASS_THRU_ENABLE pin. LSP1 LSP3
PASS_THRU_ SEL[1:0]
12,10
E1,E3
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2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
Stable signals states, with device unselected active outputs device
NAME
TYPE
NUMBER LQFP
NUMBER FPBGA
DESCRIPTION
ASIC_TEST_ ASIC_TCK ASIC_TMS ASIC_TDO ASIC_TDI Connects
POWER Ground Pins. G4,H8, J9,B1, POWER pins. 82,23, H3,G9,H1 Factory Test_Enable Input. This should left unconnected. IEEE1149.1 ASIC Test Clock Input. IEEE1149.1 ASIC Test Mode Select Input. IEEE1149.1 ASIC Test Clock Output. IEEE1149.1 ASIC Test Clock Input.
1,13,63,61, C1,E2,F7,F10 60,58,57 ,F9,G8,G10 Table AS91L0003U Signal
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2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
Absolute Maximum Ratings
Parameter Supply Voltage (Vcc) Input Voltage (Vi) sink current when -0.5V source current when 0.5V Junction Temperature with power applied Storage temperature Maximum Range -0.3V 5.5V -0.5V +0.5V -20mA +20mA +125 degrees +150 degree
Table Absolute Maximum Ratings Note: Stress above stated maximum values cause irreparable damage device. Correct operation device these values guaranteed.
Recommended Operating Conditions
Parameter Supply Voltage (Vcc) Input Voltage (Vi) Output Voltage (Vo) Operating Temperature (Ta) Commercial Industrial (Ta) Operating Range 3.0V 3.6V 3.00V 3.6V
Table Recommended Operating Conditions
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2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
Electrical Characteristics
Signal High High
Figure AS91L1003U Timing Diagram SYMBOL Parameter clock pulse width pulse width high pulse width Setup time Hold time Edge valid data enable Edge valid data Pass through Mode Primary/LSP Delay UNITS
Table AS91L1003U Timing Information
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2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
Electrical Characteristics
Symbol Parameter Minimum High Input Voltage Maximum Input Voltage Parameter Minimum High Output Voltage Minimum Output Voltage Tristate output leakage Maximum quiecennt supply current Maximum dynamic supply current -0.3V 5.25 0.8V Condition
Symbol Iccd
Value 2.4V 0.4V 80mA
Condition Ioh=24mA defined Iol=24mA defined
freq equal
Table AS91L1003U Electrical Characteristics
Timing Information
From Prim_TCK Prim_TCK Prim inputs Prim inputs Type Setup Hold Setup Hold Value
LSP[1:3]_TCK inputs LSP[1:3]_TCK inputs Prim inputs inputs Prim_TCK Prim_TCK LSP_TCK Prim_TCK outputs
Comb Delay 11.5ns
Prim outputs Comb Delay 10ns LSP_TCK Comb Delay 8.5ns 10ns 40MHz
Prim outputs Delay outputs Delay Freq
Table AS91L1003U Timing Information
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2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
Packaging Information
AS91L1003U available 100-pin LQFP 100-pin FPBGA lead free package.
Square
Square
NOTES ENSIO ILLIM PLAS FLAS TUSIO ALLO ABLE 0.25 SIDE. LEAD PRESENTATIVE CTUAL PACKAG
-C0.09/0.20
0.25
LEAD COPLANARITY
Figure LQFP-100
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2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
REV.
Revisions DESCRIPTION Initial document release. Updated ball coplanarity limits from 0.20mm 0.15mm.
91253
DATE 12-04-01
0.15
SYMBOL PACKAGE NUMBER JEDEC
DIMENSIONS MIN. -0.30 0.25 0.50
NOM. -0.60 11.00 9.00 11.00 9.00 1.00 FBGA0100-11F MO-192 VAR. AAC-1
MAX. 1.70 -1.10 0.70
0.25 0.25
Figure FPBGA-100
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
Device Selector Guide Ordering Information
AS91L
Aliance Semiconductor system solution
XXXX
TEMP
Blank leaded lead free green Commercial degrees Industrial (-40 degrees Package L100 LQFP F100 FPBGA Clock speed Frequency High Frequency
Device family 1001 1002 1003 1006 Product version standard 16-bit user code 8-bit status/user code enhanced
Figure Part Numbering Guide
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
Part Number AS91L1003U 10L100-C AS91L1003U 10L100-I AS91L1003U 10F100-C
Description 3-Port JTAG Gateway, 100-pin LQFP package, commercial 3-Port JTAG Gateway, 100-pin LQFP package, industrial 3-Port JTAG Gateway, 100-pin FPBGA package, commercial 3-Port JTAG Gateway, 100-pin FPBGA package, industrial 3-Port JTAG Gateway, 100-pin LQFP package, commercial, High Frequency 3-Port JTAG Gateway, 100-pin LQFP package, commercial, lead free, High Frequency 3-Port JTAG Gateway, 100-pin LQFP package, industrial, High Frequency 3-Port JTAG Gateway, 100-pin LQFP package, industrial, lead free, High Frequency 3-Port JTAG Gateway, 100-pin FPBGA, commercial, High Frequency 3-Port JTAG Gateway, 100-pin FPBGA, commercial, green package, High Frequency 3-Port JTAG Gateway, 100-pin FPBGA, industrial, High Frequency 3-Port JTAG Gateway, 100-pin FPBGA, industrial, green package, High Frequency Table Valid Part Number Combinations
Availability Please Contact Alliance Semiconductor Please Contact Alliance Semiconductor Please Contact Alliance Semiconductor
AS91L1003U 10F100-I
AS91L1003U 40L100-C
AS91L1003U 40L100-CF
AS91L1003U 40L100-I
Please Contact Alliance Semiconductor
AS91L1003U 40L100-IF
AS91L1003U 40F100-C
Please Contact Alliance Semiconductor Please Contact Alliance Semiconductor Please Contact Alliance Semiconductor Please Contact Alliance Semiconductor
AS91L1003U 40F100-CG
AS91L1003U 40F100-I
AS91L1003U 40F100-IG
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2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
Device Master AS91L1001 AS91L1002 AS91L1003U AS91L1006BU
FPBGA-100 (1mm pitch)
Package Options
LQFP-100
JTAG Test Controller JTAG Test Sequencer 3-Port Gateway 6-Port Gateway
Table JTAG Controller Product Family
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2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1003U
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2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.

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