JTAG Test Controller AS91L1001 device provides interface between
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AS91L1001
JTAG Test Controller
AS91L1001 device provides interface between Motorola MPC8260 processor totally independent IEEE1149.1 interfaces, namely, primary secondary ports. handles protocol write read directly registers within device with additional glue logic. AS91L1001 three distinct modes operation, namely Slave mode, Master mode, Party Support mode. These different modes control data will transferred IEEE1149.1 buses. Slave mode: This default mode after AS91L1001 received power-on reset. this mode, there transparent connection between primary secondary JTAG ports. processor interface used slave mode. This configuration typically used test line card from system back plane (the primary port usually connected back plane secondary port connected onboard JTAG chain). Once testing from system back plane completed, AS91L1001 reconfigured master mode operation through register. master mode operation used test onboard JTAG chain, using microprocessor interface. Master mode: This mode accessed command AS91L1001 register. feature this mode that both Primary Secondary both totally independent IEEE1149.1 masters, which enable concurrent operation both IEEE1149.1 channels. Master mode enables primary IEEE1149.1 channel used access other PCB's connected 5-wire IEEE1149.1 interface back plane. secondary IEEE1149.1 port used test card that hosting AS91L1001. This mode used performing Interconnect testing Flash/CPLD programming.
Features
Interprets between Motorola MPC8260 processor IEEE1149.1 ports Three distinct modes operation: Slave mode, Master mode, Party support mode Supports wide range Party tools Pinout feature compatible (complete second source) with Firecron JTS01 device Available 100-pin LQFP 100-pin FPBGA lead free package
Device Block Diagram
Figure AS91L1001 JTAG Test Controller
Alliance Semiconductor
2575 Augustine Drive Santa Clara, 95054 408-855-4900 408-855-4999 www.alsc.com
AS91L1001
Description (Cont.)
Alliance Semiconductor supplies Windowsexecutable that converts industry standard into Alliance Semiconductor proprietary file format. Users ANSI Code only required provide base read write function stream I/O. order execute file, user call primary function, which will then perform required setup AS91L1001 along with obtaining file process required time report errors applicable. user wishes embed ANSI routines from FPGA/CPLD vendors, then this handled very similar manner. IEEE1149.1 ports will operating Alliance Semiconductor mode, method reading writing data same before. However, user will need consult party routines data flow performed. Ultimately, user will call Alliance Semiconductor provided routine that will AS91L1001 party support IEEE1149.1 channels while other will used executing party code. summary, Party Support mode enables serial shifting data JTAG ports used configure legacy FPGA/CPLD devices.
MPC8260
IEEE 1149.1 secondary port
AS91L1003
AS91L1001
board JTAG chain
Back Plane TRST Back Plane Back Plane Back Plane Back Plane Back Plane Auto-Wr
IEEE 1149.1 primary port
Figure Slave mode
Data Party Data
MPC8260 AS91L1003
AS91L1001
Secondary IEEE1149.1 Port Primary IEEE1149.1 Port
Back Plane TRST Back Plane Back Plane Back Plane Back Plane Back Plane Auto-Wr
Figure Master mode Party Support mode: This mode intended support legacy FPGA/CPLD 1149.1 devices that require adaptive programming algorithms ensure data retention, fact that decision branching supported Service Vector Format (SVF). This mode will required devices that adhere IEEE1532 specification, IEEE1532 compliant parts from CPLD/FPGA vendors adhere this open standard. Party support mode which accessible control registers AS91L1001 selects IEEE1149.1 ports operate with standard SVF->BVF flow while remaining IEEE1149.1 port will support commands embedded Code routines provided FPGA/CPLD vendors. This eliminates issues regarding data retention when using AS91L1001 PCB.
Data Party Data
MPC8260 AS91L1003
AS91L1001
Secondary IEEE1149.1 Port Primary IEEE1149.1 Port
Back Plane TRST Back Plane Back Plane Back Plane Back Plane Back Plane Auto-Wr
Figure Party support mode
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1001
Signal NAME TYPE NUMBER LQFP NUMBER FPBGA DESCRIPTION
RESETn
JTS03_06_SELECTEDn
This active reset signal resets AS91L1001 places device Slave mode This active input from either AS91L1003 AS91L1006 provides control status AS91L1003/06 connected Secondary port AS91L1001 (operating Slave mode) IEEE1149.1 Primary Test Data Input Slave mode; Master mode, this acts Test Data Output IEEE1149.1 Primary Test Data Output Slave mode; Master mode, this acts Test Data Input IEEE1149.1 Primary Test Reset Input Slave mode; Master mode, this output IEEE1149.1 Primary Test Mode Select Slave mode; Master mode, this output IEEE1149.1 Primary Test Clock Slave mode; Master mode, this output Primary Auto-write input controlled test equipment shorten Flash memory programming, signal driven write pulse IEEE1149.1 Test Data Output Secondary port IEEE1149.1 Test Data Input Secondary port IEEE1149.1 Test Logic Reset Secondary port IEEE1149.1 Test Mode Select Secondary port IEEE1149.1 Test Clock Secondary port Secondary Auto-Write Output controlled test equipment shorten Flash memory programming, signal driven write pulse
Primary IEEE1149.1 Port PRIM_TDI INOUT
PRIM_TDO
INOUT
PRIM_TRST
INOUT
PRIM_TMS
INOUT
PRIM_TCK
INOUT
PRIM_AUTOWR
SECONDARY IEEE1149.1 SEC_TDO SEC_TDI SEC_TRST SEC_TMS SEC_TCK SEC_AUTOWR
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1001
TYPE NUMBER LQFP NUMBER FPBGA DESCRIPTION
NAME
SLAVE_MODE
MASTER_MODE
PRIM_TDO_OE
DATA(7:0)
ADDR(31:28)
This signal, when low, indicates that AS91L1001 Slave mode operation This signal, when low, indicates that AS91L1001 Master mode operation This active signal derived while Slave Mode, provides control foradditional current drive buffer primary signal INOUT 98,97,96,94 A3,B3,A4,B4, 8-bit data processor ,9392,85,84 C4,C5,C6,C7( interface LSB-MSB LSB-MSB) 83,81,80,79 B7,A7,B8,A8( 4-bit address processor LSB-MSB LSB-MSB) interface
OSC_IN
POWER 11,26,43,59 ,74,95,2,17, 90,55,56,38 POWER 39,91,3,18, 34,51,66,82 ,23,54
ASIC_TCK ASIC_TMS ASIC_TDO ASIC_TDI
Active low, write enable signal processor interface Active read enable signal processor interface Active low, chip select signal processor interface This master clock into AS91L1001 device Test output enable this signal when taken tristates devices D6,G5,C3,J9, AS91L1001 Ground connection G9,D7,E5,F6, G4,H8,A5,F2, AS91L1001 connection IEEE1149.1 ASIC Test IEEE1149.1 ASIC Test IEEE1149.1 ASIC Test IEEE1149.1 ASIC Test
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1001
TYPE NUMBER NUMBER LQFP FPBGA 1,5,6,7,8,9, C1,B5,E4,E3, 10,12,13,24 E1,E2,A2,B2, ,25,27,28, C2,D3,D1,D2, 29,30,31,32 J1,K1,K2,C9, D8,D10,D9,E ,33, 35,36,37,40 7,E8,J2,K3,J3 ,H4,J4,K4,H5, ,41, 42,44,45,46 J5,K5,K6,J6,H 6,K7,J7,H7,J8 ,47, 48,49,50,52 ,K8,K10,J10, ,53, 67,68,69,70 ,71, 72,89,99,10 DESCRIPTION
NAME
connects
Table AS91L1001 Signal
Absolute Maximum Ratings
Parameter Supply Voltage (Vcc) Input Voltage (Vi) sink current when -0.5V source current when 0.5V Junction Temperature with power applied Storage temperature Maximum Range -0.3V 5.5V -0.5V +0.5V -20mA +20mA +125 degrees +150 degree
Table Absolute Maximum Ratings Note: Stress above stated maximum values cause irreparable damage device, correct operation device these values guaranteed.
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1001
Recommended Operating Conditions
Parameter Supply Voltage (Vcc) Input Voltage (Vi) Output Voltage (Vo) Operating Temperature (Ta) Commercial Industrial (Ta) Operating Range 3.0V 3.6V 3.00V 3.6V Table Recommended Operating Conditions
Electrical Characteristics
Symbol Parameter Minimum High Input Voltage Maximum Input Voltage Parameter Minimum High Output Voltage Minimum Output Voltage Tristate output leakage Maximum quiecennt supply current Maximum dynamic supply current -0.3V 5.25 0.8V Condition
Symbol Iccd
Value 2.4V 0.4V 80mA
Condition Ioh=24mA defined Iol=24mA defined
freq equal
Table AS91L1001 Electrical Characteristics
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1001
Timing Information
From Type Setup Hold Value 18ns -3ns 17ns 11ns 13ns 66MHz 11ns 25ns
Prim_TCK/Sec_TCK Prim/ Inputs Prim_TCK/Sec_TCk OSC_IN OSC_IN OSC_IN OSC_IN Prim inputs inputs output Prim output inputs inputs Databus Prim/Sec Inputs
Prim_TCK/Slave_tck Delay Prim outputs outputs Delay Delay Freq Setup Hold Delay Width (low)
Comb Delay Comb Delay
Table AS91L1001 timing information
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1001
Packaging Information
AS91L1001 available 100-pin LQFP 100-pin FPBGA lead free package.
Square
Square
NOTES ENSIO ILLIM PLAS FLAS TUSIO ALLO ABLE 0.25 SIDE. LEAD PRESENTATIVE CTUAL PACKAG
-C0.09/0.20
0.25
LEAD COPLANARITY
Figure LQFP-100
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1001
REV.
Revisions DESCRIPTION Initial document release. Updated ball coplanarity limits from 0.20mm 0.15mm.
91253
DATE 12-04-01
0.15
SYMBOL PACKAGE NUMBER JEDEC
DIMENSIONS MIN. -0.30 0.25 0.50
NOM. -0.60 11.00 9.00 11.00 9.00 1.00 FBGA0100-11F MO-192 VAR. AAC-1
MAX. 1.70 -1.10 0.70
0.25 0.25
Figure FPBGA-100
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1001
Device Selector Guide Ordering Information
AS91L
Aliance Semiconductor system solution
XXXX
TEMP
Blank leaded lead free green Commercial degrees Industrial (-40 degrees Package L100 LQFP F100 FPBGA Clock speed Frequency High Frequency
Device family 1001 1002 1003 1006 Product version standard 16-bit user code 8-bit status/user code enhanced
Figure Part Numbering Guide
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1001
Part Number AS91L1001S 10L100-C AS91L1001S 10L100-I AS91L1001S 10F100-C AS91L1001S 10F100-I AS91L1001S 40L100-C
Description JTAG Test Controller, 100-pin LQFP package, commercial JTAG Test Controller, 100-pin LQFP package, industrial JTAG Test Controller 100-pin FPBGA package, commercial JTAG Test Controller 100-pin FPBGA package, industrial JTAG Test Controller, 100-pin LQFP package, commercial, High frequency JTAG Test Controller, 100-pin LQFP package, commercial, lead free, High Frequency JTAG Test Controller, 100-pin LQFP package, industrial, High Frequency JTAG Test Controller, 100-pin LQFP package, industrial, lead free, High Frequency JTAG Test Controller 100-pin FPBGA, commercial, High Frequency JTAG Test Controller 100-pin FPBGA, commercial, green package, High Frequency JTAG Test Controller 100-pin FPBGA, industrial, High Frequency JTAG Test Controller 100-pin FPBGA, industrial, green package, High Frequency Table Valid Part Number Combinations
Availability Please contact Alliance Semiconductor Please contact Alliance Semiconductor Please contact Alliance Semiconductor
AS91L1001S 40L100-CF
AS91L1001S 40L100-I
Please contact Alliance Semiconductor
AS91L1001S 40L100-IF
AS91L1001S 40F100-C
Please contact Alliance Semiconductor Please contact Alliance Semiconductor Please contact Alliance Semiconductor Please contact Alliance Semiconductor
AS91L1001S 40F100-CG
AS91L1001S 40F100-I
AS91L1001S 40F100-IG
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1001
Device Master AS91L1001 AS91L1002 AS91L1003U
FPBGA-100 (1mm pitch)
Package Options
LQFP-100
JTAG Test Controller JTAG Test Sequencer 3-Port Gateway
AS91L1006BU 6-Port Gateway
Table JTAG Controller Product Family
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Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
AS91L1001
www.alsc.com
Alliance Semiconductor
2003, 2004 Copyright Alliance Semiconductor Corporation. Rights reserved.
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