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AN122E04 Datasheet Configurable FPAA With Basic
www.anadigm.com
DS030100-U007
Disclaimer
Anadigm reserves right make changes without further notice products herein. Anadigm makes warranty, representation guarantee regarding suitability products particular purpose, does Anadigm assume liability arising application product circuit, specifically disclaims liability, including with limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Anadigm does this document convey license under patent rights rights others. Anadigm software associated products cannot used except strictly accordance with Anadigm software license. terms appropriate Anadigm software license shall prevail over above terms extent inconsistency.
Anadigm® Ltd. 2004 Anadigm®, Inc. 2004 Rights Reserved.
DS030100-U007
AN122E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced
PRODUCT ARCHITECTURE OVERVIEW
AN122E04 device consists matrix fully Configurable Analog Blocks (CABs), surrounded programmable interconnect resources. Configuration data stored on-chip SRAM configuration memory. Compared with first-generation FPAAs, AnadigmVortex architecture provides significantly improved signal-to-noise ratio well higher bandwidth. These devices also accommodate nonlinear functions such sensor response linearization arbitrary waveform synthesis.
AN122E04 devices have four configurable cells that function either input output mode, dedicated output cells. configurable cells dedicated multiplexer which allows maximum seven analog input channels. I/O-intensive applications, this means single FPAA used process multiple channels analog signals where more such devices were previously needed. Byte Look Table (LUT) gives capability arbitrary waveform generation linear functions.
Figure Architectural overview AN122E04 device
PRODUCT FEATURES
Dynamic reconfiguration Four configurable cells Input multiplexer dedicated output cells Fully differential architecture Byte Look-Up Table (LUT) linear functions (eg's. linearization, arbitrary signal generation, companding, arbitrary complex function) Four 8-bit based ADC's that drive address input based signal voltage. Typical Signal Bandwidth: DC-2MHz (Bandwidth dependent) Signal Noise Ratio: Broadband 80dB Narrowband (audio) 100dB Total Harmonic Distortion (THD): 90dB Package: 44-pin (10x10x2mm) Lead pitch 0.8mm Supply voltage: Dynamically reconfigurable FPAA Sample Pack Dynamically reconfigurable FPAA Tray (min 960/box, trays) Dynamically reconfigurable FPAA Tape Reel (1000 pcs) FPAA Development
APPLICATIONS
Real-time software control analog system peripherals Intelligent sensors Adaptive filtering control front-end Adaptive industrial control automation Ultra-low frequency signal conditioning Custom analog signal processing
ORDERING CODES
AN122E04-QFPSP AN122E04-QFPTY AN122E04-QFPTR AN221K04-DVLP2
[For more detailed information features AN122E04 device, please refer AN122E04/AN222E04 User Manual]
DS030100-U007
AN122E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Power Supplies
Symbol
AVdd(2) BVdd DVdd
-0.5 -0.5
Unit
Comment
AVss, BVss, DVss SVss held Ideally supplies should same voltage Still air, heatsink, layer board, pins. 55°C/W
xVDD xVDD Offset Package Power Dissipation Analog Digital Input Voltage Ambient Operating Temperature Storage Temperature
Pmax 25°C Pmax 85°C Vinmax Tstg
Vss-0.5
0.73 Vdd+0.5
Absolute Maximum Power Supply Rating failure mode non-catastrophic volts, will cause reduced operating life time. additional stress caused higher local electric fields within CMOS circuitry induce metal migration, oxide leakage other time/quality related issues.
Recommended Operating Conditions
Parameter
Power Supplies
Symbol
AVdd(2) BVdd DVdd Vina Vind
4.75
5.00
5.25
Unit
Comment
AVss, BVss, DVss SVss held volts above AVss Assume package 55°C/W
Analog Input Voltage. Digital Input Voltage Junction Temp
VMR-1.9
VMR+1.9 DVdd
order calculate junction temperature must first empirically determine current draw (total Idd) design. Once current consumption established then following formula used; °C/W, where ambient temperature. worst case °C/W assumes flow additional heatsink type.
General Digital Characteristics (Vdd degrees.C)
Parameter
Input Voltage Input Voltage High Output Voltage Output Voltage High Input Leakage Current Input Leakage Current Max. Capacitive Load Min. Resistive Load DCLK Frequency ACLK Frequency Clock Duty Cycle
Symbol
Cmax Rmin Fmax Fmax
±12.0
±1.0
Unit
Kohm
Comment
DVdd DVdd DVdd DVdd pins except DCLK DCLK crystal connected on-chip oscillator used maximum load digital output Kohm maximum load digital output Kohm MODE DCLK Divide down prior clock clocks
DS030100-U007
AN122E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced
Detailed Digital Interface Characteristics: 5.0volts LCCb
Parameter
Output Voltage Output Voltage High Max. Capacitive Load Min. Resistive Load Current Sink Current Source
Symbol
Cmax Rmin Isnkmax Isrcmax
Unit
Kohm
Comment
Load 20pF//50Kohm Load 20pF//50Kohm Maximum load Kohm Maximum load Kohm LCCb shorted LCCb shorted
CFGFLG, ACTIVATE
Parameter
Input Voltage Input Voltage High Output Voltage Output Voltage High Output Voltage Output Voltage High Max. Capacitive Load Min. Resistive Load Current Sink Current Source External Resistive Pullup Cmax Rmin Isnkmax Isrcmax Rpullupext Kohm Kohm
Symbol
Unit
Comment
DVdd DVdd load Internal pullup 20pF//50K load Internal pullup 20pF//50K Load External pullup 20pF//50K Load External 5Kohm pullup 20pF//50K Maximum load Kohm Maximum load Kohm shorted shorted only internal pullup deselected
ERRb
Parameter
Input Voltage Input Voltage High Output Voltage Output Voltage High Max. Capacitive Load Min. Resistive Load Current Sink Current Source External Resistive Pullup
Symbol
Cmax Rmin Isnkmax Isrcmax Rpullupext
Unit
Kohm Kohm
Comment
DVdd DVdd
Maximum load Kohm Maximum load Kohm
DCLK, MODE, DIN, EXECUTE, PORb, CS1b, CS2b
Parameter
Input Voltage Input Voltage High
Symbol
Unit
Comment
DVDD DVDD
DS030100-U007
AN122E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced
OUTCLK, DOUTCLK
Parameter
Output Voltage Output Voltage High Max. Capacitive Load Min. Resistive Load Current Sink Current Source
Symbol
Cmax Rmin Isnkmax Isrcmax
Unit
Kohm
Comment
DVdd DVdd Maximum load Kohm Maximum load Kohm
ACLK
Parameter
Input Voltage Input Voltage High Output Voltage Output Voltage High Max. Capacitive Load Min. Resistive Load Current Sink Current Source
Symbol
Cmax Rmin Isnkmax Isrcmax
Unit
Kohm
Comment
DVdd DVdd DVdd DVdd Maximum load Kohm Maximum load Kohm
DS030100-U007
AN122E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced
Analog Inputs General
Parameter
High Precision Input Range Standard precision Input Range High Precision Differential Input Standard Precision Differential Input Common Mode Input Range Input Frequency
Symbol
Vina Vina Vdiffina Vdiffina
+/-3.0 +/-3.8
Unit
Comment
1.5v 1.9v Common mode voltage Common mode voltage
Fain
value clock, input stage dependant. Input frequency limited approx <2MHz signal processing which based sampled data architectures.
High precision operating range provides optimal linearity dynamic range.
Analog Outputs
(See "Output Cell" section AN122E04/AN222E04 user manual more details)
Parameter
High Precision Output Range Standard Precision Output Range High Precision Differential Output Standard precision Differential Output Common Mode Voltage Output Load Output Load Equivalent Input Offset Offset Voltage Temperature Coefficient Output Frequency Output Frequency
Symbol
Vouta Vouta Vdiffouta Vdiffouta Rload Cload Voffsettc Faout
+/-3.0 +/-3.8
Unit
Mohm mV/°C
Comment
1.5v 1.9v Common mode voltage Common mode voltage
realizable output frequency limited approx <2MHz signal processing which based sampled data architectures.
Faout
Power Supply Rejection Ratio Large Signal Harmonic Distortion
PSRR Dist
High precision operating range provides optimal linearity dynamic range. Standard precision operating range provides maximum dynamic range reduced linearity. maximum load analog output Kohms. This load maybe with respect analog ground AVSS. maximum load analog output Kohms. This load must differential with respect analog ground (VMR).
DS030100-U007
AN122E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced
(voltage Rail) VREF (Reference Voltage) Ratings
Parameter
Output Voltage VREF+ Output Voltage VREF- Output Voltage Output Voltage Deviation VREF+, VMR, VREFVoltage Temperature Coefficient VREF+, VMR, VREFPower Supply Rejection Ratio, Power Supply Rejection Ratio Vref+ VrefStart Time
Symbol
Vvmr Vref+ VrefVrefout Vreftc PSSR PSSR Tstart
1.925 0.45
2.01 3.51 0.505
2.075 0.55
Unit
Comment
25°C, Vdd=5.00 volts 25°C, Vdd=5.00 volts 25°C, Vdd=5.00 volts Over process supply voltage corners typical graphical data below -40°C 125°C
Assuming recommended capacitors
Vref- temperature
temperature
2.010 2.005
Volts
0.510 0.505
Volts
2.000 1.995 1.990
Tchip
0.500 0.495 0.490
Tchip
DS030100-U007
AN122E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced
(Configurable Analog Block) Differential Operational Amplifier
Parameter
High Precision Input/Output Range Standard Precision Input/Output Range High Precision. Differential Input/Output Standard Precision Differential Input/Output Common Mode Input Voltage Range Common Mode Output Voltage Range Equivalent Input Voltage Offset.
Symbol
Vinouta Vinouta Vdiffioa Vdiffioa Voffset
+/-3.0 +/-3.8
Unit
Comment
1.5v +/-1.9v Common mode voltage Common mode voltage
Offset Voltage Temperature Coefficient
Voffsettc
µV/°C
Power Supply Rejection Ratio PSSR Common Mode Rejection Ratio CMRR Common Mode Rejection Ratio
CMRR
Differential Slew Rate, Internal Differential Slew Rate, External
Slew Slew
V/µsec V/µsec
Unity Gain Bandwidth, Full Power Mode. Input Impedance, Internal Output Impedance, Internal
Rout
Mohm Ohms
Some CAMs (Configurable Analog Modules) inherently compensate from -40°C 125°C some CAMs (Configurable Analog Modules) inherently compensate Variation between CAMs expected because variations architecture Example GainInv clock 1MHz parameter settings Gain Example Filterbiquad Setting pass filter clock 1MHz parameter settings Gain Corner frequency 50kHz Quality Factor 0.707 Applicable when OpAmp load internal FPAA Applicable when OpAmp driving signal FPAA package Applicable when sourcing loading OpAmp with load internal FPAA OpAmp output designed drive internal nodes, these dominantly capacitive loads Output FPAA output (ouput cell bypass mode). This variable influenced capacitor size, clock frequency architecture
Output Impedance, External Rout Output Load, External Output Load, External Output Load, External Ohms
Rload Cload
Mohm Additional loading causes internal voltage drops across output stage series resistances output stage small signal output impedance approx 10ohm Example1 GainInv clock 1MHz Gain
Rload
Kohm
Output Load, External Noise Figure
Cload Noise
0.13
µV/sqrtHz
DS030100-U007
AN122E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced
Signal-To Noise Ratio Distortion SINAD Input signal=1400 differential Audio frequency range Example. GainInv clock 1MHz Gain Input signal=1400 differential, Audio frequency range Example. GainInv clock 1MHz Gain
Spurious Free Dynamic Range SFDR
High precision operating range provides optimal linearity dynamic range. Standard precision operating range provides maximum dynamic range reduced linearity. maximum load analog output Kohms. This load with respect analog ground AVSS. Using FPAA with Amp's driving directly off-chip, requires care, full characterization performance each application circuit circuit designer necessary. This specification parameter only characterized when circuit topology configured onto differential amplifier architecture. figure provided here representative performance specific CAM, specified comments.
Idealized Open Loop Gain [dB] 1000 100000 Frequency (KHz)
Open Loop Gain (dB)
idealized open loop gain plot provided information only. This information associated with FPAA full power mode operation. FPAA operation amplifier open loop gain cannot observed used when associated with external connections device. Internal reprogrammable routing impedances switched capacitor circuit architecture using this operational amplifier limit effective usable bandwidth circuit realized FPAA less than 2MHz.
DS030100-U007
AN122E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced
(Configurable Analog Block) Differential Comparator
Parameter
Input Range, Internal Input Range, External Differential Input, Internal Differential Input, External Common Mode Output Voltage Range, Internal Common Mode Input Voltage Range, External Common Mode Input Voltage, External Differential Output Single Output (Ox1P) Input Voltage Offset Offset Voltage Temperature Coefficient Setup Time, Internal Setup Time, External Delay Time Output Load Rload Output Load Cload Differential Variable Reference Voltage Settings Differential Hysteresis Differential Hysteresis Differential Hysteresis Differential Hysteresis Hysteresis Setting Accuracy Hysteresis Temperature Coefficient Hysteresis Temperature Coefficient Hysteresis Temperature Coefficient Hysteresis Temperature Coefficient
Symbol
Vina Vina Vdiffina Vdiffina Voutdiff Vout Voffcomp Voffsettc Tsetint Tsetext Tdelay
+/-3.8 +/-5
Unit
µV/°C nsec nsec nsec Kohm
Comment
Common mode voltage
comparator will function correctly
Zero hysteresis from -40°C 125°C, Zero Hysteresis
Voffcomp
+/-4.0
µV/°C µV/°C µV/°C µV/°C
1/Fc master clock frequency Applies comparator drive chip with output cell bypass mode Applies comparator drive chip with output cell bypass mode
CompVref Hysta1 Hysta2 Hysta3 Hysta4 Hystb Hysttc1 Hysttc2 Hysttc3 Hysttc4
Hysteresis setting zero Hysteresis setting 10mV Hysteresis setting 20mV Hysteresis setting 40mV Hysteresis setting zero Hysteresis setting 10mV Hysteresis setting 20mV Hysteresis setting 40mV
High precision operating range provides optimal linearity dynamic range. Standard precision operating range provides maximum dynamic range reduced linearity.
Characteristics
DS030100-U007
AN122E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced
Type Human Body Model
4000V 4000V 4000V 4000V 2000V 1500V 1500V
Machine Model
250V 250V 250V 250V 200V 100V 100V
Charged Device Model
Digital Inputs Digital Outputs Digital Bidirectional Digital Open Drain Analog Inputs Analog Outputs Reference Voltages
AN122E04 (electrostatic discharge) sensitive device. Electrostatic charges high 4000V readily accumulate human body test equipment discharge without detection. Although AN122E04 device features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
Power Consumption Power Mode
Minimum Power Nominal Power Nominal Power Nominal Power1d Maximum Power1e
Vdd=5.00 volts, Tj=25°C Vdd=5.00 volts, Tj=25°C Vdd=5.00 volts, Tj=25°C Vdd=5.00 volts, Tj=25°C Vdd=4.75 volts, Tj=85°C Vdd=5.00 volts, Tj=25°C Vdd=5.25 volts, -40°C
Temperature Coefficient Minimum Power µA/°C Vdd=5.00 volts, Tj=25°C
Power Consumption Utilization
External clock, analog function disabled, memory active. FPAA active elements core op-amps (low power mode), comparator FPAA active elements Four core op-amps (low power mode), comparators (one using SAR),. FPAA active elements core op-amps (low power mode), three comparators (two using SAR). FPAA active elements Eight core op-amps (low power mode), four comparators (two using SAR),.
80.00 70.00 60.00
Vdd=4.75V
Vdd=5.0V
Vdd=5.25V
Idd[m
50.00 40.00 30.00 20.00 10.00
100%
Resources Utilization
Power Consumption Full Power Mode
Parameter
Full Power Mode Minimum Power Full Power Mode Nominal Power2b Full Power Mode Nominal Power2c Full Power Mode Nominal Power2d Full Power Mode Maximum Power2e
Symbol
Unit
Comment
Vdd=5.00 volts, Tj=25°C Vdd=5.00 volts, Tj=25°C Vdd=5.00 volts, Tj=25°C Vdd=5.00 volts, Tj=25°C Vdd=4.75 volts, Tj=85°C Vdd=5.00 volts, Tj=25°C Vdd=5.25 volts, -40°C
Power Consumption FULL Utilization
80.00
AN122E04 Crystal Oscillator, analog functions disabled, memory active. FPAA active elements core op-amps, comparator,. FPAA active elements Four core op-amps, comparators (one using SAR. FPAA active elements core op-amps, three comparators (two using SAR). FPAA active elements Eight core op-amps, four comparators (two using SAR).
70.00 60.00
Vdd=4.75V Vdd=5.0V Vdd=5.25V
Idd[mA]
50.00 40.00 30.00 20.00 10.00
100%
Resources Utilization
DS030100-U007
AN122E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced
PINOUT
Numb
Name
IO4PA IO4NA AVSS AVDD IO1P IO1N IO2P IO2N SHIELD AVDD2 VREFMC VREFPC VMRC BVDD BVSS CFGFLGb CS2b CS1b DCLK SVSS MODE ACLK OUTCLK DVDD DVSS LCCb ERRb ACTIVATE DOUTCLK PORb EXECUTE IO3P IO3N IO4PD IO4ND IO4PC IO4NC IO4PB IO4NB
Type
Analog IN/OUT+ Analog IN/OUT Analog OUT+ Analog OUTAnalog Analog Analog Analog Analog IN/OUT Analog IN/OUT Analog IN/OUT Analog IN/OUT Analog Analog Vref Vref Vref Analog Analog Digital (open drain) Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital (optional pull-up) Digital Digital (open drain) Digital (open drain) Digital Digital (open drain) Digital Analog IN/OUT+ Analog IN/OUT Analog IN/OUT Analog IN/OUT Analog IN/OUT Analog IN/OUT Analog IN/OUT Analog IN/OUT
Comments
Volts Volts
noise bias capacitor array n-wells: Volts Analog power: Volts Attach filter capacitor VREFAttach filter capacitor VREF+ Attach filter capacitor (Voltage Main Reference) Analog power bandgap Vref Generators: Volts Analog ground bandgap Vref Generators Volts Configuration Flag. Indicates configuration progress. Chip Select Chip Select Configuration data strobe Digital ground substrate tie: Volts Select configuration mode Analog sample clock PROM configuration clock Programmable digital output Volts Volts Serial configuration data input Local Configuration Complete Configuration error signal Enables primary configuration shadow primary transfer buffered version DCLK. Power Reset minimum pulse width required PORb 25ns. External shadow primary transfer
Analog multiplexer input signals. multiplexer accept differential inputs Analog multiplexer input signals. multiplexer accept differential inputs
DS030100-U007
AN122E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced
MECHANICAL HANDLING
AN122E04 comes industry standard lead package. pack handling recommended. package qualified MSL3 (JEDEC Standard, J-STD-020A, Level Once device removed from pack, 30°C humidity longer than hours maximum recommended exposure prior solder reflow. pack longer than this recommended period time, then recommended bake procedure prior solder reflow hours 125°C.
DS030100-U007
AN122E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced
Distortion, SINAD Measurements
following plots give indication Distortion, SINAD example CAM.
SNR[dB]
SINAD[dB]
DISTN[dB]
GAININV SNR, DSTN, SINAD This graph shows typical performance FPAA when configured with this example GainInv Input signal=1400 differential, clock 1MHz parameter settings Gain
[dB]
-100 -120
INPUT [Vp-p]
Power Supply Rejection Ratio (PSRR) Measurements
following plots give indication PSRR some representative CAMs. AVDD Power Supply (PS): 0.25v sinusoidal waveform (100 MHz)
VMR, Vref+, Vref100.00 90.00 80.00 70.00 60.00 50.00 40.00 30.00 20.00 1KHz
PSRR [dB]
PSRR_VMR PSRR_VREFP PSRR_VREFP
10KHz
100KHz
GAININV_1MHz PSRR [dB]
1KHz 10KHz 100KHz
GAININV_4MHz PSRR [dB]
1KHz
10KHz
100KHz
DS030100-U007
AN122E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced
following provided information only, when additional characterization data collected `noise measurements' will added formally datasheet.
Noise Distortion Observations
following plots give indication noise characteristics Anadigm®'s AN122E04 FPAA device. These were done using simple set-up many cases reflect noise limit setup. Actual device noise margins expected better.
DS030100-U007
AN122E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced
DS030100-U007

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