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XC2C256 CoolRunner-II CPLD DS094 (v2.4) August 2004 Prelimin


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XC2C256 CoolRunner-II CPLD
DS094 (v2.4) August 2004
Preliminary Product Specification
Features
Optimized 1.8V systems fast pin-to-pin delays quiescent current Industry's best 0.18 micron CMOS CPLD Optimized architecture effective logic synthesis. Refer CoolRunnerTM-II family data sheet architecture description. Multi-voltage operation 1.5V 3.3V Available multiple package options 100-pin VQFP with user 144-pin TQFP with user 132-ball (0.5mm) with user 208-pin PQFP with user 256-ball (1.0mm) with user Pb-free available packages Advanced system features Fastest system programming 1.8V using IEEE 1532 (JTAG) interface IEEE1149.1 JTAG Boundary Scan Test Optional Schmitt-trigger input (per pin) Unsurpassed power management DataGATE enable (DGE) signal control separate output banks RealDigital 100% CMOS product term generation Flexible clocking modes Optional DualEDGE triggered registers Clock divider (divide 2,4,6,8,10,12,14,16) CoolCLOCK Global signal options with macrocell control Multiple global clocks with phase selection macrocell Multiple global output enables Global set/reset Advanced design security architecture Superior pinout retention 100% product term routability across function block Open-drain output option Wired-OR drive Optional bus-hold, 3-state weak pull-up selected pins Optional configurable grounds unused I/Os Mixed voltages compatible with 1.5V, 1.8V, 2.5V, 3.3V logic levels SSTL2-1, SSTL3-1, HSTL-1 compatibility pluggable
Description
CoolRunnerTM-II 256-macrocell device designed both high performance power applications. This lends power savings high-end communication equipment high speed battery operated devices. power stand-by dynamic operation, overall system reliability improved This device consists sixteen Function Blocks inter-connected power Advanced Interconnect Matrix (AIM). feeds true complement inputs each Function Block. Function Blocks consist P-term macrocells which contain numerous configuration bits that allow combinational registered modes operation. Additionally, these registers globally reset preset configured flip-flop latch. There also multiple clock signals, both global local product term types, configured macrocell basis. Output configurations include slew rate limit, hold, pull-up, open drain programmable grounds. Schmitt-trigger input available input basis. addition storing macrocell output states, macrocell registers configured "direct input" registers store signals directly from input pins. Clocking available global Function Block basis. Three global clocks available Function Blocks synchronous clock source. Macrocell registers individually configured power zero state. global set/reset control line also available asynchronously reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset output enable signals formed using product terms per-macrocell per-Function Block basis. DualEDGE flip-flop feature also available macrocell basis. This feature allows high performance synchronous operation based lower frequency clocking help reduce total power consumption device. Circuitry also been included divide externally supplied global clock (GCK2) eight different selections. This yields divide even clock frequencies. clock divide (division DualEDGE flip-flop gives resultant CoolCLOCK feature. DataGATE method selectively disable inputs CPLD that interest during certain points time.
2002 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, disclaimers listed other trademarks registered trademarks property their respective owners. specifications subject change without notice.
DS094 (v2.4) August 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD mapping signal DataGATE function, lower power achieved reduction signal switching. Another feature that eases voltage translation output banking. output banks available CoolRunner-II macrocell device that permits easy interfacing 3.3V, 2.5V, 1.8V, 1.5V devices. CoolRunner-II macrocell CPLD compatible with various standards (see Table This device also 1.5V compatible with Schmitt-trigger inputs.
standard voltages. LVTTL standard general purpose EIA/JEDEC standard 3.3V applications that LVTTL input buffer Push-Pull output buffer. LVCMOS standard used 3.3V, 2.5V, 1.8V applications. Both HSTL SSTL standards make VREF JEDEC compliance. CoolRunner-II CPLDs also 1.5V compatible with Schmitt-trigger inputs Table Standards XC2C256 Output VCCIO Input VCCIO Board Input Termination VREF Voltage 0.75 1.25 0.75 1.25
RealDigital Design Technology
Xilinx CoolRunner-II CPLDs fabricated 0.18 micron process technology which derived from leading edge FPGA product development. CoolRunner-II CPLDs employ RealDigital, design technique that makes CMOS technology both fabrication design methodology. RealDigital design technology employs cascade CMOS gates implement products instead traditional sense amplifier methodology. this technology, Xilinx CoolRunner-II CPLDs achieve both high-performance power operation.
Types LVTTL LVCMOS33 LVCMOS25 LVCMOS18 1.5V HSTL-1 SSTL2-1 SSTL3-1
information Vref, XAPP399.
Supported Standards
CoolRunner-II macrocell features LVCMOS, LVTTL, SSTL HSTL implementations. Table
(mA)
30DS094_01_030102
Frequency (MHz)
Figure Frequency Table Frequency (LVCMOS 1.8V 25°C)(1) Frequency (MHz) Typical (mA) Typical (mA)
Notes: 16-bit up/down, resettable binary counter (one counter function block).
11.68
19.4
27.01
38.18
45.54
56.32
63.37
70.4
80.9
88.03
0.021
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DS094 (v2.4) August 2004 Preliminary Product Specification
XC2C256 CoolRunner-II CPLD
Absolute Maximum Ratings
Symbol VCCIO VJTAG(2) VAUX VIN(1) VTS(1) TSTG(3) Description Supply voltage relative ground Supply voltage output drivers JTAG input voltage limits JTAG input supply voltage Input voltage relative ground Voltage applied 3-state output Storage Temperature (ambient) Junction Temperature Value -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 +150 +150 Units
Notes: Maximum undershoot below must limited either 0.5V whichever easiest achieve. During transitions, device pins undershoot -2.0v overshoot +4.5V, provided this over undershoot lasts less than with forcing current being limited Valid over commercial temperature range. soldering guidelines thermal considerations, Device Packaging information Xilinx website. free packages, XAPP427.
Recommended Operating Conditions
Symbol VCCIO Parameter Supply voltage internal logic input buffers Commercial +70°C Industrial -40°C +85°C Units
Supply voltage output drivers 3.3V operation Supply voltage output drivers 2.5V operation Supply voltage output drivers 1.8V operation Supply voltage output drivers 1.5V operation
VAUX
JTAG programming
Electrical Characteristics (Over Recommended Operating Conditions)
Symbol ICCSB ICCSB ICCSB CJTAG CCLK Parameter Standby current (-5) Standby current (-6, Standby current industrial) Dynamic current (-6, Dynamic current (-5) JTAG input capacitance Global clock input capacitance capacitance Test Conditions 1.9V, VCCIO 3.6V 1.9V, VCCIO 3.6V 1.9V, VCCIO 3.6V Typical Max. Units
DS094 (v2.4) August 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
Symbol
Parameter Input leakage current High-Z leakage
Test Conditions VCCIO 3.9V VCCIO 3.9V
Typical
Max.
Units
Notes: 16-bit up/down, resettable binary counter (one counter function block) tested VCC= VCCIO 1.9V Quality Reliability section CoolRunner-II family data sheet
LVCMOS 3.3V LVTTL 3.3V Voltage Specifications
Symbol VCCIO Parameter Input source voltage High level input voltage level input voltage High level output voltage level output voltage VCCIO -0.1 VCCIO VCCIO VCCIO Test Conditions Min. -0.3 VCCIO 0.4V VCCIO 0.2V Max. Units
LVCMOS 2.5V Voltage Specifications
Symbol VCCIO Parameter Input source voltage High level input voltage level input voltage High level output voltage level output voltage VCCIO 2.3V -0.1 VCCIO 2.3V VCCIO 2.3V VCCIO 2.3V Test Conditions Min. -0.3 VCCIO 0.4V VCCIO 0.2V Max. Units
LVCMOS 1.8V Voltage Specifications
Symbol VCCIO Parameter Input source voltage High level input voltage level input voltage High level output voltage level output voltage VCCIO 1.7V -0.1 VCCIO 1.7V VCCIO 1.7V VCCIO 1.7V Test Conditions Min. 0.65 VCCIO -0.3 VCCIO 0.45 VCCIO Max. 0.35 VCCIO 0.45 Units
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DS094 (v2.4) August 2004 Preliminary Product Specification
XC2C256 CoolRunner-II CPLD
1.5V Voltage Specifications(1)
Symbol VCCIO VTVOH High level output voltage level output voltage VCCIO 1.4V -0.1 VCCIO 1.4V VCCIO 1.4V VCCIO 1.4V
Notes: Hysteresis used 1.5V inputs.
Parameter Input source voltage Input hysteresis threshold voltage
Test Conditions
Min. VCCIO VCCIO VCCIO 0.45 VCCIO
Max. VCCIO VCCIO
Units
Schmitt Trigger Input Voltage Specifications
Symbol VCCIO VTParameter Input source voltage Input hysteresis threshold voltage Test Conditions Min. VCCIO VCCIO Max. VCCIO VCCIO Units
SSTL2-1 Voltage Specifications
Symbol VCCIO VREF(1) VTT(2) Parameter Input source voltage Input reference voltage Termination voltage High level input voltage level input voltage High level output voltage level output voltage VCCIO 2.3V VCCIO 2.3V Test Conditions Min. 1.15 VREF 0.04 VREF 0.18 -0.3 VCCIO 0.62 1.25 1.25 Max. 1.35 VREF 0.04 VREF 0.18 0.54 Units
Notes: VREF should track variations VCCIO, also peak peak noise VREF exceed VREF transmitting device must track VREF receiving devices
DS094 (v2.4) August 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
SSTL3-1 Voltage Specifications
Symbol VCCIO VREF(1) VTT(2) Parameter Input source voltage Input reference voltage Termination voltage High level input voltage level input voltage High level output voltage level output voltage VCCIO VCCIO Test Conditions Min. VREF 0.05 VREF -0.3 VCCIO Max. VREF 0.05 VCCIO VREF Units
Notes: VREF should track variations VCCIO, also peak peak noise VREF exceed VREF transmitting device must track VREF receiving devices
HSTL1 Voltage Specifications
Symbol VCCIO VREF(1) VTT(2) Parameter Input source voltage Input reference voltage Termination voltage High level input voltage level input voltage High level output voltage level output voltage VCCIO 1.7V VCCIO 1.7V Test Conditions Min. 0.68 VREF -0.3 VCCIO 0.75 VCCIO Max. 0.90 VREF Units
Notes: VREF should track variations VCCIO, also peak-to-peak noise VREF exceed VREF transmitting device must track VREF receiving devices
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DS094 (v2.4) August 2004 Preliminary Product Specification
XC2C256 CoolRunner-II CPLD
Electrical Characteristics Over Recommended Operating Conditions
-5(5) Symbol TPD1 TPD2 TSUD TSU1 TSU2 FTOGGLE
Min. Max. Min.
Max. Units
Parameter Propagation delay single p-term Propagation delay array Direct input register clock setup time Setup time (single p-term) Setup time array) Direct input register hold time P-term hold time Clock output Internal toggle rate Maximum system frequency Maximum system frequency Maximum external frequency Maximum external frequency Direct input register p-term clock setup time P-term clock setup time (single p-term) P-term clock setup time array) Direct input register p-term clock hold time P-term clock hold P-term clock output Global output enable/disable P-term output enable/disable Macrocell driven output enable/disable P-term set/reset output valid Global set/reset output valid Register clock enable setup time Register clock enable hold time Global clock pulse width High P-term pulse width High Set-up before DataGATE latch assertion Hold DataGATE latch assertion DataGATE recovery data DataGATE pulse width CDRST setup time before falling edge GCLK2
Min.
Max.
FSYSTEM1 FSYSTEM2 FEXT1 FEXT2
TPSUD TPSU1 TPSU2 TPHD TPCO TOE/TOD TPOE/TPOD TMOE/TMOD TPAO TSUEC THEC TPCW TDGSU TDGH TDGR TDGW TCDRSU
DS094 (v2.4) August 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
-5(5) Symbol TCDRH TCONFIG
Min. Max. Min.
Max. Units
Parameter Hold time CDRST after falling edge GCLK2 Configuration time
Min.
Max.
Notes: FTOGGLE maximum clock frequency which T-Flip Flop reliably toggle (see CoolRunner-II family data sheet more information). FSYSTEM1 (1/TCYCLE) internal operating frequency device fully populated with 16-bit counter through p-term macrocell while FSYSTEM2 through array. FEXT1 (1/TSU1+TCO) maximum external frequency using p-term while FEXT2 through array. Typical configuration current during TCONFIG approximately speed grade Advanced Specification.
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DS094 (v2.4) August 2004 Preliminary Product Specification
XC2C256 CoolRunner-II CPLD
Internal Timing Parameters
-5(1) Symbol
Buffer Delays
Max. Min. Max. Min.
Max. Units
Parameter(2) Input buffer delay Direct data register input delay Global Clock buffer delay Global set/reset buffer delay Global 3-state buffer delay Output buffer delay Output buffer enable/disable delay Control term delay Single P-term delay adder Multiple P-term delay adder Input output valid Setup before clock Hold after clock Enable clock setup time Enable clock hold time Clock output valid Set/reset output valid Clock doubler delay Feedback delay Macrocell global delay Standard input adder Hysteresis input adder Output adder Output slew rate adder Hysteresis input adder Output adder Output slew rate adder
Min.
TDIN TGCK TGSR TGTS TOUT
P-term Delays
TLOGI1 TLOGI2 TPDI TSUI TECSU TECHO TCOI TAOI TCDBL TOEM TIN15 THYS15 TOUT15 TSLEW15 THYS18 TOUT18 TSLEW
Macrocell Delay
Feedback Delays
Standard Time Adder Delays 1.5V
Standard Time Adder Delays 1.8V CMOS
DS094 (v2.4) August 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
Internal Timing Parameters (Continued)
-5(1) Symbol TIN25 THYS25 TOUT25 TSLEW25 TIN33 THYS33 TOUT33 TSLEW33 SSTL2-1 Parameter(2) Standard input adder Hysteresis input adder Output adder Output slew rate adder Standard input adder Hysteresis input adder Output adder Output slew rate adder Input adder TIN, TDIN, TGCK, TGSR,TGTS Output adder TOUT SSTL3-1 Input adder TIN, TDIN, TGCK, TGSR,TGTS Output adder TOUT HSTL-1 Input adder TIN, TDIN, TGCK, TGSR,TGTS Output adder TOUT
Notes: speed grade Advanced Specification. input signal rise/fall.
Max. -0.5 -0.5 Min.
Max. -0.5 -0.5 Min.
Min.
Max.
Units
Standard Time Adder Delays 2.5V CMOS
Standard Time Adder Delays 3.3V CMOS/TTL
Standard Time Adder Delays HSTL, SSTL
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DS094 (v2.4) August 2004 Preliminary Product Specification
XC2C256 CoolRunner-II CPLD
Switching Characteristics
VCCIO 1.8V, 25oC
Test Circuit
Device Under Test
Test Point
TPD2 (ns)
Output Type
112.5
112.5
35pF 35pF 35pF
LVTTL33 LVCMOS33 LVCMOS25
LVCMOS18 LVCMOS15
includes test fixtures probe capacitance. nsec maximum rise/fall times inputs.
DS_ACT_08_14_02
Number Outputs Switching
DS092_02_092302
Figure Load Circuit
Figure Derating Curve
3.3V
(Output Current
1.8V
2.5V
1.5V
(Output Volts)
XC256_VoIo_all_020703
Figure Typical Curve XC2C256
DS094 (v2.4) August 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
Descriptions
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank
Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank
1(GSR) 2(GTS2) 2(GTS3) 2(GTS0) 2(GTS1)
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DS094 (v2.4) August 2004 Preliminary Product Specification
XC2C256 CoolRunner-II CPLD
Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank
Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank
5(GCK1) 5(GCK0) (CDRST) 6(GCK2) 6(DGE)
DS094 (v2.4) August 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank
Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank
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DS094 (v2.4) August 2004 Preliminary Product Specification
XC2C256 CoolRunner-II CPLD
Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank
Descriptions (Continued)
Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank
Notes: global output enable, global reset/set, global clock, CDRST clock divide reset, DataGATE enable.
DS094 (v2.4) August 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
XC2C256 JTAG, Power/Ground, Connect Pins Total User
Type VAUX (JTAG supply voltage) Power internal (VCC) Power Bank (VCCIO1) Power Bank (VCCIO2) Ground VQ100 CP132 K12, G14, A14, N12, J14, H14, E14, B14, TQ144 109, 127, 108, 123, PQ208 105, 133, 157, 172, 181, 104, 129, 130, 141, 156, 177, 190, FT256 K13, D12, J11, K11, L10, F10, F11, G10, H10, J10, K10, L11, M10, T11, T12, T13, P11, T14, J16, K12, D16, G12, C15, D14,
connects
Total user
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DS094 (v2.4) August 2004 Preliminary Product Specification
XC2C256 CoolRunner-II CPLD
Ordering Information
Commercia Part Number XC2C256-5VQ100C(2) XC2C256-6VQ100C XC2C256-7VQ100C XC2C256-5CP132C(2) XC2C256-6CP132C XC2C256-7CP132C XC2C256-5TQ144C(2) XC2C256-6TQ144C XC2C256-7TQ144C XC2C256-5PQ208C(2) XC2C256-6PQ208C XC2C256-7PQ208C XC2C256-5FT256C(2) XC2C256-6FT256C XC2C256-7FT256C XC2C256-5VQG100C(2) XC2C256-6VQG100C XC2C256-7VQG100C XC2C256-5CPG132C(2) XC2C256-6CPG132C XC2C256-7CPG132C XC2C256-5TQG144C(2) XC2C256-6TQG144C XC2C256-7TQG144C XC2C256-5PQG208C(2) Pin/Ball Spacing 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 1.0mm 1.0mm 1.0mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm (C/Watt) (C/Watt) 43.1 43.1 43.1 65.0 65.0 65.0 37.2 37.2 37.2 36.9 36.9 36.9 34.6 34.6 34.6 43.1 43.1 43.1 65.0 65.0 65.0 37.2 37.2 37.2 36.9 10.9 10.9 10.9 15.0 15.0 15.0 10.9 10.9 10.9 15.0 15.0 15.0 Package Type Very Thin Quad Flat Pack Very Thin Quad Flat Pack Very Thin Quad Flat Pack Chip Scale Package Chip Scale Package Chip Scale Package Thin Quad Flat Pack Thin Quad Flat Pack Thin Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Fine Pitch Thin Fine Pitch Thin Fine Pitch Thin Very Thin Quad Flat Pack; Pb-free Very Thin Quad Flat Pack; Pb-free Very Thin Quad Flat Pack; Pb-free Chip Scale Package; Pb-free Chip Scale Package; Pb-free Chip Scale Package; Pb-free Thin Quad Flat Pack; Pb-free Thin Quad Flat Pack; Pb-free Thin Quad Flat Pack; Pb-free Plastic Quad Flat Pack; Pb-free Package Body Dimensions 14mm 14mm 14mm 14mm 14mm 14mm 20mm 20mm 20mm 20mm 20mm 20mm 28mm 28mm 28mm 28mm 28mm 28mm 17mm 17mm 17mm 17mm 17mm 17mm 14mm 14mm 14mm 14mm 14mm 14mm 20mm 20mm 20mm 20mm 20mm 20mm 28mm 28mm Industrial (I)(1)
DS094 (v2.4) August 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
Commercia Part Number XC2C256-6PQG208C XC2C256-7PQG208C XC2C256-5FTG256C(2) XC2C256-6FTG256C XC2C256-7FTG256C XC2C256-7VQ100I XC2C256-7CP132I XC2C256-7TQ144I XC2C256-7PQ208I XC2C256-7FT256I XC2C256-7VQG100I XC2C256-7CPG132I XC2C256-7TQG144I XC2C256-7PQG208I XC2C256-7FTG256I Pin/Ball Spacing 0.5mm 0.5mm 1.0mm 1.0mm 1.0mm 0.5mm 0.5mm 0.5mm 0.5mm 1.0mm 0.5mm 0.5mm 0.5mm 0.5mm 1.0mm (C/Watt) (C/Watt) 36.9 36.9 34.6 34.6 34.6 43.1 65.0 37.2 36.9 34.6 43.1 65.0 37.2 36.9 34.6 10.9 15.0 10.9 15.0 Package Type Plastic Quad Flat Pack; Pb-free Plastic Quad Flat Pack; Pb-free Fine Pitch Thin BGA; Pb-free Fine Pitch Thin BGA; Pb-free Fine Pitch Thin BGA; Pb-free Very Thin Quad Flat Pack Chip Scale Package Thin Quad Flat Pack Plastic Quad Flat Pack Fine Pitch Thin Very Thin Quad Flat Pack; Pb-free Chip Scale Package; Pb-free Thin Quad Flat Pack; Pb-free Plastic Quad Flat Pack; Pb-free Fine Pitch Thin BGA; Pb-free Package Body Dimensions 28mm 28mm 28mm 28mm 17mm 17mm 17mm 17mm 17mm 17mm 14mm 14mm 20mm 20mm 28mm 28mm 17mm 17mm 14mm 14mm 20mm 20mm 28mm 28mm 17mm 17mm Industrial (I)(1)
Notes: Commercial +70°C); Industrial -40°C +85°C) Inquire with your local sales representative availability this part.
Standard Example: XC2C128 Device Speed Grade Package Type Number Pins Temperature Range
Pb-Free Example: XC2C128 Device Speed Grade Package Type Pb-Free Number Pins Temperature Range
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DS094 (v2.4) August 2004 Preliminary Product Specification
XC2C256 CoolRunner-II CPLD
Device Part Marking
Device Type Package Speed Operating Range
XC2Cxxx TQ144
This line related device part number
Part marking non-chip scale package
Figure Sample Package with Part Marking
Note: small size chip scale packages, complete ordering part number cannot included package marking. Part marking chip scale packages line are: Line (Xilinx logo) then truncated part number Line related device part number Line related device part number Line Package code, speed, operating temperature, three digits related device part number. Package codes: CP132, CPG132.
DS094 (v2.4) August 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
I/O(2) I/O(5) VCCIO1
I/O(1) I/O(1) I/O(1) I/O(1) VAUX VCCIO1 I/O(2) I/O(2) I/O(4)
VCCIO2
VCCIO2
I/O(3)
VQ100 View
VCCIO1
Global Output Enable Global Clock Global Set/Reset Clock Divide Reset Data Gate
Figure VQ100 Very Thin Quad Flat Pack
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DS094 (v2.4) August 2004 Preliminary Product Specification
XC2C256 CoolRunner-II CPLD
VCCIO1
I/O(5) I/O(2)
VCCIO1
I/O(4)
I/O(2)
I/O(2)
VCCIO1
CP132 Bottom View
VCCIO1
VAUX
I/O(1)
I/O(1)
VCCIO2
I/O(1)
I/O(1)
I/O(3)
VCCIO2
VCCIO2
Global Output Enable Global Clock Global Set/Reset Clock Divide Reset DataGATE Enable
Figure CP132 Chip Scale Package
DS094 (v2.4) August 2004 Preliminary Product Specification
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XC2C256 CoolRunner-II CPLD
I/O(1) I/O(1) I/O(1) I/O(1) VAUX VCCIO1 I/O(2) I/O(2) I/O(4)
I/O(3) VCCIO2 VCCIO2 VCCIO2
TQ144 View
VCCIO1 VCCIO1
I/O(2) I/O(5)
Figure TQ144 Thin Quad Flat Pack
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VCCIO1
Global Output Enable Global Clock Global Set/Reset Clock Divide Reset DataGATE Enable
DS094 (v2.4) August 2004 Preliminary Product Specification
XC2C256 CoolRunner-II CPLD
I/O(1) I/O(1) I/O(1) I/O(1) VAUX VCCIO2 VCCIO1 I/O(2) I/O(2) I/O(4)
I/O(3) VCCIO2 VCCIO2 VCCIO2 VCCIO2
PQ208 View
DS094 (v2.4) August 2004 Preliminary Product Specification
I/O(2) I/O(5) VCCIO1 VCCIO1 VCCIO1
VCCIO2 VCCIO1 VCCIO1
Global Output Enable Global Clock Global Set/Reset Clock Divide Reset DataGATE Enable
Figure PQ208 Quad Flat Package
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XC2C256 CoolRunner-II CPLD
I/O(2) I/O(4) I/O(5)
I/O(3)
I/O(1)
I/O(1)
I/O(1)
I/O(1)
VCCIO2 VCCIO2 VCCIO2 VCCIO2
VAUX
VCCIO2
VCCIO2
VCCIO2
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1 VCCIO1 VCCIO1 VCCIO1
I/O(2)
I/O(2)
FT256 Bottom View
Global Output Enable Global Clock Global Set/Reset Clock Divide Reset DataGATE Enable
Figure FT256 Fine Pitch Thin
Additional Information
CoolRunner-II Datasheets Application Notes Device Packages
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DS094 (v2.4) August 2004 Preliminary Product Specification
XC2C256 CoolRunner-II CPLD
Revision History
following table shows revision history this document. Date 05/09/02 05/13/02 10/31/02 03/17/03 04/02/03 01/26/04 02/26/04 08/03/04 Version Initial Xilinx release. Updated Electrical Characteristics added parameters. Corrected package user I/O, added Voltage Referenced tables. Added Characterization numbers product release device part marking Updated TSOL from 220. Changed ICCSB units from Updated Device Part Marking. Updated links Tsol. Corrected Theta value XC2C256-7TQ144. Pb-free documentation Revision
DS094 (v2.4) August 2004 Preliminary Product Specification
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OSM57LZG71D - OSM57LZG71D   OSM57LZG71D Datasheet
LSR102 - LSR102   LSR102 Datasheet
LSR106 - LSR106   LSR106 Datasheet
LPC9040N - LPC9040N   LPC9040N Datasheet
74LVC2G34 - 74LVC2G34   74LVC2G34 Datasheet
2SC3647 - 2SC3647   2SC3647 Datasheet

 

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