GC4114 QUAD TRANSMIT CHIP 2000 This datasheet contains

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SLWS134
GC4114
QUAD TRANSMIT CHIP
2000
This datasheet contains information which changed time without notice.
GC4114 QUAD TRANSMIT CHIP
DATA SHEET
REVISION HISTORY
Revision
Date
April 1998 July, 1998 May, 2000 Original
Description
Page added 55531C mask revision table, Page tCDLY changed from 40ns. Upgraded clock rate throughout Page revised timing specifications: Fck, tDLY, tHD,tSSU, tSHD, tCDLY, Notes. Pages Changed Notes diagnostics Page Corrected input test Table
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2000
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GC4114 QUAD TRANSMIT CHIP
DATA SHEET
3.10 3.11 3.12
FEATURES.1 BLOCK DIAGRAM FUNCTIONAL DESCRIPTION
CONTROL INTERFACE. INPUT FORMAT. GAIN. UP-CONVERTERS OVERALL INTERPOLATION FILTER RESPONSE TREE. OVERALL GAIN CLOCKING. SYNCHRONIZATION. POWER DOWN MODES DIAGNOSTICS. INITIAL BOARD DEBUG PROCEDURE.
5.10 5.11 5.12 5.13 5.14 5.15
PACKAGING CONTROL REGISTERS.14
SYNC MODE REGISTER INTERPOLATION MODE REGISTER INTERPOLATION GAIN REGISTER INTERPOLATION REGISTERS. INPUT MODE REGISTER. COUNTER MODE REGISTER. CHANNEL SYNC REGISTERS. CHANNEL FLUSH CONTROL REGISTER. SUMMER MODE REGISTER STATUS CONTROL REGISTER CHECKSUM REGISTER. CHANNEL INPUT REGISTERS. PAGE ZERO (CHANNEL CONTROL) REGISTERS. PAGE (STATUS TEST) REGISTERS. PAGES THREE (COEFFICIENT) REGISTERS.
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS. THERMAL CHARACTERISTICS CHARACTERISTICS CHARACTERISTICS.
APPLICATION NOTES.27
POWER GROUND CONNECTIONS. STATIC SENSITIVE DEVICE. SYNCHRONIZING MULTIPLE GC4114 CHIPS THERMAL MANAGEMENT. PULSE SHAPING MODULATING QPSK DATA. DIAGNOSTICS. OUTPUT TEST CONFIGURATION INPUT TEST CONFIGURATION PERIODIC SYNC MODE
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2000
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GC4114 QUAD TRANSMIT CHIP
DATA SHEET
LIST FIGURES
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure GC4114 Block Diagram Control Timing Serial Input Formats. Up-converter Channel. PFIR Spectral Response. Four Stage Interpolate Filter. Circuit Example Output Overall Filter Response. Sixteen Channel Modulator.
LIST TABLES
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Sync Modes Mask Revisions Absolute Maximum Ratings Recommended Operating Conditions Thermal Data Operating Conditions Characteristics Example QPSK Signal Parameters. QPSK Symbol QPSK Configuration QPSK Configuration Diagnostic Test Configuration Diagnostic Test Configuration Diagnostic Test Configuration Diagnostic Test Configuration Output Test Configuration Input Test Configuration. Periodic Sync Initialization Procedure.
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2000
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GC4114 QUAD TRANSMIT CHIP
DATA SHEET
GC4114
FEATURES
Four identical up-convert channels Independent modulation frequencies Independent phase/gain controls four input signals summed into single output signal Maximum output rate real complex inputs Interpolation factors 32,768 real input mode 65,536 complex input mode serial input format, Memory mapped input registers output samples Complement offset-binary output format 0.02 tuning resolution Spur Free Dynamic Range image rejection 70dB near image rejection 0.07 gain resolution 0.05 peak peak passband ripple User programmable input filter Accepts QPSK symbol data directly, performs transmit (pulse shape) filtering Meets Damps specifications path merge outputs from multiple GC4114 chips Microprocessor interface control, input, diagnostics Built diagnostics Microprocessor serial inputs will accept either volt input levels. MHz, volts thin package
BLOCK DIAGRAM
block diagram illustrating major functions chip shown Figure
FORMAT SELECT
FILTER SELECT
BANDWIDTH
FORMAT SELECT
FILTER SELECT
BANDWIDTH BITS BITS BITS
STAGE INTERPOLA FILTER
INTERPOLA FILTER
STAGE INTERPOLA FILTER
INTERPOLA FILTER
GAIN INPUT FORMAT GAIN BITS (BIT SERIAL) BITS
GAIN INPUT FORMAT GAIN BITS BITS BITS (BIT SERIAL)
BITS
PHASE OFFSET
SINE/ COSINE GENERATOR
PHASE OFFSET
SINE/ COSINE GENERATOR
ROUND
SCALE
TUNING FREQUENCY
TUNING FREQUENCY
BITS
BITS)
INTERPOLA FILTER
STAGE INTERPOLA FILTER
(BIT SERIAL)
(BIT SERIAL)
TUNING FREQUENCY PHASE OFFSET
SINE/ COSINE GENERATOR
STAGE INTERPOLA FILTER
INPUT FORMAT GAIN
INPUT FORMAT GAIN
GAIN
GAIN
TUNING FREQUENCY PHASE OFFSET
INTERPOLA FILTER SINE/ COSINE GENERATOR SYNC COUNTER DIAGNOSTIC TEST GENERATOR
CLOCK DOUBLING DISTRIBUTION CIRCUIT
CONTROL INTERFACE FILTER COEFFICIENT RAMS
A[0:5]
C[0:7]
Figure GC4114 Block Diagram
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GC4114 QUAD TRANSMIT CHIP
DATA SHEET
FUNCTIONAL DESCRIPTION
GC4114 quad transmit chip contains four identical up-conversion circuits. Each up-convert circuit
accepts real complex signal, interpolates programmable factor ranging from 65,536 32,768 single-sideband modulation), up-converts signal selected center frequency, sums with other up-converted samples outputs combined signal. chip contains user programmable input filter which used shape transmitted data, used Nyquist transmit filter digital data transmission. application notes Section details using chip transmit QPSK data. up-converters designed maintain over spur free dynamic range image rejection. Each up-convert circuit accepts inputs (bit serial) produces outputs. up-converter outputs summed with external input produce single output. frequencies phase offsets four sine/cosine sequence generators independently specified, gain each circuit. up-converters share same bandwidth, filter coefficients input formats. chip diagnostic circuits provided simplify system debug maintenance. chip receives configuration control information over microprocessor compatible consisting data port, address port, chip enable strobe, read strobe write strobe. chip's control registers bits each) memory mapped into address space control port.
CONTROL INTERFACE
chip configured writing control information into sixty four control registers within chip.
contents these control registers them described Section registers written read from using C[0:7], A[0:5], pins. Each control register been assigned unique address within chip. This interface designed allow GC4114 appear external processor memory mapped peripheral (the equivalent memory chip's pin). external processor microprocessor, computer, chip) write into register setting A[0:5] desired register address, selecting chip using pin, setting C[0:7] desired value then pulsing low. data will latched rising edge read from control register processor must A[0:5] desired address, select chip with pin, then low. chip will then drive C[0:7] with contents selected register. After processor read value from C[0:7] should high. C[0:7] pins turned (high impedance) whenever high when low. chip will only drive these pins when both high. also ground read/write direction control control strobe.
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GC4114 QUAD TRANSMIT CHIP
Figure shows timing diagrams illustrating both modes.
A[0-5] C[0-7]
READ CYCLE- NORMAL MODE
DATA SHEET
tCSU tCHD tCSU tCDLY
A[0-5]
tCSU
tCSPW tCSU tCHD
C[0-7]
WRITE CYCLE- NORMAL MODE
A[0-5] C[0-7]
READ CYCLE- HELD
tCHD tCSU tCDLY
A[0-5]
tCSPW tCSU tCHD
C[0-7]
WRITE CYCLE- HELD
Figure Control Timing
setup, hold pulse width requirements control read write operations given Section 6.0. pins will accept either volt volt input levels. Separate power supply pins (VUP) provided chip enable this feature.
INPUT FORMAT
input samples bits, either real complex, complement format. samples input
chip either through bit-serial input ports, through memory mapped control registers.
3.2.1
Serial Interface
serial format consists data input pin, clock pin, frame strobe each four
channels, data request which common channels. input accepts either individual words format compatible with almost chips, upper bits words, words packed into word. serial data always entered first. Complex values entered I-half first followed Q-half, either separate transfers, single word with I-half MSBs Q-half LSBs. Real values entered words words. mode each
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GC4114 QUAD TRANSMIT CHIP
DATA SHEET
real word placed upper bits bits. Real samples also entered complex input mode alternately placing samples halves complex input words. data request signal (REQ) output from chip identify when GC4114 ready another serial input sample. serial inputs format shown Figure
(must before next transfer)
MODE, MORE CLOCKS BETWEEN TRANSFERS
MODE, BACK BACK TRANSFER
(SFS occurs once beginning transfer)
"PACKED" MODE
Figure Serial Input Formats
Figure shows standard input mode (PACKED input control register low). user provides serial clock (SCK), frame strobe (SFS) data line (SIN). chip clocks into chip rising edge falling edge SCK_POL input control register set). user sends serial input word GC4114 setting high SFS_POL input control register set) least clock cycle, then transmitting data, first, next clocks. user must least clock cycle before next serial transfer. data transmitted "back back" shown Figure long signal toggles then high shown. PACKED control high, then samples sent single word with only strobe shown Figure GC4114 input interface sends "new sample request" strobe (REQ) when input sample required up-converter channels. input sample rate FS=FCK/2N real inputs FS=FCK/4N complex inputs, where chip's clock rate interpolation ratio filter which varies from 16,384 (See Section 5.4). This means that strobe will output from chip every clocks (CK, SCK) real mode every clocks complex mode. pulse width strobe specified user either clocks (CK) wide clocks wide. polarity user programmable. strobe typically used interrupt external device tell send another input sample. GC4114 chip must receive last data least clock (SCK) period before next strobe. serial interface timing tight, i.e., serial rate slow that serial frames barely between strobes, then serial transfer start clocks before strobe. This means that frame sync sent clocks before REQ.
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GC4114 QUAD TRANSMIT CHIP
DATA SHEET
Very Important Note: chip assumes that serial clock continuous, does stop between transfers. clock stop, must active when frame sync occurs, active cycle after last sent. Serial data sent using only clocks period frame sync word word PACKED mode) synchronized occur between periods before REQ. user choose operate serial lines either volt logic levels facilitate interface GC4114 chip with external circuitry.
3.2.2
Memory Mapped Interfaced
Input samples entered into chip using control interface. Addresses through
input data registers. Note that these registers written burst, bits time. Note that some formats write samples most significant byte first. this case then should write from address down address strobe from GC4114 chip defines when transfer start. transfer must done before next strobe received.
GAIN
Each input sample multiplied complement gain word. gain word `G', which ranges
from -128 +127, then gain adjustment will G/128. This gives gain adjustment range. Setting zero clears channel. different gain specified each channel. Gain described more detail Section 3.7.
UP-CONVERTERS
Each up-converter channel uses stage interpolate four filter stage cascaded
integrate-comb (CIC) filter increase sample rate input data sample rate equal chip's clock rate. mixer circuit modulate signal desired center frequency. block diagram each up-convert channel shown below:
FILTER_SELECT SCALE BIG_SHIFT SHIFT DOWN REAL
PFIR FILTER INTERPOLATE
CFIR FILTER INTERPOLATE
INPUT GAIN
FROM INPUT FORMATTER
FILTER INTERPOLATE
cosine
sine TUNING FREQUENCY PHASE OFFSET
Figure Up-converter Channel
After gain been applied, described previous section, input data interpolated factor filter with programmable coefficients (PFIR). user choose between internal default filter shape PFIR, download custom taps. typical user down loaded coefficients implement matched (root-raised-cosine) transmit filters.
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GC4114 QUAD TRANSMIT CHIP
DATA SHEET
PFIR will also, desired, convert real input data single-sideband complex data. this mode PFIR does interpolate factor Instead down-converts input data FS/4, where input sample rate, pass filters result. second interpolate filter compensating filter (CFIR) which pre-compensates droop associated with filter that follows filter interpolates another factor 16,384 give overall interpolation factor 65,536 32,768 real input mode). interpolated signal up-converted sine/cosine sequence generated NCO. real part (I-half) complex result saved channel output.
3.4.1
Programmable Input Filter (PFIR)
programmable input filter uses either internal based coefficients, externally downloaded filter
coefficients. filter coefficients quantized words. internal bandwidth filter flat over range -0.4FS +0.4FS with 0.03 passband ripple, with 80db band image rejection. unique coefficients symmetric filter are: -14, -20, -70, -82, 171, -49, -269, -34, 374, 192, -449, -430, 460, 751, -357, -1144, 1581, 443, -2026, -1337, 2437, 2886, -2770, -6127, 2987, 20544, 29647 internal filter typically used signals that digitized analog signals such voice, signals. internal filter also used digital signals (FSK, PSK, GMSK signals example) that have already been modulated filtered ready up-converted their desired carrier frequency. external coefficients typically used "pulse shape" then up-convert digital data. PFIR will accept QPSK, O-QPSK, PSK, PAM, OOK, /4-QPSK, symbols then filter them desired pulse shaping filter. common pulse shaping filter root-raised-cosine (RRC) filter. symbols entered directly into chip desired symbol (baud) rate, entered twice baud rate alternately entering symbol data entering zeroes.1 "twice baud rate" "2X" method results better band image rejection. application note Section more details.
Internal Coefficients
(Alpha=0.35) Filter
(Alpha=0.35)
Figure PFIR Spectral Response
Figure shows spectral response internal filter. Figure shows root-raised-cosine pulse shaping filter with excess bandwidth (alpha=0.35). Figure shows shape mode.
Called zero padding.
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GC4114 QUAD TRANSMIT CHIP
DATA SHEET
coefficients used generate filter shown Figure are: -20, -30, -37, -55, -72, -117, 112, -175, 224, -348, 286, -761, 766, 1708, -4042, -2533, 18177, 32767 coefficients used generate filter shown Figure are: -12, -117, -113, 127, 112, -38, -175, -134, 275, 224, -71, -348,-307, 398, 286, -286, -761, -442, 766, 1954, 1708, -660, -4042,-5641, -2533, 6187, 18177, 28625, 32767 PFIR will accept either complex real input data. input samples complex, filter doubles input rate inserting zeroes between each sample, then pass filtering result. input samples real, filter translates real samples down FS/4, where input sample rate, multiplying them complex sequence then lowpass filtering result. This generates single-sideband modulation real input. double sideband real upconversion desired, then chip should operated complex mode with Q-half each complex pair zero. PFIR gain which equal (PFIR_SUM/65536), where PFIR_SUM equal filter coefficients. internal filter coefficients have PFIR_SUM=65543 which gives very close unity gain. filter shown Figure PFIR_SUM=59821 filter shown Figure PFIR_SUM=119357. Section more details chip's gain settings. PFIR output rate relative input rate complex input mode real (single side band) mode. output rate relative clock rate FCK/2N.
3.4.2
Compensating Interpolate Filter (CFIR)
second stage filter fixed coefficient interpolate filter. second stage filter always
interpolates factor two. second filter passband which flat (0.01 ripple) over 100% input bandwidth (-0.5FS +0.5FS). second filter also compensates droop associated with interpolation filter described next section. unique coefficients symmetric filter are: -23, 103, 137, -21, -230, -387, -235, 802, 1851, -4372, -4774, 5134, 20605, 28216 CFIR output scaled have unity gain. output rate CFIR filter complex mode real mode. CFIR output rate relative clock rate FCK/N.
3.4.3
Interpolate Filter
CFIR output interpolated factor CIC1 filter, where integer between
16,384. filter stage filter. block diagram filter shown Figure
ZERO FACTOR SCALE ROUND
DATA
BITS
BITS
DATA
CLOCKED RATE
CLOCKED FULL RATE
Figure Four Stage Interpolate Filter
Hogenauer, Eugene Economical Class Digital Filters Decimation Interpolation, IEEE transactions Acoustics, Speech Signal Processing, April 1981.
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GC4114 QUAD TRANSMIT CHIP
DATA SHEET
output interpolation filter equal clock rate. filter gain equal which must removed "SCALE ROUND" circuit shown Figure This circuit gain equal 2-(3+SCALE+12*BIG_SHIFT), where SCALE ranges from BIG_SHIFT ranges from value chosen BIG_SHIFT must also satisfy: 2(12*BIG_SHIFT+18) Overflows improper gain settings will undetected this relationship violated. This restriction means that BIG_SHIFT between BIG_SHIFT between 1024, BIG_SHIFT between 1025 16384. filter must initialized when chip first configured whenever interpolation value shift value BIG_SHIFT changed. filter initialized using flush controls described Section 5.8. disturbed during processing noise, radiation particles, changing BIG_SHIFT, then will become unstable generate wideband white noise output. This instability prevented using "auto flush" capability chip1 (See control register Section 5.3). auto flush mode detects instability automatically re-initializes CIC. auto flush mode requires that gain output filter less than equal unity.
3.4.4
Sine/Cosine Generator
tuning frequency each up-converter specified word phase offset specified
word. tuners synchronized with tuners other chips. This allows multiple up-converter outputs coherently combined, each with unique phase amplitude. block diagram (Numerically Controlled Oscillator) circuit shown Figure
PHASE OFFSET
BITS
DITHER GENERATOR
BITS MSBs MSBs
BITS
FREQUENCY WORD
BITS
SINE/COSINE LOOKUP TABLE
BITS
SINE/COSINE
Figure Circuit
NCO's spur level reduced below through phase dithering. Figure shows example output with without dithering. Notice that spur level without dithering about spur level with dithering well below frequency chip's clock rate. phase offset setting PHASE 216P/2, where desired phase radians ranging between tuning frequency according formula FREQ 232F/FCK, where desired tuning
auto flush mode patent pending feature chip.
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GC4114 QUAD TRANSMIT CHIP
DATA SHEET
Dithering
With Dithering
Figure Example Output OVERALL INTERPOLATION FILTER RESPONSE
image rejection up-convert channel equal stop band rejection overall interpolation filter response. overall response obtained superimposing interpolated responses PFIR CFIR filters onto filter response. overall response shown Figure Figure shows overall response using default PFIR coefficients. Figure shows response using root-raised-cosine PFIR coefficient set. Figure shows response when using mode root-raised cosine PFIR coefficient set.
Internal Coefficients
(Alpha=0.35) Filter
(Alpha=0.35)
Figure Overall Filter Response TREE
four up-convert channel outputs summed together, scaled down powers then added external input. tree output rounded bits output from chip. four channels within chip scaled down powers order prevent saturation when channels from multiple chips summed together. scale factor equal 2-SUM_SCALE, where SUM_SCALE 0,1,2 (See Section 5.9). Overflows tree saturated plus minus full scale. latency from IN[0:15] OUT[[0:15] seven clock cycles. chip will optionally invert output (OUT15) from chip order drive offset binary format digital analog converters (DACs)
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GC4114 QUAD TRANSMIT CHIP OVERALL GAIN
DATA SHEET
overall gain chip function programmable filter coefficients (PFIR_SUM) described Section 3.4.1, amount interpolation filters described Section 3.4.3), scale circuit settings filter (SCALE BIG_SHIFT described Section 3.4.3), tree scale factor (SUM_SCALE described Section 3.6). overall gain
GAIN
SCALE BIG_SHIFT PFIR_SUM 65536
SUM_SCALE
where different each channel, SCALE, BIG_SHIFT, SUM_SCALE PFIR_SUM common channels. optimal gain setting which will keep amplitude data within channel high possible without causing overflow. recommended gain target keep root-mean-squared amplitude data close one-fifth (0.2) full scale crest factor). This level should maintained throughout channel computations. This means that products
PFIR_SUM 32768 65536
SCALE BIG_SHIFT PFIR_SUM 32768 65536
should both less than equal 0.2, where "RMS" root-mean-squared level input data. Other crest factors used depending upon application. example, crest factor adequate final number bits going bits. most cases input data will already have correct crest factor application, which case ratio channel should unity. tree gain (SUM_SCALE) used when outputs from multiple channels summed together.
recommended gain when uncorrelated channels being added together example, four
32768
will equal crest factor (e.g., 0.2) gain settings
channels active GC4114, then four gain should 1/2, which achieved setting SUM_SCALE equal four chips cascaded sixteen channels, then gain should 1/4, which implies SUM_SCALE should
gain rule assumes that channels treated uncorrelated signals which will result signals correlated, however, amplitude gain tree gain should Examples correlated signals pure tones modem signals that have been
average amplitude gain
synchronized that they might peak same time. These signals, however, require much smaller crest factor, such pure tones modem signals. this case crest factor will absorb much difference gain between
overflow does occur, then samples saturated plus minus full scale. Overflow monitored using overflow status register, Section 5.14 details. values BIG_SHIFT must also satisfy 2(12*BIG_SHIFT+18) (see Section 3.4.3 details). BIG_SHIFT satisfy this relationship, then overflow occur which detected. auto flush mode used, then gain must less than equal unity. This means that values SCALE BIG_SHIFT must satisfy 2(SCALE+12*BIG_SHIFT+3) (see Section 3.4.1 details). Note that noise rounding errors minimized keeping gain close unity possible. attenuation necessary, example when multiple channel outputs added together, then attenuation should added close output chip possible. This means that SUM_SCALE control should used attenuation before SCALE BIG_SHIFT controls adjusted.
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GC4114 QUAD TRANSMIT CHIP CLOCKING
DATA SHEET
chip clocked modes. standard mode, clock rate equal output data rate which MHz. internal clock doubler doubles clock rate that internal circuitry clocked twice data rate. standard mode CKMODE must grounded internal control register EN_DOUBLER must high (See Section 5.10). alternate clock mode (pin CKMODE high) accepts double rate clock CK2X bypasses clock doubler circuit. EN_DOUBLER control should low. alternate mode user must provide both standard clock double rate clock. Note that rising edges clocks must such that rising edge coincident with precedes rising edge CK2X more than nanoseconds.
SYNCHRONIZATION
Multiple chips synchronized through sync input signal, internal shot sync
generator, sync counter. Each circuit within chip, such sine/cosine generators interpolation control counter synchronized these sources. These syncs also output from chip that multiple chips synchronized sync coming from "master" chip. Figure Section 7.5. interpolation control counter generates request strobe (REQ) output from chip. This counter syncronized using input sync (see bits address This allows user lock timing request strobe timing. this done, then strobe will high clock cycles after signal. example, signal active during clock cycle then will high during clock cycle then repeat every clocks clocks real input mode) thereafter.
3.10
POWER DOWN MODES
chip power down circuit. This circuit contains slow, nominally KHz, oscillator clock-loss
detect cell. This circuit used detect loss clock provide slow "keep-alive" clock chip. circuit also used power down chip switching from high speed input clock speed keep-alive clock. speed clock rate slow enough power down chip while fast enough refresh dynamic nodes within chip. user select whether this circuit automatic clock-loss detect mode, always (power down mode), disabled (the slow clock never kicks in).
3.11
DIAGNOSTICS
chip internal ramp generator which used place data inputs diagnostics.
internal checksum circuit generates checksum output data verify chip's operation. Section diagnostic configurations checksums.
3.12
INITIAL BOARD DEBUG PROCEDURE
suggested procedure bringing GC4114 chip first check control interface writing
control registers reading them back. diagnostics described Section should next, followed output input tests described Sections 7.8. these pass successfully, then configuration customized desired application should work.
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GC4114 QUAD TRANSMIT CHIP PACKAGING
GC4114 chip comes thin plastic quad flatpack package
DATA SHEET
IN15 (MSB) IN14 IN13 IN12 IN11 IN10
(MSB) OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0
(0.5mm)
IN10 IN11 IN12 IN13 IN14 IN15
SIN-D SCK-D SFS-D
GC4114 QUAD TRANSMIT CHIP
SIN-C SCK-C SFS-C
SIN-B SCK-B SFS-B
Logic Levels (MSB) (MSB) CK2X CKMODE
PINS: NOTE: 0.01 DECOUPLING CAPACITORS SHOULD PLACED CLOSE POSSIBLE EACH SIDE CHIP
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OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0
SIN-A SCK-A SFS-A
CK2X CKMODE OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8
MMMMMM YYWW GC4114-PQ QUAD XMIT
(TOP VIEW)
SCK-A SFS-A SIN-A SCK-B SFS-B SIN-B SCK-C SFS-C SIN-C SCK-D SFS-D SIN-D
THIN QUAD FLAT PACK GC4114-PQ: PLASTIC PACKAGE GC4114-CQ: CERAMIC PACKAGE
DIMENSION (width pin) (width body) (pin pitch) (pin width) (leg length) (height) (pin thickness) PLASTIC 16.0 (0.630") 14.0 (0.551") (0.020") 0.22 (0.009") 0.60 (0.024") (0.059") 0.15 (0.006") CERAMIC 17.2 (0.677") 14.0 (0.551") (0.020") 0.20 (0.008") 0.70 (0.028") (0.122") (0.008")
MMMMM Mask Code Code YYWW Date Code
2000
GC4114 QUAD TRANSMIT CHIP
DATA SHEET
SIGNAL SIN-A,B,C,D
DESCRIPTION SERIAL INPUT DATA, Active high serial input data four channels. halves complex data entered same pin. Each time chip asserts (See below) I-half entered then Q-half. SERIAL DATA CLOCK, Active high serial data bits clocked into chip these clocks. active edge these clocks user programmable. SERIAL FRAME STROBE, Active high serial word strobe. This strobe delineates words within serial input stream. This strobe pulse beginning each serial word, window enable which active while data bits active. REQUEST FLAG, programmable active high chip requests input data asserting this signal. width input clock cycles polarity this signal user programmable. This signal typically used interrupt chip, also used start pulse dedicated circuitry. INPUT CLOCK. Active high clock input chip. IN[0:15] input signals clocked into chip rising edge this clock. DOUBLE RATE INPUT CLOCK. Active high double rate clock input chip. Used alternate clock mode clock chip. This clock must exactly twice frequency clock. Should grounded normal clock mode. CLOCK MODE, Active high clock mode control. chip uses CK2X when this tied high (alternate mode) clock internal circuitry. When this signal grounded (normal mode) chip doubles clock internal clock. SYNC Active sync input chip. timers, accumulators, control counters are, synchronized This sync clocked into chip rising edge input clock (CK). SYNC OUT. Active This signal either delayed version input sync sync counter's terminal count (TC), one-shot strobe. signal clocked chip rising edge input clock (CK). SUMMER INPUT DATA. Active high two's complement summer input samples. samples clocked into chip rising edge clock. input data rate assumed equal clock rate. SUMMER OUTPUT DATA. Active high summer data output words these pins. bits clocked rising edge clock (CK). CONTROL DATA BUS. Active high This control data bus. Control register data loaded into chip read from chip through these pins. chip will only drive these pins when low. CONTROL ADDRESS BUS. Active high These pins used address control registers within chip. Each control registers within chip assigned unique address. control register written read from setting A[0:5] register's address. READ ENABLE. Active This enables chip output contents selected register C[0:7] pins when also low. WRITE ENABLE. Active This enables chip write value C[0:7] pins into selected register when also low. CHIP ENABLE. Active This control strobe enables read write operation. contents register selected A[0:5] will output C[0:7] when low. low, then selected register will loaded with contents C[0:7]. MICROPROCESSOR INTERFACE VOLTAGE. This used voltage interface levels following control pins: C[0:7], A[0:5], SIN-A, SIN-B, SIN-C, SIN-D, SCK-A, SCK-B, SCK-C, SCK-D, SFS-A, SFS-B, SFS-C, SFS-D. This tied volts interface GC4114 microprocessors with outputs. this +3.3 volts (VCC) interface with volt microprocessors.
SCK-A,B,C,D
SFS-A,B,C,D
CK2X
CKMODE
IN[0:15]
OUT[0:15]
C[0:7]
A[0:5]
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GC4114 QUAD TRANSMIT CHIP
DATA SHEET
CONTROL REGISTERS
chip configured controlled through eight control registers. These registers
accessed reading writing using control pins (CE, A[0:5], C[0:7]) described previous section. register names their addresses are: Mode Control Registers addresses ADDRESS NAME Sync Mode Interpolation Mode Interpolation Gain Interpolation Byte Interpolation Byte Input Mode Counter Byte Counter Byte ADDRESS NAME Channel Sync Channel Sync Channel Sync Channel Sync Channel Flush Mode Summer Mode Status Checksum
Input registers addresses inputs stored least significant byte first address, most significant second. ADDRESSES NAME 16,17 18,19 20,21 22,23 Channel I-input Channel Q-input Channel I-input Channel Q-input ADDRESSES 24,25 26,27 28,29 30,31 NAME Channel I-input Channel Q-input Channel I-input Channel Q-input
Addresses used four modes determined page select control bits status register. Page zero frequency, phase gain settings four channels. Page monitoring status test points. Pages three used store coefficients programmable interpolate filter. Page zero register assignments are: ADDRESSES NAME 32,33,34,35 36,37 40,41,42,43 44,45 Channel Frequency Channel Phase Channel Gain unused Channel Frequency Channel Phase Channel Gain unused ADDRESSES NAME 48,49,50,51 52,53 56,57,58,59 60,61 Channel Frequency Channel Phase Channel Gain unused Channel Frequency Channel Phase Channel Gain unused
filter coefficients stored bytes word complement format. least significant bits lower byte most significant bits upper byte. Page stores coefficients through addresses Page three stores coefficients Coefficient center tap. lower byte coefficient must loaded then upper byte. following sections describe each these registers. type each register either indicating whether read only, write only, read/write. bits active high.
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SYNC MODE REGISTER
Sync mode control register determines circuits within chip synchronized. Each circuit
which requires synchronization configured synchronized sync input (SI), terminal count sync counter (TC). sync each circuit also always always off. Each circuit given sync mode control which defined Table Sync Modes MODE
USE_ONESHOT set) (always)
SYNC DESCRIPTION
(never asserted)
NOTE: internal syncs active high. input been inverted active high sync
ADDRESS
(LSBs)
Sync Mode, suggested default 0x65
TYPE NAME INT_SYNC COUNTER_SYNC OUTPUT_SYNC USE_ONESHOT ONE_SHOT DESCRIPTION Synchronizes interpolation control counter. interpolation counter controls filtering each channel. Synchronizes sync counter. This counter used generate periodic "TC" sync pulses. Mode counter. selected sync inverted output pin. terminal count mode Table replaced shot pulse (OS) when this set. shot sync pulse (OS) generated when this set. This must cleared before another shot pulse generated.
user wishes allow chip free run, asynchronous other chips, then sync settings zero. wishes synchronize several chips single sync source, then sync mode selections should one. suggested default output one-shot (USE_ONESHOT OUTPUT_SYNC=2) other syncs user should output GC4114 chip input other GC4114 chips system order cleanly synchronize initialize more GC4114 chips. there only single GC4114 chip, then sync mode selections receive one-shot directly. one-shot should sent after initialization each time interpolation ratio changed.
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INTERPOLATION MODE REGISTER
Registers control interpolation modes chip. These settings common channels
ADDRESS
TYPE
Interpolation Mode, suggested default 0x00
NAME REAL DESCRIPTION input samples real when this up-converted single sideband signal. input samples treated complex when this low. input rate FCK/4N when this FCK/2N when this high, where chip's clock rate interpolation setting registers (See Section 5.4). double sideband real data up-converted, then complex mode should used with Q-half zero. user downloaded filter coefficients used instead built filter coefficients PFIR filter when this set. This must cleared least clock cycles before set. This control inverts polarity output. Normally pulses high when sample requested. will pulse when REQ_POL high. Normally will pulse high clock cycles. This control forces high "N/2" clocks. NOTE: period signal either clocks, depending upon whether REAL_INPUT control high input mode control register (See Section 5.5). diagnostic ramp input source four channels. ramp starts -32768 counts +32768 starts over again. ramp increments once every complex input cycle (every clocks). When set, will whenever overflow occurs chip. Bits control register page must this mode (see Section 5.14). diagnostic ramp synchronized sync selected these bits according Table This sync also loads checksum register.
FILTER_SELECT
REQ_POL REQ_WIDTH
DIAG
SO_OVF_MODE DIAG_SYNC
INTERPOLATION GAIN REGISTER
Register controls interpolation gain chip. These settings common channels ADDRESS
TYPE
Interpolation Gain, suggested default 0x46
NAME SCALE BIG_SHIFT AUTO_FLUSH MSB_INVERT DESCRIPTION SCALE ranges from BIG_SHIFT equals chip will automatically flush channel instability channel's filter detected this set. Inverts output data (OUT15) with offset binary DACs. equal remove this gain outputs shifted
filter gain which
down
(3+SCALE+12*BIG_SHIFT) bits then rounded bits before they sent mixer circuit. value chosen BIG_SHIFT must also satisfy: 2(12*BIG_SHIFT+18) Overflows improper gain settings will undetected this relationship violated. This restriction means that BIG_SHIFT between BIG_SHIFT between 1024, BIG_SHIFT between 1025 16384.
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INTERPOLATION REGISTERS
Registers contain interpolation ratio control.
ADDRESS
Interpolation Byte suggested default 0x07
TYPE NAME INT[0:7] DESCRIPTION LSBs interpolation control
ADDRESS
Interpolation Byte suggested default 0x00
TYPE NAME INT[8:13] zero DESCRIPTION MSBs interpolation control Reads back zeros.
Where equal N-1. chip interpolates input data factor real input data complex input data, where ranges from 16384. This provides interpolation range from 65,536 complex input signals 32,768 real input signals. NOTE: chip needs flushed each time interpolation registers changed. Section 5.8.
INPUT MODE REGISTER
This register controls input serial format.
ADDRESS
TYPE
Input Mode Register, suggested default 0x00
NAME PACKED DESCRIPTION Puts serial inputs into transfer mode where each complex pair packed into words. complex pair formatted word upper bits word lower bits. Each word formatted first. serial input accepts real data samples (not complex) when this set. this mode single word expected after every strobe, complex pair. user option enter real input samples complex pairs real input mode. complex mode (REAL_INPUT used enter real words, then real samples should alternately placed halves complex input pairs. NOTE: REAL control interpolation mode register still needs enable real data conversion. Input bits frame strobes clocked trailing edge when this set. rising edge used when this low. signal treated active when this set. Otherwise signal treated active high. parallel/Serial control channel parallel/Serial control channel parallel/Serial control channel parallel/Serial control channel
REAL_INPUT
SCK_POL SFS_POL PARALLEL_A PARALLEL_B PARALLEL_C PARALLEL_D
parallel/serial control serial input high parallel input. Section 5.12.
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COUNTER MODE REGISTER
Registers counter's cycle period.
ADDRESS
Counter Byte suggested default 0xff TYPE
NAME
CNT[0:7]
DESCRIPTION
LSBs counter cycle period
ADDRESS
Counter Byte suggested default 0xff TYPE
NAME
CNT[8:15]
DESCRIPTION
MSBs counter cycle period
chip's internal sync counter counts cycles 128(CNT+1) clocks. terminal count signal (TC) output each cycle. counter synchronized external sync specified Sync mode Register (See Section 5.1). that 128(CNT+1) multiple twice interpolation ratio (i.e., multiple 16N), then terminal count this counter output used periodically synchronize multiple GC4114 chips.
CHANNEL SYNC REGISTERS
Registers 8,9,10 control synchronization modes four channels. sync modes described
here unique each channels. modes same settings shown Table (See Section 5.1). ADDRESS ADDRESS ADDRESS ADDRESS
Channel-A Sync Modes, suggested default 0x5f Channel-B Sync Modes Channel-C Sync Modes Channel-D Sync Modes
TYPE NAME FREQ_SYNC PHASE_SYNC NCO_SYNC DITHER_SYNC DESCRIPTION frequency setting takes affect this sync phase offset takes affect this sync initialized phase setting this sync dither circuit initialized this sync zero.
NCO_SYNC usually always off, unless user wants coherently control phases multiple channels. FREQ_SYNC PHASE_SYNC typically always that frequency phase settings will take effect immediately they written into their control registers (See Section addresses 63). Alternately, FREQ_SYNC PHASE_SYNC controls shot modes allow frequency phase changed smoothly, coherently with another event. DITHER_SYNC used turn dithering phase. turn dithering DITHER_SYNC always that remains initialized zero. turn dithering sync always off. During diagnostics NCO_SYNC DITHER_SYNC should "TC".
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CHANNEL FLUSH CONTROL REGISTER
This register controls flushing four channels. Each channel flushed when selected sync occurs
sync selected according Table Section 5.1. ADDRESS
Channel Flush Register, suggested default 0x55
TYPE NAME FLUSH_A[0:1] FLUSH_B[0:1] FLUSH_C[0:1] FLUSH_D[0:1] DESCRIPTION flush sync channel flush sync channel flush sync channel flush sync channel
Each channel needs flushed when chip being initialized when interpolation control changed. flush lasts clocks after sync occurs. channel flush syncs will normally left "never" mode. channel unused, then user should leave channel "always" flush mode which will clear datapath, clear channel's output, lower power consumption. During diagnostics channels will need flushed beginning each sync cycle.
SUMMER MODE REGISTER
This register controls output summer round circuit.
ADDRESS
Summer Mode Register, suggested default 0x09
TYPE NAME SUM_SCALE SUM_DELAY DESCRIPTION four channels shifted down SUM_SCALE bits before being added sum-in signal. four channels delayed seven clock cycles when this high. This allows outputs chips coherently summed. Clears IN[0:15] inputs summer. Round output bits. Round output bits. Round output bits. Round output bits.
SUM_CLR RND8 RND10 RND12 RND14
Only round control bits should set. none set, then output rounded bits. lower bits rounded into upper bits. Bits below rounding point cleared.
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5.10
STATUS CONTROL REGISTER
This register contains miscellaneous control status information.
ADDRESS
Status Control Register, suggested default 0x08
TYPE NAME INPUT_READY DESCRIPTION user sets this after loading input registers. chip clears this when values have been read time load ones. chip sets this user INPUT_READY before chip reads input registers. This high indicates that error occurred. Power_Down modes normally keep alive clock. This clock disabled when this high. Enables clock doubling circuit. This defaults low. user must enable clock doubler. Selects page mode control addresses follows: MODE PAGE Frequency, Phase Gain Status Test monitors Filter coefficients Filter coefficients This field controls power down keep alive circuit follows: POWER_DOWN MODE Clock loss detect mode Power down mode Disabled Test power_down bits default (clock loss detect mode) upon power
MISSED
PD_CLOCK_OFF EN_DOUBLER PAGE
POWER_DOWN
INPUT_READY used tell external processor when load input samples. desired, used interrupt external processor (See Section 5.2) tell processor when load samples. user does need INPUT_READY used. INPUT_READY set, however, MISSED flag will valid. NOTE: parallel input mode assumes data being entered complex pairs, even when data real. enter real data parallel mode, user must real data into complex pairs, first sample each pair I-half second Q-half.
5.11
CHECKSUM REGISTER
checksum register read only register which contains checksum OUT[0:15] data.
checksum stored checksum register then starts over again each time DIAG_SYNC (See Section 5.2) occurs. This read only register. example diagnostic configurations Section 7.6. ADDRESS
Checksum Register TYPE
NAME
CHECKSUM[0:7]
DESCRIPTION
checksum.
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5.12
CHANNEL INPUT REGISTERS
Addresses through used input values into chip when channels parallel input
mode. inputs two's complement numbers which loaded bytes. address assignments are: ADDRESSES NAME 16,17 18,19 20,21 22,23 Channel I-input Channel Q-input Channel I-input Channel Q-input ADDRESSES 24,25 26,27 28,29 30,31 NAME Channel I-input Channel Q-input Channel I-input Channel Q-input
These read/write registers.
5.13
PAGE ZERO (CHANNEL CONTROL) REGISTERS
Addresses used load each channel's frequency, phase gain settings when PAGE
status register (see Section 5.10). address assignments are: ADDRESSES NAME 32,33,34,35 36,37 40,41,42,43 44,45 FREQ_A[31:0] PHASE_A[15:0] GAIN_A[7:0] unused FREQ_B[31:0] PHASE_B[15:0] GAIN_B[7:0] unused ADDRESSES NAME 48,49,50,51 52,53 56,57,58,59 60,61 FREQ_C[31:0] PHASE_C[15:0] GAIN_C[7:0] unused FREQ_D[31:0] PHASE_D[15:0] GAIN_D[7:0] unused
frequency control words (FREQ_A, FREQ_B, FREQ_C FREQ_D) defined FREQ 232F/FCK where desired center frequency channel chip's clock rate (not CK2X rate). negative frequency vales invert signal's spectrum. frequency words entered four bytes, least significant byte lowest address, most significant higher address. phase offsets defined where desired phase radian from gain defined GAIN G/128 where ranges from -128 +127. Note that GAIN only part chip's gain should used conjunction with SCALE, BIG_SCALE, COARSE SUM_SCALE. Section details. channel control registers read/write. PHASE 216P/2
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5.14
PAGE (STATUS TEST) REGISTERS
Addresses used status test monitors when PAGE one.
ADDRESS
Overflow Status, suggested default 0x00
TYPE NAME OVER_A OVER_B OVER_C OVER_D OVER_SUM OVER_ROUND DESCRIPTION chip sets this when overflow occurs channel chip sets this when overflow occurs channel chip sets this when overflow occurs channel chip sets this when overflow occurs channel chip sets this when there overflow SUM_SCALE setting being (See Section 5.9) chip sets this rounding output causes overflow. Reserved factory test. These bits must zero SO_OVF_MODE (see Section 5.2)
channel overflow detected SCALE ROUND circuit each filter (See Section 3.4.3). overflow bits must cleared user before overflow will detected. ADDRESS
Clock Status
TYPE NAME KACK KA_MODE unused DESCRIPTION This monitors keepalive clock. This monitors keepalive mode. chip sets this when keep alive circuit activated.
ADDRESS
Mask Revision
TYPE NAME REVISION DESCRIPTION Mask revision number.
This address used determine mask revision number GC4114. mask revision numbers shown Table below (the mask codes printed GC4114 package). Table Mask Revisions Mask Revision Number (Address Mask Code Package 55531B 55531C Original Metal mask changed, functional changes
Release Date July 1997 March 1998
Description
ADDRESS 39,47,55,63:
Test Points
These test points factory tests monitor filters. used normal operation.
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5.15
PAGES THREE (COEFFICIENT) REGISTERS
user programmable filter coefficients stored addresses when PAGE
Page coefficients through page three coefficients through where coefficient first coefficient coefficient middle coefficient filter's impulse response. coefficients stored bytes, least significant byte first. example, LSBs coefficient stored address MSBs address LOAD COEFFICIENT USER MUST WRITE LSBYTE FIRST FOLLOWED MSBYTE. Unknown values will written into LSBs written first. coefficient registers write only. coefficients should entered after chip been configured setting control registers through their desired values. coefficients should written chip while FILTER_SELECT cleared (bit address described Section FILTER_SELECT after coefficients have been loaded. Note that FILTER_SELECT must least clock cycles whenever low.
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SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS
Table Absolute Maximum Ratings PARAMETER Supply Voltage Control I/O, CKMODE, SFS, Supply Voltage Input voltage (undershoot overshoot) Storage Temperature Lead Soldering Temperature seconds) Notes:
VUP+0.5 Control I/O, CKMODE serial input pins.
SYMBOL
TSTG
-0.3 -0.3
UNITS
NOTES
-0.5
VCC+0.5
RECOMMENDED OPERATING CONDITIONS
Table Recommended Operating Conditions PARAMETER Supply Voltage Control I/O, CKMODE, SFS, Supply Voltage Temperature Ambient, flow Junction Temperature SYMBOL
UNITS
NOTES
specifications tested this range. GC4114 will operate derated specifications lower supply voltages. Thermal management required full rate operation, Table below
THERMAL CHARACTERISTICS
Table Thermal Data THERMAL CONDUCTIVITY Theta Junction Ambient Theta Junction Case GC4114-CQ SYMBOL Watt Watt
GC4114-PQ UNITS Watt
Watt
°C/W °C/W
Note: flow will reduce highly recommended.
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CHARACTERISTICS
parameters industrial temperature range ambient unless noted.: Table Operating Conditions 3.3V PARAMETER
Voltage input Voltage input high Input current (VIN Voltage output (IOL 2mA) Voltage output high (IOH -2mA) Data input capacitance (All inputs except Clock input capacitance input)
SYMBOL
Typical
UNITS
NOTES
Typical Typical
Notes:
Controlled design process directly tested. Verified initial parts evaluation. Each part tested 85°C given specification. VUP=5V, VIH=2.5V Control I/O, CKMODE pins. VUP=5V, VOH=2.8V (MIN) VOH=5V (MAX) Control pins.
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CHARACTERISTICS
Table Characteristics (-40 +85oC Ambient, unless noted) 3.1V 3.5V PARAMETER SYMBOL
Note Note tCKL tCKH FSCK tSCKL/H tSSU tSHD tDLY tCSU tCHD tCSPW tCDLY ICCQ Note
UNITS
NOTES
Clock Frequency Clock period (Below VIL) Clock high period (Above VIH) Clock rise fall times (VIL VIH) Input setup before goes high Input hold time after goes high Serial Clock Frequency Serial Clock high period Serial Data Setup before Serial Data Hold from Data output delay from rising edge (OUT Control Setup before both Control hold after high Control strobe pulse width (Write operation) Control output delay (Read Operation) Control tristate delay after high Quiescent supply current (VIN=0 VCC, 1KHz POWER_DOWN=1) Supply current (FCK =50MHz, N=8)
Notes:
Controlled design process directly tested. Verified initial part evaluation. Each part tested degrees given specification. chip operate properly clock frequencies below above MAX. Output load 2mA. Delays measured from rising edge clock output level rising above Falling below VCC/2. minimum clock rate must satisfy FCK/(4N) 1KHz, where interpolation ratio. 6.Output load 2mA. Current changes linearly with voltage clock speed: (MAX) 88mA where number active channels interpolation ratio. timing diagram Figure description Section 3.1. timing diagram Figure description Section tested volts.
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APPLICATION NOTES POWER GROUND CONNECTIONS
GC4114 chip very high performance chip which requires solid power ground connections
avoid noise pins. possible GC4114 chip should mounted circuit board with dedicated power ground planes with least decoupling capacitors (0.01 adjacent each GC4114 chip. dedicated power ground planes possible, then user should place decoupling capacitors adjacent each pair.
IMPORTANT
GC4114 chip operate properly these power ground guidelines violated.
STATIC SENSITIVE DEVICE
GC4114 chip fabricated high performance CMOS process which sensitive high voltage
transients caused static electricity. These parts permanently damaged static electricity should only handled static free environments.
SYNCHRONIZING MULTIPLE GC4114 CHIPS
system containing more GC4114 chips will need synchronized coherent operation
desired. synchronize multiple GC4114 chips connect sync input pins together they driven common sync strobe. common sync strobe from external source, sync output from chips. sync output from chips used, then user choose output shot sync pulse from that chip, terminal count from chip's sync counter. terminal count used, then sync cycle must multiple FLUSH (Address 12), NCO_SYNC DITHER_SYNC (Addresses sync control bits must "never" (see Table after initial synchronization. Figure Section example configuration multiple chips Section description periodically synchronize multiple chips.
THERMAL MANAGEMENT
junction temperature must kept below reliable operation. chip's power dissipation
should calculated using equation supply current Section then chip's junction temperature calculated using package's thermal conductivity shown Section 6.3. full rate operation (FCK=70MHz) power 1.44 Watts junction ambient rise degrees Watt plastic package. This represents rise degrees over ambient. This means that under these conditions ambient temperature between 84°C Increasing decimation ratio decreasing number active channels will also allow higher ambient temperature operation. less than flow will decrease thermal resistance 40%, allowing ambient temperatures
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PULSE SHAPING MODULATING QPSK DATA
chip designed pulse shape up-convert digital symbol data BPSK, PSK, QPSK
modulation types. symbol data entered into chip pairs either symbol rate (baud rate) mode, twice symbol rate mode. PFIR used pulse shape data using root-raised cosine (RRC) filter. formula which calculates coefficients
32767 taps
where desired excess bandwidth (typically 0.35), ratio sample rate PFIR baud rate data (0.5 mode 0.25 mode), number ranging from Only taps through needed chip. weights excess bandwidth 0.35 given Section 3.4.1. choice between entering data baud rate mode) entering data twice baud rate mode), depends upon amount image rejection required application. image rejection adequate (see Figure Section 3.5), then entering data baud rate will work. more image rejection required, then data should entered twice baud rate alternately entering symbol pairs zeros. input mode greater than image rejection shown Figure sample rate chip, which same clock rate chip (FCK), equal mode mode. maximum baud rate accepted chip therefore, FCK/4N mode FCK/8N mode. following subsections give examples configure initialize chip both modes example QPSK signal with baud rate 25KHz output sample rate 60MHz. These examples configuration using four chips modulate channels data. Figure shows suggested interconnection between four chips. SIXTEEN SERIAL INPUTS
GC4114
GC4114
GC4114
GC4114
14MSBs
MODULE
ANALOG OUTPUT
input circuitry chips
Figure Sixteen Channel Modulator
Note that chip provides sync pulse that goes four chips. output from chips will same from four chips) must used synchronize input serial data (see Section 3.2).
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7.5.1
Modulating 25K-Baud QPSK signal Mode
This section illustrates modulate signals mode. signal parameters used this example
shown Table below. Table Example QPSK Signal Parameters
Parameter
Baud Rate Excess Bandwidth Digital Analog Converter (DAC) Size Desired Crest Factor Number Channels
Symbol
0.35
Value
Kbaud
Units
Bits (-14dB)
assumed that QPSK symbols have been mapped into pairs shown Table value Table QPSK Symbol
Symbol
16384 -16384 16384 -16384
16384 16384 -16384 -16384
16384 arbitrary, should greater than 8192 allow reasonable gain settings. information Tables used derive interpolation ratio gain settings SCALE, BIG_SHIFT SUM_SCALE). filter coefficients mode root-raised cosine filter with excess bandwidth 0.35 derived using formula shown above. These coefficients listed Section 3.4.1. these coefficients (PFIR_SUM) used gain calculation equal 59835. mode clock rate equal 4BN, equal 60MHz equal 25KHz. optimal gain setting chip described Section 3.7. first equation optimized
PFIR_SUM 32768 65536
crest factor 0.2, input level1 16384, PFIR_SUM 59835. Solving gives value G=56. second equation satisfy term slightly less than 228, value BIG_SHIFT=1
this
equation
SCALE BIG_SHIFT PFIR_SUM 32768 65536
SCALE=13 appropriate. Solving this equation using complex data's level 23170 gives G=49. tree gain (SUM_SCALE) should keep final output level, after adding signals together, desired crest factor. output level increases
which M=16 gain Setting
SUM_SCALE=2 will cancel gain tree leave crest factor 0.25 (-12dB). suggested control register settings chip with these parameters shown Table
level data 16384, level data 16384, level combined complex data times16384 23170. level combined data must considered second equation order prevent overflow mixer.
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Table QPSK Configuration
Control Registers Address
(HEX)
Channel, Status Coefficient Pages Address
(HEX) FREQ[0:7] FREQ[8:15] FREQ[16:23] FREQ[24:31] FREQ[0:7] FREQ[8:15] FREQ[16:23] FREQ[24:31] FREQ[0:7] FREQ[8:15] FREQ[16:23] FREQ[24:31]
Data
(HEX) 00->022 read only
Page
FREQ[0:7] FREQ[8:15] FREQ[16:23] FREQ[24:31]
Page
read only
Page
Page
Initialize chip (Master) while configuring chips, then fire shot pulse, then back 65.This assumes that tied four chips Initialize then after generating shot pulse. Chip uses SUM_CLR, mode, uses round bits. page number. lower nibble should stay Serial interface dependent.
initialization procedure load control coefficient registers four chips shown Table then synchronize chips using shot pulse from chip then back write 02HEX into address each chip select downloaded coefficients. shot pulse generated setting address chip E5HEX then back 65HEX.
7.5.2
Modulating 25K-Baud QPSK signal Mode
This section illustrates modulate signals mode. signal parameters same
shown Tables except that data entered into chip twice baud rate KHz) alternating
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between symbol data zeros. This cuts interpolation ratio half, that interpolation ratio instead 600. root-raised-cosine filter coefficients derived using formula Section with 0.25. These coefficients listed Section 3.4.1. PFIR_SUM value this coefficients 119387 alternating with zeroes causes amplitude inputs decrease factor two. Evaluating first gain equation Section 7.5.2 using PFIR_SUM values gives second equation term slightly less than 225, BIG_SHIFT=1 SCALE=10 appropriate. Solving gives suggested control register settings chip with these parameters shown Table Table QPSK Configuration
Control Registers Address
(HEX)
Channel, Status Coefficient Pages Address
(HEX) FREQ[0:7] FREQ[8:15] FREQ[16:23] FREQ[24:31] FREQ[0:7] FREQ[8:15] FREQ[16:23] FREQ[24:31] FREQ[0:7] FREQ[8:15] FREQ[16:23] FREQ[24:31]
Data
(HEX)1 00->022 read only
Page
FREQ[0:7] FREQ[8:15] FREQ[16:23] FREQ[24:31]
Page
read only
Page
Page
Initialize chip (Master) while configuring chips, then fire shot pulse, then back 65.This assumes that tied four chips Initialize then after generating shot pulse. Chip uses SUM_CLR, mode, uses round bits. page number. lower nibble should stay Serial interface dependent.
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DIAGNOSTICS
Four diagnostic tests described here. These tests diagnostic ramp input data source
counter synchronization. tests loading configurations, waiting checksum stabilize (about million clock cycles), then reading checksum from address comparing expected checksum shown each configuration table address Table Diagnostic Test Configuration
Control Registers Address
(HEX)
Channel, Status Coefficient Pages Address
(HEX)
Data
(HEX)
Page
Page
read only
Page
unused
Page
This read-only expected checksum.
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Table Diagnostic Test Configuration
Control Registers Address
(HEX)
Channel, Status Coefficient Pages Address
(HEX)
Data
(HEX)
Page
Page
read only
Page
unused
Page
This read-only expected checksum.
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Table Diagnostic Test Configuration
Control Registers Address
(HEX)
Channel, Status Coefficient Pages Address
(HEX)
Data
(HEX) 90->922
Page
Page
read only
Page
Page
This read-only expected checksum. Initialize load remaining registers coefficients, wait clock cycles, then
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Table Diagnostic Test Configuration
Control Registers Address
(HEX)
Channel, Status Coefficient Pages Address
(HEX)
Data
(HEX) 90->922
Page
Page
read only
Page
Page
This read-only expected checksum. Initialize load remaining registers coefficients, wait clock cycles, then
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OUTPUT TEST CONFIGURATION
following configuration allows user debug output interface insure that GC4114 data
being received properly following circuitry. configuration following table will generate fixed output sequence sixteen values which will repeat indefinitely: Note that coefficients except last zero. Table Output Test Configuration
Control Registers Address
(HEX)
Channel, Status Coefficient Pages Address
(HEX)
Data
6A->EA->6A1 00->022 read only
Page
Page
read only
Page
Page
After configuring chip fire shot setting then back Initialize send shot, wait least clocks, then
this test load control registers coefficient registers shown above, then generate shot setting address 0xEA then back 0x6A, then enabling programmable coefficients setting address 0x02. After approximately clock cycles output will settle repeat following sample sequence (Note alternating pattern bits except LSBs): 0x5556 0xaaaa 0x5556 0xaaaa 0x5556 0xaaaa 0x5556 0xaaaa 0x5556 0xaaa9 0x5557 0xaaa9 0x5557 0xaaa9 0x5557 0xaaa9
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INPUT TEST CONFIGURATION
serial input configuration timing checked using following configuration. input data
pair 0xAA00 0x5500. following configuration will output known constant that complex pair received correctly. power interpolation ratios where SCALE BIG_SCALE satisfy: 2(SCALE+BIG_SHIFT*12+3), constant 0x9090. power ratios other SCALE BIG_SHIFT settings constant determined described below. Note that coefficients except last zero. Table Input Test Configuration
Control Registers Address
(HEX)
Channel, Status Coefficient Pages Address
(HEX)
Data
6A->EA->6A1 00->022 read only
Page
Page
read only
Page
Page
After configuring chip fire shot setting then back Initialize send shot, wait least clocks, then calibrate expected output then change desired serial input configuration.
this configuration change addresses reflect desired interpolation gain values, leave serial controls 0xF0 address value pins should constant. Record that value then configure address match characteristics desired serial input format. serial
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interface working, then output should same recorded. expected value 0x9090 power interpolation ratios. QPSK mode described Section with addresses 0x5A, 0x2B 0x01 respectfully, output should 0xA654. same value expected QPSK mode where addresses 0x5D, 0x57 0x02 respectfully.
PERIODIC SYNC MODE
configuration shown Figure allows four chips synchronized master chip's
output. This connection allows system periodically synchronized master chip using internal counter. periodically synchronizing system user insure that chips will return being sync, even chip thrown sync noise, alpha particles other factors such lightning. periodic sync mode chips configured that interpolation control counter (bits address synchronized other syncs ignore (set "never" Table internal counter registers (addresses should count cycles equal multiples interpolation factor suggested counter setting equal (See Sections 5.6). This will result periodic sync every 128N clocks (every complex inputs). sync output control (bits address should (TC), USE_ONESHOT mode should turned off. FLUSH (address 12), NCO_SYNC DITHER_SYNC (addresses must never. suggested initialization procedure using periodic sync mode configure chips normal mode (see example Tables 11), send shot pulse, wait clock cycles chips become synchronized, periodic sync mode registers except address (also FILTER_SELECT necessary address then address periodic sync mode. Table shows necessary settings. Table Periodic Sync Initialization Procedure
Control Address
(HEX)
Initial Normal Mode Settings Chips
Generate Shot Chip only
Wait clocks, Then Change Syncs chips
Then Change chip Periodic Mode
1.Configure REQ_POL, REQ_WIDTH REAL necessary. FILTER_SELECT necessary. appropriate SCALE, BIG_SCALE AUTO_FLUSH values. necessary desired input format. example, chip uses SUM_CLR, mode, uses round bits.
Texas Instruments Inc.
2000
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