SBAS328 JULY 2004 Precision Analog-to-Digital Converter (ADC) Dig
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MSC1202
SBAS328 JULY 2004
Precision Analog-to-Digital Converter (ADC) Digital-to-Analog Converter (DAC) with 8051 Microcontroller Flash Memory
FEATURES
ANALOG FEATURES BITS MISSING CODES BITS EFFECTIVE RESOLUTION 200Hz Noise: 600nV 10Hz FROM PRECISION ON-CHIP VOLTAGE REFERENCE DIFFERENTIAL/SINGLE-ENDED CHANNELS ON-CHIP OFFSET/GAIN CALIBRATION OFFSET DRIFT: 0.02ppm/°C GAIN DRIFT: 0.5ppm/°C ON-CHIP TEMPERATURE SENSOR SELECTABLE BUFFER INPUT BURNOUT DETECT 8-BIT CURRENT DIGITAL FEATURES Microcontroller Core 8051-COMPATIBLE HIGH-SPEED CORE: Clocks Instruction Cycle 33MHz ON-CHIP OSCILLATOR WITH 32kHz CAPABILITY SINGLE INSTRUCTION 121ns DUAL DATA POINTER Memory FLASH MEMORY FLASH MEMORY PARTITIONING ENDURANCE ERASE/WRITE CYCLES, YEAR DATA RETENTION BYTES DATA SRAM IN-SYSTEM SERIALLY PROGRAMMABLE FLASH MEMORY SECURITY BOOT Peripheral Features DIGITAL PINS ADDITIONAL 32-BIT ACCUMULATOR 16-BIT TIMER/COUNTERS SYSTEM TIMERS PROGRAMMABLE WATCHDOG TIMER FULL DUPLEX USART BASIC SPIq BASIC I2Cq POWER MANAGEMENT CONTROL INTERNAL CLOCK DIVIDER IDLE MODE CURRENT 200µA STOP MODE CURRENT 100nA DIGITAL BROWNOUT RESET ANALOG VOLTAGE DETECT INTERRUPT SOURCES GENERAL FEATURES PACKAGE: QFN-36 POWER: INDUSTRIAL TEMPERATURE RANGE: -40°C +85°C POWER SUPPLY: 2.7V 5.25V
APPLICATIONS
INDUSTRIAL PROCESS CONTROL INSTRUMENTATION LIQUID/GAS CHROMATOGRAPHY BLOOD ANALYSIS SMART TRANSMITTERS PORTABLE INSTRUMENTS WEIGH SCALES PRESSURE TRANSDUCERS INTELLIGENT SENSORS PORTABLE APPLICATIONS SYSTEMS
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. trademarks property their respective owners.
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
Copyright 2004, Texas Instruments Incorporated
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PACKAGE/ORDERING INFORMATION(1)
FLASH MEMORY PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE -40°C +85°C -40°C +85°C PACKAGE MARKING MSC1202Y2 MSC1202Y3
PRODUCT MSC1202Y2 MSC1202Y3
PACKAGE-LEAD QFN-36 QFN-36
NOTE: most current package ordering information, Package Option Addendum located this data sheet.
ABSOLUTE MAXIMUM RATINGS(1)
Analog Inputs Input Current 100mA, Momentary Input Current 10mA, Continuous Input Voltage AGND 0.5V AVDD 0.5V Power Supply DVDD DGND -0.3V AVDD AGND -0.3V AGND DGND -0.3V +0.3V VREF AGND -0.3V AVDD 0.3V Digital Input Voltage DGND -0.3V DVDD 0.3V Digital Output Voltage DGND -0.3V DVDD 0.3V Maximum Junction Temperature +150°C Operating Temperature Range -40°C +85°C Storage Temperature Range -65°C +150°C Lead Temperature (soldering, 10s) +300°C Package Power Dissipation 2038mW Output Current Pins 200mA Output Short Circuit Thermal Resistance, Junction-to-Ambient (JA) 31.9°C/W Thermal Resistance, Junction-to-Case (JC) 0.9°C/W Digital Outputs Output Current 100mA, Continuous Source/Sink Current 100mA Power Maximum 300mA NOTE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute-maximumrated conditions extended periods affect device reliability.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit damaged ESD. Texas Instruments recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
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MSC1202Yx FAMILY FEATURES
FEATURES(1) Flash Program Memory (Bytes) Flash Data Memory (Bytes) Internal Scratchpad (Bytes) MSC1202Y2(2) MSC1202Y3(2)
NOTES: peripheral features same devices; flash memory size only difference. last digit part number represents onboard flash size (2N)kBytes.
ELECTRICAL CHARACTERISTICS: AVDD
specifications from TMIN TMAX, DVDD +2.7V 5.25V, fMOD 15.625kHz, Buffer fDATA 10Hz, Bipolar, VREF (REF IN+) (REF IN-) +2.5V, unless otherwise noted. MSC1202Yx PARAMETER ANALOG INPUT (AIN0-AIN5, AINCOM) Analog Input Range Full-Scale Input Voltage Range Differential Input Impedance Input Current Bandwidth Fast Settling Filter Sinc2 Filter Sinc3 Filter Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources OFFSET Offset Range Offset Monotonicity Offset Gain Error Offset Gain Error Drift CONDITION Buffer Buffer (In+) (In-) Buffer Buffer -3dB -3dB -3dB User-Selectable Gain Ranges Buffer Multiplexer Channel Off, +25°C Buffer AGND AGND 50mV 7/PGA 0.469 fDATA 0.318 fDATA 0.262 fDATA ±VREF/(2 PGA) ±1.0 Bits Range ppm/°C AVDD AVDD ±VREF/PGA UNITS
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ELECTRICAL CHARACTERISTICS: AVDD (Cont.)
specifications from TMIN TMAX, DVDD +2.7V 5.25V, fMOD 15.625kHz, Buffer fDATA 10Hz, Bipolar, VREF (REF IN+) (REF IN-) +2.5V, unless otherwise noted. MSC1202Yx PARAMETER SYSTEM PERFORMANCE Resolution ENOB Output Noise Missing Codes Integral Nonlinearity Offset Error Offset Drift(1) Gain Error(2) Gain Error Drift(1) System Gain Calibration Range System Offset Calibration Range Common-Mode Rejection CONDITION UNITS
Typical Characteristics Sinc3 Filter Point Fit, Differential Input After Calibration Before Calibration After Calibration Before Calibration ±0.0004 0.02 0.005 ±0.0015
Bits Bits Bits %FSR FS/°C ppm/°C µV/°C
AVDD(2) AVDD
Normal Mode Rejection Power-Supply Rejection VOLTAGE REFERENCE INPUTS Reference Input Range VREF Common-Mode Rejection Input Current ON-CHIP VOLTAGE REFERENCE Output Voltage Short-Circuit Current Source Short-Circuit Current Sink Short-Circuit Duration Startup Time from Power Temperature Sensor Temperature Sensor Voltage Temperature Sensor Coefficient IDAC OUTPUT CHARACTERISTICS Full-Scale Output Current Maximum Short-Circuit Current Duration Compliance Voltage ANALOG POWER-SUPPLY REQUIREMENTS Power-Supply Voltage Analog Current Current IADC
60Hz, fDATA 10Hz 50Hz, fDATA 50Hz 60Hz, fDATA 60Hz fSIG 50Hz, fDATA 50Hz fSIG 60Hz, fDATA 60Hz -20log(VOUT/VDD)(3) IN+, VREF (REF IN+) (REF IN-) VREF 2.5V, VREFH +25°C VREFH
AGND
Sink Source
1.25 Indefinite Indefinite AVDD
+25°C
VREF Supply Current IDAC Supply Current
IVREF IIDAC
AVDD Analog OFF, ALVD OFF, PDADC PDIDAC Buffer 128, Buffer Buffer 128, Buffer IDAC
4.75
5.25
NOTES: Calibration minimize these errors. gain calibration cannot have more than AVDD 1.5V with buffer calibrate gain, turn buffer off. DVOUT change digital result.
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ELECTRICAL CHARACTERISTICS: AVDD
specifications from TMIN TMAX, AVDD +3V, DVDD +2.7V 5.25V, fMOD 15.625kHz, Buffer fDATA 10Hz, Bipolar, VREF (REF IN+) (REF IN-) +1.25V, unless otherwise noted. MSC1202Yx PARAMETER ANALOG INPUT (AIN0-AIN5, AINCOM) Analog Input Range Full-Scale Input Voltage Range Differential Input Impedance Input Current Bandwidth Fast Settling Filter Sinc2 Filter Sinc3 Filter Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources OFFSET Offset Range Offset Monotonicity Offset Gain Error Offset Gain Error Drift SYSTEM PERFORMANCE Resolution ENOB Output Noise Missing Codes Integral Nonlinearity Offset Error Offset Drift(1) Gain Error(2) Gain Error Drift(1) System Gain Calibration Range System Offset Calibration Range Common-Mode Rejection CONDITION Buffer Buffer (In+) (In-) Buffer Buffer -3dB -3dB -3dB User-Selectable Gain Ranges Buffer Multiplexer Channel Off, +25°C Buffer AGND AGND 50mV 7/PGA 0.469 fDATA 0.318 fDATA 0.262 fDATA ±VREF/(2 PGA) ±1.5 Typical Characteristics Sinc3 Filter Point Fit, Differential Input After Calibration Before Calibration After Calibration Before Calibration ±0.0004 0.02 0.005 ±0.0015 Bits Range ppm/°C Bits Bits Bits %FSR FS/°C ppm/°C µV/°C AVDD AVDD ±VREF/PGA UNITS
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AVDD(2) AVDD
Normal Mode Rejection Power-Supply Rejection VOLTAGE REFERENCE INPUTS Reference Input Range VREF Common-Mode Rejection Input Current ON-CHIP VOLTAGE REFERENCE Output Voltage Short-Circuit Current Source Short-Circuit Current Sink Short-Circuit Duration Startup Time from Power Temperature Sensor Temperature Sensor Voltage Temperature Sensor Coefficient IDAC OUTPUT CHARACTERISTICS Full-Scale Output Current Maximum Short-Circuit Current Duration Compliance Voltage POWER-SUPPLY REQUIREMENTS Power-Supply Voltage Analog Current Current
fSIG fSIG
60Hz, fDATA 10Hz 50Hz, fDATA 50Hz 60Hz, fDATA 60Hz 50Hz, fDATA 50Hz 60Hz, fDATA 60Hz -20log(DVOUT/DVDD)(3)
IN+, VREF (REF IN+) (REF IN-) VREF 1.25V, VREFH +25°C
AGND
1.25 1.25 Indefinite Indefinite AVDD
Sink Source
+25°C
IADC
VREF Supply Current IDAC Supply Current
IVREF IIDAC
AVDD Analog OFF, ALVD OFF, PDADC PDIDAC Buffer 128, Buffer Buffer 128, Buffer IDAC
NOTES: Calibration minimize these errors. gain calibration cannot have more than AVDD 1.5V with buffer calibrate gain, turn buffer off. DVOUT change digital result.
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DIGITAL CHARACTERISTICS: DVDD 2.7V 5.25V
specifications from TMIN TMAX, unless otherwise specified. MSC1202Yx PARAMETER POWER-SUPPLY REQUIREMENTS Digital Supply Current CONDITION DVDD Normal Mode, fOSC 1MHz Normal Mode, fOSC 8MHz, Peripherals Internal Oscillator Mode (12.8MHz nominal) Stop Mode, DBOR DVDD Normal Mode, fOSC 1MHz Normal Mode, fOSC 8MHz, Peripherals Internal Oscillator Mode (12.8MHz nominal) Internal Oscillator Mode (25.6MHz nominal) Stop Mode, DBOR DIGITAL INPUT/OUTPUT (CMOS) Logic Level: (except pin) (except pin) Ports Input Leakage Current, Input Mode Input Leakage Current Hysteresis VOL, Ports Output Modes VOL, Ports Output Modes VOH, Ports Strong Drive Output VOH, Ports Strong Drive Output Ports Pull-Up Resistors UNITS
4.75
5.25
DVDD DGND DVDD DGND DVDD DVDD DVDD
DVDD DVDD
30mA, (20mA) 30mA, (20mA)
DVDD
FLASH MEMORY CHARACTERISTICS: DVDD 2.7V 5.25V
tUSEC 1µs, tMSEC MSC1202Yx PARAMETER Flash Flash Mass Flash Memory Endurance Memory Data Retention Page Erase Time Memory Write Time CONDITION 100,000 1,000,000 UNITS cycles Years
with Value FTCON with Value FTCON
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ELECTRICAL CHARACTERISTICS(1): DVDD 2.7V 5.25V
MSC1202Yx PARAMETER PHASE LOCK LOOP (PLL) Input Frequency Range Mode Mode Lock Time INTERNAL OSCILLATOR (IO) Mode Mode Internal Oscillator Settling Time CONDITION External Crystal/Clock Frequency (fOSC) PLLDIV (default) PLLDIV (must user) Within Typical Characteristics 12.8 25.6 Within 32.768 14.7456 29.4912 UNITS
NOTE: Parameters valid over operating temperature range, unless otherwise specified.
EXTERNAL CLOCK DRIVE TIMING
2.7V 3.6V SYMBOL External Clock Mode fOSC(1) 1/tOSC(1) fOSC(1) tHIGH tLOW FIGURE PARAMETER External Crystal Frequency (fOSC) External Clock Frequency (fOSC) External Ceramic Resonator Frequency (fOSC) HIGH Time(2) Time(2) Rise Time(2) Fall Time(2) 4.75V 5.25V UNITS
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NOTES: tCLK 1/fOSC oscillator clock period clock divider These values characterized 100% production tested.
tHIGH 0.8V 0.8V tLOW 0.8V tOSC
0.8V
FIGURE External Clock Drive CLK.
SERIAL FLASH PROGRAMMING TIMING
SYMBOL tRRD tRFD FIGURE PARAMETER width rise P1.0 internal pull high falling start Input signal falling setup time falling P1.0 hold time tOSC tOSC UNIT
tRRD P1.0/PROG NOTE: P1.0 internally pulled-up with ~11k during high. tRFD,
FIGURE Serial Flash Programming Power-On Timing.
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CONFIGURATION
View
P3.6/SCK/SCL/CLKS
P3.0/RxD0
P3.1/TxD0
P3.3/INT1
P3.2/INT0
XOUT DGND AVDD AGND AGND AINCOM IDAC
DVDD DGND P1.6/INT4 P1.5/INT3 P1.4/INT2/SS P1.3/DIN P1.2/DOUT P1.1 P1.0/PROG
MSC1202
P1.7/INT5
P3.5/T1
P3.4/T0
P3.7
REFOUT/REFIN+
REFIN-
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
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DESCRIPTIONS
19-25, NAME XOUT DGND AVDD AGND AINCOM IDAC REFOUT/REF AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 P1.0-P1.7 DESCRIPTION crystal oscillator supports parallel resonant fundamental frequency crystals ceramic resonators. also input there external clock source instead crystal. crystal oscillator XOUT supports parallel resonant fundamental frequency crystals ceramic resonators. XOUT serves output crystal amplifier. Digital Ground HIGH reset input tOSC periods will reset device. connection Analog Power Supply Analog Ground Analog Input (can analog common single-ended inputs analog input differential inputs) IDAC Output Internal Voltage Reference Output/Voltage Reference Positive Input Voltage Reference Negative Input (tie AGND internal voltage reference) Analog Input Channel Analog Input Channel Analog Input Channel Analog Input Channel Analog Input Channel Analog Input Channel Port bidirectional port (refer P1DDRL, AEH, P1DDRH, AFH, port configuration control). Port 1-Alternate Functions: PORT ALTERNATE MODE P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 29-36 DVDD P3.0-P3.7 Digital Power Supply Port bidirectional port (refer P3DDRL, B3H, P3DDRH, B4H, port configuration control). Port 3-Alternate Functions: PORT P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 ALTERNATE RxD0 TxD0 INT0 INT1 SCK/SCL/CLKS MODE Serial Port Input Serial Port Output External Interrupt External Interrupt Timer External Input Timer External Input SCK/SCL/Various Clocks (refer PASEL, F2H) PROG DOUT INT2/SS INT3 INT4 INT5 Serial Programming Mode Serial Data Serial Data External Interrupt External Interrupt External Interrupt External Interrupt
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2/Slave Select
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TYPICAL CHARACTERISTICS
AVDD +5V, DVDD +5V, fOSC 8MHz, fMOD 15.625kHz, Bipolar, Buffer VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified.
EFFECTIVE NUMBER BITS DATA RATE ENOB (rms) ENOB (rms) Data Rate (SPS) 1000 PGA128 Sinc3 Filter, Buffer PGA1
EFFECTIVE NUMBER BITS DECIMATION RATIO 1000 Decimation Ratio fMOD fDATA 1500 2000 Sinc3 Filter, Buffer PGA128 PGA1
ENOB (rms)
1000 Decimation Ratio fMOD fDATA 1500 2000 PGA128 Sinc3 Filter, Buffer
ENOB (rms)
PGA1
PGA1 PGA128
AVDD Sinc3 Filter, VREF 1.25V, Buffer 1000 Decimation Ratio fMOD fDATA 1500 2000
EFFECTIVE NUMBER BITS DECIMATION RATIO
ENOB (rms)
ENOB (rms)
EFFECTIVE NUMBER BITS DECIMATION RATIO
PGA1 PGA128
1000 Decimation Ratio fMOD fDATA 1500 2000 AVDD Sinc3 Filter, VREF 1.25V, Buffer
PGA1 PGA128
Sinc2 Filter
1000 Decimation Ratio 1500 fMOD fDATA 2000
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EFFECTIVE NUMBER BITS DECIMATION RATIO
EFFECTIVE NUMBER BITS DECIMATION RATIO
TYPICAL CHARACTERISTICS (Cont.)
AVDD +5V, DVDD +5V, fOSC 8MHz, fMOD 15.625kHz, Bipolar, Buffer VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified.
FAST SETTLING FILTER EFFECTIVE NUMBER BITS DECIMATION RATIO
EFFECTIVE NUMBER BITS fMOD (set with ACLK) fMOD 203kHz fMOD 15.6kHz fMOD 110kHz
ENOB (rms)
1000 Decimation Ratio 1500 fMOD fDATA 2000
ENOB (rms)
fMOD 31.25kHz
Fast Settling Filter
fMOD 62.5kHz Data Rate (SPS) 100k
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ANALOG SUPPLY CURRENT
Analog Supply Current (mA)
CURRENT
+85°C
AVDD Buffer
+25°C
IADC (µA)
128, VREF DBOR ALVD IDAC
AVDD Buffer AVDD Buffer AVDD Buffer
-40°C
Analog Supply Voltage
Setting
DIGITAL SUPPLY CURRENT FREQUENCY
DIGITAL SUPPLY CURRENT CLOCK DIVIDER Divider Values
Digital Supply Current (mA)
Digital Supply Current (mA)
1024
DVDD Clock Frequency (MHz)
Clock Frequency (MHz)
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TYPICAL CHARACTERISTICS (Cont.)
AVDD +5V, DVDD +5V, fOSC 8MHz, fMOD 15.625kHz, Bipolar, Buffer VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified.
DIGITAL SUPPLY CURRENT SUPPLY VOLTAGE
Digital Supply Current (mA)
NORMALIZED GAIN Buffer
+85°C +25°C -40°C
Normalized Gain
Supply Voltage
Setting
MODE TEMPERATURE AVDD DVDD 3.3V 4.75V 2.7V 5.25V
Output
Output
Temperature (°C)
Output Current (mA)
MODE TEMPERATURE AVDD DVDD
Frequency (MHz)
5.25V 4.75V
Temperature (°C)
MSC1202
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CMOS DIGITAL OUTPUT
Frequency (MHz)
Output Voltage
DESCRIPTION
MSC1202Yx completely integrated family mixedsignal devices incorporating high-resolution delta-sigma ADC, 8-bit IDAC, 8-channel multiplexer, burnout detect current sources, selectable buffered input, offset DAC, programmable gain amplifier (PGA), temperature sensor, voltage reference, 8-bit microcontroller, Flash Program Memory, Flash Data Memory, Data SRAM, shown Figure On-chip peripherals include additional 32-bit accumulator, basic SPI, basic I2C, UART, multiple digital input/output ports, watchdog timer, low-voltage detect, on-chip power-on reset, brownout reset, timer/counters, system clock divider, PLL, on-chip oscillator, external interrupts. device accepts low-level differential single-ended signals directly from transducer. provides bits resolution bits no-missing-code performance using Sinc3 filter with programmable sample rate. also selectable filter that allows high-resolution single-cycle conversion. microcontroller core 8051 instruction compatible. microcontroller core optimized 8051 core that executes three times faster than standard 8051 core, given same clock source. This makes possible device lower external clock frequency achieve same performance lower power than standard 8051 core.
MSC1202Yx allows user uniquely configure Flash memory meet needs their application. Flash programmable down 2.7V using serial programming. Flash endurance typically Erase/Write cycles. part separate analog digital supplies, which independently powered from 2.7V +5.25V. operation, power dissipation part typically less than 3mW. MSC1202Yx packaged QFN-36 package. MSC1202Yx designed high-resolution measurement applications smart transmitters, industrial process control, weigh scales, chromatography, portable instrumentation.
ENHANCED 8051 CORE
instructions MSC1202 family perform exactly same functions they would standard 8051. effect bits, flags, registers same. However, timing different. MSC1202 family utilizes efficient 8051 core which results improved instruction execution speed between times faster than original core same external clock speed clock cycles instruction versus clock cycles instruction, shown Figure This translates into effective throughput improvement more than times, using same code same external clock speed. Therefore, device frequency 33MHz MSC1202Yx actually performs equivalent execution speed 82.5MHz compared
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AVDD AVDD
AGND
REFOUT/REFIN+ REFIN-
DVDD
DGND
Burnout Detect
Temperature Sensor
VREF
ALVD DBOR
Timers/ Counters
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AINCOM
8-Bit Offset
Alternate Functions Modulator FLASH Bytes SRAM Digital Filter PORT1 DOUT PROG USART SCK/SCL/CLKS
8051 PORT3 On-Chip Oscillator
Burnout Detect
AGND IDAC 8-Bit IDAC
System Clock Divider
XOUT
FIGURE Block Diagram.
instr_cycle
cpu_cycle
FIGURE Instruction Cycle Timing.
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SBAS328
standard 8051 core. This allows user device slower clock speeds, which reduces system noise power consumption, provides greater throughput. This performance difference seen Figure timing software loops will faster with MSC1202. However, timer/counter operation MSC1202 maintained clocks increment optionally clocks increment.
MSC1202 also provides dual data pointers (DPTRs). Furthermore, improvements were made peripheral features that off-load processing from core user, further improve efficiency. instance, 32-bit accumulator added significantly reduce processing overhead multiple byte data from other sources. This allows 32-bit addition shifting accomplished instruction cycles, compared hundreds instruction cycles through software implementation.
Single-Byte, Single-Cycle Instruction
Family Device Compatibility
hardware functionality configuration across MSC1202 family fully compatible. user, only difference between family members memory configuration. This makes migration between family members simple. Code written MSC1202Y2 executed directly MSC1202Y3. This gives user ability subtract software functions freely migrate between family members. Thus, MSC1202 become standard device used across several application platforms.
MSC1202 Timing
PSEN Internal AD0-AD7 Internal A8-A15 Cycles Cycles
Standard 8051 Timing
Family Development Tools
MSC1202 fully compatible with standard 8051 instruction set. This means that user develop software MSC1202 with existing 8051 development tools. Additionally, complete, integrated development environment provided with each demo board, third-party developers also provide support.
PSEN AD0-AD7 PORT Single-Byte, Single-Cycle Instruction
Power Down Modes
MSC1202 power several peripherals into IDLE. This accomplished shutting clocks those sections, shown Figure
FIGURE Comparison MSC1202 Timing Standard 8051 Timing.
tSYS Clock Divider tCLK SPICON/ I2CCON PDCON.0 USEC Flash Write FTCON (30µs 40µs) [3:0] Timing Flash Erase (5ms 11ms) FTCON [7:4] Timing milliseconds interrupt PDCON.1 SECINT HMSEC PDCON.2 ACLK divide ADCON3 ADCON2 Output Rate 100ms WDTCON watchdog seconds interrupt SCL/SCK
MSECH MSECL
MSINT
Power Down PDCON.3
Decimation Ratio Modulator Clock
Timers IDLE Clock
USART
FIGURE MSC1202 Timing Chain Clock Control.
MSC1202
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OVERVIEW
MSC1202 structure shown Figure figure lists components that make ADC, along with corresponding special function register (SFR) associated with each component.
AVDD
Burnout Detect
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AINCOM Temperature Sensor
REFIN+ fSAMP
Input Multiplexer Buffer Sample Hold
Burnout Detect
REFIN- AGND ADCON0 ACLK
Offset ODAC
ADMUX
REFIN+
fMOD
fDATA
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FAST Modulator SINC2 SINC3 AUTO
Offset Calibration Register
Gain Calibration Register
Result Register
Summation Block
REFIN- ADCON1 ADCON2 ADCON3
ADRES SUMR SSCON
FIGURE MSC1202 Structure.
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INPUT MULTIPLEXER
input multiplexer provides combination differential inputs selected input channel, shown Figure AIN0 selected positive differential input channel, other channel selected negative differential input channel. With this method, possible have fully differential input channels. also possible switch polarity differential input pair negate offset voltages.
BURNOUT DETECT
When Burnout Detect (BOD) control configuration register (ADCON0 DCH), current sources enabled. current source positive input channel sources approximately current. current source negative input channel sinks approximately 2µA. This allows detection open circuit (full-scale reading) short circuit (small differential reading) selected input differential pair. Enabling buffer recommended when enabled.
INPUT BUFFER
AIN0
AIN1 AVDD
analog input impedance always high, regardless setting (when buffer enabled). With buffer enabled, input voltage range reduced analog power-supply current higher. limitation input voltage range acceptable, then buffer always preferred.
Burnout Detect (2µA)
AIN2
input impedance MSC1202 without buffer 7M/PGA. buffer controlled state control register (ADCON0 DCH).
AIN3 AIN4 Buffer
ANALOG INPUT
AIN5 Burnout Detect (2µA) Temperature Sensor AVDD AVDD
AGND
1MHz pedance ACLK Frequency where ACLK frequency (fACLK) ACLK ACLK fMOD Figure shows basic input structure MSC1202.
AINCOM
RSWITCH typical) High Impedance 18pF 36pF
FIGURE Input Multiplexer Configuration. addition, current sources supplied that will source sink current detect open short circuits pins.
Sampling Frequency fSAMP fSAMP fMOD fMOD fMOD fMOD fMOD AGND
TEMPERATURE SENSOR
On-chip diodes provide temperature sensing capability. When configuration register input diodes connected input ADC. other channels open.
FIGURE Analog Input Structure (without buffer).
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When buffer selected, input impedance analog input changes with ACLK clock frequency (ACLK F6H) gain (PGA). relationship
gains 128. Using actually improve effective resolution ADC. instance, with ±2.5V fullscale range, resolve 76µV. With ±19mV full-scale range, resolve 2µV, shown Table
MEASUREMENT RESOLUTION (µV)
requires positive full-scale differential input signal. then computes gain value nullify gain errors system. Each these calibrations will take seven tDATA periods complete. Calibration should performed after power change temperature, power supply, voltage reference, decimation ratio, buffer, change PGA. Calibration will remove effects Offset DAC; therefore, changes Offset register should done after calibration. completion calibration, Interrupt goes high, which indicates calibration finished valid data available.
SETTING
FULL-SCALE RANGE ±2.5 ±1.25 ±0.625 ±0.313 ±0.156 ±0.0781 ±0.039 ±0.019
ENOB 200Hz (BITS) 15.6 15.5 15.4 15.4 15.3 15.2 14.2
DIGITAL FILTER
Digital Filter either Fast Settling, Sinc2, Sinc3 filter, shown Figure addition, Auto mode changes Sinc filter after input channel changed. When switching channel, will Fast Settling filter, next conversions first which should discarded. will then Sinc2 followed Sinc3 filter improve noise performance. This combines low-noise advantage Sinc3 filter with quick response Fast Settling Time filter. frequency response each filter shown Figure
TABLE ENOB Versus PGA.
OFFSET
PRODUCT PREVIEW
analog output from offset half full-scale input range using ODAC register (SFR E6H). ODAC (Offset DAC) register 8bit value; sign seven LSBs provide magnitude offset. Since ODAC introduces analog (instead digital) offset PGA, using ODAC does reduce range ADC.
Adjustable Digital Filter Sinc3
MODULATOR
modulator single-loop 2nd-order system. modulator runs clock speed (fMOD) that derived from using value Analog Clock register (ACLK, F6H). data output rate Data Rate fDATA where fMOD fMOD Decimation Ratio
Modulator Sinc2 Data
Fast Settling
fCLK ACLK (ACLK
FILTER SETTLING TIME FILTER SETTLING TIME (Conversion Cycles) 3(1) 2(1) 1(1)
CALIBRATION
offset gain errors MSC1202, complete system, reduced with calibration. Calibration controlled through ADCON1 register (SFR DDH), bits CAL2:CAL0. Each calibration process takes seven tDATA periods (data conversion time) complete. Therefore, takes tDATA periods complete both offset gain calibration. system calibration, appropriate signal must applied inputs. system offset calibration requires zero-differential input signal. then computes offset value that will nullify offset system. system gain calibration
Sinc3 Sinc2 Fast
NOTE: With Synchronized Channel Changes.
AUTO MODE FILTER SELECTION CONVERSION CYCLE Discard Fast Sinc2 Sinc3
FIGURE Filter Step Responses.
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SINC3 FILTER RESPONSE (-3dB 0.262 fDATA)
Gain (dB)
external voltage reference differential represented voltage difference between pins: REFIN+ REFIN-. absolute voltage either (REFIN+ REFIN-) range from AGND AVDD; however, differential voltage must exceed AVDD. differential voltage reference provides easy means performing ratiometric measurement.
-100 -120 fDATA SINC2 FILTER RESPONSE (-3dB 0.318 fDATA)
IDAC
8-bit IDAC MSC1202 used provide current source that used ratiometric measurements. full-scale output current IDAC approximately 1mA. equation IDAC output current IDACOUT IDAC 3.8µA
DIGITAL BROWNOUT RESET
MSC1202 contains programmable digital brownout reset (DBOR). When digital supply drops below value programmed HCR1, device held reset state until supply rises above this value. Once supply rises above this value, device released from reset executes normal sequence. digital supply voltage comparison performed against analog reference, therefore, analog supply must within valid operating range order DBOR.
Gain (dB)
-100 -120 fDATA FAST SETTLING FILTER RESPONSE (-3dB 0.469 fDATA)
ANALOG VOLTAGE DETECT
MSC1202 contains analog low-voltage detect. When analog supply drops below value programmed LVDCON (SFR E7H), interrupt generated.
POWER-UP-SUPPLY VOLTAGE RAMP RATE
-100 -120 fDATA NOTE: fDATA Data Output Rate 1/tDATA
built-in (on-chip) power-on reset circuitry designed accommodate analog digital supply ramp rates slow 1V/10ms. ensure proper operation, power supply should ramp monotonically specified rate. DBOR enabled, ramp rate slower.
RESET
typical reset circuit shown Figure
FIGURE Filter Frequency Responses.
DVDD
DVDD MSC1202
VOLTAGE REFERENCE
voltage reference used MSC1202 either internal external. power-up configuration voltage reference 2.5V internal. selection voltage reference made through ADCON0 register (SFR DCH). internal voltage reference selectable either 1.25V (AVDD 2.7V 5.25V) 2.5V (AVDD 4.1V 5.25V). internal VREF used, should turned off. REFOUT/REFIN+ should have 0.1µF capacitor AGND.
FIGURE Typical Reset Circuit.
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Gain (dB)
CLOCKS
MSC1202 operate four separate clock modes: internal oscillator mode (IOM), external clock mode (ECM), external oscillator mode (EOM), mode. block diagram shown Figure clock mode MSC1202 selected CLKSEL bits HCR2. default mode device. Serial Flash Programming mode uses mode (the HCR2 CLKSEL bits have effect). Table shows active clock mode various startup conditions.
Phase Lock Loop (PLL) mode (HCR2, CLKSEL HCR2, CLKSEL 100), execute from external 32.768 crystal. This mode enables phase-lock loop (PLL) circuit that synthesizes selected clock frequencies (PLL mode mode). external clock detected startup, then will begin execution mode after startup. external clock detected startup, then device will revert mode shown Table status determined first writing PLLLOCK (enable) then reading PLLLOCK status PLLH SFR. frequency preloaded with default trimmed values. However, frequency fine-tuned writing PLLH PLLL SFRs. equation frequency Frequency ((PLL9:PLL0) fOSC where fOSC 32.768kHz. default value modes automatically loaded into PLLDIV SFR. different connections external clocks, Figures
Internal Oscillator
IOM, executes either mode HCR2, CLKSEL 111) mode HCR2, CLKSEL 110).
External Crystal
(HCR2, CLKSEL 011), execute from external crystal external ceramic resonator. external crystal detected startup, then will begin execution after startup. external crystal detected startup, then device will revert mode shown Table
External Oscillator
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(HCR2, CLKSEL 010), execute from external oscillator external clock. external clock detected startup, then will begin execution after startup. external crystal detected startup, then device will revert mode shown Table
tOSC STOP Phase Detector Charge Pump 100k tPLL/tIOM tSYS SYSDIV tCLK
XOUT
LF/HF Mode
Internal Oscillator
PLLDIV
FIGURE Clock Block Diagram.
SELECTED CLOCK MODE (HCR2, CLKCON2:0) External Crystal Mode (ECM) Active Crystal Present Crystal Present External Oscillator Mode (EOM) Active Clock Present Clock Present Internal Oscillator Mode (IOM) Mode Mode PLL(2) Mode Mode Active 32.768kHz Clock Clock Present Active 32.768kHz Clock Clock Present External Clock Mode Mode Mode Mode Mode Nominal: Mode Rate Mode Nominal: Mode Rate External Crystal Mode Mode STARTUP CONDITION(1) ACTIVE CLOCK MODE (fSYS)
NOTES: Clock detection only done startup; refer Electrical Characteristics parameter tRFD Figure operation requires that both AVDD DVDD within their specified operating range.
TABLE Active Clock Modes.
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XOUT
MSC1202 implements basic interface which includes hardware simple serial data transfers. Figure shows block digram SPI. peripheral supports master slave mode, full duplex data transfers, both clock polarities, both clock phases, order, slave select. timing diagram supported data transfers shown Figure pins needed data transfer Data (DIN), Data (DOUT) serial clock (SCK). slave select (SS) also used control output data DOUT. used shifting data both master slave modes. DOUT used shifting data both master slave modes. used synchronize transfer data both master slave modes. always generated master. generation master mode done simply toggling port pin, generation accomplished configuring output PASEL (SFR F2H). list most common methods generating follows, complete list clock sources found referring PASEL SFR. Toggle setting clearing port pin.
NOTE: Refer crystal manufacturer's specification values.
FIGURE External Crystal Connection.
External Clock
32.768kHz XOUT
Memory Write Pulse (WR) which idle high. Whenever external memory write command (MOVX) executed then pulse seen P3.6. This method used only CPOL `1'. Memory Write Pulse toggle version: this mode, toggles whenever external write command (MOVX) executed. T0_Out signal used clock. pulse generated whenever Timer expires. idle state signal low, this used only CPOL cleared `0'. T0_Out Toggle: toggles whenever Timer expires. T1_Out signal used clock. pulse generated whenever Timer expires. idle state signal low, this used only CPOL cleared `0'.
DOUT
NOTE: Typical configuration shown.
FIGURE Connection.
DOUT /I2C Data Write TX_CLK SPICON I2CCON Counter Start/Stop Detect CNT_CLK Logic SCK/SCL Control P3.6 Stretch Control RX_CLK /I2C Data Read P1.4 P1.2
T1_Out Toggle: toggles whenever Timer expires. used control output data DOUT when MSC1202 slave mode. function enabled disabled SPICON SFR. When enabled, input slave device must externally asserted before master device exchange data with slave device. must before data transactions must stay duration transaction. When high then data will shifted into shift register will counter increment. When enabled, also controls drive line DOUT (P1.2). When slave mode, DOUT will driven when high then DOUT will high impedance.
P1.3
CLKS (refer PASEL, F2H)
FIGURE SPI/I2C Block Diagram.
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FIGURE External Clock Connection.
Cycle (CPOL
(CPOL
Sample Input (CPHA Data Sample Input (CPHA Data Slave Slave CPHA Transfer Progress Asserted First Edge CNTIF (dependent CPHA bit) Negated Slave CPHA Transfer Progress
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FIGURE Timing Diagram. generates interrupt ECNT (AIE.2) indicate that transfer/reception byte complete. interrupt goes high whenever counter value equal (indicating that SCKs have occurred). interrupt cleared reading writing SPIDATA register. During data transfer, actual counter value read from SPICON SFR. Master Mode Application Flow Configure port pins. Configure SPI. Assert enable slave communications applicable). Write data SPIDATA. Generate SCKs. Read received data from SPIDATA. Slave Mode Application Flow Configure ports pins. Enable applicable). Configure SPI. Write data SPIDATA. Wait Count Interrupt SCKs). Read data from SPIDATA. Warning: SPIDATA read before next transaction ECNT interrupt will removed previous data will lost.
Power Down
powered down PDSPI power control register (PDCON). This needs cleared enable function. When powered down pins P1.2, P1.3, P1.4, P3.6 revert general-purpose pins.
Application Flow
Explained below steps typical application usage flow master slave mode:
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pins needed transfer are: serial clock (SCL) serial data (SDA-implemented connecting DOUT externally). MSC1202 supports: Master slave operation (control software) Standard fast modes transfer Clock stretching General call When used mode, pins (P1.3) DOUT (P1.2) should tied together externally. should configured input DOUT should configured open drain standard 8051 setting P1DDR (DOUT should high that pulled low). MSC1202 generate interrupts: interrupt START/STOP interrupt (AIE.3) interrupt counter interrupt (AIE.2) START/STOP interrupt generated when START condition STOP condition detected bus. counter generates interrupt complete (8-bit) data transfer also after transfer ACK/NACK. counter serial transfer always incremented falling edge reset reading writing I2CDATA (SFR 9BH) when START/STOP condition detected. counter polled used interrupt. counter interrupt occurs when counter value equal indicating that eight bits data have been transferred. mode also allows interrupt generation data transfer (I2CCON.CNTSEL). This used ACK/NACK interrupt generation. instance, interrupt configured 8-bit interrupt detection, eighth interrupt generated. Following this interrupt, clock will stretched (SCL held low). interrupt then configured 1-bit detection. ACK/NACK written software, which will terminate clock stretching. next interrupt will generated after ACK/NACK been latched receiving device. interrupt cleared reading writing I2CDATA register. I2CDATA read before next data transfer, interrupt will removed previous data will lost.
Master Operation
source controlled PASEL register generated software.
Transmit
serial data must stable while high. Therefore, writing serial data I2CDATA must coordinated with generation SCL, since transitions interpreted START STOP while high. START STOP conditions must generated software. After serial data been transmitted, generation ACK/NACK clock must enabled writing 0xFFH I2CDATA. This allows master read state ACK/NACK.
Receive
serial data latched into receive buffer rising edge SCL. After serial data been received, ACK/NACK generated writing 0x7FH (for ACK) 0xFFH (for NACK) I2CDATA.
Slave Operation
Slave operation supported, address recognition, determination, ACK/NACK must done under software control.
Transmit
Once address recognition, determination, ACK/NACK complete, serial data transferred written I2CDATA. data automatically shifted based master SCL. After data transmission, CNTIF generated stretched MSC1202 until I2CDATA register written with 0xFFH. ACK/NACK from master then read.
Receive
Once address recognition, determination, ACK/NACK complete, I2CDATA must written with 0xFFH enable data reception. Upon completion data shift, MSC1202 generates interrupt stretches SCL. Received data then read from I2CDATA. After serial data been received, ACK/NACK generated writing 0x7FH (for ACK) 0xFFH (for NACK) I2CDATA. write I2CDATA clears interrupt clock stretch.
START ADDRESS(2) Condition(1)
R/W(2)
ACK(3)
DATA(2)
ACK(3)
DATA(2)
ACK(3)
STOP Condition(4)
NOTES: Generate software; write 0x7F I2CDATA. I2CDATA register. Generate software. enable count interrupt prior ACK/NACK interrupt use. Generate writing 0x7F I2CDATA; generate NACK writing 0xFF I2CDATA. Generate software; write 0xFF I2CDATA.
FIGURE Timing Diagram Transmission Reception.
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MEMORY
MSC1202 contains on-chip SFR, Flash Memory, Scratchpad Memory, Boot ROM. registers primarily used control status. standard 8051 features additional peripheral features MSC1202 controlled through SFR. Reading from undefined will return zero; writing undefined registers recommended have indeterminate effects. Flash Memory used both Program Memory Data Memory. user ability select partition size Program Data Memories. partition size through hardware configuration bits, which programmed through serial programming. Both Program Data Flash Memories erasable writable (programmable) user application mode. However, program execution only occur from Program Memory. added precaution, lock feature activated through hardware configuration bits, which disables erase writes first Program Flash Memory entire Program Flash Memory user application mode.
MSC1202 three Hardware (HW) Configuration registers (HCR0, HCR1, HCR2) that programmable only during Flash Memory Programming mode. MSC1202 allows user partition Flash Memory between Program Memory Data Memory. instance, MSC1202Y3 contains Flash Memory on-chip. Through configuration registers, user define partition between Program Memory (PM) Data Memory (DM), shown Tables Figure MSC1202 family offers memory configurations.
HCR0 DFSEL (default) MSC1202Y2 MSC1202Y3
TABLE III. MSC1202Y Flash Partitioning.
HCR0 DFSEL MSC1202Y2 0000-07FF 0000-07FF 0000-0BFF 0000-0FFF 0400-0BFF 0400-0BFF 0400-07FF 0000 MSC1202Y3 0000-0FFF 0000-17FF 0000-1BFF 0000-1FFF 0400-13FF 0400-0BFF 0400-07FF 0000
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FLASH MEMORY
MSC1202 uses memory addressing scheme that separates Program Memory from Data Memory. program data segments overlap since they accessed different instructions. Program Memory fetched microcontroller automatically. There instruction (MOVC) that used explicitly read program area. This commonly used read lookup tables.
(default)
TABLE Flash Memory Partitioning Addresses.
Program Memory
Unused
Select HCR0
Data Memory
FFFFH FC00H FFFFH
Internal Boot F800H Unused Unused
2000H, (Y3)
lash
1000H, (Y2) 0000H,
On-C
1400H, (Y3)
0C00H, (Y2) 0400H,
FIGURE Memory Map.
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important note that Flash Memory readable writable (depending MXWS SFR) user through MOVX instruction when configured either Program Data Memory. This means that user partition device maximum Flash Program Memory size Flash Data Memory) Flash Program Memory Flash Data Memory. This lead undesirable behavior points area Flash Program Memory that being used data storage. Therefore, recommended Flash partitioning when Flash Memory used data storage. Flash partitioning prohibits execution code from Data Flash Memory. Additionally, Program Memory erase/ write disabled through hardware configuration bits (HCR0), while still providing access (read/write/erase) Data Flash Memory. effect memory mapping Program Data Memory straightforward. Program Memory decreased size from Flash Memory. maintain compatibility with MSC121x, Flash Data Memory maps addresses 0400H. Therefore, access Data Memory (through MOVX) will access Flash Memory addresses shown Table
SFRs accessed directly between (128 255). Scratchpad available general-purpose data storage. commonly used place off-chip when total data contents small. Within bytes RAM, there several special-purpose areas.
Addressable Locations
addition direct register access, some individual bits also accessible. These individually addressable bits both area. Scratchpad area, registers addressable. This provides individual bits available software. access distinguished from full-register access type instruction. area, register location ending addressable. Figure shows details on-chip addressing including locations individual bits.
Direct
Addressable
Data Memory
MSC1202 on-chip Flash Data Memory, which readable writable (depending Memory Write Select register) during normal operation (full range). This memory mapped into external Data Memory space, which requires MOVX instruction program. Note that page size bytes both Program Data Memory page must erased before written.
REGISTER
Register illustrated Figure entirely separate from Program Data Memory areas mentioned before. separate class instructions used access registers. There register locations. practice, MSC1202 bytes Scratchpad SFRs. Thus, direct reference upper locations will access. Direct reached locations 255).
Bank
Indirect Direct Scratchpad Direct Special Function Registers Registers
Bank Bank Bank
FIGURE Register Map.
FIGURE Scratchpad Register Addressing.
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Working Registers
part lower bytes RAM, there four banks Working Registers, shown Figure Working Registers general-purpose locations that addressed special way. They designated through Since there four banks, currently selected bank will used instruction using R0-R7. This allows software change context simply switching banks. This controlled Program Status Word register (PSW; 0D0H) area described below. bytes immediately above R0-R7 registers addressable. bits this area directly accessed using addressable instructions.
last used value. Therefore, next value placed Stack Each PUSH CALL will increment appropriate value. Each will decrement well.
Program Memory
After reset, begins execution from Program Memory location 0000H. standard internal Program Memory size MSC1202 family members shown Table enabled Boot will appear from address F800H FBFFH.
STANDARD INTERNAL PROGRAM MEMORY SIZE (BYTES)
MODEL NUMBER MSC1202Y3 MSC1202Y2
Stack
Another Scratchpad area programmer's stack. This area selected using Stack Pointer (SP; 81H) SFR. Whenever call interrupt invoked, return address placed Stack. also available programmer variables, etc., since Stack moved there fixed location within designated Stack. Stack Pointer will default reset. user then move needed. will point
TABLE MSC1202 Maximum Internal Program Memory Sizes.
Boot
There Boot that controls operation during serial programming. Additionally, Boot routines shown Table accessed during user mode enabled. When enabled, Boot routines will located memory addresses F800H-FBFFH during user mode.
DESCRIPTION Return value pointed CADDR(1) Write pointed CADDR(1) Push registers call cmd_parser SBAA076B.pdf Output string Erase flash page Flash write(2) Write flash byte, verify Write flash byte(2) Read config byte from faddr Read xdata code byte Send byte UART0 Send value UART0 Send UART0 Read byte from UART0 Read echo byte UART0 Read echo UART0 Read echo: UART0 Read reversed echo: UART0 baud with received CR(3) Output space UART0 Output UART0
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ADDRESS F802 F805 FBD8 FBDA FBDC FBDE FBE0 FBE2 FBE4 FBE6 FBE8 FBEA FBEC FBEE FBF0 FBF2 FBF4 FBF6 FBF8 FBFA FBFC FBFE
ROUTINE sfr_rd sfr_wr monitor_isr cmd_parser put_string page_erase write_flash write_flash_chk write_flash_byte faddr_data_read data_x_c_read tx_byte tx_hex putx rx_byte rx_byte_echo rx_hex_echo rx_hex_dbl_echo rx_hex_word_echo autobaud putspace1 putcr
DECLARATIONS char sfr_rd(void); void sfr_wr(char void monitor_isr() interrupt void cmd_parser(void); void put_string(char code *string); char page_erase (int faddr, char fdata, char fdm); Assembly only; DPTR address, data char write_flash_chk (int faddr, char fdata, char fdm); void write_flash_byte (int faddr, char fdata); char faddr_data_read(char faddr); char data_x_c_read(int faddr, char fdm); void tx_byte(char); void tx_hex(char); void putx(char); char rx_byte(void); char rx_byte_echo(void); char rx_hex_echo(void); rx_hex_dbl_echo(void); rx_hex_word_echo(void); void autobaud(void); void putspace1(void); void putcr(void);
NOTES: CADDR must using faddr_data_read routine. register (SFR 8FH) defines Data Memory Program Memory write. registers CKCON TCON must initialized: CKCON 0x10 TCON 0x00.
TABLE MSC1202 Boot Routines.
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Serial Flash Programming Mode
methods programming available: serial programming mode user application mode. Serial programming mode initiated holding P1.0/PROG during POR, shown Figure User Application mode also allows Flash programming. Code execution from Flash Memory cannot occur this mode while programming, code execution occur from Boot while programming.
MSC1202 P3.0/RxD0 P3.1/TxD0 P1.0/PROG Programmer
INTERRUPTS
MSC1202 uses three-priority interrupt system. shown Table VII, each interrupt source independent priority bit, flag, interrupt vector, enable (except that nine interrupts share Auxiliary Interrupt (AI) highest priority). addition, interrupts globally enabled disabled. interrupt structure compatible with original 8051 family. standard interrupts available.
HARDWARE CONFIGURATION MEMORY
configuration bytes only written during program mode. bytes accessed through registers CADDR (SFR 93H) CDATA (SFR 94H). Three configuration bytes control Flash partitioning system control. security set, these bits cannot changed except with Mass Erase command that erases Flash Memory including configuration bytes.
NOTE: user application mode, avoid heavy loading P1.0/PROG, which result erroneously entering serial programming mode power-up.
FIGURE Serial Programming Mode.
INTERRUPT INTERRUPT/EVENT ADDR PRIORITY HIGH FLAG
INTERRUPT ENABLE
CONTROL
AVDD Voltage Detect Count (SPI/ I2C) Start/Stop Milliseconds Timer Summation Register Seconds Timer External Interrupt Timer Overflow External Interrupt Timer Overflow Serial Port External Interrupt External Interrupt External Interrupt External Interrupt Watchdog
ALVDIP (AIPOL.1)(1) CNTIP (AIPOL.2)(1) I2CIP (AIPOL.3)(1) MSECIP (AAIPOLIE.4)(1) ADCIP (AIPOL.5)(1) SUMIP (AIPOL.6)(1) SECIP (AIPOL.7)(1) (TCON.1)(2) (TCON.5)(3) (TCON.3)(2) (TCON.7)(3) RI_0 (SCON0.0) TI_0 (SCON0.1) (EXIF.4) (EXIF.5) (EXIF.6) (EXIF.7) WDTI (EICON.3)
EALV (AIE.1)(1) ECNT (AIE.2)(1) EI2C (AIE.3)(1) EMSEC (AIE.4)(1) EADC (AIE .5)(1) ESUM (AIE.6)(1) ESEC (AIE.7)(1) (IE.0)(4) (IE.1)(4) (IE.2)(4) (IE.3)(4) (IE.4)(4) (EIE.0)(4) (EIE.1)(4) (EIE.2)(4) (EIE.3)(4) EWDI (EIE.4)(4)
(IP.0) (IP.1) (IP.2) (IP.3) (IP.4) (IP.0) (IP.1) (IP.2) (IP.3) PWDI (IP.4)
NOTES: These interrupts flag (EICON.4) enabled (EICON.5). edge triggered, cleared automatically hardware when service routine vectored level triggered, flag follows state pin. Cleared automatically hardware when interrupt vector occurs. Globally enabled (IE.7).
TABLE VII. Interrupt Summary.
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Hardware Configuration Register (HCR0)-Accessed Using Registers CADDR CDATA.
CADDR EPMA EWDR DFSEL1 DFSEL0
read this register during normal operation, refer register descriptions CADDR CDATA. EPMA Enable Programming Memory Access (Security Bit). After reset programming modes, Flash Memory only accessed mode until mass erase done. Fully Accessible (default) Program Memory Lock (PML Priority Over RSL). Enable Flash Programming Modes Program Memory; written UAM. Enable read only Program Memory; cannot written (default). Reset Sector Lock. reset sector used provide another method Flash Memory programming. This will allow Program Memory updates without changing jumpers in-circuit code updates program development. code this boot sector would then provide monitor programming routines with ability jump into main Flash code when programming finished. Enable Reset Sector Writing Enable Read Only Mode Reset Sector (4kB) (default) Enable Boot ROM. Boot code located ROM, confused with Boot Sector located Flash Memory. Disable Internal Boot Enable Internal Boot (default) Enable Watchdog Reset. Disable Watchdog Reset Enable Watchdog Reset (default)
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EWDR
DFSEL1-0 Data Flash Memory Size (see Table II). bits Data Flash Memory (MSC1202Y3 Only) Data Flash Memory Data Flash Memory Data Flash Memory (default)
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Hardware Configuration Register (HCR1)
CADDR
read this register during normal operation, refer register descriptions CADDR CDATA. Disable Digital Brownout Detection Enable Digital Brownout Detection (2.7V) Disable Digital Brownout Detection (default)
Hardware Configuration Register (HCR2)
CADDR CLKSEL2 CLKSEL1 CLKSEL0
read this register during normal operation, refer register descriptions CADDR CDATA. CLKSEL2-0 Clock Select bits 000: Reserved 001: Reserved 010: External Oscillator Mode 011: External Crystal Mode 100: High-Frequency (HF) Mode 110: Internal Oscillator High-Frequency (HF) Mode 111: Internal Oscillator Low-Frequency (LF) Mode 101: Low-Frequency (LF) Mode
Configuration Memory Programming
Certain functions such Brownout Reset Watchdog Timer controlled hardware configuration bits. These bits nonvolatile only changed through serial flash programming. Other peripheral control status functions, such configuration timer setup, Flash control controlled through SFRs.
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Definitions
ADDRESS REGISTER DPL0 DPH0 DPL1 DPH1 PCON TCON TMOD CKCON EXIF CADDR CDATA RESET VALUES
SMOD |-Timer GATE
|-Timer GATE
STOP IDLE
P1.7 INT5
P1.6 INT4
P1.5 INT3
P1.4 INT2/SS
P1.3
P1.2 DOUT
P1.1
MXWS P1.0
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SCON0 SBUF0 SPICON I2CCON SPIDATA I2CDATA
SM0_0 SBIT3 SBIT3
SM1_0 SBIT2 SBIT2
SM2_0 SBIT1 SBIT1
REN_0 SBIT0 SBIT0
TB8_0 ORDER STOP
RB8_0 CPHA START
TI_0
RI_0 CPOL CNTSEL
AIPOL AISTAT Reserved
SECIP ESEC
SUMIP ESUM
ADCIP EADC
MSECIP EMSEC MSEC
I2CIP PAI3 EI2C
CNTIP PAI2 ECNT
ALVDIP PAI1 EALV ALVD
PAI0
P1DDRL P1DDRH
P13H P17H P3.7
P13L P17L P3.6
SCK/SCL/CLKS
P12H P16H P3.5
P12L P16L P3.4
P11H P15H P3.3 INT1
P11L P15L P3.2 INT0
P10H P14H P3.1 TXD0
P10L P14L P3.0 RXD0
P3DDRL P3DDRH IDAC
P33H P37H
P33L P37L
P32H P36H
P32L P36L
P31H P35H
P31L P35L
P30H P34H
P30L P34L
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Definitions (Cont.)
ADDRESS REGISTER RESET VALUES
SYSCLK
DIVMOD1
DIVMOD0
EWUWDT DIV2
EWUEX1 DIV1
EWUEX0 DIV0
ADMUX EICON ADRESL ADRESM ADCON0 ADCON1 ADCON2 ADCON3 SSCON SUMR0 SUMR1 SUMR2 SUMR3 ODAC LVDCON HWPC0 HWPC1 HWVER Reserved Reserved FMCON FTCON PDCON PASEL Reserved PLLL PLLH ACLK SRST SECINT MSINT USEC MSECL MSECH HMSEC WDTCON
INP3 SSCON1 SSCON0 EVREF SCNT2 VREFH SCNT1 EBUF SCNT0 PGA2 CAL2 DR10 SHF2 PGA1 CAL1 SHF1 PGA0 CAL0 SHF0 INP2 INP1 INP0 INN3 WDTI INN2 INN1 INN0
ALVDIS EWDI MEMORY
0000_000xB
FER3 PDICLK PSEN4 PLL7 CLKSTAT2 MSECL7 MSECH7 HMSEC7 EWDT
PGERA FER2 PDIDAC PSEN3 PLL6 CLKSTAT1 FREQ6 SECINT6 MSINT6 MSECL6 MSECH6 HMSEC6 DWDT
FER1 PDI2C PSEN2 PLL5 CLKSTAT0 FREQ5 SECINT5 MSINT5 FREQ5 MSECL5 MSECH5 HMSEC5 RWDT
FRCM FER0 PSEN1 PLL4 PLLLOCK FREQ4 PWDI SECINT4 MSINT4 FREQ4 MSECL4 MSECH4 HMSEC4 WDCNT4
FWR3 PDADC PSEN0 PLL3 FREQ3 SECINT3 MSINT3 FREQ3 MSECL3 MSECH3 HMSEC3 WDCNT3
BUSY FWR2 PDWDT PLL2 FREQ2 SECINT2 MSINT2 FREQ2 MSECL2 MSECH2 HMSEC2 WDCNT2
FWR1 PDST PLL1 PLL9 FREQ1 SECINT1 MSINT1 FREQ1 MSECL1 MSECH1 HMSEC1 WDCNT1
FWR0 PDSPI PLL0 PLL8 FREQ0 RSTREQ SECINT0 MSINT0 FREQ0 MSECL0 MSECH0 HMSEC0 WDCNT0
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Stack Pointer (SP)
SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0 Reset Value
SP.7-0 bits
Stack Pointer. stack pointer identifies location where stack will begin. stack pointer incremented before every PUSH CALL operation decremented after each RET/RETI. This register defaults after reset.
Data Pointer (DPL0)
DPL0.7 DPL0.6 DPL0.5 DPL0.4 DPL0.3 DPL0.2 DPL0.1 DPL0.0 Reset Value
DPL0.7-0 bits
Data Pointer This register byte standard 8051 16-bit data pointer. DPL0 DPH0 used point non-scratchpad data RAM. current data pointer selected (SFR 86H).
Data Pointer High (DPH0)
DPH0.7 DPH0.6 DPH0.5 DPH0.4 DPH0.3 DPH0.2 DPH0.1 DPH0.0 Reset Value
DPH0.7-0 Data Pointer High This register high byte standard 8051 16-bit data pointer. DPL0 DPH0 bits used point non-scratchpad data RAM. current data pointer selected (SFR 86H).
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Data Pointer (DPL1)
DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0 Reset Value
DPL1.7-0 bits
Data Pointer This register byte auxiliary 16-bit data pointer. When (DPS.0) (SFR 86H) set, DPL1 DPH1 used place DPL0 DPH0 during DPTR operations.
Data Pointer High (DPH1)
DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0 Reset Value
DPH1.7-0 Data Pointer High. This register high byte auxiliary 16-bit data pointer. When (DPS.0) bits (SFR 86H) set, DPL1 DPH1 used place DPL0 DPH0 during DPTR operations.
Data Pointer Select (DPS)
Reset Value
Data Pointer Select. This selects active data pointer. Instructions that DPTR will DPL0 DPH0. Instructions that DPTR will DPL1 DPH1.
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Power Control (PCON)
SMOD STOP IDLE Reset Value
SMOD STOP IDLE
Serial Port Baud Rate Doubler Enable. serial baud rate doubling function Serial Port Serial Port baud rate will standard baud rate. Serial Port baud rate will double that defined baud rate generation equation. General-Purpose User Flag This general-purpose flag software control. General-Purpose User Flag This general-purpose flag software control. Stop Mode Select. Setting this will halt oscillator block external clocks. This will always read Exit with RESET. this mode, internal peripherals frozen pins held their current state. frozen, IDAC VREF remain active. Idle Mode Select. Setting this will freeze CPU, Timer UART; other peripherals remain active. This will always read Exit with (A6H) (C6H) interrupts (refer Figure clocks affected during IDLE).
Timer/Counter Control (TCON)
Reset Value
Timer Overflow Flag. This indicates when Timer overflows maximum count defined current mode. This cleared software automatically cleared when vectors Timer interrupt service routine. Timer overflow been detected. Timer overflowed maximum count. Timer Control. This enables/disables operation Timer Halting this timer will preserve current count TH1, TL1. Timer halted. Timer enabled. Timer Overflow Flag. This indicates when Timer overflows maximum count defined current mode. This cleared software automatically cleared when vectors Timer interrupt service routine. Timer overflow been detected. Timer overflowed maximum count. Timer Control. This enables/disables operation Timer Halting this timer will preserve current count TH0, TL0. Timer halted. Timer enabled. Interrupt Edge Detect. This when edge/level type defined detected. this will remain until cleared software start External Interrupt service routine. this will inversely reflect state INT1 pin. Interrupt Type Select. This selects whether INT1 will detect edge level triggered interrupts. INT1 level triggered. INT1 edge triggered. Interrupt Edge Detect. This when edge/level type defined detected. this will remain until cleared software start External Interrupt service routine. this will inversely reflect state INT0 pin. Interrupt Type Select. This selects whether INT0 will detect edge level triggered interrupts. INT0 level triggered. INT0 edge triggered.
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Timer Mode Control (TMOD)
TIMER TIMER Reset Value
GATE
GATE
GATE bits
Timer Gate Control. This enables/disables ability Timer increment. Timer will clock when regardless state INT1. Timer will clock only when INT1 Timer Counter/Timer Select. Timer incremented internal clocks. Timer incremented pulses when (TCON.6, 88H) Timer Mode Select. These bits select operating mode Timer
MODE Mode Mode Mode Mode 8-bit counter with 5-bit prescale. bits. 8-bit counter with auto reload. Timer halted, holds count.
GATE bits
Timer Gate Control. This enables/disables ability Timer increment. Timer will clock when regardless state INT0 (software control). Timer will clock only when INT0 (hardware control). Timer Counter/Timer Select. Timer incremented internal clocks. Timer incremented pulses when (TCON.4, 88H) Timer Mode Select. These bits select operating mode Timer
MODE Mode Mode Mode Mode 8-bit counter with 5-bit prescale. bits. 8-bit counter with auto reload. Timer halted, holds count.
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Timer (TL0)
TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0 Reset Value
TL0.7-0 bits
Timer LSB. This register contains least significant byte Timer
Timer (TL1)
TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0 Reset Value
TL1.7-0 bits
Timer LSB. This register contains least significant byte Timer
Timer (TH0)
TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 Reset Value
TH0.7-0 bits
Timer MSB. This register contains most significant byte Timer
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Timer (TH1)
TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0 Reset Value
TH1.7-0 bits
Timer MSB. This register contains most significant byte Timer
Clock Control (CKCON)
Reset Value
Timer Clock Select. This controls division system clock that drives Timer Clearing this maintains 8051 compatibility. This effect instruction cycle timing. Timer uses divide crystal frequency. Timer uses divide crystal frequency. Timer Clock Select. This controls division system clock that drives Timer Clearing this maintains 8051 compatibility. This effect instruction cycle timing. Timer uses divide crystal frequency. Timer uses divide crystal frequency.
MXWS
Reset Value
Memory Write Select (MWS)
MXWS MOVX Write Select. This allows writing internal Flash program memory. writes allowed internal Flash program memory. Writing allowed internal Flash program memory, unless (HCR0) (HCR0)
P1.7 INT5 P1.6 INT4 P1.5 INT3 P1.4 INT2/SS P1.3 P1.2 DOUT P1.1 P1.0 PROG Reset Value
Port (P1)
P1.7-0 bits
General-Purpose Port This register functions general-purpose port. addition, pins have alternative function listed below. Each functions controlled several other SFRs. associated Port latch must contain logic before used alternate function capacity. alternate function, appropriate mode P1DDRL (SFR AEH), P1DDRH (SFR AFH). External Interrupt falling edge this will cause external interrupt enabled. External Interrupt rising edge this will cause external interrupt enabled. External Interrupt falling edge this will cause external interrupt enabled. External Interrupt rising edge this will cause external interrupt enabled. This used slave select (SS) slave mode. Serial Data This receives serial data modes mode, this should configured input) standard 8051. Serial Data Out. This transmits serial data modes mode, this should configured open drain) standard 8051. Program Mode. When this pulled power-up, device enters Serial Programming mode (refer Figure
INT5 INT4 INT3 INT2/SS DOUT PROG
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MD2, MD1, Stretch MOVX Select. These bits select time which MOVX cycles stretched. Since MSC1202 does allow external memory access, these bits should 000B allow fastest flash data memory access.
External Interrupt Flag (EXIF)
Reset Value
External Interrupt Flag. This will when falling edge detected INT5. This must cleared manually software. Setting this software will cause interrupt enabled. External Interrupt Flag. This will when rising edge detected INT4. This must cleared manually software. Setting this software will cause interrupt enabled. External Interrupt Flag. This will when falling edge detected INT3. This must cleared manually software. Setting this software will cause interrupt enabled. External Interrupt Flag. This will when rising edge detected INT2. This must cleared manually software. Setting this software will cause interrupt enabled.
Configuration Address Register (CADDR) (write only)
Reset Value
CADDR bits
Configuration Address Register. This register supplies address reading bytes bytes Flash Configuration Memory. Always Boot CADDR access routine. This register also used read write routines. WARNING: this register written while executing from Flash Memory, CDATA register will incorrect.
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Configuration Data Register (CDATA)
Reset Value
CDATA bits
Configuration Data Register. This register will contain data bytes Flash Configuration Memory that located last written address CADDR register. This read-only register.
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Serial Port Control (SCON0)
SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 Reset Value
SM0-2 bits
Serial Port Mode. These bits control mode serial Port Modes have start stop addition data bits.
MODE FUNCTION Synchronous Synchronous Asynchronous Asynchronous-Valid Stop Required(2) Asynchronous Asynchronous with Multiprocessor Communication Asynchronous Asynchronous with Multiprocessor Communication(3) LENGTH PERIOD bits bits bits bits bits bits bits bits pCLK(1) pCLK(1) Timer Baud Rate Equation Timer Baud Rate Equation pCLK(1) pCLK(1) pCLK(1) pCLK(1) (SMOD (SMOD (SMOD (SMOD
Timer Baud Rate Equation Timer Baud Rate Equation
NOTES: pCLK will equal tCLK, except that pCLK will stop IDLE. RI_0 will only activated when valid stop received. RI_0 will activated
REN_0 TB8_0 RB8_0 TI_0 RI_0
Receive Enable. This enables/disables serial Port received shift register. Serial Port reception disabled. Serial Port received enabled (modes Initiate synchronous reception (mode Transmission State. This defines state transmission serial Port modes Received State. This identifies state reception received data serial Port modes serial port mode when SM2_0 RB8_0 state stop bit. RB8_0 used mode Transmitter Interrupt Flag. This indicates that data serial Port buffer been completely shifted out. serial port mode TI_0 data bit. other modes, this last data bit. This must manually cleared software. Receiver Interrupt Flag. This indicates that byte data been received serial Port buffer. serial port mode RI_0 bit. serial port mode RI_0 after last sample incoming stop subject state SM2_0. modes RI_0 after last sample RB8_0. This must manually cleared software.
Serial Data Buffer (SBUF0)
Reset Value
SBUF0 bits
Serial Data Buffer Data Serial Port read from written this location. serial transmit receive buffers separate registers, both addressed this location.
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Control (SPICON) (SERSEL determines SPICON control)
SBIT3 SBIT2 SBIT1 SBIT0 ORDER CPHA CPOL Reset Value
SBIT3-0 bits
Serial Count. Number bits transferred (read only).
SBIT3:0 0x00 0x01 0x03 0x02 0x06 0x07 0x05 0x04 0x0C COUNT
ORDER CPHA
Order Transmit Receive. Most Significant Bits First Least Significant Bits First Serial Clock Phase Control. Valid data starting from half period before first edge Valid data starting from first edge Enable Slave Select. (P1.4) configured general-purpose (default). (P1.4) configured mode. DOUT (P1.2) drives when low, DOUT (P1.2) highimpedance when high. Serial Clock Polarity. idle logic idle logic HIGH
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CPOL
Control (I2CCON) (SERSEL determines I2CCON control)
SBIT3 SBIT2 SBIT1 SBIT0 STOP START CNTSEL Reset Value
SBIT3-0 bits
Serial Count. Number bits transferred (read only).
SBIT3:0 0x00 0x01 0x03 0x02 0x06 0x07 0x05 0x04 0x0C COUNT
STOP START
Stop-Bit Status. Stop Stop Condition Received I2CCNT (cleared write I2CDATA) Start-Bit Status. Stop Start Repeated Start Condition Received I2CCNT (cleared write I2CDATA)
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CNTSEL
Disable Serial Clock Stretch. Enable Stretch (cleared firmware START condition) Disable Stretch Counter Select. Counter Counter (default) Counter Counter
Data Register (SPIDATA) Data Register (I2CDATA)
Reset Value
SPIDATA bits I2CDATA bits
Data Register. Data read from written this location. transmit receive buffers separate registers, both addressed this location. Data Register. Data read from written this location. transmit receive buffers separate registers, both addressed this location.
Auxilliary Interrupt Poll (AIPOL)
SECIP SUMIP ADCIP MSECIP I2CIP CNTIP ALVDIP Unused Reset Value
SECIP SUMIP bits ADCIP bits MSECIP bits I2CIP bits CNTIP bits ALVDIP bits
Second System Timer Interrupt Poll (before masking). Seconds System Timer Interrupt Poll Inactive Seconds System Timer Interrupt Poll Active Accumulator Interrupt Poll (before masking). Accumulator Interrupt Poll Inactive Accumulator Interrupt Poll Active Interrupt Poll (before masking). Interrupt Poll Inactive Interrupt Poll Active Millisecond System Timer Interrupt Poll (before masking). Millisecond System Timer Interrupt Poll Inactive Millisecond System Timer Interrupt Poll Active Interrupt Poll (before masking). Interrupt Poll Inactive Interrupt Poll Active Serial Count Interrupt Poll (before masking). Serial Count Interrupt Poll Inactive Serial Count Interrupt Poll Active Analog Voltage Detect Interrupt Poll (before masking). Analog Voltage Detect Interrupt Poll Inactive Analog Voltage Detect Interrupt Poll Active
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Pending Auxiliary Interrupt (PAI)
PAI3 PAI2 PAI1 PAI0 Reset Value
bits
Pending Auxiliary Interrupt Register. results this register used index vector appropriate interrupt routine. these interrupts vector through address 0033H.
PAI3 PAI2 PAI1 PAI0 AUXILIARY INTERRUPT STATUS Pending Auxiliary Reserved Analog Voltage Detect Possible Lower Priority Pending Possible Lower Priority Pending Serial Count Interrupt Possible Lower Priority Pending Millisecond System Timer Possible Lower Priority Pending Possible Lower Priority Pending Accumulator Possible Lower Priority Pending Second System Timer Possible Lower Priority Pending
Auxiliary Interrupt Enable (AIE)
ESEC ESUM EADC EMSEC EI2C ECNT EALV Reset Value
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Interrupts enabled EICON.4 (SFR D8H). other interrupts controlled registers. ESEC ESUM EADC EMSEC EI2C ECNT EALV Enable Second System Timer Interrupt (lowest priority auxiliary interrupt). Write: mask this interrupt; masked, enabled. Read: Second Timer Interrupt mask. Enable Summation Interrupt. Write: mask this interrupt; masked, enabled. Read: Summation Interrupt mask. Enable Interrupt. Write: mask this interrupt; masked, enabled. Read: Interrupt mask. Enable Millisecond System Timer Interrupt. Write: mask this interrupt; masked, enabled. Read: Millisecond System Timer Interrupt mask. Enable Start/Stop Bit. Write: mask this interrupt; masked, enabled. Read: Start/Stop mask. Enable Serial Count Interrupt. Write: mask this interrupt; masked, enabled. Read: Serial Count Interrupt mask. Enable Analog Voltage Interrupt. Write: mask this interrupt; masked, enabled. Read: Analog Voltage Detect Interrupt mask. Enable Breakpoint Interrupt (highest priority auxialiary interrupt). Write: Must (default). Read: Breakpoint Interrupt enable status.
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Auxiliary Interrupt Status Register (AISTAT)
MSEC ALVD Reset Value
Second System Timer Interrupt Status Flag (lowest priority AI). Interrupt cleared masked. Interrupt active cleared reading SECINT, F9H). Summation Register Interrupt Status Flag. Interrupt cleared masked. Interrupt active cleared reading lowest byte SUMR0, E2H). Interrupt Status Flag. Interrupt cleared masked. Interrupt active cleared reading lowest byte ADRESL, D9H; active, data will written Results registers). Millisecond System Timer Interrupt Status Flag. MSEC Interrupt cleared masked. MSEC Interrupt active cleared reading MSINT, FAH). Start/Stop Interrupt Status Flag. Start/stop Interrupt cleared masked. Start/stop Interrupt active cleared writing I2CDATA, 9BH).
MSEC ALVD
Analog Voltage Detect Interrupt Status Flag. ALVD Interrupt cleared masked. ALVD Interrupt active (cleared AVDD exceeds ALVD threshold).
NOTE: interrupt masked, status read AIPOL, A4H.
Interrupt Enable (IE)
Reset Value
Global Interrupt Enable. This controls global masking interrupts except those (SFR A6H). Disable interrupt sources. This overrides individual interrupt mask settings this register. Enable individual interrupt masks. Individual interrupts this register will occur enabled. Enable Serial port interrupt. This controls masking serial Port interrupt. Disable serial Port interrupts. Enable interrupt requests generated RI_0 (SCON0.0, 98H) TI_0 (SCON0.1, 98H) flags. Enable Timer Interrupt. This controls masking Timer interrupt. Disable Timer interrupt. Enable interrupt requests generated flag (TCON.7, 88H). Enable External Interrupt This controls masking external interrupt Disable external interrupt Enable interrupt requests generated INT1 pin. Enable Timer Interrupt. This controls masking Timer interrupt. Disable Timer interrupts. Enable interrupt requests generated flag (TCON.5, 88H). Enable External Interrupt This controls masking external interrupt Disable external interrupt Enable interrupt requests generated INT0 pin.
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Interrupt Status Flag. Interrupt cleared masked. Interrupt active cleared reading from writing SPIDATA/I2CDATA, 9BH).
Port Data Direction Register (P1DDRL)
P13H P13L P12H P12L P11H P11L P10H P10L Reset Value
P1.3 bits
Port control.
P13H P13L Standard 8051 CMOS Output Open Drain Output Input
P1.2 bits
Port control.
P12H P12L Standard 8051 CMOS Output Open Drain Output Input
P1.1 bits
Port control.
P11H P11L Standard 8051 CMOS Output Open Drain Output Input
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P1.0 bits
Port control.
P10H P10L Standard 8051 CMOS Output Open Drain Output Input
Port Data Direction High Register (P1DDRH)
P17H P17L P16H P16L P15H P15L P14H P14L Reset Value
P1.7 bits
Port control.
P17H P17L Standard 8051 CMOS Output Open Drain Output Input
P1.6 bits
Port control.
P16H P16L Standard 8051 CMOS Output Open Drain Output Input
P1.5 bits
Port control.
P15H P15L Standard 8051 CMOS Output Open Drain Output Input
P1.4 bits
Port control.
P14H P14L Standard 8051 CMOS Output Open Drain Output Input
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Port (P3)
P3.7 P3.6 SCK/SCL/CLKS P3.5 P3.4 P3.3 INT1 P3.2 INT0 P3.1 TXD0 P3.0 RXD0 Reset Value
P3.7-0 bits
General-Purpose Port This register functions general-purpose port. addition, pins have alternative function listed below. Each functions controlled several other SFRs. associated Port latch must contain logic before used alternate function capacity. Clock Source Select. Refer PASEL (SFR F2H).
SCK/SCL/CLKS INT1 INT0 TXD0 RXD0
Timer/Counter External Input. transition this will increment Timer Timer/Counter External Input. transition this will increment Timer External Interrupt falling edge/low level this will cause external interrupt enabled. External Interrupt falling edge/low level this will cause external interrupt enabled. Serial Port Transmit. This transmits serial Port data serial port modes emits synchronizing clock serial port mode Serial Port Receive. This receives serial Port data serial port modes bidirectional data transfer serial port mode
Port Data Direction Register (P3DDRL)
P33H P33L P32H P32L P31H P31L P30H P30L Reset Value
P3.3 bits
Port control.
P33H P33L Standard 8051 CMOS Output Open Drain Output Input
P3.2 bits
Port control.
P32H P32L Standard 8051 CMOS Output Open Drain Output Input
P3.1 bits
Port control.
P31H P31L Standard 8051 CMOS Output Open Drain Output Input
P3.0 bits
Port control.
P30H P30L Standard 8051 CMOS Output Open Drain Output Input
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Port Data Direction High Register (P3DDRH)
P37H P37L P36H P36L P35H P35L P34H P34L Reset Value
P3.7 bits
Port control.
P37H P37L Standard 8051 CMOS Output Open Drain Output Input
P3.6 bits
Port control.
P36H P36L Standard 8051 CMOS Output Open Drain Output Input
P3.5 bits
Port control.
P35H P35L Standard 8051 CMOS Output Open Drain Output Input
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P3.4 bits
Port control.
P34H P34L Standard 8051 CMOS Output Open Drain Output Input
IDAC Register
Reset Value
IDAC bits
IDAC Register. IDACOUT IDAC 3.8µA (~1mA full-scale). Setting (PDCON.PDIDAC) will shut down IDAC float IDAC pin.
Interrupt Priority (IP)
Reset Value
Serial Port Interrupt. This controls priority serial Port interrupt. Serial Port priority determined natural priority order. Serial Port high priority interrupt. Timer Interrupt. This controls priority Timer interrupt. Timer priority determined natural priority order. Timer priority high priority interrupt. External Interrupt This controls priority external interrupt External interrupt priority determined natural priority order. External interrupt high priority interrupt. Timer Interrupt. This controls priority Timer interrupt. Timer priority determined natural priority order. Timer priority high priority interrupt. External Interrupt This controls priority external interrupt External interrupt priority determined natural priority order. External interrupt high priority interrupt.
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Enable Wake (EWU) Waking from IDLE Mode
EWUWDT EWUEX1 EWUEX0 Reset Value
Auxiliary interrupts will wake from IDLE. They enabled with (EICON.5). EWUWDT EWUEX1 EWUEX0 Enable Wake Watchdog Timer. Wake using watchdog timer interrupt. Don't wake watchdog timer interrupt. Wake watchdog timer interrupt. Enable Wake External Wake using external interrupt source Don't wake external interrupt source Wake external interrupt source Enable Wake External Wake using external interrupt source Don't wake external interrupt source Wake external interrupt source
System Clock Divider Register (SYSCLK)
DIVMOD1 DIVMOD0 DIV2 DIV1 DIV0 Reset Value
DIVMOD1-0 Clock Divide Mode bits Write:
DIVMOD DIVIDE MODE Normal mode (default, divide) Immediate mode: start divide immediately, return Normal mode IDLE wakeup condition Normal mode write. Delay mode: same Immediate mode, except that mode changes with millisecond interrupt (MSINT). MSINT enabled, divide will start next MSINT return normal mode following MSINT. MSINT enabled, divide will start next MSINT condition (even masked) will leave divide mode until MSINT counter overflows, which follows wakeup condition. exit Normal mode write. Manual mode: start divide immediately; exit mode only write DIVMOD.
Read:
DIVMOD DIVISION MODE STATUS divide Divider Immediate mode Divider Delay mode Reserved
DIV2-0
Divide Mode
DIVISOR Divide Divide Divide Divide Divide Divide Divide Divide (default) 1024 2048 4096 fCLK fCLK fCLK fCLK fCLK fCLK fCLK fCLK fSYS/2 fSYS/4 fSYS/8 fSYS/16 fSYS/32 fSYS/1024 fSYS/2048 fSYS/4096
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Program Status Word (PSW)
Reset Value
RS1, bits
Carry Flag. This when last arithmetic operation resulted carry (during addition) borrow (during subtraction). Otherwise cleared arithmetic operations. Auxiliary Carry Flag. This last arithmetic operation resulted carry into (during addition), borrow (during substraction) from high order nibble. Otherwise cleared arithmetic operations. User Flag This bit-addressable, general-purpose flag software control. Register Bank Select 1-0. These bits select which register bank addressed during register accesses.
REGISTER BANK ADDRESS 00H-07H 08H-0FH 10H-17H 18H-1FH
Overflow Flag. This last arithmetic operation resulted carry (addition), borrow (subtraction), overflow (multiply divide). Otherwise cleared arithmetic operations. User Flag This bit-addressable, general-purpose flag software control. Parity Flag. This modulo-2 bits accumulator (odd parity); cleared even parity.
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Offset Calibration Register Middle Byte (OCM)
Reset Value
Offset Calibration Register Byte. This byte 16-bit word that contains bits offset calibration. value which written this location will offset calibration value.
Offset Calibration Register High Byte (OCH)
Reset Value
bits
Offset Calibration Register High Byte. This high byte 16-bit word that contains offset calibration. value which written this location will offset calibration value.
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Gain Calibration Register Middle Byte (GCM)
Reset Value
bits
Gain Calibration Register Byte. This byte 16-bit word that contains gain calibration. value which written this location will gain calibration value.
Gain Calibration Register High Byte (GCH)
Reset Value
bits
Gain Calibration Register High Byte. This high byte 16-bit word that contains gain calibration. value which written this location will gain calibration value.
Multiplexer Register (ADMUX)
INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 Reset Value
INP3-0 bits
Input Multiplexer Positive Channel. This selects positive signal input.
INP3 INP2 INP1 INP0 POSITIVE INPUT AIN0 (default) AIN1 AIN2 AIN3 AIN4 AIN5 REFIN- REFIN- AINCOM Temperature Sensor (requires ADMUX FFH)
INN3-0 bits
Input Multiplexer Negative Channel. This selects negative signal input.
INN3 INN2 INN1 INN0 NEGATIVE INPUT AIN0 AIN1 (default) AIN2 AIN3 AIN4 AIN5 REFIN- REFIN- AINCOM Temperature Sensor (requires ADMUX FFH)
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Enable Interrupt Control (EICON)
WDTI Reset Value
Enable Auxiliary Interrupt. Auxiliary Interrupt accesses nine different interrupts which masked identified registers (SFR A5H), (SFR A6H), AISTAT (SFR A7H). Auxiliary Interrupt disabled (default). Auxiliary Interrupt enabled. Auxiliary Interrupt Flag. must cleared software before exiting interrupt service routine, after source interrupt cleared. Otherwise, interrupt occurs again. Setting software generates Auxiliary Interrupt, enabled. Auxiliary Interrupt detected (default). Auxiliary Interrupt detected. Watchdog Timer Interrupt Flag. WDTI must cleared software before exiting interrupt service routine. Otherwise, interrupt occurs again. Setting WDTI software generates watchdog time interrupt, enabled. Watchdog timer generate interrupt reset. interrupt available only reset action disabledin HCR0. Watchdog Timer Interrupt Detected (default). Watchdog Timer Interrupt Detected.
WDTI
Results Register Byte (ADRESL)
Reset Value
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ADRESL bits
Results Byte. This byte 16-bit word that contains Results. Reading from this register clears interrupt; however, EICON (SFR must also cleared.
Results Register Middle Byte (ADRESM)
Reset Value
ADRESM bits
Results High Byte. This high byte 16-bit word that contains Results.
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Control Register (ADCON0)
EVREF VREFH EBUF PGA2 PGA1 PGA0 Reset Value
Burnout Detect. When enabled this connects positive current source positive channel negative current source negative channel. channel open circuit then results will full-scale (buffer must enabled). Burnout Current Sources (default). Burnout Current Sources Enable Internal Voltage Reference. external voltage reference used, internal voltage reference should disabled. Internal Voltage Reference Off. Internal Voltage Reference (default). Voltage Reference High Select. internal voltage reference selected 2.5V 1.25V. REFOUT/REFIN+ 1.25V. REFOUT/REFIN+ 2.5V (default). Enable Buffer. Enable input buffer provide higher input impedance limits input voltage range dissipates more power. Buffer disabled (default). Buffer enabled. Programmable Gain Amplifier. Sets gain from 128.
PGA2 PGA1 PGA0 GAIN (default)
EVREF
VREFH EBUF
PGA2-0 bits
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Control Register (ADCON1)
CAL2 CAL1 CAL0 Reset Value x000 0000B
Polarity. Polarity result Summation register. Bipolar. Unipolar.
ANALOG INPUT +FSR ZERO -FSR +FSR ZERO -FSR DIGITAL OUTPUT 0x7FFFFF 0x000000 0x800000 0xFFFFFF 0x000000 0x000000
SM1-0 bits
Settling Mode. Selects type filter auto select which defines digital filter settling characteristics.
SETTLING MODE Auto Fast Settling Filter Sinc2 Filter Sinc3 Filter
CAL2-0 bits
Calibration Mode Control Bits. Writing this register initiates calibration.
CAL2 CAL1 CAL0 CALIBRATION MODE Calibration (default) Self Calibration, Offset Gain Self Calibration, Offset Only Self Calibration, Gain Only System Calibration, Offset Only System Calibration, Gain Only Reserved Reserved
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Read Value-000B.
Control Register (ADCON2)
Reset Value
DR7-0 bits
Decimation Ratio (refer ADCON3, DFH).
Control Register (ADCON3)
DR10 Reset Value
DR10-8 bits
fMOD fCLK Decimation Ratio Most Significant Bits. output data rate where fMOD Decimation Ratio (ACLK
Accumulator ACC)
ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Reset Value
ACC.7-0 bits
Accumulator. This register serves accumulator arithmetic logic operations.
Summation/Shifter Control (SSCON)
SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 Reset Value
Summation register powered down when powered down. zeroes written this register 32-bit SUMR3-0 registers will cleared. Summation registers will sign extend Bipolar selected ADCON1.
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SSCON1-0 Summation/Shift Control. bits SSCON1 SSCON0 SCNT2
Note Note
SCNT1 Note Note
SCNT0 Note Note
SHF2 Note Note
SHF1 Note Note
SHF0 Note Note
DESCRIPTION Clear Summation Register Summation Write SUMR0 Subtraction Write SUMR0 Shift Only Summation Only Summation Completes then Shift Completes
NOTES: Refer register definition.
SCNT2-0 bits
Summation Count. When summation complete interrupt will generated unless masked. Reading SUMR0 register clears interrupt.
SCNT2 SCNT1 SCNT0 SUMMATION COUNT
SHF2-0 bits
Shift Count.
SHF2 SHF1 SHF0 SHIFT DIVIDE
Summation Register (SUMR0)
Reset Value
SUMR0 bits
Summation Register This least significant byte 32-bit summation register bits Write: Causes values SUMR3-0 added subtracted from summation register. Read: Clears Summation Interrupt; however, EICON (SFR D8H) must aslo cleared.
Summation Register (SUMR1)
Reset Value
SUMR1 bits
Summation Register This most significant byte lowest bits summation register bits 8-15.
Summation Register (SUMR2)
Reset Value
SUMR2 bits
Summation Register This most significant byte lowest bits summation register bits 16-23.
Summation Register (SUMR3)
Reset Value
SUMR3 bits
Summation Register This most significant byte 32-bit summation register bits 24-31.
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Offset Register (ODAC)
Reset Value
ODAC bit7-0
Offset Register. This register will shift input half full-scale input range. offset value summed into prior conversion. Writing ODAC turns Offset DAC. Offset Sign bit. Positive Negative Offset
VREF ODAC[6 (-1)
NOTE: ODAC cannot used offset input that buffer used AGND signals.
Voltage Detect Control (LVDCON)
ALVDIS Reset Value
ALVDIS
Analog Voltage Detect Disable. Enable Detection Analog Supply Voltage (ALVD interrupt when AVDD 2.8V). Disable Detection Analog Supply Voltage.
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Extended Interrupt Enable (EIE)
EWDI Reset Value
EWDI
Enable Watchdog Interrupt. This enables/disables watchdog interrupt. Watchdog timer enabled WDTCON (SFR FFH) PDCON (SFR F1H) registers. Disable Watchdog Interrupt Enable Interrupt Request Generated Watchdog Timer External Interrupt Enable. This enables/disables external interrupt Disable External Interrupt Enable External Interrupt External Interrupt Enable. This enables/disables external interrupt Disable External Interrupt Enable External Interrupt External Interrupt Enable. This enables/disables external interrupt Disable External Interrupt Enable External Interrupt External Interrupt Enable. This enables/disables external interrupt Disable External Interrupt Enable External Interrupt
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Hardware Product Code Register (HWPC0)
MEMORY Reset Value 0000_001xB
HWPC0.7-0 bits
Hardware Product Code LSB. Read only.
MEMORY SIZE
MODEL MSC1202Y2 MSC1202Y3
FLASH MEMORY
Hardware Product Code Register (HWPC1)
Reset Value
HWPC1.7-0 bits
Hardware Product Code MSB. Read only.
Hardware Version Register (HWVER)
Reset Value
Flash Memory Control (FMCON)
PGERA FRCM BUSY Reset Value
PGERA FRCM BUSY
Page Erase. Available both user program modes. Disable Page Erase Mode Enable Page Erase Mode Frequency Control Mode. bypass only used slow clocks save power. Bypass (default) Delay Line. Saves power (Recommended). Write/Erase BUSY Signal. Idle Available Busy
Flash Memory Timing Control Register (FTCON)
FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 Reset Value
Refer Flash Timing Characteristics FER3-0 bits FWR3-0 bits Erase. Flash Erase Time FER) (MSEC tCLK. 11ms industrial temperature range. commercial temperature range. Write. Flash Write Time FWR) (USEC tCLK. 30µs 40µs.
Register
Reset Value
bits
Register. This register serves second accumulator certain arithmetic operations.
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Power-Down Control Register (PDCON)
PDICLK PDIDAC PDI2C PDADC PDWDT PDSPI PDSPI Reset Value
Turning peripheral modules puts MSC1202 lowest power mode. PDICLK PDIDAC PDI2C PDADC PDWDT Internal Clock Control. Internal Oscillator (Internal Oscillator mode) (default) Internal Oscillator Power Down (External Clock mode) IDAC Control. IDAC IDAC Power Down (default) Control. (only when PDSPI Power Down (default) Control. ADC, VREF, Summation registers powered down (default). Watchdog Timer Control. Watchdog Timer Watchdog Timer Power Down (default) System Timer Control. System Timer System Timer Power Down (default) Control. System System Power Down (default)
PRODUCT PREVIEW
PDST PDSPI
PSEN/ALE Select (PASEL)
PSEN4 PSEN3 PSEN2 PSEN1 PSEN0 Reset Value
PSEN4-0 bits
PSEN Mode Select. Defines output P3.6 User Application mode Serial Flash Programming mode. 00000: General-Purpose (default) 00001: SYSCLK 00011: Internal PSEN (refer Figure timing) 00101: Internal (refer Figure timing) 00111: fOSC(buffered oscillator clock) 01001: Memory (MOVX write) 01011: (overflow)(1) 01101: (overflow)(1) 01111: fMOD(2) 10001: SYSCLK/2 (toggles rising edge)(2) 10011: Internal PSEN/2(2) 10101: Internal ALE/2(2) 10111: fOSC/2(2) 11001: Memory WR/2 (MOVX write)(2) 11011: Out/2 (overflow)(2) 11101: Out/2 (overflow)(2) 11111: fMOD/2(2)
NOTES: period these signals equal tCLK. Duty cycle 50%.
MSC1202
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SBAS328
Phase Lock Loop Register (PLLL)
PLL7 PLL6 PLL5 PLL4 PLL3 PLL2 PLL1 PLL0 Reset Value
PLL7-0 bits
Counter Value Least Significant Bit.
Frequency External Crystal Frequency PLL9:0
Phase Lock Loop High Register (PLLH)
CLKSTAT2 CLKSTAT1 CLKSTAT0 PLLLOCK PLL9 PLL8 Reset Value
CLKSTAT2-0 Active Clock Status (read only). Derived from HCR2 setting; refer Table bits 000: Reserved 001: Reserved 010: Reserved 011: External Clock Mode 100: High-Frequency (HF) Mode (must read PLLLOCK determine active clock status) 101: Low-Frequency (LF) Mode (must read PLLLOCK determine active clock status) 110: Internal Oscillator High-Frequency (HF) Mode 111: Internal Oscillator Low-Frequency (LF) Mode
Read (PLL Lock Status): Locked (PLL inactive; refer Table active clock mode) Locked (PLL active clock) PLL9-8 bits Counter Value Most Significant Bits (refer PLLL, F4H)
Analog Clock (ACLK)
FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 Reset Value
FREQ6-0 bits
Clock Frequency This value divides system clock create clock. fCLK fOSC fACLK where fCLK SYSCLK Divider (ACLK ACLK fMOD fMOD Data Rate fDATA Decimation Ratio
System Reset Register (SRST)
RSTREQ Reset Value
RSTREQ
Reset Request. Setting this then clearing will generate system reset.
MSC1202
SBAS328
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PRODUCT PREVIEW
PLLLOCK
Lock Status Status Enable. Write (PLL Lock Status Enable): Effect Enable Lock Detection (must wait 20ms before PLLLOCK read status valid).
Extended Interrupt Priority (EIP)
PWDI Reset Value
PWDI
Watchdog Interrupt Priority. This controls priority watchdog interrupt. watchdog interrupt priority. watchdog interrupt high priority. External Interrupt Priority. This controls priority external interrupt External interrupt priority. External interrupt high priority. External Interrupt Priority. This controls priority external interrupt External interrupt priority. External interrupt high priority. External Interrupt Priority. This controls priority external interrupt External interrupt priority. External interrupt high priority. External Interrupt Priority. This controls priority external interrupt External interrupt priority. External interrupt high priority.
Seconds Timer Interrupt (SECINT)
PRODUCT PREVIEW
SECINT6
SECINT5
SECINT4
SECINT3
SECINT2
SECINT1
SECINT0
Reset Value
This system clock divided value 16-bit register MSECH:MSECL. Then that timer tick divided register HMSEC which provides 100ms signal used this seconds timer. Therefore, this seconds timer generate interrupt which occurs from 100ms 12.8 seconds. Reading this register will clear Seconds Interrupt. This Interrupt monitored register. Write Control. Determines whether write value immediately wait until current count finished. Read Delay Write Operation. value loaded when current count expires. Write Immediately. counter loaded once completes write operation.
SECINT6-0 Seconds Count. Normal operation would 100ms clock interval. bits Seconds Interrupt SEC) (HMSEC (MSEC tCLK.
Milliseconds Interrupt (MSINT)
MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 Reset Value
clock used this timer clock which results from dividing system clock values registers MSECH:MSECL. Reading this register will clear MSINT. MSINT6-0 bits Write Control. Determines whether write value immediately wait until current count finished. Read Delay Write Operation. MSINT value loaded when current count expires. Write Immediately. MSINT counter loaded once completes write operation. Seconds Count. Normal operation would clock interval. Interrupt Interval MSINT) (MSEC tCLK
MSC1202
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SBAS328
Microsecond Register (USEC)
FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 Reset Value
FREQ5-0 bits
Clock Frequency This value divides system clock create Clock. USEC CLK/(FREQ This clock used Flash write time. FTCON (SFR EFH).
Millisecond Register (MSECL)
MSECL7 MSECL6 MSECL5 MSECL4 MSECL3 MSECL2 MSECL1 MSECL0 Reset Value
MSECL7-0 bits
Millisecond Low. This value combination with next register used create Clock. Clock (MSECH MSECL tCLK. This clock used Flash erase time. FTCON (SFR EFH).
Millisecond High Register (MSECH)
MSECH7 MSECH6 MSECH5 MSECH4 MSECH3 MSECH2 MSECH1 MSECH0 Reset Value
MSECH7-0 Millisecond High. This value combination with previous register used create clock. bits (MSECH MSECL tCLK.
HMSEC7
HMSEC6
HMSEC5
HMSEC4
HMSEC3
HMSEC2
HMSEC1
HMSEC0
Reset Value
HMSEC7-0 Hundred Millisecond. This clock divides clock create 100ms clock. bits 100ms (MSECH MSECL (HMSEC tCLK.
Watchdog Timer Register (WDTCON)
EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 Reset Value
EWDT DWDT RWDT WDCNT4-0 bits
Enable Watchdog (R/W). Write 1/Write sequence sets Watchdog Enable Counting bit. Disable Watchdog (R/W). Write 1/Write sequence clears Watchdog Enable Counting bit. Reset Watchdog (R/W). Write 1/Write sequence restarts Watchdog Counter.
Watchdog Count (R/W). Watchdog expires (WDCNT HMSEC (WDCNT HMSEC, sequence asserted. There uncertainty count. NOTE: HCR0.3 (EWDR) watchdog timer expires, system reset generated. HCR0.3 (EWDR) cleared watchdog timer expires, interrupt generated (see Table VII).
MSC1202
SBAS328
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PRODUCT PREVIEW
Hundred Millisecond Register (HMSEC)
PACKAGE OPTION ADDENDUM
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2-Aug-2004
PACKAGING INFORMATION
ORDERABLE DEVICE MSC1202Y2RHHR MSC1202Y2RHHT MSC1202Y3RHHR MSC1202Y3RHHT STATUS(1) PREVIEW PREVIEW PREVIEW PREVIEW PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE 2500 2500
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements. Following URLs where obtain information other Texas Instruments products application solutions: Products Amplifiers Data Converters Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video Imaging Wireless Mailing Address: Texas Instruments Post Office 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
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