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PCM3002 PCM3003
most current data sheet other product information, visit www.burr-brown.com
16-/20-Bit Single-Ended Analog Input /Output STEREO AUDIO CODECs
FEATURES
MONOLITHIC 20-BIT 16-/20-BIT INPUT/OUTPUT DATA SOFTWARE CONTROL: PCM3002 HARDWARE CONTROL: PCM3003 STEREO ADC: Single-Ended Voltage Input Oversampling High Performance THD+N: -86dB SNR: 90dB Dynamic Range: 90dB STEREO DAC: Single-Ended Voltage Output Analog Pass Filter Oversampling High Performance THD+N: -86dB SNR: 94dB Dynamic Range: 94dB SPECIAL FEATURES Digital De-emphasis Digital Attenuation (256 Steps) Soft Mute Digital Loop Back Power Down: ADC/DAC Independent SAMPLING RATE: 48kHz SYSTEM CLOCK: 256fS, 384fS, 512fS SINGLE POWER SUPPLY SMALL PACKAGE: SSOP-24
Analog Front-End
DESCRIPTION
PCM3002 PCM3003 cost single chip stereo audio CODECs (analog-to-digital digital-toanalog converters) with single-ended analog voltage input output. ADCs DACs employ delta-sigma modulation with oversampling. ADCs include digital decimation filter, DACs include oversampling digital interpolation filter. DACs also include digital attenuation, de-emphasis, infinite zero detection soft mute form complete subsystem. PCM3002 PCM3003 operate with left-justified, right-justified formats, while PCM3002 also supports data format. PCM3002 PCM3003 provide power-down mode that operates ADCs DACs independently. Fabricated highly advanced CMOS process, PCM3002 PCM3003 suitable wide variety cost-sensitive consumer applications where good performance required. PCM3002's programmable functions controlled software PCM3003's functions include deemphasis, power down, audio data format selections, which controlled hardware.
Delta-Sigma Modulator
Digital Decimation Filter Serial Interface Mode Control
Digital Digital
Pass Filter Output Buffer
Multi-Level Delta-Sigma Modulator
Digital Interpolation Filter
Serial Mode Control System Clock
International Airport Industrial Park Mailing Address: 11400, Tucson, 85734 Street Address: 6730 Tucson Blvd., Tucson, 85706 Tel: (520) 746-1111 Twx: 910-952-1111 Internet: http://www.burr-brown.com/ Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
1997 Burr-Brown Corporation
PDS-1414C
Printed U.S.A. PCM3002/3003January, 2000
SBAS079
SPECIFICATIONS
specifications +25°C, 3.0V, 44.1kHz, SYSCLK 384fS, 16-bit data, unless otherwise noted. PCM3002E/3003E PARAMETER DIGITAL INPUT/OUTPUT Input Logic Input Logic Level: VIH(1, VIL(1, Input Logic Current: IIN(2) Input Logic Current: IIN(1) Output Logic Output Logic Level: VOH(5) VOL(5) Output Logic Level: VOL(4) CLOCK FREQUENCY Sampling Frequency (fS) System Clock Frequency IOUT -1mA IOUT +1mA IOUT +1mA CONDITIONS UNITS
-0.3 32(7) 8.1920 12.2880 16.3840 44.1 11.2896 16.9344 22.5792 12.2880 18.4320 24.5760
256fS 384fS 512fS
CHARACTERISTICS RESOLUTION ACCURACY Gain Mismatch Channel-to-Channel Gain Error Gain Drift Bipolar Zero Error Bipolar Zero Drift DYNAMIC PERFORMANCE(8) THD+N: -0.5dB -60dB Dynamic Range Signal-to-Noise Ratio Channel Separation DIGITAL FILTER PERFORMANCE Passband Stopband Passband Ripple Stopband Attenuation Delay Time Frequency Response ANALOG INPUT Voltage Range Center Voltage Input Impedance Anti-Aliasing Filter Frequency Response ±1.0 ±2.0 ±1.7 ±3.0 ±5.0 Bits FSR/°C FSR/°C Vp-p
High-Pass Filter Disabled(6) High-Pass Filter Disabled(6)
A-Weighted A-Weighted
0.454fS 0.583fS ±0.05 -3dB 17.4/fS 0.019fS 0.60 0.50
-3dB
NOTES: Pins RST, PCM3002; PDAD, PDDA, DEM1, DEM0 PCM3003 (Schmitt-Trigger input with 100k typical internal pull-down resistor). Pins SYSCLK, LRCIN, BCKIN, (Schmitt Trigger input). Pin16: 20BIT PCM3003 (Schmitt-Trigger input, 100k typical internal pull-down resistor). DOUT. ZFLG (open drain output). High Pass Filter Offset Cancel. Refer Application Bulletin AB-148 information relating operation lower sampling frequencies. 1kHz, using Audio Precision System mode with 20kHz LPF, 400Hz used performance calculation. fOUT 1kHz, using Audio Precision System mode with 20kHz LPF, 400Hz used performance calculation. (10) Applies voltages between 2.4V 2.7V +70°C 256fS /512fS operation (384fS available). (11) SYSCLK, BCKIN, LRCIN stopped.
information provided herein believed reliable; however, BURR-BROWN assumes responsibility inaccuracies omissions. BURR-BROWN assumes responsibility this information, such information shall entirely user's risk. Prices specifications subject change without notice. patent rights licenses circuits described herein implied granted third party. BURR-BROWN does authorize warrant BURR-BROWN product life support devices and/or systems.
PCM3002/3003
SPECIFICATIONS
specifications +25°C, 3.0V, 44.1kHz, SYSCLK 384fS, CLKIO Input, 18-bit data, unless otherwise noted. PCM3002E/3003E PARAMETER CHARACTERISTICS RESOLUTION ACCURACY Gain Mismatch Channel-to-Channel Gain Error Gain Drift Bipolar Zero Error Bipolar Zero Drift DYNAMIC PERFORMANCE(9) THD+N: VOUT (Full Scale) VOUT -60dB Dynamic Range Signal-to-Noise Ratio Channel Separation DIGITAL FILTER PERFORMANCE Passband Stopband Passband Ripple Stopband Attenuation Delay Time ANALOG OUTPUT Voltage Range Center Voltage Load Impedance Frequency Response POWER SUPPLY REQUIREMENTS Voltage Range: VCC, Supply Current: Operation Power-Down Power Dissipation: Operation Power-Down(11) TEMPERATURE RANGE Operation Storage Thermal Resistance, ±1.0 ±1.0 ±1.0 Bits FSR/°C FSR/°C Vp-p °C/W CONDITIONS UNITS
EIAJ, A-Weighted EIAJ, A-Weighted
0.445fS 0.555fS 11.1/fS 0.60 AC-Coupling 20kHz -25°C +85°C +70°C(10) 3.0V 3.0V 3.0V 3.0V -0.16 ±0.17
+125
PACKAGE/ORDERING INFORMATION
PACKAGE DRAWING NUMBER SPECIFIED TEMPERATURE RANGE -25°C +85°C -25°C +85°C PACKAGE MARKING PCM3002E PCM3003E ORDERING NUMBER(1) PCM3002E PCM3002E/2K PCM3003E PCM3003E/2K TRANSPORT MEDIA Rails Tape Reel Rails Tape Reel
PRODUCT PCM3002E PCM3003E
PACKAGE SSOP-24 SSOP-24
NOTES: Models with slash available only Tape Reel quantities indicated (e.g., indicates 2000 devices reel). Ordering 2000 pieces "PCM3002E/2K" will single 2000-piece Tape Reel.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage +VDD, +VCC1, +VCC2 +6.5V Supply Voltage Differences ±0.1V Voltage Differences ±0.1V Digital Input Voltage -0.3 0.3V Analog Input Voltage -0.3 VCC1, VCC2 0.3V Power Dissipation 300mW Input Current ±10mA Operating Temperature Range -25°C +85°C Storage Temperature -55°C +125°C Lead Temperature (soldering, +260°C (reflow, 10s) +235°C
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit damaged ESD. Burr-Brown recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
PCM3002/3003
CONFIGURATION-PCM3002
View SSOP
CONFIGURATION-PCM3003
View SSOP
PCM3002 VCC1 VCC1 VINR VREFL VREFR VINL SYSCLK LRCIN BCKIN DOUT VCC2 AGND1 AGND2 VCOM VOUTR VOUTL ZFLG DGND VCC1 VCC1 VINR VREFL VREFR VINL PDAD PDDA SYSCLK LRCIN BCKIN DOUT
PCM3003 VCC2 AGND1 AGND2 VCOM VOUTR VOUTL DEM0 DEM1 20BIT DGND
ASSIGNMENTS-PCM3002
NAME VCC1 VCC1 VINR VREFL VREFR VINL SYSCLK LRCIN BCKIN DOUT DGND ZFLG VOUTL VOUTR VCOM AGND2 AGND1 VCC2 DESCRIPTION Analog Power Supply Analog Power Supply Analog Input, Reference, Reference, Analog Input, Reset, Active LOW(1, Strobe Pulse Mode System Clock Input(2) Sample Rate Clock Input (fS)(2) Clock Input(2) Data Output Digital Ground Digital Power Supply Data Input(2) Zero Flag Output, Active LOW(3) Serial Data Mode Control(1, Clock Mode Control(1, Analog Output, Analog Output, ADC/DAC Common Analog Ground Analog Ground Analog Power Supply Control(1,
ASSIGNMENTS-PCM3003
NAME VCC1 VCC1 VINR VREFL VREFR VINL PDAD PDDA SYSCLK LRCIN BCKIN DOUT DGND 20BIT DEM1 DEM0 VOUTL VOUTR VCOM AGND2 AGND1 VCC2 DESCRIPTION Analog Power Supply Analog Power Supply Analog Input, Reference, Reference, Analog Input, Power Down, Active LOW(1, Power Down, Active LOW(1, System Clock Input(2) Sample Rate Clock Input (fS)(2) Clock Input(2) Data Output Digital Ground Digital Power Supply Data Input 20-Bit Format Select(1, De-emphasis Control(1, De-emphasis Control 0(1, Analog Output, Analog Output, ADC/DAC Common Analog Ground Analog Ground Analog Power Supply
NOTES: With 100k typical internal pull-down resistor. Schmitt-Trigger input. Open drain output.
NOTE: With 100k typical internal pull-down resistor. Schmitt-Trigger input.
PCM3002/3003
TYPICAL PERFORMANCE CURVES SECTION
+25°C, 3.0V, 44.1kHz, fSYSCLK 384fS, FSIGNAL 1kHz, unless otherwise noted.
THD+N TEMPERATURE 0.010 -60dB
THD+N -0.5dB THD+N -60dB
Dynamic Range (dB)
DYNAMIC RANGE TEMPERATURE
Dynamic Range
(dB)
0.008
0.006
0.5dB
0.004
0.002
Temperature (°C)
Temperature (°C)
THD+N SUPPLY VOLTAGE 0.010 -60dB
DYNAMIC RANGE SUPPLY VOLTAGE
THD+N -0.50dB
THD+N -60dB
Dynamic Range (dB)
0.008
Dynamic Range
0.006
0.004 -0.5dB
0.002 Supply Voltage
Supply Voltage
THD+N SAMPLING FREQUENCY 0.010
DYNAMIC RANGE SAMPLING FREQUENCY
THD+N -0.5dB
-60dB
THD+N -60dB
Dynamic Range (dB)
0.008
Dynamic Range
(dB)
0.006 -0.5dB 0.004
0.002 44.1 (kHz)
44.1 (kHz)
PCM3002/3003
(dB)
TYPICAL PERFORMANCE CURVES SECTION
+25°C, 3.0V, 44.1kHz, fSYSCLK 384fS, FSIGNAL 1kHz, unless otherwise noted.
THD+N TEMPERATURE 0.010
DYNAMIC RANGE TEMPERATURE
THD+N -60dB
Dynamic Range (dB)
THD+N
0.008
-60dB
Dynamic Range
0.006 0.004
0.002
Temperature (°C)
Temperature (°C)
THD+N SUPPLY VOLTAGE 0.010
DYNAMIC RANGE SUPPLY VOLTAGE
-60dB THD+N -60dB
Dynamic Range (dB)
THD+N
0.008
Dynamic Range
0.006 0.004
0.002 Supply Voltage
Supply Voltage
THD+N SAMPLING FREQUENCY SYSTEM CLOCK 0.010
DYNAMIC RANGE SAMPLING FREQUENCY SYSTEM CLOCK 256fS, 512fS
THD+N -60dB
THD+N
-60dB
0.006 0.004
384fS 256fS, 512fS
Dynamic Range 384fS
0.002 44.1 (kHz)
44.1 (kHz)
PCM3002/3003
(dB)
384fS 256fS, 512fS
Dynamic Range (dB)
0.008
(dB)
(dB)
TYPICAL PERFORMANCE CURVES Output Spectrum
+25°C, 3.0V, 44.1kHz, fSYSCLK 384fS, FSIGNAL 1kHz, unless otherwise noted.
DACs
OUTPUT SPECTRUM (0dB, 8192) -100 -120 -140 Frequency (kHz) -100 -120 -140
ADCs
OUTPUT SPECTRUM (0dB, 8192)
Amplitude (dB)
Amplitude (dB)
Frequency (kHz)
OUTPUT SPECTRUM (-60dB, 8192)
Amplitude (dB)
-100 -120 -140
OUTPUT SPECTRUM (-60dB, 8192)
Amplitude (dB)
-100 -120 -140 Frequency (kHz)
Frequency (kHz)
THD+N SIGNAL LEVEL
THD+N SIGNAL LEVEL
THD+N
THD+N
0.001
0.001
0.001 Signal Level (dB)
0.001 Signal Level (dB)
PCM3002/3003
TYPICAL PERFORMANCE CURVES Supply Current
+25°C, 3.0V, 44.1kHz, fSYSCLK 384fS, BPZ, BPZ, unless otherwise noted. TEMPERATURE
IDD: Power Down (mA)
SUPPLY VOLTAGE
IDD: Power Down (mA)
(mA)
(mA)
Power Down Temperature (°C)
Power Down
Supply Voltage
SAMPLING FREQUENCY
(mA)
512fS
256fS
44.1 (kHz)
PCM3002/3003
TYPICAL PERFORMANCE CURVES
+25°C, 3.0V, 44.1kHz, fSYSCLK 384fS, unless otherwise noted.
DIGITAL FILTER
OVERALL CHARACTERISTICS STOPBAND ATTENUATION CHARACTERISTICS
Amplitude (dB)
Amplitude (dB)
-100
-150
-200 Normalized Frequency
-100 Normalized Frequency
PASSBAND RIPPLE CHARACTERISTICS
TRANSITION BAND CHARACTERISTICS
Amplitude (dB)
Amplitude (dB)
-0.2 -0.4 -0.6 -0.8 -1.0 Normalized Frequency
-4.13dB
0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 Normalized Frequency
HIGH PASS FILTER RESPONSE
HIGH PASS FILTER RESPONSE
Amplitude (dB)
-100 Normalized Frequency /1000
Amplitude (dB)
-0.2 -0.4 -0.6 -0.8 -1.0 Normalized Frequency /1000
PCM3002/3003
TYPICAL PERFORMANCE CURVES
+25°C, 3.0V, 44.1kHz, fSYSCLK 384fS, unless otherwise noted.
ANTI-ALIASING FILTER
ANTI-ALIASING FILTER OVERALL FREQUENCY RESPONSE
ANTI-ALIASING FILTER PASSBAND FREQUENCY RESPONSE
Amplitude (dB)
Amplitude (dB)
100k
-0.2 -0.4 -0.6 -0.8 -1.0 100k
Frequency (Hz)
Frequency (Hz)
PCM3002/3003
TYPICAL PERFORMANCE CURVES
+25°C, 3.0V, 44.1kHz, fSYSCLK 384fS, unless otherwise noted.
DIGITAL FILTER
OVERALL FREQUENCY CHARACTERISTICS 44.1kHz)
PASSBAND RIPPLE CHARACTERISTICS 44.1kHz)
Level (dB)
-0.2
Level (dB)
-0.4
-0.6
-0.8
-100 100k Frequency (Hz) 150k
-1.0 Frequency (Hz)
DE-EMPHASIS FREQUENCY RESPONSE (32kHz) Frequency (Hz) DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz) Frequency (Hz) DE-EMPHASIS FREQUENCY RESPONSE (48kHz) Frequency (Hz) -0.2 -0.4 -0.6 -0.2 -0.4 -0.6 -0.2 -0.4 -0.6
DE-EMPHASIS ERROR (32kHz)
Level (dB)
Error (dB)
3628
7256 Frequency (Hz)
10884
14512
DE-EMPHASIS ERROR (44.1kHz)
Level (dB)
Error (dB)
4999.8375
9999.675 Frequency (Hz)
14999.5125
19999.35
DE-EMPHASIS ERROR (48kHz)
Level (dB)
Error (dB)
5442
10884 Frequency (Hz)
16326
21768
INTERNAL ANALOG FILTER FREQUENCY RESPONSE (10Hz~10MHz)
INTERNAL ANALOG FILTER FREQUENCY RESPONSE (1Hz~20kHz) 0.15 0.10 0.05
Level (dB)
-100 100k Frequency (Hz)
Level (dB)
-0.05 -0.10 -0.15 100k Frequency (Hz)
PCM3002/3003
BLOCK DIAGRAM
VINL
Analog Front-End Circuit
Delta-Sigma Modulator
Decimation High Pass Filter
LRCIN
VREFL VCOM VREFR Reference
BCKIN
Serial Data Interface
VINR
Analog Front-End Circuit
Delta-Sigma Modulator
Decimation High Pass Filter
DOUT
VOUTL
Analog Low-Pass Filter
Multi-Level Delta-Sigma Modulator
Interpolation Filter Oversampling
MC(1 )/DEM0(2) Mode Control Interface
MD(1 )/DEM1(2) ML(1 20BIT(2)
VOUTR Analog Low-Pass Filter Multi-Level Delta-Sigma Modulator Interpolation Filter Oversampling
Reset Power Down
PDDA(2) RST(1)/PDAD(2)
Power Supply
Clock
Zero Detect(1)
AGND2
VCC2
AGND1
VCC1
DGND
SYSCLK
ZFLG(1)
NOTES: RST, ZFLG PCM3002 only. DEM0, DEM1, 20BIT, PDAD, PDDA PCM3003 only.
1.0µF
VINR
VCOM 4.7µF 4.7µF 4.7µF VREF VREFL VREFR
Delta-Sigma Modulator
FIGURE Analog Front-End (Single-Channel).
PCM3002/3003
AUDIO INTERFACE
four-wire digital audio interface PCM3002/3003 comprised LRCIN (pin 10), BCKIN (pin 11), (pin 15), DOUT (pin 12). PCM3002 used with four input/output data formats (Formats while PCM3003 only used with selected input/ output formats (Formats PCM3002, these formats selected through PROGRAM REGISTER
FORMAT PCM3002/3003
DAC: 16-Bit, MSB-First, Right-Justified LRCIN BCKIN ADC: 16-Bit, MSB-First, Left-Justified LRCIN BCKIN DOUT L-ch R-ch L-ch R-ch
software mode. PCM3003, data formats selected 20BIT input (pin 16). Figures illustrate audio data input/output formats timing. PCM3002/3003 accept 32-, 48-, 64-bit clocks (BCKIN) clock LRCIN. Only 16-bit data formats selected when 32-bit clocks/LRCIN applied.
FORMAT PCM3002/3003
DAC: 20-Bit, MSB-First, Right-Justified LRCIN BCKIN ADC: 20-Bit, MSB-First, Left-Justified LRCIN BCKIN DOUT L-ch R-ch L-ch R-ch
FORMAT PCM3002 Only
DAC: 20-Bit, MSB-First, Left-Justified LRCIN BCIN ADC: 20-Bit, MSB-First, Left-Justified LRCIN BCIN DOUT L-ch R-ch L-ch R-ch
FIGURE Audio Data Input/Output Format.
PCM3002/3003
FORMAT PCM3002 Only
DAC: 20-Bit, MSB-First, LRCIN BCKIN ADC: 20-Bit, MSB-First, LRCIN BCKIN DOUT L-ch L-ch
R-ch
R-ch
FIGURE Audio Data Input/Output Format.
tLRP LRCIN tBCH tBCL 0.5VDD tBCY tDIS tDIH 0.5VDD 0.5VDD
BCKIN
tBDO DOUT
tLDO 0.5VDD
BCKIN Pulse Cycle Time BCKIN Pulse Width High BCKIN Pulse Width BCKIN Rising Edge LRCIN Edge LRCIN Edge BCKIN Rising Edge LRCIN Pulse Width Set-up Time Hold Time DOUT Delay Time BCKIN Falling Edge DOUT Delay Time LRCIN Edge Rising Time Signals Falling Time Signals
tBCY tBCH tBCL tLRP tDIS tDIH tBDO tLDO tRISE tFALL
300ns (min) 120ns (min) 120ns (min) 40ns (min) 40ns (min) tBCY (min) 40ns (min) 40ns (min) 40ns (max) 40ns (max) 20ns (max) 20ns (max)
FIGURE Audio Data Input/Output Timing.
PCM3002/3003
SYSTEM CLOCK
system clock PCM3002/3003 must either 256fS, 384fS 512fS, where audio sampling frequency. system clock should provided SYSCLK input (pin PCM3002/3003 also system clock detection circuit which automatically senses system clock operating 256fS, 384fS, 512fS. When 384fS 512fS system clock used, clock divided into 256fS automatically. 256fS clock used operate digital filters delta-sigma modulators. Table lists relationship typical sampling frequencies system clock frequencies, while Figure illustrates system clock timing.
SAMPLING RATE FREQUENCY (kHz) SYSTEM CLOCK FREQUENCY (MHz) 256fS 44.1 8.1920 11.2896 12.2880 384fS 12.2880 16.9340 18.4320 512fS 16.3840 22.5792 24.5760
POWER-ON RESET Both PCM3002 PCM3003 have internal power-on reset circuitry. Power-on reset occurs when system clock (SYSCLK) active 2.2V. PCM3003, SYSCLK must complete minimum complete cycles prior 2.2V ensure proper reset operation. initialization sequence requires 1024 SYSCLK cycles completion, shown Figure Figure shows state outputs during after reset sequence. EXTERNAL RESET PCM3002 includes reset input, (pin while PCM3003 utilizes both PDAD (pin PDDA (pin external reset control. shown Figure external reset signal must drive PDAD/PDDA minimum nanoseconds while SYSCLK active order initiate reset sequence. Initialization starts rising edge PDAD/PDDA, requires 1024 SYSCLK cycles completion. Figure shows state outputs during after reset sequence.
TABLE System Clock Frequencies.
tSCKH SYSCLK tSCKL
0.7V 0.3VDD
1/256fS,1/384fS,or 1/512fS tSCKH tSCKL 12ns 12ns (min) (min)
System Clock Pulse Width High System Clock Pulse Width
FIGURE System Clock Timing.
2.4V 2.2V 2.0V Reset Reset Removal
Internal Reset 1024 System Clock Periods SYSCLK
FIGURE Internal Power-On Reset Timing.
PDAD PDDA tRST 40ns minimum tRST Reset Reset Removal Internal Reset 1024 System Clock Periods SYSCLK
FIGURE External Forced Reset Timing.
PCM3002/3003
SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM PCM3002/3003 operates with LRCIN synchronized system clock. PCM3002/3003 does require specific phase relationship between LRCIN system clock, there must synchronization. synchronization between system clock LRCIN changes more than clocks (BCKIN) during sample (LRCIN) period because phase jitter LRCIN, internal operation will stop within 1/fS, analog output will forced bipolar zero (0.5VCC) until system clock resynchronized LRCIN followed tDACDLY2 delay time. Internal operation will also stop within 1/fS, digital output codes will bipolar zero until
synchronization occurs followed tADCDLY2 delay time. LRCIN synchronized with less clocks system clock, operation will normal. Figure illustrates effects output when synchronization lost. Before outputs forced bipolar zero (<1/fS seconds), outputs defined some noise occur. During transitions between normal data undefined states, output discontinuities, which will cause output noise. ZERO FLAG OUTPUT: PCM3002 ONLY open-drain output, used infinite zero detection flag PCM3002 only. When input data continuously zero 65,536 BCKIN cycles, ZFLG LOW, otherwise, ZFLG high-impedance state.
Reset Removal Power Down Internal Reset Power Down Reset Power Down tDACDLY1 (16384/fS) VCOM (0.5VCC) tADCDLY1 (18436/fS) DOUT Zero Zero Normal Data(1) Ready/Operation
VOUT
NOTE: transient response (exponentially attenuated signal from ±0.2% with 200ms time constant) appears initially.
FIGURE Output Output Reset Power Down.
Synchronization Lost State Synchronization
Resynchronization
Synchronous
Asynchronous within 1/fS
Synchronous
tDACDLY2 (32/fS) Undefined Data VOUT Normal VCOM VCC) tADCDLY2 (32/fS) Normal
Undefined Data DOUT Normal Zero
Normal(1
NOTES: transient response (exponentially attenuated signal from ±0.2% with 200ms time constant) appears initially.
FIGURE Output Output Loss Synchronization.
PCM3002/3003
FIGURE Control Data Input Format.
tMLH tMLH tMCH tMCY tMCL tMLL tMLS
tMDS tMDH tMCY tMCL tMCH tMDS tMDH tMLL tMLH tMLS tMLH
Pulse Cycle Time Pulse Width Pulse Width HIGH Setup Time Hold Time Level Time High Level Time Setup Time Hold Time
100ns (min) 40ns (min) 40ns (min) 40ns (min) 40ns (min) 40ns 1SYSCLK (min) 40ns 1SYSCLK (min) 40ns (min) 40ns (min)
SYSCLK: 1/256fS 1/384fS 1/512fS
FIGURE Control Data Input Timing.
FUNCTION Audio Data Format LRCIN Polarity Loop-Back Control Left Channel Attenuation Right Channel Attenuation Attenuation Control Infinite Zero Detection Output Control Soft Mute Control De-Emphasis (OFF, 32kHz, 44.1kHz, 48kHz) Power-Down Control Power-Down Control High Pass Filter Operation
ADC/DAC ADC/DAC ADC/DAC ADC/DAC
PCM3002 Selectable Formats
PCM3003 Selectable Formats
TABLE Selectable Functions User Selectable; Available).
OPERATIONAL CONTROL
PCM3002 controlled software mode with three-wire serial interface (pin 18), (pin 17), (pin Table indicates selectable functions, Figure illustrate control data input format timing. PCM3003 only allows control 16-/20-bit data format, digital de-emphasis, Power-Down Control hardware pins.
PCM3002/3003
MAPPING PROGRAM REGISTERS
REGISTER REGISTER REGISTER REGISTER PDAD BYPS PDDA FMT1 DEM1 FMT0 DEM0
SOFTWARE CONTROL (PCM3002) PCM3002's special functions controlled using four program registers which bits long. There four distinct registers, with bits determining which register use. Table describes functions four registers.
REGISTER NAME Register NAME (1:0) (7:0) (1:0) (7:0) (1:0) PDAD PDDA BYPS (1:0) (1:0) (1:0)
attenuation data will ignored, output level will remain previous attenuation level. REGISTER equivalent function LDL. When either "1", output level left right channels simultaneously controlled. (7:0): Attenuation Data Left Channel LSB, respectively. attenuation level (ATT) given log10 (ATT data/255) (dB)
(7:0) ATTENUATION LEVEL (Mute) -48.16dB -0.07dB (default)
DESCRIPTION Register Address "00" Reserved, should Attenuation Data Load Control Attenuation Data Register Address "01" Reserved, should Attenuation Data Load Control Attenuation Register Address "10" Reserved, should Power-Down Control Power-Down Control High-Pass Filter Operation Control Attenuation Data Mode Control Infinite Zero Detection Circuit Control Output Enable Control De-emphasis Control Soft Mute Control Register Address "11" Reserved, should ADC/DAC Analog Loop-Back Control ADC/DAC Audio Data Format Selection ADC/DAC Polarity LR-clock Selection
Register
Register
PROGRAM REGISTER (1:0): Register Address These bits define address REGISTER
Register
Register
res: LDR:
15:11
Reserved
TABLE III. Functions Registers. PROGRAM REGISTER (1:0): Register Address These bits define address REGISTER
Register
These bits reserved should Attenuation Data Load Control Right Channel This used simultaneously analog outputs left right channels. output level controlled (7:0) attenuation data when this "1". When "0", attenuation data will ignored, output level will remain previous attenuation level. REGISTER equivalent function LDR. When either "1", output level left right channels simultaneously controlled. (7:0): Attenuation Data Left Channel
res: LDL:
Reserved These bits reserved should "0". Attenuation Data Load Control Left Channel This used simultaneously analog outputs left right channels. output level controlled (7:0) attenuation data when this "1". When "0",
respectively. REGISTER attenuation formula.
PCM3002/3003
PROGRAM REGISTER (1:0): Register Address These bits define address REGISTER
Register
IZD:
Infinite Zero Detection Circuit Control
res: PDAD:
15:11, Reserved These bits reserved should "0". Power-Down Control OUT: This places section lowest power consumption mode. operation stopped cutting supply current section, DOUT fixed zero during Power-down mode enable. Figure illustrates DOUT response power-down OFF. This does affect operation.
PDAD POWER-DOWN Power Down Mode Disabled (default) Power Down Mode Enabled
This enables Infinite Zero Detection Circuit PCM3002. When enabled, this circuit will disconnect analog output amplifier from deltasigma when input continuously zero 65,536 consecutive cycles BCKIN.
Infinite Zero Detection Disabled (default) Infinite Zero Detection Enabled
Output Enable Control
When "1", outputs forced VCC/2 (bipolar zero). this case, registers PCM3002 hold present data. Therefore, when "0", outputs return previous programmed state.
Outputs Enabled (default normal operation) Outputs Disabled (forced BPZ)
BYPS:
High-Pass Filter Bypass Control
(1:0):Bit
De-emphasis Control
This enables disables high-pass filter ADC.
BYPS High-Pass Filter Enabled (default) High-Pass Filter Disabled (bypassed)
These bits select de-emphasis mode shown below:
DEM1 DEM0 De-emphasis 44.1kHz De-emphasis (default) De-emphasis 48kHz De-emphasis 32kHz
PDDA:
Power-Down Control MUT:
This places section lowest power consumption mode. operation stopped cutting supply current section VOUT fixed during PowerDown Mode enable. Figure illustrates VOUT response Power-Down ON/OFF. This does affect operation.
PDDA Power-Down Mode Disabled (default) Power-Down Mode Enabled
Soft Mute Control
When "1", both left right-channel outputs muted same time. This muting done attenuating data digital filter, there audible click noise when soft mute turned
Mute Disable (default) Mute Enable
ATC:
Attenuation Channel Control
When "1", REGISTER attenuation data used both channels. this case, REGISTER attenuation data ignored.
Individual Channel Attenuation Data Control (default) Common Channel Attenuation Data Control
PROGRAM REGISTER (1:0): 10:9 Register Address These bits define address REGISTER
Register
res:
15:11, 8:6,
Reserved
These bits reserved, should "0".
PCM3002/3003
LOP:
Loop-Back Control
LRP:
When this "1", ADC's audio data sent directly DAC. data format will default I2S. Format (I2S Frame), Loopback supported.
Loop-back Disable (default) Loop-back Enable
Polarity LRCIN Applies only Formats through
Left-channel "H", Right-channel "L". (default) Left-channel "L", Right-channel "H".
(1,0)
Audio Data Format Select
These bits determine input output audio data formats.
FMT1 FMT0 Data Format 16-bit, MSB-first, Right-justified 20-bit, MSB-first, Right-justified 20-bit, MSB-first, Left-justified 20-bit, MSB-first, Data Format 16-bit, MSB-first, Left-justified 20-bit, MSB-first, Left-justified 20-bit, MSB-first, Left-justified 20-bit, MSB-first, NAME Format (default) Format Format Format
Analog
0.1µF 10µF(1) 4.7µF(2) 4.7µF(2)
PCM3002/3003
0.1µF 10µF(1) VCC1 VCC1 VINR VREFL VREFR VINL RST/PDAD ML/PDDA SYSCLK VCC2 AGND1 AGND2 VCOM VOUTR VOUTL MC/DEM0 MD/DEM1 4.7µF(4) 4.7µF(4) 4.7µF(4) Out(5) MC(6)/DEM0(7) MD(6)/DEM1(7) ZFLG(6)/20BIT(7) Control Interface 0.1µF 10µF(1) Out(5)
SYSCLK Audio Interface DATA
ZFLG/20BIT DGND
LRCIN BCKIN DOUT
DATA ML(6)/PDDA(7) RST(6)/PDAD(7) NOTES: 0.1µF ceramic 10µF tantalum, typical, depending power supply quality pattern layout. 4.7µF typical, gives settling time with 30ms (4.7µF 6.4k) time constant Power Power-Down period. typical, gives 5.3Hz cut-off frequency input normal operation gives settling time with 30ms (1µF 30k) time constant Power Power -Down period. 4.7µF typical, gives 3.4Hz cut-off frequency output normal operation gives settling time with 47ms (4.7µF 10k) time constant Power Power-Down period. Post pass filter with >10k, depending requirement system performance. ZFLG, pull-up resistor PCM3002. DEM0, DEM1, 20BIT, PDAD, PDDA PCM3003.
FIGURE Typical Connection Diagram PCM3002/3003.
PCM3002/3003
PCM3003 DATA FORMAT CONTROL PCM3003 hardware functional control using PDAD (pin PDDA (pin Power-Down Control; DEM0 (pin DEM1 (pin de-emphasis; 20BIT (pin 16-/20-bit format selection. Power-Down Control (Pin Both ADC's DAC's Power-Down Control pins place section lowest power consumption mode. ADC/DAC operation stopped cutting supply current ADC/DAC section. DOUT fixed zero during Power-Down Mode enable VOUT fixed during Power-Down Mode enable. Figure illustrates output response Power-Down ON/OFF.
PDAD High High PDDA High High POWER DOWN Reset (ADC/DAC Power-Down Enable) Power-Down/DAC Operates Operates/DAC Power-Down Normal Operation
GROUNDING order optimize dynamic performance PCM3002/ 3003, analog digital grounds connected internally. PCM3002/3003 performance optimized with single ground plane returns. recommended PCM3002/3003 ground pins with impedance connections analog ground plane. PCM3002/3003 should reside entirely over this plane avoid coupling high frequency digital switching noise into analog ground plane. VOLTAGE INPUT PINS tantalum aluminum electrolytic capacitor, between 10µF, recommended AC-coupling capacitor inputs. Combined with characteristic input impedance, 1.0µF coupling capacitor will establish 5.3Hz cut-off frequency blocking input voltage range increased adding series resistor analog input line. This series resistor, when combined with input impedance, creates voltage divider enables larger input ranges. VREF INPUTS 4.7µF 10µF tantalum capacitor recommended between VREFL, VREFR, AGND ensure source impedance ADC's references. These capacitors should located close possible reference pins reduce dynamic errors reference. VCOM INPUTS 4.7µF 10µF tantalum capacitor recommended between VCOM AGND ensure source impedance common voltage. This capacitor should located close possible VCOM reduce dynamic errors common mode voltage. SYSTEM CLOCK
De-Emphasis Control (Pin DEM0 (pin DEM1 (pin used de-emphasis control pins.
DEM1 High High DEM0 High High DE-EMPHASIS De-Emphasis Enabled 44.1kHz De-Emphasis Disabled De-Emphasis Enabled 48kHz De-Emphasis Enabled 32kHz
20BIT Audio Data Selection (Pin
20BIT High FORMAT ADC: 16-bit MSB-first, Left-justified DAC: 16-bit MSB-first, Right-justified ADC: 20-bit MSB-first, Left-justified DAC: 20-bit MSB-first, Right-justified
APPLICATION LAYOUT CONSIDERATIONS
POWER SUPPLY BYPASSING digital analog power supply lines PCM3002/ 3003 should bypassed corresponding ground pins with both 0.1µF ceramic 10µF tantalum capacitors close device pins possible. Although PCM3002/ 3003 three power supply lines optimize dynamic performance, common power supply generally recommended avoid unexpected latch-up noise power supply sequencing problems. separate power supplies used, back-to-back diodes recommended avoid latch-up problems.
quality system clock influence dynamic performance both PCM3002/ 3003. duty cycle jitter system clock input must carefully managed. When power supplied part, system clock, clock (BCKIN) word clock (LCRIN) should also supplied simultaneously. Failure supply audio clocks will result power dissipation increase three times normal dissipation degrade long term reliability maximum power dissipation limit exceeded.
PCM3002/3003
EXTERNAL MUTE CONTROL Power-Down ON/OFF control without click noise which generated output level change, external mute control recommended. control sequence, which external mute CODEC Power-Down SYSCLK stop resume necessary, CODEC Power-down OFF, external mute recommended.
delta-sigma noise shaper consists five integrators which switched-capacitor topology, comparator feedback loop consisting one-bit DAC. delta-sigma modulator shapes quantization noise, shifting audio band frequency domain. high order modulator enables randomize modulator outputs, reducing idle tone levels. 64fS one-bit data stream from modulator converted 18-bit data words decimation filter, which also acts pass filter remove shaped quantization noise. components removed high pass filter function contained within decimation filter.
THEORY OPERATION
SECTION PCM3002/3003 consists reference circuits, stereo single-to-differential converter, fully differential 5th-order delta-sigma modulator, decimation filter (including digital high pass), serial interface circuit. Block Diagram this data sheet illustrates architecture section, Figure shows single-to-differential converter, Figure illustrates architecture 5th-order delta-sigma modulator transfer functions. internal reference circuit with three external capacitors provides reference voltages which required ADC, which defines full scale range converter. internal single-to-differential voltage converter saves space extra parts needed external circuitry required many delta-sigma converters. internal fulldifferential signal processing architecture provides wide dynamic range excellent power supply rejection performance. input signal sampled oversampling rate, eliminating need sample-and-hold circuit, simplifying anti-alias filtering requirements. 5th-order
THEORY OPERATION
SECTION delta-sigma section PCM3002/3003 based 5-level amplitude quantizer 3rd-order noise shaper. This section converts oversampled input data 5-level delta-sigma format. block diagram 5-level deltasigma modulator shown Figure This 5-level deltasigma modulator advantage improved stability reduced clock jitter sensitivity over typical one-bit level) delta-sigma modulator. combined oversampling rate delta-sigma modulator internal interpolation filter 64fS 256fS system clock. theoretical quantization noise performance 5-level deltasigma modulator shown Figure
Analog X(z)
SW-CAP Integrator SW-CAP Integrator SW-CAP Integrator
SW-CAP Integrator SW-CAP Integrator Qn(z) H(z) Comparator Digital Y(z)
1-Bit Y(z) STF(z) X(z) NTF(z) Qn(z) Signal Transfer Function Noise Transfer Function STF(z) H(z)/[1 H(z)] NTF(z) 1/[1 H(z)]
FIGURE Simplified 5th-Order Delta-Sigma Modulator.
PCM3002/3003
18-Bit
5-level Quantizer 64fS (256fS)
FIGURE 5-Level Delta-Sigma Modulator Block Diagram.
ORDER MODULATOR -100 -110 -120 -130 -140 -150 Frequency (kHz)
FIGURE Quantization Noise Spectrum.
Gain (-dB)
PCM3002/3003
PACKAGE OPTION ADDENDUM
www.ti.com
4-Aug-2004
PACKAGING INFORMATION
ORDERABLE DEVICE PCM3002E PCM3002E/2K PCM3002EG PCM3002EG/2K PCM3003E PCM3003E/2K STATUS(1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE PACKAGE TYPE SSOP SSOP SSOP SSOP SSOP SSOP PACKAGE DRAWING PINS PACKAGE 2000 2000 2000
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
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