Channel Dual Mapper TXC-04218 DATA SHEET PRODUCT PREVIEW FEATURES
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TEMx8 Device
Channel Dual Mapper TXC-04218 DATA SHEET PRODUCT PREVIEW FEATURES
Add/drop DS1, VT/TU payloads from drop STM-1/VC4, STS-3 buses drop timing modes Cross mapping applications (DS1 mapped to/from VT2/TU-12s) Selectable HDB3/B8ZS/AMI positive/negative rail, NRZ, VT/TU interfaces channel multiframe option place Telecom pulse Digital desynchronizer Drop buses monitored parity, loss clock, upstream Performance counters pointer movements, BIP-2 errors, coding violations Single-bit three-bit operation channel Tandem connection capability ETSI standards trail trace comparison option Processor access H1/H2, overhead bytes, V1/V2 bytes Selectable positive, negative positive/negative alarm transition interrupt options Line facility loopbacks, generation BIP-2 errors, PRBS generator analyzer channel Polling registers global summary alarm status second measurements: counters alarms Software device driver provided IEEE 1149.1 standard boundary scan +3.3 power supplies, tolerant leads 376-lead plastic ball grid array (PBGA) package
TEMx8 device designed add/drop multiplexer, terminal multiplexer, dual single unidirectional ring applications. DS1, VT/TU payloads mapped from VT1.5/TU-11s VT2/TU-12s carried STM-1 VC-4 STS-3 format. device interfaces multiple-segment, byte-parallel SDH/SONET-formatted 19.44 Mbyte/s byte rate. signals HDB3 B8ZS/AMI rail signals, signals. VT/TU interface provided with without overhead bytes virtual concatenation applications. TEMx8 performs pointer tracking overhead byte processing, including single-bit three-bit operation, optional tandem connection capability. overhead bytes, including V1/V2/V4 bytes, provided microprocessor access. TEMx8 generate receive transmit line AIS, transmit unequipped supervisory unequipped channels, transmit VT/TU AIS, addition standards-compliant overhead byte monitoring. also provides test features microprocessor interface.
APPLICATIONS
STS-3/STM-1 1.544 Mbit/s 2.048 Mbit/s add/drop mux/demux Unidirectional bidirectional ring applications STS-3/STM-1 termination terminal mode multiplexer STS-3/STM-1 test equipment
STM-1/STS-3 SDH/SONET SIDE
side drop side side drop side
+3.3 +1.8
Desynchronizer Clock
LINE SIDE
TEMx8
Channel Dual Mapper TXC-04218
Channel
lines
Channel
Boundary Scan U.S. and/or foreign patents issued pending Copyright 2003 TranSwitch Corporation PHAST, TEMx28, TranSwitch registered trademarks TranSwitch Corporation
Microprocessor interface
Controls
Document Number: PRODUCT PREVIEW TXC-04218-MB, August 2003
TranSwitch Corporation Enterprise Drive Shelton, Connecticut 06484 Tel: 203-929-8810 Fax: 203-926-9453 www.transwitch.com
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TEMx8 TXC-04218
DATA SHEET
TABLE CONTENTS
Section Page
List Figures Overview Features Block Diagram Block Diagram Description Application Example Interoperability. Lead Diagram Lead Descriptions. Absolute Maximum Ratings Environmental Limitations Thermal Characteristics. Power Requirements Input, Output Input/Output Parameters Timing Characteristics Operation. Interface Modes Mode Selection SDH/SONET Add/Drop Multiplexing Format Selections Drop TU/VT Selection Timing Performance Counters Alarm Structure Second (Shadow) Registers. Interrupt Structure Drop Interface Drop Parity Selection Drop Multiframe Alignment. SDH/SONET Detection TU/VT Pointer Tracking. Overhead Byte Processing Overhead Communications Access Overhead Byte Insertion Test Functions. PRBS Pattern Generator Analyzer. Resets Data Throughput Delay Pointer Leak Rate Calculations Jitter Measurements. Boundary Scan. Multiplex Format Mapping Information Memory Memory Descriptions. Package Information Ordering Information Related Products Reference Documents. Standards Documentation Sources.
Please note that TranSwitch provides documentation products. Current editions many documents available from Products page TranSwitch site www.transwitch.com. Customers using TranSwitch Product, planning should register with TranSwitch Marketing Department receive relevant updated supplemental documentation issued. They should also contact Applications Engineering Department ensure that they provided with latest available information about product, especially before undertaking development designs incorporating product.
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DATA SHEET LIST FIGURES
Figure
TEMx8 TXC-04218
Page
TEMx8 TXC-04218 Block Diagram 1544 kbit/s Asynchronous Mapping. 2048 kbit/s Asynchronous Mapping. VC-11 VC-12 Cross Mapping Application Using TEMx8 TXC-04218 TEMx8 TXC-04218 376-Lead Plastic Ball Grid Array Package Lead Diagram Channels DS1/E1 Transmit Rail Interface Timing. Channels DS1/E1 Transmit Interface Timing. Channels Transmit VT/TU Interface Timing -Gapped Pointer Bytes. Channels Transmit VT/TU Interface Timing-Gapped Pointer Byte Channels DS1/E1 Receive Rail Timing. Channels DS1/E1 Receive Timing. Channels Receive VT/TU Interface Timing -Gapped Pointer Bytes. Channels Receive VT/TU Interface Timing-Gapped Pointer Byte STS-3 Drop Signals, Timing Derived from Drop (lead ABTE low) STS-3 Drop Signals, Timing Derived from Drop (lead ABTE high) STM-1 VC-4 Drop Signals, Timing Derived from Drop (lead ABTE low) STM-1 VC-4 Drop Signals, Timing Derived from Drop (lead ABTE high) STS-3 Signals, Timing Derived from STM-1 VC-4 Signals, Timing Derived from Microprocessor Read Cycle Timing Intel. Microprocessor Write Cycle Timing Intel Microprocessor Read Cycle Timing Motorola Microprocessor Write Cycle Timing Motorola Boundary Scan Timing Alarm Latching Configurations Second (Shadow) Register Operation Channel Polling Alarms Global Indication Alarms. Hardware Interrupt Indication Byte Floating Mode Allocation. VT/TU Pointer Tracking State Machine Loopback, Line PRBS Generator/Analyzer (2048 kbit/s) Jitter Tolerance. (1544 kbit/s) Jitter Tolerance Jitter Tolerance Measurements Jitter Transfer Jitter Transfer Measurements Jitter Transfer Measurements. TU-12 Standard Pointer Test Sequences. VT1.5 Standard Pointer Test Sequences Boundary Scan Schematic TEMx8 TXC-04218 376-Lead Plastic Ball Grid Array Package.
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TEMx8 TXC-04218 OVERVIEW
DATA SHEET
TEMx8 generate receive transmit line AIS, transmit unequipped supervisory unequipped channels, transmit VT/TU AIS, addition standards-compliant overhead byte monitoring. testing, device provides IEEE 1149.1 boundary scan, PRBS generator analyzer, both line facility loopbacks. TEMx8 supports split access either Intel Motorola microprocessors. performance counters configured either saturating roll over. Interrupts generated alarms that latch positive, negative, both positive negative status transitions, they disabled mask bits. software polling register summary alarm status also provided. second measurements performed alarms counters.
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TEMx8 device designed add/drop multiplexer, terminal multiplexer, dual single unidirectional ring applications. DS1, VT/TU payloads mapped from VT1.5/TU-11s VT2/TU-12s carried STM-1 VC-4 STS-3 format. device interfaces multiple-segment, byte-parallel SDH/SONET-formatted 19.44 Mbyte/s byte rate. signals HDB3 B8ZS/AMI positive/negative rail (dual unipolar) signals, signals. VT/TU interface provided with without overhead bytes virtual concatenation applications. TEMx8 performs pointer tracking overhead byte processing, including single-bit three-bit operation, optional tandem connection capability. overhead bytes, including V1/V2/V4 bytes, provided microprocessor access.
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DATA SHEET FEATURES
following detailed list features supported TEMx8: Modes operation (Each Channel) Drop Mode Only Drop from Mode only Single Unidirectional Ring Drop from Drop from Multiplexer Drop from Drop from Dual Protection Ring Drop from Drop from Timing Drop Timing Timing Derived from same named Drop Timing Timing independent Drop Lead Selectable
TEMx8 TXC-04218
SONET/SDH COMBUS Interface Drop Timing Enabled Drop Bus: C1J1V1, SPE, Byte Wide Data, Clock, Parity Bus: Byte Wide Data, Parity, Indicator Option: Clock, C1J1V1, Outputs Timing Enabled Drop Bus: C1J1V1, SPE, Byte Wide Data, Clock, Parity Bus: Clock, C1J1V1, inputs; Byte Wide Data, Parity, Indicator Outputs. Mappings Maximum Channels DS1/E1 Line Asynchronous Formats, VC-11/VC-12s Independent VT1.5/TU-11 VT2/TU12 Selection Channel both Drop Buses Cross Mapping: mapped into VT1.5/TU-12 SONET/SDH Operating Formats STS-3 STS-1 (19.44 Mbyte/s) STM-1 VC-4/TUG-3/TUG-2 (19.44 Mbyte/s) STM-1 AU-3s (19.44 Mbyte/s)
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TEMx8 TXC-04218
DATA SHEET
SONET/SDH Features In-band upstream Detection H1/H2 Pointer Bytes Bytes using Majority Voting Byte Multiframe Detectors pulse (C1J1V1) reference input Determines Location V1/V2 Pointer Bytes Pointer Tracking ETSI/ITU/ANSI State Machine Wrong Size Bits Detection Positive/Negative Justification 8-bit Counters Microprocessor Access V1/V2 Pointer Bytes (Each Channel) Bytes (Both Buses, VC-4 Three STS-1s) (used Upstream Indication) Bytes (Both Buses, VC-4 Three STS-1s) H1/H2 Pointer Bytes (Both Buses, VC-4 Three STS-1s) VT/TU Overhead Byte Processing Byte Byte Read Segment with Optional CR/LF Alignment Byte Read Segment with Optional Trail Trace Message Comparison V5/K4 Byte Three Single (Programmable Each Channel) Detection/Recovery Selection: event Option Error Counter Detector BIP-2 Bit/Block Error Counter Option Signal Label Mismatch, Unequipped, detection Detection/Recovery: events Byte Tandem Connection Option Trail Trace Message Comparison against Microprocessor Written Message
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Other Features Drop Buses Input Parity Check with Alarm Indication Odd, Even Data Only, Signals Input Loss Clock Detection Stuck High Buses Output Parity Generation Odd, Even Data Only, Signals Indicator High Output Signals Control Individual Channel High VT/TU Time Slots
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DATA SHEET
Overhead Byte Access Both Buses Desynchronizer Meets ANSI/ETSI/ITU Requirements Pointer Test Sequences Jitter/MTIE External Clock (Common Both Rates) Leak Rate Control Microprocessor Control Bits Line (DS1/E1) Generation Mask Bits Individual Alarms Global Mask Alarms Microprocessor Control VT/TU Overhead Byte Insertion (per Channel) Byte byte Microprocessor Written Message Forced Option V5/K4 Byte Insertion (from Drop Side VT/TU) Value from Microprocessor BIP-2 Calculation Insertion Insertion Single Three Generated Minimum Multiframes Mask bits Alarms Global Mask Alarms Microprocessor Control Byte Input Bits from External VT/TU interface Byte Tandem Connection Option byte Message Insertion Mask Alarm Bits Microprocessor Generation Internal Multiframe Generation Generation Unequipped Generation Overhead Single Byte Insertion Bytes Test purpose Unequipped Generation (per Channel) Supervisory Unequipped Generation Option Transmit Generation
TEMx8 TXC-04218
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TEMx8 TXC-04218
TU/VT Microprocessor Control Alarms with mask Bits Microprocessor Control
DATA SHEET
Line Interface External Loss Signal Coding Violation Input Rail CODEC AMI/B8ZS/HDB3 Coding Violation Counter Loss Signal Detector VT/TU Interface Timing Mode Only Fixed C1J1 Locations Direction Modes: With Without (Gapped Clock) Overhead Bytes Transmit Direction: Fixed Framing References Clock Outputs, Data Bits byte clocked with data symmetrical clock Microprocessor Interface Intel Motorola Split lead Option (683XX Processors) READY/DTACK Leads Interrupt Structure Positive, Negative, Positive/Negative Alarm Transitions Polling Registers with Mask Bits Alarm Summary Bits with Mask Bits Second Measurements Counters Roll Over Saturating Second Measurements Test features Boundary Scan DS-1/E1 loopbacks Facility Line COMBUS loopback High Leads (except Boundary Scan Output) PRBS Generator Analyzer 215-1 defined O.151 T1M1.3/92-006R3 QRSS (220-1) defined ANSI T1.403-1195) Drop Direction Placement Single Error Generation Transmit BIP-2
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O-bit Access Drop both Buses
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DATA SHEET BLOCK DIAGRAM
TEMx8 TXC-04218
block diagram TEMx8 device shown Figure Further information device operation interfaces external circuits provided following paragraphs.
External Desync Clock
Receive
Test TU/VT Terminate Drop Interface Drop Pointer Tracking TU/VTs Drop Overhead Byte Processing TU/VTs Drop Byte Processing TU/VTs Access Port
Drop Signals
Destuff
Desynchronizer Receive Interface RAIL RCLKn RCOn RVTCn RDATn RPOn RVTDn RNOn RVTFn
Receive
Drop Signals
Drop Interface
Drop Pointer Tracking TU/VTs
Drop Overhead Byte Processing TU/VTs
Drop Byte Processing TU/VTs
Destuff
Desynchronizer
Select Drop Side
VT/TU Payload Memory Registers
Microprocessor Interface
RDI/REI States Channels TU/VT Build Transmit Insert Bytes Construct Pointer Generation Insert Bytes Construct Pointer Generation
States Channels
VT/TU Payload
RESET TEST HIGHZ Control
Signals
Interface
Select Drop Side Stuff Synchronizer
Data
Address Frame Pulses Frame Pulses
Transmit
Signals
Interface
Transmit Interface Stuff Synchronizer
RAIL
TCLKn TCIn TVTCn TDATn TPIn TVTDn TLOSn TNIn
Figure TEMx8 TXC-04218 Block Diagram
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TEMx8 TXC-04218
DATA SHEET
BLOCK DIAGRAM illustrated Figure TEMx8 interfaces four buses, designated Drop, Drop, Add, Add. four buses STM-1/STS-3 rate 19.44 Mbyte/s. North American applications, asynchronous signals carried floating Virtual Tributary (VT1.5) format, while signals carried floating Virtual Tributary (VT2) format. maximum VT1.5 signals carried Synchronous Transport Signal (STS-1) format. Three STS-1s turn carried STS-3 signal. ITU-T applications, asynchronous signals carried floating mode Tributary Unit (TU-12) format signals carried floating mode Tributary Unit (TU-11) format. TU-12s TU-11s carried STM-1 Virtual Container (VC-4) structure using Tributary Unit Group (TUG-3), STM-1 Virtual Container (VC-3) structure using Tributary Unit Group (TUG-2) mapping schemes. signals, combination signals, dropped from Drop Drop) lines. maximum asynchronous signals converted into TU-11/TU-12 VT1.5/VT2 format added either buses, both, depending upon mode operation. TEMx8 provide, channel basis, Virtual Container (VC-11), Virtual Container (VC-12) formats place signals Virtual Concatenation applications. format contains payload overhead bytes associated with TU-11 TU-12 formats. TEMx8 also supports cross mapping feature specified Recommendation G707. This feature enables asynchronous line signal carried TU-12/VT2 payload. This feature supported TEMx8 channel basis. When TEMx8 configured drop timing, buses are, definition, byte- multiframe-synchronous with their like-named drop buses, delayed byte times because internal processing. example, byte STM-1 Virtual Container (VC-4) structure using Tributary Unit Group (TUG-3), TU-12/VT2 added bus, time placement derived from Drop timing, from software instructions specifying which TU/VT number being added. Note that TU/VT drop selection different from selection. option provided which enables dropped timing signals sent outputs bus. When device configured timing, bus, parity, indicator signals derived from input clock, C1J1V1 signals. drop (receive) direction, Receive Drop Interface block identical Receive block. TU/VT Terminate block, Destuff block Desychronizer block repeated times, each side sides). Channel Receive Interface blocks repeated times, each channel. interface between drop receive block consists input leads: 19.44 byte clock, byte-wide data, C1J1 indicator which also carrying indication making signal C1J1V1 indicator, indicator, odd/even parity bit. Drop C1J1V1 signal used conjunction with Drop signal determine location various bytes SONET/SDH format. single pulse identifies starting location byte VC-4 format, when signal high. Three pulses provided STS-3 format, each identifying starting location byte each three STS-1 signals. TEMx8 function with either pulse C1J1V1 signal, internal detector, determining location byte. pulse location used determine location pointer bytes STM-1 VC-4 operation, C1J1V1 signal used, drop clock cycle wide pulse must occur every four frames three drop clock cycles after pulse while high. pulse identifies byte location (defined starting location VC-4) bytes. next column (first clock cycle) rows assigned fixed stuff. Similarly, next column (second clock cycle) rows assigned fixed stuff. next column (third clock cycle) defines start TUG-3 This column where pulse occurs every four frames. However, actual byte location clock cycles after pulse. STS-3 operation, three pulses must present every four frames. Each three pulses must present three clock cycles after corresponding pulse, when signal high.
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DATA SHEET
TEMx8 TXC-04218
Each drop monitored parity errors, loss clock, multiframe alignment selected, upstream SDH/SONET indication. TEMx8 monitor either order wire bytes H1/H2 bytes upstream indication. Each TU/VT Terminate block side) performs pointer processing using bytes. pointer bytes monitored loss pointer, Alarm Indication Signal (AIS), Data Flag (NDF). pointer tracking process based ETSI/ITU-T standards, which also meets ANSI requirements. Pointer increments decrements also counted, size bits monitored correct value. This block also processes monitors various alarms found four overhead bytes. These operations including signal label mismatch detection, unequipped status detection, BIP-2 parity error detection error counter, error counting, single-bit three-bit Remote Defect Indications (RDI). TEMx8 performs 16-byte trail trace comparison channels selected. 64-byte messages, bytes stored memory segment microprocessor read cycle. device also provides tandem connection feature performs 16-byte message comparison (formerly known byte message. VT/TU overhead bytes, eight overhead communications channel bits (O-bits), V1/V2 pointer bytes, byte each channel available microprocessor read cycle. Also, order wire bytes, H1/H2 pointer bytes, bytes from upstream circuitry also available microprocessor read cycle. control each port selects TU/VT from either Drop Drop bus. TU/VT destuffed Destuff block using majority logic rules three sets three justification control bits determine S-bits data bits frequency justification bits. Desynchronizer block removes effects output systemic jitter that might occur because signal mappings pointer movements network. Desynchronizer block comprised pointer leak buffer loop buffer. pointer leak buffer spaces bursts pointer movements more gradually over time accept five consecutive pointer movements. loop buffer consists digital loop filter, which designed track frequency received signal remove both transmission stuffing jitter. Channel Receive Interface block each channel provides either data, positive negative rail signal, VT/TU interface. Receive data (towards line), each channels, clocked either rising falling edges clock. addition, control provided forcing data clock signals high impedance state (tristate), zero state. (transmit) direction, TEMx8 accepts clock either data positive negative rail signals. Data, each channels, clocked either falling rising edge clock. mode, external loss clock indication external coding violations provided. rail signal, coding violations counted, there loss signal detector. DS1/E1 detector also provided. Each channel also configured VT/TU interface Virtual Concatenation data applications. When this interface selected, clock signal provided strobing data either bus. Four framing pulses also provided which define starting location VT1.5/TU-11 VT2/TU-12. option provided including four overhead bytes. However, except bits bytes, other bits ignored. Bits byte carry extended signal label information pertaining payload position within Virtual Concatenation channel. Virtual Concatenation channel will assigned VT/TUs based data bandwidth required application.
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TEMx8 TXC-04218
DATA SHEET
TU/VT Build blocks format TU/VT into STS-3 STM-1 structure asynchronous signals. pointer value carried bytes transmitted with fixed value VT1.5/TU-11 VT2/TU-12. Transmit access provided eight overhead communications channel bits (O-bits) microprocessor. microprocessor also writes signal label, value message, either 16-byte 64-byte message. TEMx8 provides tandem connection feature TU-11 TU-12, including transmission 16-byte message various alarms associated with tandem connection feature. device provides either single-bit three-bit using bytes. Local alarms, microprocessor, generate remote payload, server, connectivity defect indications. Remote Error Indication (REI) inserted from BIP-2 errors detected receive side, BIP-2 parity generated byte. Control bits provided generating unequipped status, generating TU/VT AIS, inserting BIP-2 errors byte. Control bits also provided that enable microprocessor insert overhead byte test values, including V1/V2 pointer bytes byte. Transmit block identical Transmit block. interface between Transmit block consists three input leads output leads, when timing mode selected. input leads byte clock, C1J1V1 indicator, indicator. output leads byte-wide data, parity indicator, add-to-bus indicator signal. C1J1V1 signal used conjunction with signal determine location various bytes SONET/SDH format. When drop timing selected, output leads byte-wide data, parity indicator, add-to-bus indicator. clock, C1J1V1 signals, which derived from drop bus, disabled provided. selection performed lead. Microprocessor Input/Output Interface block consists Intel- Motorola-compatible split address/data interface that provides access assigned TEMx8 memory addresses. Interrupt capability, interrupt mask bits, alarm summary bits, software polling bits also provided. alarms that cause interrupt positive, negative, both positive negative transitions. Control bits provided which enable facility line loopback. addition, PRBS analyzer generator provided. 215-1 220-1 PRBS pattern supported. analyzer generator used drop line direction additional testing flexibility. Test Access Port (TAP) block provides five-lead Boundary Scan capability that conforms IEEE 1149.1 standard. This standard provides external boundary scan functions read write external Input/Output leads from board component test. TEMx8 software driver same architecture other TranSwitch device drivers such ML3M TEMx28 software, meant easily integrated with them. application software calls driver functions configure, control manage TEMx8 device. device driver insulates application from internal details device register usage provides higher level abstraction. Particularly powerful default configurations provided within driver that allow single command bring device operational mode.
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positive/negative rail transmit interface, line signal written into FIFOs, side other side, Stuff/Synchronizer block pairs. Threshold modulation used frequency justification process. Timing information from drop buses from buses used read FIFO perform TU/VT justification process. Synchronizer block permits tracking incoming signal having average frequency offset high ppm, peak-to-peak jitter. Since TEMx8 supports different network architectures (DS1 E1), sets blocks provided each channel. TU/VT selection different. VT/TU selection different from drop VT/TU selection. control bit, transmit line alarms, also generate DS1/E1 AIS.
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DATA SHEET
Figure 1544 kbit/s Asynchronous Mapping
TEMx8 TXC-04218
VC-11 RRRRRRIR
TU-11/VT1.5 (Pointer Byte)
bytes
bytes (1544 kbit/s Data)
(Pointer Byte)
bytes bytes (1544 kbit/s Data) bytes (1544 kbit/s Data) Bytes bytes Path Overhead (V5) Byte BIP-2 BIP-2 Interleaved Parity bits) Remote Error Indication (formerly FEBE, Block Error Indication) Remote Failure Indication L1L2L3 Signal Label Remote Defect Indication (formerly FERF, Receive Failure Indication)
(FEBE)
(Action)
Information Overhead communications Justification control Justification opportunity Fixed stuff (set
bytes
(Reserved)
Bytes
(FERF)
Signal Label
Data Flag Normal 0110, 1110, 0010, 0100 0111 1001, 0001, 1101, 1011 1000 Positive Justification Invert five I-bits Negative Justification Invert five D-bits Pointer Range decimal
Size S1S2
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bytes (1544 kbit/s Data)
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TEMx8 TXC-04218
DATA SHEET
VC-12 RRRRRRRR bytes (2048 kbit/s Data) RRRRRRRR bytes (2048 kbit/s Data) RRRRRRRR (Z6) bytes (2048 kbit/s Data) RRRRRRRR (Z7) bytes (2048 kbit/s Data) RRRRRRRR Bytes Path Overhead (V5) Byte BIP-2 BIP-2 Interleaved Parity bits) Remote Error Indication (formerly FEBE, Block Error Indication) Remote Failure Indication L1L2L3 Signal Label Remote Defect Indication (formerly FERF, Receive Failure Indication)
(FEBE)
TU-12/VT2 (Pointer Byte)
bytes
(Pointer Byte)
bytes
(Action)
Information Overhead communications Justification control Justification opportunity Fixed stuff (set
bytes
(Reserved)
bytes
Bytes
(FERF)
Signal Label
Data Flag Normal 0110, 1110, 0010, 0100 0111 1001, 0001, 1101, 1011 1000 Positive Justification Invert five I-bits Negative Justification Invert five D-bits Pointer Range decimal
Size S1S2
Figure 2048 kbit/s Asynchronous Mapping
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DATA SHEET
Figure VC-11 VC-12 Cross Mapping
TEMx8 TXC-04218
VC-12 bytes (2048 kbit/s Data)
TU-12/VT2 (Pointer Byte)
bytes bytes (2048 kbit/s Data) (Pointer Byte)
N2(Z6) bytes (2048 kbit/s Data)
bytes
(Action)
K4(Z7) bytes bytes (2048 kbit/s Data) (Reserved) bytes
Bytes
When mapping VC-11 VC-12, VC-11 adapted adding fixed stuff with even parity.
Fixed stuffed with even parity G.707.
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TEMx8 TXC-04218 APPLICATION EXAMPLE
DATA SHEET
application diagram Figure below shows fully configured bidirectional add/drop fiber multiplexer. Using four-bus capability TEMx8, channels dropped from either direction with full time slot reuse both directions. Using only Drop buses provides add/drop service back network source only, eliminates block marked "East Terminal" terminal configuration.
WEST TERMINAL
STM-1 STS-3
DROP
EAST TERMINAL
PHAST-3N (TXC-06103) Drivers/Receivers
PHAST-3N (TXC-06103) Drivers/Receivers
STM-1 STS-3
DROP MICROPROCESSOR
TEMx8 TXC-04218
TEMx8 TXC-04218
channels
channels
Figure Application Using TEMx8 TXC-04218 INTEROPERABILITY TEMx8 works directly with following TranSwitch devices: QT1F-Plus (TXC-03103) T1Fx8 (TXC-03108) E1Fx8 (TXC-03109) QE1F-Plus (TXC-03114) PHAST®-3N (TXC-06103) TEMx28®-(TXC-04222) T3BwP (TXC-06826) TEPro (TXC-06830)
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DATA SHEET LEAD DIAGRAM
TEMx8 TXC-04218
DSCLK
TPI1 RCO2
TPI2
RCO3
TNI3
RPO4
TCI4 RNO5
TESTI TESTO RESET MOTO RNO1 RPO2 TNI2 TPI3 RNO4 RCO5 TCI5 RCO6 RNO7
ABUST TESTO TESTI RPO1 TNI1 TCI2 RNO3 RCO4 TNI4 TPI5 RNO6 TNI6 RPO8
ABTE TESTI TESTI TESTO VDD2 VDD1 VDD1 VDD2 VDD2 VDD1 VDD1 VDD2 VDD2 VDD1 VDD1 VDD2 TPI6 RPO7 TPI7 RCO8
VTFB15 PM1S TEST TESTO VDD2 VDD2 RCO7 TCI7 RNO8 TPI8 TNI8
AAPAR VTFA15 VTFB2 HIGHZ VDD1 VDD1 TNI7
AAC1J1 AASPE AADD VTFA2 VDD1 VDD1 TCI8
AACLK VDD2 VDD2
VDD2 VDD2 VDD1
BACLK BAPAR BADD VDD1
BASPE BAC1J1 VDD1 VDD1
VDD2 VDD2
ADCLK VDD2 VDD1 VDD2
ADPAR ADSPE VDD1
ADC1J1 BDCLK VDD1 VDD2 VDD1
BDSPE VDD2 VDD1 VDD2
BDC1J1 VDD2 VDD1 VDD2 VDD1 VDD1 VDD2 VDD2 VDD1
VDD1 VDD2
BDPAR
Note:
This bottom view. leads solder balls. Figure package information. Some signal Symbols have been abbreviated space available. Symbols shown full Lead Descriptions section.
Figure TEMx8 TXC-04218 376-Lead Plastic Ball Grid Array Package Lead Diagram
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TESTI
RCO1 TCI1 RNO2
RPO3
TCI3
TPI4
RPO5
TNI5 RPO6
TCI6
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TEMx8 TXC-04218 LEAD DESCRIPTIONS
DATA SHEET
POWER SUPPLY, GROUND CONNECTS Symbol VDD1 Lead E11, E12, E15, E16, G18, H18, L18, M18, R18, T18, V11, V12, V15, E10, E13, E14, E17, F18, J18, K18, N18, P18, U18, V10, V13, V14, A10, A13, A18, A19, A20, A22, AB1, AB22, B11, B14, B16, B17, B20, B21, B22, C10, C11, C12, C14, C15, C18, C19, C20, D10, D12, D13, D14, D17, D19, D21, D22, E18, E20, F20, F22, G19, G21, H19, H21, H22, J9-J14, J20, K9-K14, K20, K21, L19, L22, L9-L14, M9-M14, M21, M22, N9-N14, N20, N21, P9-P14, P22, R21, R22, T22, V18, W19, A11, A12, A14, A15, A16, A17, A21, AA4, AB3, B10, B12, B13, B15, B18, B19, C13, C16, C17, C21, C22, D11, D15, D16, D18, D20, E19, E21, E22, F19, F21, G20, G22, H20, J19, J21, J22, K19, K22, L20, L21, M19, M20, N19, N22, P19, P20, P21, R20, T21, I/O/P Name/Function VDD1: +1.8 volt supply voltage, ±5%.
VDD2
VDD2: +3.3 volt supply voltage, ±5%. This supply voltage should powered prior (VDD1) supply voltage same time. This supply voltage must below VDD1 more than time including power down. Ground: volt reference.
Connect: leads connected, even another lead, must left floating. Connection these leads impair performance cause damage device.
*Note: Input; Output; Power; T=Tristate *See Input, Output Input/Output Parameters section below Type definitions.
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DATA SHEET
DROP Symbol ADCLK Lead I/O/P Type TTL3V Name/Function
TEMx8 TXC-04218
ADPAR
TTL3V
Drop Parity Bit: parity input signal representing even parity calculation each data byte, SPE, C1J1V1 signal from drop bus, data byte only. Drop Data Byte: Byte-wide data that corresponds STM-1/STS-3 signal drop bus. first received (dropped) corresponds which lead Drop Indicator: signal that active high each byte STM-1 VC-4 STS-3/STS-1 SPEs, overhead byte times. Drop C1J1V1 Indications: active high timing signal that carries STM-1/STS-3 frame information. This signal works conjunction with ADSPE signal. pulse identifies location first byte STM-1 STS-3 signals, when ADSPE signal low. pulse identifies starting location byte STM-1 VC-4 signal when ADSPE high. Three pulses identify starting location each three STS-1 signals STS-3 signal. single pulse identifies location V1/V2 bytes TUG-3 within VC-4. Three pulses identify location V1/V2 bytes within each three STS-1s. pulses absent. which case mapper will detect starting location multiframe within byte.
AD(7-0)
TTL3V
ADSPE
TTL3V
ADC1J1(V1)
TTL3V
AACLK
I/O(T)
TTL3V/ Clock: When timing mode selected (lead CMOS3V ABUST low), this input must provided timing. This clock operates 19.44 STM-1/STS-3 operation. indication (AASPE), C1J1V1 indication (AAC1J1V1) clocked falling edges this clock. byte-wide data (AA7-AA0), indicator (AADD), parity (AAPAR) clocked rising edges clock during time slots that correspond selected TU/VT. When drop timing selected (lead ABUST high), lead ABTE low, this clock, which derived from like-named drop output. When lead ABTE high drop timing mode, this lead disabled.
AAPAR
O(T) CMOS3V Parity Bit: even parity output signal that calculated over byte-wide data. When drop timing selected (lead ABUST high), lead ABTE low, parity also calculated C1J1V1 signals. This lead only active when there data being added bus.
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Drop Clock: This clock operates 19.44 STM-1/STS-3 operation. Drop byte-wide data (AD7-AD0), parity (ADPAR), indication (ADSPE), C1J1V1 indication (ADC1J1V1) clocked falling edges this clock. This clock also used timing deriving like-named byte-wide data, TU/VT indications, parity bits.
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TEMx8 TXC-04218
DATA SHEET
Symbol AA(7-0)
Lead I/O/P
Type
Name/Function
O(T) CMOS3V Data Byte: Byte-wide data that corresponds selected TU/VT. first transmitted (added) corresponds which lead I/O(T) TTL3V/ Indicator: When timing mode CMOS3V selected, this signal must provided timing. This signal must high during each byte STM-1/STS-3 payload, during Transport Overhead byte times. When drop timing selected (lead ABUST high), lead ABTE low, this signal, which derived from like-named drop output. When lead ABTE high drop timing mode, this lead disabled. TTL3V/ C1J1V1 Indications: active high timing signal that CMOS3V carries STM-1/STS-3 frame information. This signal works conjunction with AASPE signal. pulse identifies location first byte STM-1 STS-3 signals, when AASPE signal low. pulse identifies starting location byte STM-1 VC-4 signal when ADSPE high. Three pulses identify starting location each three STS-1 signals STS-3 signal. single pulse identifies starting location V1/V2 bytes TUG-3 within VC-4. Three pulses identify starting location V1/V2 bytes within each three STS-1s. When drop timing selected (lead ABUST high), lead ABTE low, this signal, which derived from like-named drop output. When lead ABTE high drop timing mode, this lead disabled. CMOS3V Data Present Indicator: This normally active signal present when output data valid. identifies location TU/VT time slots being selected. When control ADDI (bit register 03AH) indicator active high instead active low.
AASPE
AAC1J1(V1)
I/O(T)
AADD
DROP Symbol BDCLK Lead I/O/P Type TTL3V Name/Function Drop Clock: This clock operates 19.44 STM-1/STS-3 operation. Drop byte-wide data (BD7-BD0), parity (BDPAR), indication (BDSPE), C1J1V1 indication (BADC1J1V1) clocked falling edges this clock. This clock also used timing deriving like-named byte-wide data, TU/VT indications, parity bits. Drop Parity Bit: parity input signal representing even parity calculation each data byte, SPE, C1J1V1 signal from drop bus, data byte only. Drop Data Byte: Byte-wide data that corresponds STM-1/STS-3 signal drop bus. first received (dropped) corresponds which lead
BDPAR
TTL3V
BD(7-0)
TTL3V
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TEMx8 TXC-04218
Symbol BDSPE
Lead
I/O/P
Type TTL3V
Name/Function Drop Indicator: signal that active high each byte STM-1 VC-4 STS-3/STS-1 SPEs, overhead byte times. Drop C1J1V1 Indications: active high timing signal that carries STM-1/STS-3 frame information. This signal works conjunction with BDSPE signal. pulse identifies location first byte STM-1 STS-3 signals, when BDSPE signal low. pulse identifies starting location byte STM-1 VC-4 signal when BDSPE high. Three pulses identify starting location each three STS-1 signals STS-3 signal. single pulse identifies location V1/V2 bytes TUG-3 within VC-4. Three pulses identify location V1/V2 bytes within each three STS-1s. pulses absent. which case mapper will detect starting location multiframe within byte.
BDC1J1(V1)
TTL3V
BACLK
I/O(T) TTL3V/ Clock: When timing mode selected (lead CMOS3V ABUST low), this input must provided timing. This clock operates 19.44 STM-1/STS-3 operation. indication (BASPE), C1J1V1 indication (BAC1J1V1) clocked falling edges this clock. byte-wide data (BA7-BA0), indicator (BADD), parity (BAPAR) clocked rising edges clock during time slots that correspond selected TU/VT. When drop timing selected (lead ABUST high), lead ABTE low, this clock, which derived from like-named drop output. When lead ABTE high drop timing mode, this lead disabled forced high impedance state. O(T) CMOS3V Parity Bit: even parity output signal that calculated over byte-wide data. When drop timing selected (lead ABUST high), lead ABTE low, parity also calculated C1J1V1 signals. This lead only active when there data being added bus.
BAPAR
BA(7-0)
O(T) CMOS3V Data Byte: Byte-wide data that corresponds selected TU/VT. first transmitted (added) corresponds which lead I/O(T) TTL3V/ Indicator: When timing mode CMOS3V selected, this signal must provided timing. This signal must high during each byte STM-1/STS-3 payload, during Transport Overhead byte times. When drop timing selected (lead ABUST high), lead ABTE low, this signal, which derived from like-named drop output. When lead ABTE high drop timing mode, this lead disabled forced high impedance state.
BASPE
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TEMx8 TXC-04218
DATA SHEET
Symbol
BAC1J1(V1)
Lead
I/O/P
Type
Name/Function
BADD
CMOS3V Data Present Indicator: This normally active signal present when output data valid. identifies location TU/VT time slots being selected. When control ADDI (bit register 03AH) indicator active high instead active low.
CHANNEL LINE INTERFACE Symbol RCOn RCLKn RVTCn (n=1-8) Lead AA13, AB15, AB17, W16, Y18, Y21, U19, I/O/P O(T) Type Name/Function
CMOS3V Receive Channel Rail, NRZ, TU/VT Output Clock: DS1, VT/TU clock output. Data (Rail NRZ) clocked positive transitions this clock when control RnCLKI (bit register X+000H) When control RnCLKI data clocked negative transitions this clock. RCOn E1/T1 rail clock (control bits RnLINT1/0 (bits 7/6, register X+006H) 10). RCLKn clock (control bits RnLINT1/0 01). RVTCn TU/VT clock (control bits RnLINT1/0 11). This lead disabled when control bits RnLINT1/0 When disabled, this lead forced ether high impedance state (control RnOUTL (bit register 006H) zeros (control RnOUTL Lead AA13 RCO1/RCLK1/RVTC1 (Channel Note: Description control RnOUTL detailed operation. CMOS3V Receive Channel Data Positive Rail, NRZ, TU/VT: When control bits RnLINT1/0 positive rail E1/T1 data (RPOn) provided this lead. When control RnLINT1/0 E1/T1 data (RDATn) provided this lead. When control bits RnLINT1/0 VT/TU data (RVTDn) provided this lead. This lead disabled when control bits RnLINT1/0 When disabled, this lead forced ether high impedance state (control RnOUTL zeros (control RnOUTL Lead RPO1/RDAT1/RVTD1 (Channel Note: Description control RnOUTL detailed operation.
RPOn RDATn RVTDn (n=1-8)
W12, Y14, AA16, AB19, AA19, AA21, V20,
O(T)
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I/O(T) TTL3V/ C1J1V1 Indications: active high timing signal that CMOS3V carries STM-1/STS-3 frame information. This signal works conjunction with AASPE signal. pulse identifies location first byte STM-1 STS-3 signals, when AASPE signal low. pulse identifies starting location byte STM-1 VC-4 signal when ADSPE high. Three pulses identify starting location each three STS-1 signals STS-3 signal. single pulse identifies starting location V1/V2 bytes TUG-3 within VC-4. Three pulses identify starting location V1/V2 bytes within each three STS-1s. When drop timing selected (lead ABUST high), lead ABTE low, this signal, which derived from like-named drop output. When lead ABTE high drop timing mode, this lead disabled forced high impedance state.
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DATA SHEET
TEMx8 TXC-04218
Symbol RNOn RVTFn (n=1-8)
Lead Y13, AA15, W15, Y17, AB21, W20, Y22,
I/O/P O(T)
Type
Name/Function
TCIn TCLKn TVTCn (n=1-8)
AA14, W14, AA17, AB20, Y19, AA22, U20,
I/O(T)
TTL3V/ Transmit Channel Rail, Input Clock, VT/TU Output CMOS3V Clock: clock input when Rail interface selected VT/TU clock output when VT/TU interface selected. TCIn E1/T1 rail clock (control bits TnLINT1/0 (bits 7/6, register X+002H) 10). TCLKn E1/T1 clock (control bits TnLINT1/0 01). TVTCn VT/TU clock output (control bits TnLINT1/0 11). Rail (TPIn/TNIn), (TDATn/TLOSn) VT/TU data (TVTDn) clocked negative transitions this clock when control TnCLKI (bit register X+002H) When control TnCLKI data clocked positive transitions this clock. Lead AA14 TCI1/TCLK1/TVTC1 (Channel TTL3V Transmit Channel Data Positive Rail, NRZ, VT/TU: When control bits TnLINT1/0 positive rail E1/T1 data (TPIn) clocked this lead. When control TnLINT1/0 E1/T1 data (TDATn) clocked this lead. When control bits TnLINT1/0 VT/TU data (TVTDn) clocked this lead. Lead AB14 TPI1/TDAT1/TVTD1 (Channel TTL3V Transmit Channel Data Negative Rail, External Loss Signal, Coding Violations: When control bits TnLINT1/0 negative rail E1/T1 data (TNIn) clocked this lead. When control bits TnLINT1/0 external loss signal (when control EXnLOS (bit register X+003H) clocked this lead. When control EXnLOS external coding violations clocked this lead. Lead TNI1/TLOS1.
TPIn TDATn TVTDn (n=1-8)
AB14, AB16, Y16, AA18, W18, V19, V21,
TNln/ TLOSn (n=1-8)
W13, Y15, AB18, W17, AA20, W21, T19,
CONTROLS, EXTERNAL CLOCK, FRAMING PULSES TEST LEADS Symbol Lead I/O/P TEST Type Name/Function
TTL3Vp TranSwitch Test Lead: This lead used TranSwitch testing must remain active high mapper function. This lead pulled high internal pull-up VDD2. must left floating held high.
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CMOS3V Receive Channel Data Negative Rail, TU/VT Framing Pulse: When control bits RnLINT1/0 negative rail E1/T1 data (RNOn) provided this lead. When control bits RnLINT1/0 VT/TU framing pulse (RVTFn) provided this lead. This lead disabled when control bits RnLINT1/0 When disabled, this lead forced ether high impedance state (control RnOUTL zeros (control RnOUTL Lead RNO1/RVTF1 (Channel Note: Description control RnOUTL detailed operation. Output will forced during normal operation while mode.
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TEMx8 TXC-04218
DATA SHEET
Symbol Lead I/O/P DSCLK AB12
Type TTL3V
Name/Function Desynchronizer Reference Clock: This clock used desynchronizer operation other internal functions, such generating receive signal. clock frequency must 68.68 (+/- over life) clock duty cycle must 10)%.
RESET
HIGHZ
TTL3Vp High Impedance Select: forces output leads, except boundary scan lead TDO, high impedance state testing purposes. This lead pulled high internal pull-up VDD2. TTL3V Second Performance Clock Input. This clock input used second shadow counters, (Performance Monitoring)/FM (Fault Monitoring) alarm registers. This clock should clock, with minimum high time. When this lead held low, PM/FM alarm shadow counter features disabled. This clock required write Leak Registers X+017H X+018H.
PM1S
ABTE
TTL3Vp Timing Output Signals enable: active enables like-named drop clock, C1J1V1 signals provided output signals when drop timing mode selected (lead ABUST high). When high, clock, C1J1V1, signals disabled outputs buses when drop timing mode selected. This lead pulled high internal pull-up VDD2. CMOS3V Transmit VT1.5 Framing Pulse. Positive clock cycle pulse that used when VT/TU line interface selected channel. pulse determines start VT1.5/TU-11 multiframe transmit direction pulse occurs even when VT/TU line interface selected long active). pulse clocked rising edge TVTCn clock when control TnCLKI (bit register X+002H) CMOS3V Transmit Framing Pulse. Positive clock cycle pulse that used when VT/TU line interface selected channel. pulse determines start VT2/TU-12 multiframe transmit direction pulse occurs even when VT/TU line interface selected long active). pulse clocked rising edge TVTCn clock when control TnCLKI (bit register X+002H) CMOS3V Transmit VT1.5 Framing Pulse. Positive clock cycle pulse that used when VT/TU line interface selected channel. pulse determines start VT1.5/TU-11 multiframe transmit direction pulse occurs even when VT/TU line interface selected long active). pulse clocked rising edge TVTCn clock when control TnCLKI (bit register X+002H)
VTFA15
VTFA2
VTFB15
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TTL3Vp Hardware Reset: When active pulse applied this lead minimum duration nanoseconds after power applied, this pulse clears performance counters alarms, resets control bits, initializes internal FIFOs. This action takes approximately microseconds. Status RESETD (bit register 059H) when reset complete. This lead pulled high internal pull-up VDD2.
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DATA SHEET
TEMx8 TXC-04218
Symbol Lead I/O/P VTFB2
Type
Name/Function
CMOS3V Transmit Framing Pulse. Positive clock cycle pulse that used when VT/TU line interface selected channel. pulse determines start VT2/TU-12 multiframes transmit direction pulse occurs even when VT/TU line interface selected long active). pulse clocked rising edge TVTCn clock when control TnCLKI (bit register X+002H) TTL3Vp Timing Select: selects timing mode. this timing mode, drop timing signals independent each other. high selects drop timing mode. this timing mode, signals (Add clock, C1J1V1 signals) derived from like-named drop bus. Note: timing mode must selected when channels assigned VT/TU interface. addition, pulses must fixed regarding their locations. This restriction required, because TEMx8 provides downstream circuitry with timing information. This lead pulled high internal pull-up VDD2.
ABUST
MICROPROCESSOR INTERFACE SELECTION Symbol MOTO Lead I/O/P Type MOTO Name/Function Action Intel interface Motorola interface
TTL3V Motorola Mode: following table lists selection options.
MICROPROCESSOR INTERFACE SPLIT MOTOROLA INTEL Symbol A(14-0) Lead AB6, AA7, AB7, AA8, AB8, W10, AA9, AB9, Y10, AA10, W11, AB10 AA5, AB4, AB5, AA6, I/O/P Type TTL3V Name/Function Address (Motorola/Intel Buses): These address line inputs used accessing memory locations read/write cycle. (lead AB6) most significant bit.
D(7-0)
I/O(T)
TTL3V/ Data (Motorola/Intel Buses): Bidirectional data lines used CMOS3V transferring data from memory location. (lead AA5) most significant bit. TTL3V Select: active enables data transfers between microprocessor memory location during read/write cycle.
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TEMx8 TXC-04218
DATA SHEET
Symbol RD/WR
Lead AA11
I/O/P
Type TTL3V
Name/Function Read mode) Read/Write mode): Intel Mode active signal generated microprocessor reading memory locations. Motorola Mode active high signal generated microprocessor reading memory locations. active signal used write memory locations. Write mode) Device Select mode): Intel Mode active signal generated microprocessor writing memory locations. Motorola Mode inputs logically OR-gated inside device, generating internal active select signal (CS) that similar SEL. This internal signal used enable data transfer. This lead used interface with Motorola 68302 microprocessor. this lead used, should tied ground.
AB11
TTL3V
DTACK
AB13
O(T)
CMOS3V Ready mode) Data Transfer Acknowledge mode): Intel Mode high acknowledgment from addressed memory location that transfer completed. indicates that Mapper cannot complete transfer cycle, that microprocessor wait states must generated. Motorola Mode During read cycle, signal indicates that information data valid. During write cycle, signal acknowledges acceptance data. CMOS3V Interrupt: high this output lead signals interrupt request microprocessor, required Intel compatibility microprocessors. Motorola operation, signals interrupt request microprocessor. Please note: will take approximately microseconds before interrupt asserted after last enabling mask interrupt asserted immediately when gating event latched alarm.
INT/
AA12
BOUNDARY SCAN INTERFACE Symbol Lead I/O/P Type TTL3V Name/Function IEEE 1149.1 Test Port Serial Scan Clock: This signal used shift data into rising edge, falling edge. maximum clock frequency MHz.
TTL3Vp IEEE 1149.1 Test Port Mode Select: sampled rising edge TCK, used place Test Access Port controller into various states defined IEEE 1149.1. This lead high internally internal pull-up VDD2 normal operation. TTL3Vp IEEE 1149.1 Test Port Serial Scan Data Serial test instructions data clocked into this lead rising edge TCK. This input internal pull-up VDD2.
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DATA SHEET
TEMx8 TXC-04218
Symbol Lead
I/O/P O(T)
Type
Name/Function
CMOS3V IEEE 1149.1 Test Port Serial Scan Data Out: Serial test instruc4mA tions data clocked this lead falling edge TCK. When inactive, this 3-state output will into high impedance state. TTL3Vp IEEE 1149.1 Test Port Reset Lead: This lead will asynchronously reset Test Access Port (TAP) controller. This lead must held low, asserted pulsed (for minimum duration reset controller TEMx8 power-up. This input internal pull-up VDD2. Failure perform controller reset cause controller take control some TEMx8 output leads.
TRANSWITCH TEST LEADS Symbol Lead TESTI I/O/P Type Name/Function
TTL3Vd TranSwitch Test Input Leads: TranSwitch testing purposes only. These leads have internal pull down should held low. CMOS3V TranSwitch Test Output Leads: TranSwitch testing purposes only. These leads should left open (floating).
TESTO
O(T)
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TEMx8 TXC-04218
DATA SHEET
ABSOLUTE MAXIMUM RATINGS ENVIRONMENTAL LIMITATIONS
Parameter Core Supply Voltage, +1.8V nominal Supply Voltage, +3.3V nominal input voltage Storage temperature range Ambient operating temperature Moisture Exposure Level Relative humidity, during assembly Relative humidity, in-circuit Classification Latch-up Symbol VDD1 VDD2 -0.3 -0.3 -0.5 Unit Level Conditions Notes Notes
Note ft/min. linear airflow EIA/JEDEC JESD22-A112-A Note non-condensing Note Meets JEDEC STD-78
absolute value 2000
Notes: Conditions exceeding values cause permanent failure. Exposure conditions near values extended periods impair device reliability. Pre-assembly storage non-drypack conditions recommended. Please refer instructions "CAUTION" label drypack which devices supplied. Test method MIL-STD-883E, Method 3015.7. Device core 1.8V only.
THERMAL CHARACTERISTICS
Parameter Thermal resistance junction ambient Unit
Test Conditions ft/min linear airflow
POWER REQUIREMENTS
Parameter VDD2 IDD2 PDD2 VDD1 IDD1 PDD1
Notes: Typical values based measurements made with nominal voltages Maximum values based measurements made maximum voltages channels configured being added dropped Dual Protection Ring Mode.
3.15
3.45 1.89
Unit
Test Conditions Notes Notes Notes Notes
1.71
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Notes
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DATA SHEET INPUT, OUTPUT INPUT/OUTPUT PARAMETERS
INPUT PARAMETERS TTL3V VOLT TOLERANT) Parameter Input leakage current Input capacitance Unit
TEMx8 TXC-04218
Test Conditions 3.15 VDD2 3.45 VDD2 3.45
INPUT PARAMETERS TTL3Vp VOLT TOLERANT, PULL-UP RESISTOR) Parameter Input current Input leakage current Input capacitance Unit Test Conditions 3.15 VDD2 3.45 3.15 VDD2 3.45 VDD2 VDD2 =3.45; Input volts
INPUT PARAMETERS TTL3Vd VOLT TOLERANT, PULL-DOWN RESISTOR) Parameter Input current Input leakage current Input capacitance Unit Test Conditions 3.15 VDD2 3.45 3.15 VDD2 3.45 VDD2 3.45; Input 3.45 volts
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3.15 VDD2 3.45
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TEMx8 TXC-04218
DATA SHEET
OUTPUT PARAMETERS CMOS3V Parameter tRISE tFALL Leakage tristate Output capacitance -6.4 Unit Test Conditions VDD2 3.15; -4.0 VDD2 3.15; VOL=0.4 VOH=2.4 CLOAD CLOAD input
OUTPUT PARAMETERS CMOS3V Parameter Output capacitance tRISE tFALL Leakage tristate input -12.8 Unit VDD2 3.15; -8.0 VDD2 3.15; Test Conditions
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INPUT/OUTPUT PARAMETERS TTL3VP INPUT CMOS3V OUTPUT VOLT TOLERANT Input) Parameter Input leakage current Input capacitance tRISE tFALL -4.0 -0.5 CLOAD CLOAD Unit
TEMx8 TXC-04218
Test Conditions 3.15 VDD2 3.45 3.15 VDD2 3.45 input VDD2 3.15; -4.0 VDD2 3.15;
INPUT/OUTPUT PARAMETERS TTL3V INPUT CMOS3V OUTPUT VOLT TOLERANT Input) Parameter Input leakage current Input capacitance tRISE tFALL -8.0 CLOAD CLOAD VDD2 3.15; -8.0 VDD2 3.15; Unit Test Conditions 3.15 VDD2 3.45 3.15 VDD2 3.45 input; Note
Note: leakage current from VDD2. most pronounced
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TEMx8 TXC-04218 TIMING CHARACTERISTICS
DATA SHEET
Figure Channels DS1/E1 Transmit Rail Interface Timing
tCYC tPWL TCIn (Input) TPIn/TNIn (Input)
Note:
tPWH
Notes: TCIn shown TnCLKI where data clocked falling edges channel Data clocked rising edges when TnCLKI
Interface Parameter TCIn Clock period TCIn clock time TCIn clock high time TPIn/TNIn data setup time before TCIn TPIn/TNIn data hold time after TCIn Interface Parameter TCIn Clock period TCIn clock time TCIn clock high time TPIn/TNIn data setup time before TCIn TPIn/TNIn data hold time after TCIn Symbol tCYC tPWL tPWH 435.0 488.28 Unit Symbol tCYC tPWL tPWH 580.0 647.7 Unit
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Detailed timing diagrams TEMx8 device illustrated following Figures with values timing intervals tabulated below waveform diagrams. tristate condition signal waveform shown midway between high low. timing parameters measured voltage levels (VIH VIL)/2 input signals (VOH VOL)/2 output signals, unless otherwise indicated. Where waveform diagram describes both signals, their symbols combined labeling waveform (e.g., A/BADD AADD BADD).
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DATA SHEET
Figure Channels DS1/E1 Transmit Interface Timing
tCYC tPWL TCLKn (Input) tPWH
TEMx8 TXC-04218
TDATn (Input)
tSU(2) TLOSn (Input)
tH(2)
Notes: TCLKn shown TnCLKI where data clocked falling edges channel Data clocked rising edges when TnCLKI Negative Rail lead used input external loss signal indication when control EXnLOS loss-of-signal indication must present minimum TCLKn cycles. When control EXnLOS external coding violations clocked When control EXnLOSP external loss-of-signal. Code violations counted when TLOSn high TCLKn edge occurs TnCLKI selection (see Note above).
Interface Parameter TCLKn clock period TCLKn clock time TCLKn clock high time TDATn data setup time before TCLKn TDATn data hold time after TCLKn TLOSn data setup time before TCLKn TLOSn data hold time after TCLKn Interface Parameter TCLKn clock period TCLkn clock time TCLKn clock high time TDATn data setup time before TCLKn TDATn data hold time after TCLKn TLOSn data setup time before TCLKn TLOSn data hold time after TCLKn Symbol tCYC tPWL tPWH tSU(1) tH(1) tSU(2) tH(2) 435.0 488.28 Unit Symbol tCYC tPWL tPWH tSU(1) tH(1) tSU(2) tH(2) 580.0 647.7 Unit
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tSU(1)
tH(1)
Note:
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TEMx8 TXC-04218
DATA SHEET
Figure Channels Transmit VT/TU Interface Timing -Gapped Pointer Bytes
TVTCn (Output) VTFA15 VTFA2 VTFB15 VTFB2 (Outputs) Byte tpw(1)
TVTDn (Input) tCYC tPWH TVTCn (Output) tD(1) VTFA15 VTFA2 VTFB15 VTFB2 (Outputs) TVTDn (Input) tPW(2) tPWL
Note:
Last multi-frame
Notes:- TVTCn shown TnCLKI data with falling edge Frame pulse with rising edge. Clock gaps present during time pointer bytes V1-V4. When TnCLKI timing similar Figure
INTERFACE
Parameter TVTCn clock period TVTCn clock time TVTCn clock high time TVTCn Clock frequency (nominal) TVTDn data setup time before TVTCn TVTDn data hold time after TVTCn VTFA/B15 delay from TVTCn Multiframe Time VTFA/B15 pulse width tD(1) tPW(1) tPW(2) 565.84 875.0 Symbol tCYC tPWL tPWH 565.84 257.20 257.20 1.664 5401.20 5144.0 5144.0 Unit
INTERFACE
Parameter TVTCn clock period TVTCn clock time TVTCn clock high time TVTCn clock frequency (nominal) TVTDn data setup time before TVTCn TVTDn data hold time after TVTCn VTFA/B2 delay from TVTCn Multiframe Time VTFA/B2 pulse width tD(1) tPW(1) tPW(2) 462.96 Symbol tCYC tPWL tPWH 411.52 205.76 205.76 2.240 4166.64 3960.88 3960.88 Unit
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TEMx8 TXC-04218
Figure Channels Transmit VT/TU Interface Timing-Gapped Pointer Byte
TVTCn (Output) VTFA15 VTFA2 VTFB15 VTFB2 (Outputs) bytes tpw(1)
TVTDn (Input) tCYC tPWL TVTCn (Output) tD(1) VTFA15 VTFA2 VTFB15 VTFB2 (Outputs) TVTDn (Input) tPW(2) tPWH
Note:
Last multiframe
Notes: TVTCn shown TnCLKI data with rising edge Frame pulse with falling edge. Clock gaps present during time pointer bytes (V1-V4) overhead bytes (V5, N2/Z6, K4/Z7), contiguous. When TnCLKI timing similar Figure
INTERFACE
Parameter TVTCn clock period TVTCn clock time TVTCn clock high time TVTCn clock frequency (nominal) TVTDn data setup time before TVTCn TVTDn data hold time after TVTCn VTFA/B15 delay from TVTCn Multiframe Time VTFA/B15 pulse width tSU(2) tPW(1) tPW(2) Symbol tCYC tPWL tPWH tSU(2) tPW(1) tPW(2) 565.84 411.52 205.76 205.76 2.176 462.96 875.0 7561.68 7355.92 7355.92 Symbol tCYC tPWL tPWH 565.84 257.20 257.20 1.600 9927.92 9670.72 9670.72 Unit Unit
INTERFACE
Parameter TVTCn clock period TVTCn clock time TVTCn clock high time TVTCn clock frequency (nominal) TVTDn data setup time before TVTCn TVTDn data hold time after TVTCn VTFA/B2 delay from TVTCn Multiframe Time VTFA/B2 pulse width
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Figure Channels DS1/E1 Receive Rail Timing
tCYC RCOn (Output) tPWL tPWH
RPOn/RNOn (Output)
Note:
Note: RCOn shown RnCLKI=0, where data clocked falling edges. Data clocked rising edges when RnCLKI=1.
Interface Parameter RCOn clock period RCOn clock time RCOn clock high time RPOn/RNOn data delay after RCOn Interface Parameter RCOn clock period RCOn clock time RCOn clock high time RPOn/RNOn data delay after RCOn Symbol tCYC tPWL tPWH -5.0 Unit Symbol tCYC tPWL tPWH -5.0 Unit
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Figure Channels DS1/E1 Receive Timing
TEMx8 TXC-04218
tCYC RCLKn (Output) tPWL tPWH
RDATn (Output)
Note:
Note: RCOn shown RnCLKI=0, where data clocked falling edges. Data clocked rising edges when RnCLKI=1.
Interface Parameter RCLKn clock period RCLKn clock time RCLKn clock high time RDATn data delay after RCLKn Interface Parameter RCLKn clock period RCLKn clock time RCLKn clock high time RDATn data delay after RCLKn Symbol tCYC tPWL tPWH -5.0 Unit Symbol tCYC tPWL tPWH -5.0 Unit
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Figure Channels Receive VT/TU Interface Timing -Gapped Pointer Bytes
RVTCn (Output) byte tpw(1) RVTFn (Outputs)
RVTDn (Output) tCYC tPWL RVTCn (Output) tD(1) RVTFn (Output)
Last multiframe
tPWH
tPW(2)
Note:
tD(2)
RTVDn (Output)
Notes: RVTCn shown RnCLKI data Frame pulse with falling edge. Clock gaps present during time pointer bytes V1-V4. When RnCLKI timing similar Figure
INTERFACE
Parameter RVTCn clock period RVTCn clock time RVTCn clock high time RVTCn clock frequency (nominal) RVTFn delay after RVTCn RVTDn delay after RVTCn Multiframe Time RVTFn pulse width tD(1) tD(2) tPW(1) tPW(2) 13.1 14.0 567.8 Symbol tCYC tPWL tPWH 553.3 291.2 262.1 1.664 14.5 14.5 5080.0 4804.0 276.6 Unit
INTERFACE
Parameter RVTCn clock period RVTCn clock time RVTCn clock high time RVTCn clock frequency (nominal) RVTFn delay after RVTCn RVTDn delay after RVTCn Multiframe Time RVTFn pulse width tD(1) tD(2) tPW(1) tPW(2) 13.1 14.0 422.2 Symbol tCYC tPWL tPWH 422.2 233.0 189.3 2.240 14.5 14.5 4000.0 3811.0 189.3 Unit
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TEMx8 TXC-04218
Figure Channels Receive VT/TU Interface Timing-Gapped Pointer Byte
RVTCn (Output) bytes tpw(1) RVTF15 (Outputs)
RVTDn (Output) tCYC tPWH RVTCn (Output) tD(1) RVTFn (Output)
Last multiframe
tPWL
tPW(2)
Note:
tD(2)
RVTDn (Output)
Notes: RVTCn shown RnCLKI data Frame pulse with Rising Edge. Clock gaps present during time pointer bytes (V1-V4) overhead bytes (V5, N2/Z6, K4/Z7), contiguous. When RnCLKI timing similar Figure
INTERFACE
Parameter RVTCn clock period RVTCn clock time RVTCn clock high time RVTCn clock frequency (nominal) RVTFn delay after RVTCn RVTDn delay after RVTCn Multiframe Time RVTFn pulse width tD(1) tD(2) tPW(1) tPW(2) 13.1 14.0 567.8 Symbol tCYC tPWL tPWH 553.3 291.2 262.1 1.600 14.5 14.5 9930.1 9668.0 276.6 Unit
INTERFACE
Parameter RVTCn clock period RVTCn clock time RVTCn clock high time RVTCn clock frequency (nominal) RVTFn delay after RVTCn RVTDn delay after RVTCn Multiframe Time RVTFn pulse width tD(1) tD(2) tPW(1) tPW(2) 13.1 14.0 422.2 Symbol tCYC tPWL tPWH 422.2 233.0 189.3 2.176 14.5 14.5 7425.7 7236.4 189.3 Unit
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DATA SHEET
Figure STS-3 Drop Signals, Timing Derived from Drop (lead ABTE low)
tCYC A/BDCLK (Input) A/BD(7-0) A/BDPAR (Input) A/BDSPE (Input) A/BDC1J1V1 (Input) A/BACLK (Output) tOD(2) A/BAC1J1V1 (Output) A/BASPE (Output) A/BA(7-0) A/BAPAR (Output) A/BADD (Output)
C1(1) STS-1 STS-1 STS-1
tPWH
tSU(1)
C1(1)
tH(1)
C1(2) C1(3) Data
TU/VT Selected Byte STS-1
STS-1
STS-1
Data STS-1
tSU(3)
C1(1)
tH(3)
STS-1
Occurs every four frames when provided place byte STS-1 STS-1 STS-1
tOD(1)
tOD(3)
tOD(4)
TU/VT Selected
tOD(5)
Note: single TU/VT (number 21/28 STS-1 number shown illustration purposes. outputs delayed additional clock cycle from their respective drop timing inputs when control ABOD (bit 03BH) written with
Parameter A/BDCLK clock period A/BDCLK duty cycle tPWH/tCYC A/BD(7-0)/A/BDPAR data /parity setup time before A/BDCLK A/BD(7-0)/A/BDPAR data /parity hold time after A/BDCLK A/BDSPE setup time before A/BDCLK A/BDSPE hold time after A/BDCLK A/BDC1J1V1 setup time before A/BDCLK A/BDC1J1V1 hold time after A/BDCLK A/BACLK delay from A/BDCLK A/BAC1J1V1 delay from A/BACLK A/BASPE delay from A/BCLK A/B(7-0) A/BAPAR data /parity valid delay from A/BACLK A/BADD delay from A/BACLK
Note: output times measured with load capacitance.
Symbol tCYC
51.44
Unit
tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3) tOD(1) tOD(2) tOD(3) tOD(4) tOD(5)
-2.0 -2.0 -2.0 -2.0 12.0 10.0
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tSU(2)
tH(2)
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TEMx8 TXC-04218
Figure STS-3 Drop Signals, Timing Derived from Drop (lead ABTE high)
tCYC A/BDCLK (Input) A/BD(7-0) A/BDPAR (Input) A/BDSPE (Input) A/BDC1J1V1 (Input) A/BA(7-0) A/BAPAR (Output) A/BADD (Output)
tSU(3)
C1(1)
tPWH
tSU(1)
C1(1)
tH(1)
C1(2) C1(3) Data
TU/VT Selected Byte STS-1
STS-1
STS-1
Data STS-1
tH(3)
STS-1
Occurs every four frames when provided place byte STS-1 STS-1 STS-1
tOD(1) tOD(3)
TU/VT Selected
tOD(2)
tOD(4)
Note: single TU/VT (number 21/28 STS-1 number shown illustration purposes. outputs delayed additional clock cycle from their respective drop timing inputs when control ABOD (bit 03BH) written with
Parameter A/BDCLK clock period A/BDCLK duty cycle tPWH/tCYC A/BD(7-0)/A/BDPAR data /parity setup time before A/BDCLK A/BD(7-0)/A/BDPAR data /parity hold time after A/BDCLK A/BDSPE setup time before A/BDCLK A/BDSPE hold time after A/BDCLK A/BDC1J1V1 setup time before A/BDCLK A/BDC1J1V1 hold time after A/BDCLK A/BA(7-0)/A/BAPAR data /parity valid delay from A/BDCLK A/BA(7-0)/A/BAPAR data /parity tristate delay from A/BDCLK A/BADD indicator delay from A/BDCLK A/BA(7-0)/A/BAPAR data /parity tristate driven delay from A/BDCLK
Note: output times measured with load capacitance.
Symbol tCYC
51.44
Unit
tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3) tOD(1) tOD(2) tOD(4) tOD(3)
21.0 15.0 18.0 15.0
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tH(2)
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DATA SHEET
Figure STM-1 VC-4 Drop Signals, Timing Derived from Drop (lead ABTE low)
tCYC A/BDCLK (Input) A/BD(7-0) A/BDPAR (Input) A/BDSPE (Input) A/BDC1J1V1 (Input) A/BACLK (Output) tOD(2) A/BAC1J1V1 (Output) A/BASPE (Output) A/BA(7-0) A/BAPAR (Output) A/BADD (Output)
C1(1)
tPWH
tSU(1)
C1(1)
tH(1)
C1(2) C1(3) Data
TU/VT Selected Byte STS-1
STS-1
STS-1
Data STS-1
tSU(2)
tH(2)
Occurs every four frames when provided place byte
tSU(3)
C1(1)
tH(3)
tOD(1)
tOD(3)
tOD(4)
TU/VT Selected
tOD(5)
Note: single TU/VT (number 21/28 STS-1 number shown illustration purposes. outputs delayed additional clock cycle from their respective drop timing inputs when control ABOD (bit 03BH) written with
Parameter A/BDCLK clock period A/BDCLK duty cycle tPWH/tCYC A/BD(7-0)/A/BDPAR data /parity setup time before A/BDCLK A/BD(7-0)/A/BDPAR data /parity hold time after A/BDCLK A/BDSPE setup time before A/BDCLK A/BDSPE hold time after A/BDCLK A/BDC1J1V1 setup time before A/BDCLK A/BDC1J1V1 hold time after A/BDCLK A/BACLK delay from A/BDCLK A/BAC1J1V1 delay from A/BACLK A/BASPE delay from A/BCLK A/B(7-0) A/BAPAR data /parity valid delay from A/BACLK A/BADD delay from A/BACLK
Note: output times measured with load capacitance.
Symbol tCYC
51.44
Unit
tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3) tOD(1) tOD(2) tOD(3) tOD(4) tOD(5) -2.0 -2.0 -2.0 -2.0
12.0 10.0
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TEMx8 TXC-04218
Figure STM-1 VC-4 Drop Signals, Timing Derived from Drop (lead ABTE high)
tCYC A/BDCLK (Input) A/BD(7-0) A/BDPAR (Input) A/BDSPE (Input) A/BDC1J1V1 (Input) A/BA(7-0) A/BAPAR (Output) A/BADD (Output)
tSU(3)
C1(1)
tPWH
tSU(1)
C1(1)
tH(1)
C1(2) C1(3) Data
TU/VT Selected Byte VC-4
tSU(2)
tH(2)
Occurs every four frames when provided place byte
tH(3)
tOD(1) tOD(3)
TU/VT Selected
tOD(2)
tOD(4)
Note: single TU/VT (number 21/28 STS-1 number shown illustration purposes. outputs delayed additional clock cycle from their respective drop timing inputs when control ABOD (bit 03BH) written with
Parameter A/BDCLK clock period A/BDCLK duty cycle tPWH/tCYC A/BD(7-0)/A/BDPAR data /parity setup time before A/BDCLK A/BD(7-0)/A/BDPAR data /parity hold time after A/BDCLK A/BDSPE setup time before A/BDCLK A/BDSPE hold time after A/BDCLK A/BDC1J1V1 setup time before A/BDCLK A/BDC1J1V1 hold time after A/BDCLK A/BA(7-0)/A/BAPAR data /parity valid delay from A/BDCLK A/BA(7-0)/A/BAPAR data /parity tristate delay from A/BDCLK A/BADD indicator delay from A/BDCLK A/BA(7-0)/A/BAPAR data /parity tristate driven delay from A/BDCLK
Note: output times measured with load capacitance.
Symbol tCYC
51.44
Unit
tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3) tOD(1) tOD(2) tOD(4) tOD(3)
21.0 18.0 15.0
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DATA SHEET
Figure STS-3 Signals, Timing Derived from
tCYC A/BACLK (Input) A/BASPE (Input)
tSU(1) tH(1)
C1(1) STS-1 STS-1 STS-1
tPWH tSU(2)
tH(2)
Occurs every four frames when enabled
A/BAC1J1V1
(Input)
STS-1
STS-1
STS-1
tOD(2) A/BA(7-0) A/BAPAR (Output) A/BADD (Output)
TU/VT Selected
tOD(3)
tOD(4) tOD(1)
Note: single TU/VT (number 21/28 STS-1 number shown illustration purposes. outputs delayed additional clock cycle from their respective timing inputs when control ABOD (bit 03BH) written with
Parameter ACLK clock period ACLK duty cycle, tPWH/tCYC AC1J1V1 setup time before ACLK AC1J1V1 hold time after ACLK ASPE setup time before ACLK ASPE hold time after ACLK A(7-0)/APAR data /parity valid delay from ACLK A(7-0)/APAR data /parity tristate delay from ACLK indicator delayed from ACLK A(7-0)/APAR data /parity tristate driven delay from ACLK
Symbol tCYC
Load
51.44
Unit
tSU(1) tH(1) tSU(2) tH(2) tOD(2) tOD(3) tOD(1) tOD(4) 50pF 50pF 50pF
21.0 17.0
Note: output times measured with specified load capacitance.
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Figure STM-1 VC-4 Signals, Timing Derived from
tCYC A/BACLK (Input) A/BASPE (Input)
tSU(1) tH(1)
C1(1)
TEMx8 TXC-04218
tPWH tSU(2)
tH(2)
Occurs every four frames when enabled
A/BAC1J1V1
(Input)
tOD(2) A/BA(7-0) A/BAPAR (Output) A/BADD (Output)
TU/VT Selected
tOD(3)
tOD(4) tOD(1)
Note: single TU/VT (number 21/28 STS-1 number shown illustration purposes. outputs delayed additional clock cycle from their respective timing inputs when control ABOD (bit 03BH) written with
Parameter ACLK clock period ACLK duty cycle, tPWH/tCYC AC1J1V1 setup time before ACLK AC1J1V1 hold time after ACLK ASPE setup time before ACLK ASPE hold time after ACLK A(7-0)/APAR data /parity valid delay from ACLK A(7-0)/APAR data /parity tristate delay from ACLK indicator delayed from ACLK A(7-0)/APAR data /parity tristate driven delay from ACLK
Symbol tCYC
Load
51.44
Unit
tSU(1) tH(1) tSU(2) tH(2) tOD(2) tOD(3) tOD(1) tOD(4) 50pF 50pF 50pF
Note: output times measured with specified load capacitance.
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DATA SHEET
Figure Microprocessor Read Cycle Timing Intel tH(1)
A(14-0) (Input)
Address
D(7-0) (Output)
Data tF(1) tSU(1) tD(1)
(Input)
tSU(2)
(Input)
tH(2) tPW(1) tD(3)
tD(2)
(Output)
tD(4)
tF(2)
tPW(2)
Parameter A(14-0) address setup time A(14-0) address hold time after D(7-0) data output float time after setup time pulse width hold time after delay after delay after float time after pulse width Data output valid delay after Data output valid delay after Data output tristate driven delay after
Symbol tSU(1) tH(1) tF(1) tSU(2) tPW(1) tH(2) tD(2) tD(3) tF(2) tPW(2) tD(1) tD(4) tD(5)
Unit
15.0 14.0 12.0 12.0
Note: output times measured with maximum load capacitance.
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tD(5)
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Figure Microprocessor Write Cycle Timing Intel
TEMx8 TXC-04218
tH(1) A(14-0) (Input) Address
D(7-0) (Input) tSU(1) (Input) tSU(3) (Input) tD(1) (Output)
Data tSU(2) tSU(4)
tPW(1)
tD(2)
tPW(2)
Parameter A(14-0) address setup time A(14-0) address hold time after D(7-0) data input valid setup time D(7-0) data input hold time after setup time pulse width delay after delay after float time after pulse width D(7-0) data valid setup time
Symbol tSU(1) tH(1) tSU(2) tH(2) tSU(3) tPW(1) tD(1) tD(2) tPW(2) tSU(4)
Unit
Note: output times measured with maximum load capacitance.
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tH(2)
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DATA SHEET
Figure Microprocessor Read Cycle Timing Motorola
tH(1)
RD/WR (Input) A(14-0) (Input)
tD(1)
D(7-0) (Output)
tD(5) Data tSU(1) tPW(1) tF(1)
WR/LDS (Input) (Input)
tD(6) tD(2)
DTACK (Output)
tD(4)
tF(2)
Parameter A(14-0) address setup time RD/WR setup time before SEL, WR/LDS (See Note
WR/LDS (See Note
Symbol tSU(1) tH(1) tF(1) tPW(1) tD(2) tF(2) tD(6) tD(1) tD(4) tD(5)
Unit
A(14-0) address hold time RD/WR delay time after SEL,
D(7-0) data output float time after SEL, WR/LDS (See Note WR/LDS pulse width DTACK driven delay after SEL, WR/LDS (See Note DTACK float time after SEL, WR/LDS (See Note DTACK delay after SEL, WR/LDS (See Note D(7-0) data output delay after SEL, WR/LDS (See Note D(7-0) data output delay after DTACK D(7-0) data output tristate drive delay after WR/LDS (See Note
Notes: output times measured with maximum load capacitance. Measured with respect later WR/LDS falling edge. Measured with respect earlier WR/LDS rising edge.
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Address
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Figure Microprocessor Write Cycle Timing Motorola
TEMx8 TXC-04218
tH(1)
RD/WR (Input) A(14-0) (Input) D(7-0) (Input)
Address tSU(2) Data tH(2) tSU(1)
WR/LDS (Input) (Input)
tPW(1)
tD(4) tD(2)
DTACK (Output)
Parameter A(14-0) address setup time RD/WR setup time before WR/LDS (See Note A(14-0) address hold time RD/WR delay time after SEL, WR/LDS (See Note D(7-0) data input setup time before SEL, WR/LDS (See Note D(7-0) data input hold time after SEL, WR/LDS (See Note WR/LDS pulse width DTACK driven delay after WR/LDS (See Note DTACK float time after SEL, WR/LDS (See Note DTACK delay after WR/LDS (See Note
Symbol tSU(1) tH(1) tSU(2) tH(2) tPW(1) tD(2) tD(4)
Unit
Notes: output times measured with maximum load capacitance. Measured with respect later WR/LDS falling edge. Measured with respect earlier WR/LDS rising edge.
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DATA SHEET
Figure Boundary Scan Timing
tPWL tPWH (INPUT) tH(1) (INPUT) tSU(1)
tH(2) (INPUT) tSU(2)
tPW(1) (OUTPUT)
tPW(1) (INPUT)
Parameter clock high time clock time setup time before hold time after setup time before hold time after delay from (see Note) Pulse Width
Symbol tPWH tPWL tSU(1) tH(1) tSU(2) tH(2) tPW(1)
Unit
Note: output time (TDO) measured with maximum load capacitance.
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DATA SHEET OPERATION
following sections detail operation TEMx8 Mapper. INTERFACE MODES
TEMx8 TXC-04218
Each channel TEMx8 Mapper supports following SONET/SDH modes operation: Drop Mode Mode Single Unidirectional Ring Mode Multiplexer Mode Dual Unidirectional Ring Mode Drop Mode drop mode operation, TU/VTs from both buses monitored, TU/VT terminated from either Drop receive output, without return path transmit direction buses. Mode mode operation, TU/VTs monitored from Drop buses without receive output, path transmit direction either buses provided. Single Unidirectional Ring Mode single unidirectional ring mode operation, TU/VT dropped from Drop bus, with return path bus. other drop monitors VT/TU. Timing TU/VT added derived from either Drop bus, from bus. Multiplexer Mode multiplexer mode operation, TU/VT dropped from Drop bus, with return path bus. other drop monitors VT/TU. Timing TU/VT added derived from either Drop bus, from bus. Dual Unidirectional Ring Mode dual unidirectional ring mode operation, TU/VT dropped from Drop bus, with return path both buses. other drop monitors VT/TU. Timing TU/VT added derived from either Drop bus, from bus.
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MODE SELECTION
DATA SHEET
TU/VT mode selection performed control bits defined table shown below. represents channel number (1-8). Note: Both buses upon power reset high impedance state. must written control bits AAHZE (bit 03AH) BAHZE (bit 03AH) normal operation. Mode Type Dropping only, from Dropping only, from Single unidirectional ring Single unidirectional ring Multiplexer, Multiplexer, Dual unidirectional ring Dual unidirectional ring
Notes: When drop-only mode selected, ability TU/VT disabled, tristated. Writing control FnRDIS (bit X+006H) causes value always transmitted zero. addition, receive side alarms disabled from generating transmitted zero. However, microprocessor send RDI, required.
TnSEL1
TnSEL0
RnSEL
DROP from
Drop-only Drop-only
(bit X+006H) (bit X+006H) (bit X+006H)
Mode Selection Channel SDH/SONET ADD/DROP MULTIPLEXING FORMAT SELECTIONS control settings SONET/SDH mapping format selection given table shown below. This selection valid both Drop buses. Drop Reset operation should performed after modifying STS-3 bit. DRESET address 039H Memory Description. Format STS-3 Format STM-1 AU-3 Format STM-1 Format STS3 (bit 01AH)
STS-3 STS-1/STM-1 VC-4 Format Selection
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DATA SHEET
DROP TU/VT SELECTION
TEMx8 TXC-04218
TU/VT Type
Meaning TU/VT Selected VT1.5/TU-11 Format VT2/TU-12 Format
AU-3/TUG-3 STS-1
TU/VT Group Number
TU/VT Number
used AU-3/TUG-3 STS-1 AU-3/TUG-3 STS-1 AU-3/TUG-3 STS-1 TU/VT Group Number TU/VT Group Number TU/VT Group Number TU/VT Group Number TU/VT Group Number TU/VT Group Number TU/VT Group Number TU/VT Number TU/VT Number TU/VT Number TU/VT Number (VT1.5/TU-11 format)
Drop VT/TU Selection
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There four VT/TU selection registers channel. registers used selecting VT1.5/TU-11 VT2/TU-12 (VT2) drop buses, other registers used selecting VT1.5/TU-11 VT2/TU-12 (VT2) buses. Thus, different VT/TUs assigned drop buses, different VT/TUs assigned buses channel addition, broadcast capability supported drop direction. This feature permits same VT/TU dropped more than channel. direction only channel used broadcast mode. Each selection register consists eight bits, which programmed according following table. forces high impedance state receive interface channel addition, states will transmitted zeros. unlatched Drop channel alarms that channel will remain when written into that channel's Drop selection register regardless change alarm condition. direction, invalid value forces high impedance state that channel. register assignment side drop X+012H, side X+01AH, side drop X+082H, X+08AHB, where channel number hex. When changing value channel selection register, should written into register first, followed channel assignment value. When changing value Drop channel Selection Register, should written into register, followed channel assignment value. another channel been assigned same value, then nothing else needs done. other channel been assigned same value, then Drop channel reset (control DACHnR DBCHnR) operation should performed channel whose selection register been modified.
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TEMx8 TXC-04218
TIMING
DATA SHEET
ABUST lead High
Action timing selected. Drop timing selected. Timing Selection
PERFORMANCE COUNTERS There three types performance counters provided: saturating/rollover, current second, previous one-second counters. counters, other than one-second counters, configured saturating (when control CROV (bit 01AH) rollover (when control CROV When counter configured saturating, stops maximum count. rollover counter rolls over zero after maximum count reached. saturating counter reset hardware reset (RESET lead), software reset (RESETH control bit), when read microprocessor, following resets they apply: RESETC (resets performance counters), DRESET (resets drop side performance counters), DACHnR/DBCHnR (resets drop side performance counters selected channel), TRESET (resets side performance counters), TnRESET (resets side performance counters selected channel). rollover counter reset FFFEH/FEH software reset. hardware reset sets CROV (saturating) performance counters Rollover counters reset when read microprocessor. software resets must held high minimum DSCLK clock cycle (excluding RESETH which self clearing). Since these resets self-clearing they must brought before another reset operation take place. Reset action Current one-second previous one-second counters dependent upon CROV control bit. These counters always reset (never FFFEH/FEH) hardware software reset. 16-bit counter, order byte must read first, followed read high order byte, before other order byte read. During microprocessor read cycle performance counter, counts held updated afterwards ensure that counts lost. ALARM STRUCTURE alarm indications reported unlatched latched status bits. latched alarm positive transitions, negative transitions, both positive negative transitions. Reading latched alarm clears Control bits INTR1 INTR0 (bits 01BH) should programmed select transition(s) which latched bits (see table below). INTR1 (bit 01BH) INTR0 (bit 01BH) Action Alarm used. latched alarm event indication, interrupt indication. Alarm sets latched alarm positive transitions alarm. Alarm sets latched alarm negative transitions alarm. Alarm sets latched alarm positive negative transitions alarm.
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Timing adding TU/VT derived from like-named drop bus, from like-named bus. timing-source selection determined lead ABUST, shown table below. drop timing mode, timing derived from drop clock, C1J1(V1), signals. pulse present signal derived from internal multiframe detectors. option also provided which internal clock, C1J1V1, signals provided outputs buses drop timing mode. timing, input clock, C1J1V1, signal must provided input signals.
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DATA SHEET
alarm bits latch according various states shown Figure below.
POSITIVE TRANSITION INTR1, INTR0=10 Alarm (Unlatched)
TEMx8 TXC-04218
Pos. Transition
Latched
NEGATIVE TRANSITION INTR1, INTR0=01 Alarm (Unlatched)
Neg. Transition
Latched Clear Read POSITIVE/NEGATIVE TRANSITION INTR1, INTR0=11 Alarm (Unlatched)
Transition
Latched Clear Read
Figure Alarm Latching Configurations shown above diagram there three possible alarm latching configurations: positive transition, negative transition, positive/negative transition. positive level latching configuration supported this device. example, assume that control bits INTR1 INTR0 equal This configures latched alarm circuits positive transitions alarm. positive transition alarm causes corresponding latched latched will remain until register containing latched position read microprocessor, which time latched positions register will reset Even though alarm (unlatched) remains active, will cause latched state recur. latched will remain reset until another positive alarm (unlatched) transition occurs SECOND (SHADOW) REGISTERS TEMx8 also provides Second registers alarms. Second register feature TEMx8 enabled applying positive pulse one-second intervals lead PM1S. Figure illustrates operation Second (Shadow) registers alarm. This figure assumes that interrupt control bits INTR1 INTR0 (bits 01BH) value Second (PM) status whenever there alarm transition during last one-second interval alarm present last one-second interval. Persistent (FM) status alarm active become active during previous one-second interval.
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Clear Read
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TEMx8 TXC-04218
DATA SHEET
PM1S UNLATCHED ALARM LATCHED ALARM SECOND (PM) ALARM SECOND (FM) ALARM
Note this example, latched events only positive negative event transitions.
Figure Second (Shadow) Register Operation INTERRUPT STRUCTURE interrupt indication structure contains both global alarm indication polling registers, along with mask bits various levels interrupt structure. following figures illustrate interrupt structure. shown Figure hardware interrupt controlled control HINT (bit 005H). When this control written with hardware interrupt microprocessor disabled. When written with hardware interrupt lead enabled. Status bits GDA, GDB, GAB, PCDA, PCDB, PCAB (050H) global status bits, will provided their corresponding mask bits (MGDA, MGDB, MGA, MPCDA, MPCDB, MPCAB (005H)), mask bits that correspond alarms also Status (bit 050H) when alarm occurs drop (e.g., loss clock). Status (bit 050H) when alarm occurs drop (e.g., loss clock). Status (bit 050H) when alarm occurs either buses (e.g., loss clock). Status PCDA (bit 050H) when alarm occurs channels that dropping VT/TU from drop (e.g., channel detected loss pointer alarm). Status PCDB (bit 050H) when alarm occurs channels that dropping VT/TU from drop (e.g., channel detected loss pointer alarm). Status PCAB (bit 050H) when alarm occurs channels that adding VT/TU from and/or (e.g., channel detected transmit loss signal alarm). shown Figure each channel there polling bits through drop side, drop side, side, with each setting when there corresponding alarm, mask bits that correspond polling alarms also polling polling register (055H) sets when channel detects side alarm (e.g., channel detects transmit loss clock). polling drop polling register (074H) sets when channel detects drop side alarm VT/TU selected (e.g., channel detects signal label mismatch alarm). polling drop polling registers (094H) sets when channel detects drop side alarm VT/TU selected (e.g., channel detects unequipped alarm). Associated with each three polling bits channel corresponding mask bits when
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TEMx8 TXC-04218
enable global polling indication bits. Also shown Figure drop alarm locations their corresponding mask bits setting three global indication bits. example, upstream indication detected drop STS-3 STS-1 corresponding mask set, global indication also set. shown Figure each alarms corresponding mask each channel. These correspond side alarms (e.g., line detected), drop VT/TU alarms (e.g., alarm detected), drop VT/TU alarms (e.g., alarm detected). When corresponding mask alarm sets three polling registers corresponding channel. addition, there mask bits which inhibit alarm type from setting more channel bits polling register. example, unequipped alarm that occurs channel masked from setting that channels polling register location. interrupt cleared reading latched alarm position, setting appropriate mask bits Please note: will take approximately microseconds before interrupt will change states when alarm mask enabled (turned off).
Channel Drop Latched Alarms (X+114H X117H)
Alarms Channel Channel Polling Drop Alarms (74H)
Channel Mask Bits Drop Alarms (X+013H X+016H)
Alarms Mask Bits
Channel Drop Latched Alarms (X+194H X+197H)
Alarms Channel Channel Polling Drop Alarms (094H)
Channel Mask Bits Drop Alarms (X+083H X+086H)
Alarms Mask Bits
Channel Latched Alarms (X+101H)
Alarms Channel Channel Polling Alarms (055H)
Channel Mask Bits Alarms (X+005H)
Alarms Mask Bits
Mask Bits Alarm Type (007H 00AH)
Figure Channel Polling Alarms
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TEMx8 TXC-04218
DATA SHEET
Channel Polling Alarms (055H) Channel Polling Mask Bits Alarms (03FH) Channel Polling Drop Alarms (074H)
Global Indication Channel Polling
Global Indication Channel Polling Drop Alarms (PCDA, 050H)
Channel Polling Mask Bits Drop Alarms (045H) Channel Polling Drop Alarms (094H)
Global Indication Channel Polling Drop Alarms (PCDB, 050H)
Channel Polling Mask Bits Drop Alarms (04BH)
Drop Latched Alarms (062H 0063H) Mask Bits Drop (043H 044H)
Alarms
Mask Bits
Global Indication Drop Alarms (GDA, 50H)
Drop Latched Alarms (082H 083H) Mask Bits Drop (049H 04AH)
Alarms
Mask Bits
Global Indication Drop Alarms (GDB, 50H)
Latched Alarms (052H) Mask Bits Drop (03DH)
Alarms
Mask Bits
Global Indication Alarms (GAB, 50H)
Figure Global Indication Alarms
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Alarms
(PCAB, 050H)
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TEMx8 TXC-04218
Global Indication
Channel Polling
Alarms (PCAB, 050H) Mask (MPCAB, 005H) Global Indication Channel Polling Drop Alarms (PCDA, 050H) Mask (MPCDA, 005H) Global Indication Channel Polling Drop Alarms (PCDB, 050H) Mask (MPCDB, 005H)
Global Indication Drop Alarms (GDA, 050H) Mask (MGDA, 005H)
Hardware Interrupt Indication
Global Indication Drop Alarms (GDB Bit, 050H) Mask (MGDB, 005H)
Control HINT=1 (Bit 005H)
Global Indication Alarms (GAB, 050H) Mask (MGAB, 005H)
Figure Hardware Interrupt Indication
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TEMx8 TXC-04218
DROP INTERFACE
DATA SHEET
SONET/SDH Drop buses provided, labeled side Drop, side Drop. drop buses consist following leads: Input data (A/BD(7-0)), Input parity, (A/BDPAR), Input optional marker pulses (A/BDC1J1V1), Input payload indication (A/BDSPE).
Most Significant (MSB) assigned AD(7-0) BD(7-0) signals. defined first received SONET/SDH byte (i.e., SONET/SDH byte). rate 19.44 kbit/s STS-3 STM-1 operation. STS-1 rate supported. drop buses monitored loss clock. alarms ADLOC (bit 060H) side drop BDLOC (bit 080H) side. DROP PARITY SELECTION parity selection drop buses, Drop, according following table. parity error side drop indicated alarm ADPAR (bit 060H), side drop indicated alarm BDPAR (bit 080H). Other than alarm indication, action taken within TEMx8.
DBPE (bit 019H)
PDDO (bit 019H)
Drop Parity Selection parity calculated input leads consisting data (A/BD(7-0)), clock (A/BDCLK), marker pulses (A/BDC1J1V1), payload indication (A/BDSPE). parity calculated data input leads (A/BD(7-0)). Even parity calculated input leads consisting data (A/BD(7-0)), clock (A/BDCLK), marker pulses (A/BDC1J1V1), payload indication (A/BDSPE). Even parity calculated data Input leads (A/BD(7-0)).
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DROP MULTIFRAME ALIGNMENT
TEMx8 TXC-04218
STM-1 VC-4 operation, single pulse must occur three drop clock cycles every four frames following pulse. STM-1 AU3/STS-3 operation, three pulses must present every four frames. Each pulse must present clock cycle, three clock cycles after corresponding pulse, when signal high. example, VC-4 signal, pulse identifies byte location (defined starting location VC-4) bytes. next column (first clock cycle) rows assigned fixed stuff. Similarly, next column (second clock cycle) rows assigned fixed stuff. next column (third clock cycle) defines start TUG-3 This column where pulse occurs every four frames. However, actual byte occurs clock cycles after pulse. STS-1 operation, pulse must present. pulse must occur next clock cycle after when signal high. pulse identifies byte location (defined starting location STS-1) bytes. next column (first clock cycle) defines starting location. Thus, pulse identifies starting location first byte signal. rest bytes VT2s also aligned with respect pulse. timing relationships between other signals shown Timing Characteristics section. byte used identify location byte shown Figure below: TU-12/VT2 (XXXX XX00) Previous Bytes (XXXX XX01) Bytes (XXXX XX10) Bytes (XXXX XX11) Bytes Figure Byte Floating Mode Allocation byte monitored multiframe alignment when enabled. STM-1 operation, there only detector drop buses. STS-3 operation, there three byte detectors, each STS-1 side side drop buses. Each STS-1 have phase regarding multiframe sequence.
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TU-11/VT1.5 (XXXX XX00) Previous Bytes (XXXX XX01) Bytes (XXXX XX10) Bytes (XXXX XX11) Bytes
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Pointer byte alignment bytes) VT/TUs receive direction (from drop bus) established detecting multiframe pattern byte reference pulse ADC1J1V1 BDC1J1V1 signal. Depending format, three pulses will present this signal. When byte used establish byte alignment, pulse does have present ADC1J1V1 BDC1J1V1 signal. Writing control DV1SEL (bit 019H) selects pulse ADC1J1V1 BDC1J1V1 signal used establish byte location reference, while selects byte multiframe detector establishing reference. multiframe detection circuits disabled when pulse selected place byte. Drop Reset operation should performed after modifying DV1SEL bit. DRESET address Memory Description.
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TEMx8 TXC-04218
DATA SHEET
When multiframe detector enabled, Out-Of-Multiframe alarm (AxHOOM BxHOOM) declared when error detected bits byte (where each STS-1 signals STS-3 STM-1 VC-4 format). Recovery occurs when error free byte sequence detected four consecutive frames (beginning with detection code). Once state, recovery does take place within Out-Of-Multiframe alarm (AxHLOM BxHLOM) declared (where each STS-1 signals STS-3 STM-1 VC-4 format). Recovery occurs upon recovering AxHOOM BxHOOM alarm. SDH/SONET DETECTION TEMx8 detect upstream SONET/SDH condition using either H1/H2 pointer bytes order wire byte. selection according following table.
HEAISE (bit 01DH)
SE1AIS (bit 01DH)
Action upstream monitoring performed. H1/H2 bytes monitored upstream AIS. byte monitored upstream AIS.
Note: VT/TU detected each pointer tracking state machines independently SONET/SDH H1/H2 byte detection circuitry.
When control STS3 (bit1, 01AH) selects VC-4/TUG-3 format, bytes byte drop buses monitored AIS. When STS3 control selects STS-3 AU-3 format, each three H1/H2 bytes bytes Drop Drop buses monitored indication. Each three H1/H2 pointer bytes bytes corresponds like-numbered AU-3/STS-1 signal (n=1-3). When H1/H2 bytes selected ones detected H1/H2 bytes drop three consecutive frames, alarm bits AxUAIS will set, where equal which corresponds like numbered STS-1. VC-4 format, equal only. ones detected H1/H2 bytes drop three consecutive frames, alarm bits BxUAIS will set. Recovery occurs when normal (bits through detected three consecutive frames. When bytes monitored upstream condition majority logic used determine byte carrying upstream indication. five more ones detected Drop byte, alarm AxUAIS BxUAIS set. Recovery occurs when four less ones detected byte.
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TU/VT POINTER TRACKING
TEMx8 TXC-04218
starting location byte determined either pulses A/BC1J1V1 signals multiframe detection circuits, described earlier section. TU/VT pointer assignment bytes shown below. alignment necessary determine starting locations byte other bytes that carrying format. Byte SS-bits Byte
Increment Decrement Data Flag (enabled 1001 0001/1101/1011/1000, normal disabled 0110 1110/0010/0100/0111) SS-bits Size) (1544 kbit/s) (2048 kbit/s) Pointer Bytes Assignment pointer value binary number with range (1544 kbit/s) (2048 kbit/s) format. pointer offset indicates offset from byte byte VT1.5/TU-11 TU-12/VT2 mapping. pointer bytes counted offset calculation. pointer offset arrangement this format shown below. VT1.5/TU-11 79-102 1-24 27-50 53-76 TU/VT Pointer Offset Locations VT2/TU-12 106-138 1-33 36-68 71-103
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TEMx8 TXC-04218
DATA SHEET
Sixteen independent pointer-tracking state machines used TEMx8, each channel drop buses. values V1/V2 pointer bytes each multiframe provided registers X+183H X+184H side, registers X+203H X+204H side. pointer tracking algorithm illustrated following Figure pointer tracking state machine based pointer tracking state machine defined ETSI ANSI requirements. When control PTALTE (bit 01BH) transition from disabled (shown dotted).
(Offset Undefined)
inc_ind (Incr. Offset) any_point new_point (Accept Offset)
NDF_enable (Accept Offset) NDF_enable (Accept Offset)
AIS_ind (Offset Undefined)
new_point (Accept Offset) NDF_enable (Accept Offset) new_point (Accept Offset) any_point NDF_enable (Accept Offset) inv_point (Offset Undefined) dec_ind (Decr. Offset) any_point
NORM
new_point (Accept Offset) AIS_ind (Offset Undefined) new_point (Accept Offset)
new_point (Accept Offset)
AIS_ind NDF_enable (Offset Undefined) (Offset Undefined)
inv_point (Offset Undefined) NDF_enable (Accept Offset) AIS_ind (Offset Undefined)
Figure VT/TU Pointer Tracking State Machine Indication (A/BnAIS) provided registers X+111/X+191H. Indication (A/BnLOP) provided registers X+111/X+191H. Indication (A/BnNDF) provided registers X+111/X+191H. Wrong Size Indication (A/BnSIZE) provided registers X+111/X+191H. Positive Justification Counter located registers X+120H side X+1A0H side. Negative Justification Counter located registers X+121H side X+1A1H side.
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AIS_ind
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Pointer Tracking State Machine States Definition Event norm_point Definition Disabled (0110, 1110, 0010, 0100, 0111) match SS-bits receive pointer offset value equal active offset value.
TEMx8 TXC-04218
NDF_enable
AIS_ind inc_ind
pointer 11111111 11111111 Hex, Hex) disabled (0110, 1110, 0010, 0100, 0111) match SS-bits match more bits. Please note that this requirement differs from majority bits inverted majority bits received. disabled (0110, 1110, 0010, 0100, 0111) match SS-bits match more bits. Please note that this requirement differs from majority bits inverted majority bits received. norm_point NDF_enable AIS_ind {(inc_ind dec_ind) norm_state}. consecutive NDF_ enable. consecutive AIS_ind. NDF_enable AIS_ind new_point. Disabled (0110, 1110, 0010, 0100, 0111) match SS-bits receive pointer offset value range equal active offset value. consecutive new_point received.
dec_ind
inv_point
NDF_enable AIS_ind any_point
new_point
new_point
Notes: active offset value defined accepted current phase VT1.5/VT2 state norm_state undefined other states. Enabled defined following patterns: 1001, 0001, 1101, 1011, 1000. Disabled defined following patterns: 0110, 1110, 0010, 0100, 0111. remaining codes (0000, 0011, 0101, 1010, 1100 1111) result inv_point indication. code 1111 does result inv_point indication part AIS_ind. Note that new_point also inv_point. new_point takes precedence over other events. second third offset value received new_point must identical with first. consecutive new_point counter reset change state, except transitions occurring among INC, DEC, NORM states. consecutive inv_point counter incremented states. consecutive inv_point counter reset change state. consecutive AIS_ind counter reset change state. consecutive NDF_enable counter reset zero change state. Otherwise counter reset. Inc_ind/dec_ind causes active offset value incremented/decremented, respectively. subsequent detection new_point with offset value equal offset value caused inc_ind/dec_ind will cause pointer flag assert. SS-bits match
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enabled (1001, 0001, 1101, 1011, 1000) match SS-bits received pointer offset value range.
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TEMx8 TXC-04218
OVERHEAD BYTE PROCESSING
DATA SHEET
addition overhead byte (V5, bytes) processing, four overhead bytes both drop buses written into single byte locations channel selected, every microseconds. Byte Processing placement bits within byte shown below.
BIP-2
Signal Label
BIP-2 Bits used error performance monitoring. Interleaved Parity scheme used. errors detected BIP-2 comparison, they counted individually 8-bit counter when control BLOCK (bit 01AH) written with When control BLOCK written with parity errors counted single block error. Remote Error Indication (REI) Remote Error Indications (REI) sent distant when errors detected BIP-2. Otherwise Remote Error Indication (REI) counted 8-bit counter. Remote Failure Indication (RFI) Remote Failure Indication (RFI) normally used byte synchronous applications normally received value equal five times consecutively, alarm indication (AnRFI (bit X+110H) drop BnRFI (bit X+190H) drop) asserted. Recovery occurs when byte equal five times consecutively. Signal Label Bits byte provide signal label. TEMx8 provides following monitoring circuits signal label: Signal label Mismatch Detection Unequipped Detection Detection
Remote Defect Indication Detection There Remote Defect Indication schemes defined: single three RDI. common circuit channel used detect both three states, single state. single scheme defined applications, while three defined SONET applications. Single uses byte, while three uses bits byte, conjunction with byte. Three enhanced RDI) allows user differentiate between server, connectivity, payload defects. equal byte. byte inverse byte order distinguish enhanced version from single RDI. should noted that when bits byte either indication also influenced byte, shown table below. When bits either then determined solely
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TEMx8 TXC-04218
byte. This allows detection originating from equipment that generates single byte. following table lists defect indications that carried bytes.
Definition defect indications defect indications Remote Payload Defect, indicates Path Label Mismatch defect indications defect indications defect indications defect indications defect indications Remote defect indication (single RDI) Remote defect indication (single RDI) Remote defect indication (single RDI) Remote defect indication (single RDI) Remote defect indication (single RDI) Remote Server Defect; indicates Loss Pointer detected Upstream detected H1/H2 Bytes). Remote Connectivity Defect Unequipped Signal Label Mismatch Loss Lock Remote defect indication (single RDI)
Three Single Detection
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TEMx8 TXC-04218
Receive Detection Recovery
DATA SHEET
alarm indications defined table below. number consecutive events detection recovery controlled control V5AL10 (bit 01BH). value five selected when V5AL10 control value selected when V5AL10 control number detection recovery events valid both three single RDI. AnRDIC BnRDIC AnRDIP BnRDIP AnRDIS BnRDIS Action Remote Server Defect Indication, single indication (Bit byte). Remote Payload Defect Indication. Remote Connectivity Indication.
Alarm Definitions
Byte Processing There possible received message sizes, bytes (ITU-T), bytes (ANSI). TEMx8 capable dimensioning transmit memory segment sizes (16-Byte 64-Byte). addition, modes operation provided 16-byte (ITU-T) format: microprocessor read mode, compare read mode. following table lists various control states associated with processing. Please note: byte used shared basis with bytes. When byte configured byte message, tandem connection feature disabled. When segment configured byte byte message, byte segment provided Tandem Connection feature when enabled, byte processing feature.
ARnJ2S1 (bit X+010H) BRnJ2S1 (bit X+080H)
ARnJ2S0 (bit X+010H) BRnJ2S0 (bit X+080H
Action
Receive segment channel configured 16-byte message size. bytes written into segment rotating basis, starting with arbitrary address. alarms disabled. Receive segment channel configured 16-byte message size, comparison. received 16-byte message compared against byte microprocessor written message, that must aligned starting address segment. alarms enabled. Receive segment channel configured 64-byte message size. bytes written into segment rotating basis, starting with arbitrary address. alarms disabled.
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TEMx8 TXC-04218
ARnJ2S1 (bit X+010H) BRnJ2S1 (bit X+080H)
ARnJ2S0 (bit X+010H) BRnJ2S0 (bit X+080H
Action
ITU-T defined 16-byte message consists alignment signal (10000000 00000000) most significant (bit message. remaining bits each byte carry data message, illustrated below.
16-Byte Message
ITU-T 16-Byte Message Format 16-byte message comparison works according following steps: microprocessor-written byte segment should initialized with 16-byte message before enabling message comparison function. message comparison function then enabled (A/BRnJ2S0 A/BRnJ2S1 immediately Loss Lock alarm will active (A/BnJ2LOL Trace Identifier Mismatch alarm will inactive (A/BnJ2TIM This first step sequence initialize these alarms. incoming trace message received, comparison circuit searches alignment pattern (Bit 1000.0 patt
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