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Universe IIUser Manual
Spring 1998
http://www.tundra.com
information this document subject change without notice should construed commitment Tundra Semiconductor Corporation. While reasonable precautions have been taken, Tundra Semiconductor Corporation assumes responsibility errors that appear this document. part this document copied reproduced form means without prior written consent Tundra Semiconductor Corporation. Tundra® products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Tundra product could create situation where personal injury death occur. Should Buyer purchase Tundra products such unintended unauthorized application, Buyer shall indemnify hold Tundra officers, employees, subsidiaries, affiliates distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Tundra negligent regarding design manufacture part. acceptance this document will construed acceptance foregoing conditions.
Universe IIUser Manual Copyright 1998, Tundra Semiconductor Corporation rights reserved. Document: 8091142.MD300.01 Printed Canada
Tundra Tundra logo registered trademarks Tundra Semiconductor Corporation. Universe Universe, SCV64, Trooper QSpan trademarks Tundra Semiconductor Corporation. BI-Mode registered trademark DY-4 Systems, Inc.
Overview
Chapter Chapter Chapter Chapter Appendix Appendix Appendix Appendix Appendix Appendix Appendix Introduction Functional Description Description Signals Signals Characteristics Registers Performance Typical Applications Reliability Prediction Cycle Mapping Operating Storage Conditions Mechanical Ordering Information
Table Contents
Introduction Features Benefits Universe Past Future Universe About This Document. Universe Technical Support Universe Documentation. Conventions 1.7.1 1.7.2 1.7.3 Signals Symbols. Terminology.
Functional Description. Architectural Overview. 2.1.1 2.1.1.1 2.1.1.2 2.1.2 2.1.2.1 2.1.2.2 2.1.3 2.1.3.1 2.1.3.2 2.1.4 2.2.1 2.2.1.1 2.2.1.2 2.2.1.3 VMEbus Interface Universe VMEbus Slave. Universe VMEbus Master Interface Universe Target Universe Master. Interrupter Interrupt Handler Interrupter VMEbus Interrupt Handling Controller VMEbus Requester Internal Arbitration VMEbus Requests. Request Modes. VMEbus Release.
VMEbus Interface
2.2.2 2.2.2.1 2.2.2.2 2.2.2.3 2.2.3 2.2.3.1 2.2.3.2 2.2.3.3 2.2.3.4 2.2.3.5 2.2.3.6 2.2.3.7 2.2.3.8 2.2.4 2.2.4.1 2.2.4.2 2.2.5 2.2.5.1 2.2.5.2 2.2.6 2.2.6.1 2.2.6.2 2.2.6.3 2.2.6.4 2.2.7 2.3.1 2.3.1.1 2.3.1.2 2.3.1.3 2.3.1.4
Universe VMEbus Master. Addressing Capabilities Data Transfer Capabilities 2-10 Cycle Terminations. 2-13 Universe VMEbus Slave. 2-13 Coupled Transfers. 2-14 Posted Writes 2-15 Prefetched Block Reads 2-16 VMEbus Lock Commands (ADOH Cycles). 2-18 VMEbus Read-Modify-Write Cycles (RMW Cycles). 2-19 Register Accesses. 2-19 Location Monitors. 2-19 Generating Configuration Cycles 2-20 VMEbus Configuration. 2-23 First Slot Detector 2-23 VMEbus Register Access Power-up 2-23 Automatic Slot Identification 2-24 Auto Slot VME64 Specified. 2-24 Auto-ID: Proprietary Tundra Method 2-25 System Controller Functions. 2-26 System Clock Driver. 2-26 VMEbus Arbiter. 2-27 IACK Daisy-Chain Driver Module. 2-27 VMEbus Time-out 2-28 BI-Mode 2-28 Cycles-Overview. 2-30 32-Bit Versus 64-Bit 2-30 Request Parking 2-31 Address Phase 2-31 Data Transfer 2-33
Interface 2-30
2.3.1.5 2.3.1.6 2.3.2 2.3.2.1 2.3.2.2 2.3.2.3 2.3.3 2.3.3.1 2.3.3.2 2.3.3.3 2.3.3.4 2.3.3.5 2.3.3.6 2.3.3.7 2.4.1 2.4.1.1 2.4.1.2 2.4.1.3 2.4.2 2.4.2.1 2.4.2.2 2.4.2.3 2.4.3 2.5.1 2.5.2 2.5.2.1 2.5.2.2 2.5.2.3 2.5.2.4
Termination Phase 2-33 Parity Checking. 2-34 Universe Master 2-35 Burst Transfers 2-36 Termination. 2-37 Parity. 2-37 Universe Target. 2-38 Overview. 2-38 Data Transfer 2-39 Coupled Transfers. 2-42 Posted Writes 2-44 Special Cycle Generator 2-45 Using VOWN 2-48 Terminations 2-49 Slave Images 2-50 VMEbus Fields 2-51 Fields 2-51 Control Fields 2-52 Target Images 2-53 Fields 2-54 VMEbus Fields 2-54 Control Fields 2-55 Special Target Image 2-55 Coupled Cycles 2-58 Decoupled Transactions 2-58 Posted Writes 2-58 Prefetched Reads. 2-60 Errors 2-60 Parity Errors 2-60
Slave Image Programming. 2-50
Error Handling 2-58
Interrupt Generation 2-62 2.6.1 2.6.2 Interrupt Generation. 2-63 VMEbus Interrupt Generation. 2-65 Interrupt Handling. 2-68 VMEbus Interrupt Handling. 2-68 Error During VMEbus IACK Cycle 2-70 Internal Interrupt Handling. 2-71 VMEbus Software Interrupts 2-73 Software IACK Interrupt 2-74 VMEbus Ownership Interrupt. 2-75 Interrupt 2-75 Mailbox Register Access Interrupts. 2-75 Location Monitors. 2-75 VMEbus Error Interrupts 2-76 VME64 Auto-ID 2-76 Registers Outline. 2-77 Source Destination Addresses. 2-78 Transfer Size 2-79 Transfer Data Width 2-79 Command Packet Pointer 2-80 Control Status 2-80 Direct Mode Operation. 2-83 Linked-List Operation 2-86 Linked List Updating 2-91 FIFO Operation Ownership. 2-92 VMEbus Transfers. 2-92 VMEbus Transfers. 2-94 Interrupts 2-95 Interactions with Other Channels. 2-96
Interrupt Handling. 2-68 2.7.1 2.7.2 2.7.2.1 2.7.3 2.7.3.1 2.7.3.2 2.7.3.3 2.7.3.4 2.7.3.5 2.7.3.6 2.7.3.7 2.7.4
Controller 2-77 2.8.1 2.8.1.1 2.8.1.2 2.8.1.3 2.8.1.4 2.8.1.5 2.8.2 2.8.3 2.8.3.1 2.8.4 2.8.4.1 2.8.4.2 2.8.5 2.8.6
viii
2.8.7 2.8.7.1 2.8.7.2 2.8.7.3 2.9.1 2.9.2 2.9.2.1 2.9.2.2 2.9.2.3 2.9.3 2.9.3.1 2.9.3.2 2.9.3.3 2.9.4 2.9.5 2.10 2.10.1
Error Handling 2-96 Software Response Error. 2-97 Hardware Response Error 2-97 Resuming Transfers. 2-98 Overview Universe Registers. 2-100 Register Access from 2-101 Configuration Access 2-102 Memory Access. 2-103 Locking Register Block from bus. 2-103 Register Access from VMEbus 2-104 VMEbus Register Access Image (VRAI) 2-104 CR/CSR Accesses. 2-106 ADOH Register Access Cycles. 2-106 Mailbox Registers 2-108 Semaphores 2-109 Resets 2-110 Overview Reset Support. 2-110 Universe Reset Circuitry 2-112 Reset Implementation Cautions 2-114 Power-up Option Descriptions. 2-117 Power-Up Option Implementation. 2-119
Registers. 2-100
Utility Functions 2-110 2.10.1.1 2.10.1.2 2.10.1.3 2.10.2 2.10.2.1 2.10.2.2 2.10.3 2.10.4
Power-Up Options. 2-115
Hardware Initialization (Normal Operating Mode) 2-121 Test Modes 2-122 Auxiliary Test Modes 2-122 JTAG support. 2-123
2.10.4.1 2.10.4.2 2.10.5
Clocks. 2-123
Description Signals VMEbus Signals
Signals
Signals Characteristics Terminology. Characteristics Assignments.
Appendix Registers .App Appendix Performance Slave Channel B.1.1 B.1.1.1 B.1.1.2 B.1.1.3 B.1.2 B.2.1 B.2.1.1 B.2.1.2 B.2.1.3 B.2.2 B.2.2.1 B.2.2.2 B.3.1 B.3.2 B.3.3 B.3.3.1 B.3.3.2 B.3.4 Coupled Cycles .App Request VMEbus. Read Cycles Write Cycles. Decoupled Cycles.App Coupled Cycles .App Block non-Block Transfers Read Cycles Write Cycles. Decoupled Cycles.App Write Cycles. Prefetched Read Cycles B-12 Relative FIFO sizes .App B-14 VMEbus Ownership Modes .App B-14 Transfers.App B-14 Read Transfers B-15 Write Transfers B-15 Transfers.App B-15
Slave Channel.
Channel B-14
Summary B-17
Appendix Typical Applications Interface. C.1.1 C.1.1.1 C.1.2 C.1.3 C.2.1 C.2.2 Transceivers .App Pull-down resistors Direction control .App Power-up Options.App Resets .App Local Interrupts .App
Interface
Manufacturing Test Pins C-10 Decoupling Universe C-10
Appendix Reliability Prediction Physical characteristics Thermal characteristics Universe Ambient Operating Calculations. Thermal vias.
Appendix Cycle Mapping Little-endian Mode.
Appendix Operating Storage Conditions Appendix Mechanical Ordering Information .App Index Mechanical Information. Ordering Information
Index-1
List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 2.10 Figure 2.11 Figure 2.12 Figure 2.13 Figure 2.14 Figure 2.15 Figure 2.16 Figure 2.17 Figure 2.18 Figure 2.19 Figure 2.20 Figure 2.21 Figure 2.22 Figure Figure Figure Figure Architectural Diagram Universe Influence Transaction Data Width Target Image Data Width Data Packing/Unpacking 2-12 VMEbus Slave Channel Dataflow. 2-14 Timing Auto-ID Cycle. 2-26 Target Channel Dataflow 2-40 Influence Transaction Data Width Target Image Data Width Data Packing/Unpacking 2-41 Address Translation Mechanism VMEbus Transfers 2-52 Address Translation Mechanism VMEbus Transfers 2-54 Memory Mapping Special Target Image 2-57 Universe Interrupt Circuitry 2-62 STATUS/ID Provided Universe 2-67 Sources Internal Interrupts 2-72 Direct Mode transfers. 2-84 Command Packet Structure Linked List Operation. 2-87 Linked List Operation 2-88 Universe Control Status Register Space 2-101 Access UCSR Memory Space 2-102 UCSR Access from VMEbus Register Access Image. 2-105 UCSR Access VMEbus CR/CSR Space 2-107 Reset Circuitry. 2-113 Resistor-Capacitor Circuit Ensuring Power-Up Reset Duration 2-114 Power-up Options Timing 2-120 UCSR Access Mechanisms Coupled Read Cycle Universe Master Several Coupled Read Cycles Universe Master. Coupled Write Cycle Universe Master
xiii
Figure Figure Figure Figure Figure Figure Figure B.10 Figure B.11 Figure B.12 Figure B.13 Figure Figure Figure Figure Figure Figure Figure Figure
Several Non-Block Decoupled Writes Universe Master Decoupled Write Universe Master Coupled Read Cycle Universe Slave Coupled Write Cycle Universe Slave (bus parked Universe Non-Block Decoupled Write Cycle Universe Slave B-10 Decoupled Write Cycle Universe Slave B-11 MBLT Decoupled Write Cycle Universe Slave. B-11 Pre-fetched Read Cycle Universe Slave B-13 Read Transactions During Operation. B-16 Multiple Read Transactions During Operation. B-17 Universe Connections VMEbus Through Buffers Power-up Configuration Using Passive Pull-ups Power-up Configuration Using Active Circuitry Analog Isolation Scheme. C-10 Noise Filter Scheme C-11 Mechanical Dimensions 324-Pin Ceramic Package 313-PBGA (Generic). 313-PBGA View (OMPAC GTPAC Drawings).
List Tables
Table Table Table Table Table Table Table Table Table Table 2.10 Table 2.11 Table 2.12 Table 2.13 Table 2.14 Table 2.15: Table 2.16 Table 2.17 Table 2.18 Table 2.19 Table 2.20 Table 2.21 Table 2.22 Table 2.23 Table 2.24 Table 2.25 Table Table Suffixes Active Signals Address Line Asserted Function VA[15:11] 2-21 Command Type Encoding Transfer Type 2-32 Register Fields Special Cycle Generator 2-45 VMEbus Fields VMEbus Slave Image. 2-50 Fields VMEbus Slave Image. 2-50 Control Fields VMEbus Slave Image 2-50 Fields Target Image 2-53 VMEbus Fields Target Image 2-53 Control Fields Target Image. 2-53 Fields Special Target Image. 2-56 VMEbus Fields Special Target Image. 2-56 Control Fields Special Target Image. 2-56 Source, Enabling, Mapping, Status Interrupt Output. 2-64 Source, Enabling, Mapping, Status VMEbus Interrupt Outputs 2-66 Internal Interrupt Routing. 2-71 Interrupt Sources Enable Bits. 2-95 Programming VMEbus Register Access Image 2-104 Hardware Reset Mechanism. 2-110 Software Reset Mechanism 2-111 Functions Affected Reset Initiatiors. 2-112 Power-Up Options 2-116 VRAI Base Address Power-up Options 2-117 Manufacturing Requirements Normal Operating Mode. 2-121 Test Mode Operation. 2-122 Electrical Characteristics (VDD 10%) List Characteristics Universe Signals
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table A.10 Table A.11 Table A.12 Table A.13 Table A.14 Table A.15 Table A.16 Table A.17 Table A.18 Table A.19 Table A.20 Table A.21 Table A.22 Table A.23 Table A.24
Address/Data Pins VMEbus Address Pins. VMEbus Data Pins 4-10 Assignments Power Ground 4-11 Pinout 313-pin Plastic Package 4-12 Pinout 324-pin Ceramic Package. 4-13 Universe Register Configuration Space Register (PCI_ID) Configuration Space Control Status Register (PCI_CSR). Configuration Class Register (PCI_CLASS) A-10 Configuration Miscellaneous Register (PCI_MISC0) A-11 Configuration Base Address Register (PCI_BS0) A-12 Configuration Base Address Register (PCI_BS1) A-13 Configuration Miscellaneous Register (PCI_MISC1) A-14 Target Image Control (LSI0_CTL) A-15 Target Image Base Address Register (LSI0_BS). A-16 Target Image Bound Address Register (LSI0_BD) A-17 Target Image Translation Offset (LSI0_TO) A-18 Target Image Control (LSI1_CTL) A-19 Target Image Base Address Register (LSI1_BS). A-20 Target Image Bound Address Register (LSI1_BD) A-21 Target Image Translation Offset (LSI1_TO) A-22 Target Image Control (LSI2_CTL) A-23 Target Image Base Address Register (LSI2_BS). A-24 Target Image Bound Address Register (LSI2_BD) A-25 Target Image Translation Offset (LSI2_TO) A-26 Target Image Control (LSI3_CTL) A-27 Target Image Base Address Register (LSI3_BS). A-28 Target Image Bound Address Register (LSI3_BD) A-29 Target Image Translation Offset (LSI3_TO) A-30
Table A.25 Table A.26 Table A.27 Table A.28 Table A.29 Table A.30 Table A.31 Table A.32 Table A.33 Table A.34 Table A.35 Table A.36 Table A.37 Table A.38 Table A.39 Table A.40 Table A.41 Table A.42 Table A.43 Table A.44 Table A.45 Table A.46 Table A.47 Table A.48 Table A.49 Table A.50 Table A.51 Table A.52 Table A.53 Table A.54 Table A.55
Special Cycle Control Register (SCYC_CTL). A-31 Special Cycle Address Register (SCYC_ADDR). A-32 Special Cycle Swap/Compare Enable Register (SCYC_EN) A-33 Special Cycle Compare Data Register (SCYC_CMP) A-34 Special Cycle Swap Data Register (SCYC_SWP). A-35 Miscellaneous Register (LMISC). A-36 Special Target Image (SLSI). A-37 Command Error Register (L_CMDERR) A-39 Address Error (LAERR) A-40 Target Image Control Register (LSI4_CTL). A-41 Target Image Base Address Register (LSI4_BS). A-42 Target Image Bound Address Register (LSI4_BD) A-43 Target Image Translation Offset (LSI4_TO) A-44 Target Image Control Register (LSI5_CTL). A-45 Target Image Base Address Register (LSI5_BS). A-46 Target Image Bound Address Register (LSI5_BD) A-47 Target Image Translation Offset (LSI5_TO) A-48 Target Image Control Register (LSI6_CTL). A-49 Target Image Base Address Register (LSI6_BS). A-50 Target Image Bound Address Register (LSI6_BD) A-51 Target Image Translation Offset (LSI6_TO) A-52 Target Image Control Register (LSI7_CTL). A-53 Target Image Base Address Register (LSI7_BS). A-54 Target Image Bound Address Register (LSI7_BD) A-55 Target Image Translation Offset (LSI7_TO) A-56 Transfer Control Register (DCTL). A-57 Transfer Byte Count Register (DTBC) A-58 Address Register (DLA) A-59 VMEbus Address Register (DVA). A-60 Command Packet Pointer (DCPP) A-61 General Control/Status Register (DGCS) A-62
xvii
Table A.56 Table A.57 Table A.58 Table A.59 Table A.60 Table A.61 Table A.62 Table A.63 Table A.64 Table A.65 Table A.66 Table A.67 Table A.68 Table A.69 Table A.70 Table A.71 Table A.72 Table A.73 Table A.74 Table A.75 Table A.76 Table A.77 Table A.78 Table A.79 Table A.80 Table A.81 Table A.82 Table A.83 Table A.84 Table A.85 Table A.86 Table A.87 Table A.88
Linked List Update Enable Register (D_LLUE) A-64 Interrupt Enable Register (LINT_EN) A-65 Interrupt Status Register (LINT_STAT) A-67 Interrupt Register (LINT_MAP0). A-69 Interrupt Register (LINT_MAP1). A-70 VMEbus Interrupt Enable Register (VINT_EN). A-71 VMEbus Interrupt Status Register (VINT_STAT) A-73 Interrupt Register (VINT_MAP0). A-75 Interrupt Register (VINT_MAP1). A-76 Interrupt STATUS/ID Register (STATID) A-77 VIRQ1 STATUS/ID Register (V1_STATID). A-78 VIRQ2 STATUS/ID Register (V2_STATID). A-79 VIRQ3 STATUS/ID Register (V3_STATID). A-80 VIRQ4 STATUS/ID Register (V4_STATID). A-81 VIRQ5 STATUS/ID Register (V5_STATID). A-82 VIRQ6 STATUS/ID Register (V6_STATID). A-83 VIRQ7 STATUS/ID Register (V7_STATID). A-84 Interrupt Register (LINT_MAP2). A-85 Interrupt Register (VINT_MAP2). A-86 Mailbox Register (MBOX0). A-87 Mailbox Register (MBOX1). A-88 Mailbox Register (MBOX2). A-89 Mailbox Register (MBOX3). A-90 Semaphore Register (SEMA0) A-91 Semaphore Register (SEMA1) A-92 Master Control Register (MAST_CTL) A-93 Miscellaneous Control Register (MISC_CTL) A-95 Miscellaneous Status Register (MISC_STAT) A-97 User Codes Register (USER_AM) A-98 VMEbus Slave Image Control (VSI0_CTL). A-99 VMEbus Slave Image Base Address Register (VSI0_BS). A-100 VMEbus Slave Image Bound Address Register (VSI0_BD) A-101 VMEbus Slave Image Translation Offset (VSI0_TO) A-102 xviii
Table A.89 Table A.90 Table A.91 Table A.92 Table A.93 Table A.94 Table A.95 Table A.96 Table A.97 Table A.98 Table A.99 Table A.100 Table A.101 Table A.102 Table A.103 Table A.104 Table A.105 Table A.106 Table A.107 Table A.108 Table A.109 Table A.110 Table A.111 Table A.112 Table A.113 Table A.114 Table A.115 Table A.116 Table A.117 Table A.118
VMEbus Slave Image Control (VSI1_CTL). A-103 VMEbus Slave Image Base Address Register (VSI1_BS). A-104 VMEbus Slave Image Bound Address Register (VSI1_BD) A-105 VMEbus Slave Image Translation Offset (VSI1_TO) A-106 VMEbus Slave Image Control (VSI2_CTL). A-107 VMEbus Slave Image Base Address Register (VSI2_BS). A-108 VMEbus Slave Image Bound Address Register (VSI2_BD) A-109 VMEbus Slave Image Translation Offset (VSI2_TO) A-110 VMEbus Slave Image Control (VSI3_CTL). A-111 VMEbus Slave Image Base Address Register (VSI3_BS). A-112 VMEbus Slave Image Bound Address Register (VSI3_BD) A-113 VMEbus Slave Image Translation Offset (VSI3_TO) A-114 Location Monitor Control Register (LM_CTL) A-115 Location Monitor Base Address Register (LM_BS) A-116 VMEbus Register Access Image Control Register (VRAI_CTL) A-117 VMEbus Register Access Image Base Address Register (VRAI_BS). A-118 VMEbus Control Register (VCSR_CTL). A-119 VMEbus Translation Offset (VCSR_TO) A-120 VMEbus Code Error (V_AMERR) A-121 VMEbus Address Error (VAERR) A-122 VMEbus Slave Image Control (VSI4_CTL). A-123 VMEbus Slave Image Base Address Register (VSI4_BS). A-124 VMEbus Slave Image Bound Address Register (VSI4_BD) A-125 VMEbus Slave Image Translation Offset (VSI4_TO) A-126 VMEbus Slave Image Control (VSI5_CTL). A-127 VMEbus Slave Image Base Address Register (VSI5_BS). A-128 VMEbus Slave Image Bound Address Register (VSI5_BD) A-129 VMEbus Slave Image Translation Offset (VSI5_TO) A-130 VMEbus Slave Image Control (VSI6_CTL). A-131 VMEbus Slave Image Base Address Register (VSI6_BS). A-132
Table A.119 Table A.120 Table A.121 Table A.122 Table A.123 Table A.124 Table A.125 Table A.126 Table A.127 Table Table Table Table Table Table Table Table Table Table Table Table Table Table
VMEbus Slave Image Bound Address Register (VSI6_BD) A-133 VMEbus Slave Image Translation Offset (VSI6_TO) A-134 VMEbus Slave Image Control (VSI7_CTL). A-135 VMEbus Slave Image Base Address Register (VSI7_BS). A-136 VMEbus Slave Image Bound Address Register (VSI7_BD) A-137 VMEbus Slave Image Translation Offset (VSI7_TO) A-138 VMEbus Clear Register (VCSR_CLR) A-139 VMEbus Register (VCSR_SET). A-140 VMEbus Base Address Register (VCSR_BS). A-141 Slave Channel Performance B-17 Slave Channel Performance. B-18 Channel Performance B-19 VMEbus Signal Drive Strength Requirements. VMEbus Transceiver Requirements. Reset Signals Ambient Junction Thermal Impedance Maximum Universe Junction Temperature Mapping 32-bit Little-Endian 32-bit VMEbus Mapping 32-bit Little-Endian 64-bit VMEbus Recommended Operating Conditions. Absolute Maximum Ratings. Power Dissipation. Standard Ordering Information
VMEbus Interface Components-Universe User Manual
Introduction
Features
Universe (CA91C142) facto industry standard VMEbus bridge, providing: 64-bit, interface, fully compliant, high performance 64-bit VMEbus interface, integral FIFOs buffer multiple transactions both directions, programmable controller with linked-list support, industry leading performance, Wide range VMEbus address data transfer modes, A32/A24/A16 master slave, (not A40) D64/D32/D16/D08 master slave, MD32) -MBLT, BLT, ADOH, RMW, LOCK, location monitors, nine user programmable slave images VMEbus ports, seven interrupt lines either flexible mapping software hardware sources hardware interrupt, automatic initialization slave-only applications, flexible register set, programmable from both VMEbus bus, four mailboxes location monitor message-oriented system, support RMWs, lock cycles, semaphores guarantee exclusive access, isolation mode board maintenance, diagnostics, live fault recovery, full VMEbus system controller functionality, several power-up options, IEEE 1149.1 JTAG testability support, commercial industrial extended temperature options, available 313-pin Plastic 324-pin Ceramic BGA.
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Benefits Universe
Universe User Manual
Benefits Universe
Interfacing VMEbus with presents number opportunities challenges. Universe solves problems allows benefit from opportunities. opportunities involve merging best VMEbus worlds. VMEbus proven standard specifically designed support embedded systems. distributed environment VMEbus supports multiprocessing real-time intensive applications. large number off-the-shelf boards, software, chassis components available. VMEbus supports 21-slot systems without bridging continually evolving while providing backward compatibility. swap solutions, higher performance protocols have been defined will incorporated future revisions VMEbus. Meanwhile, become standard local bus. result, leading semiconductor vendors have built support into their newest processor peripheral families. challenges involved interfacing VMEbus include: address mapping, byte-lane swapping, cycle mapping. allow VMEbus single-board computer vendors benefit from components, while overcoming challenges involved merging with VMEbus, Tundra developed VMEbus interface controller, Universe Universe industry proven, high performance 64-bit VMEbus interface, fully compliant with VME64 tailored generation high performance processors peripherals. availability Universe eases development multi-master, multi-processor architectures VMEbus systems using PCI. Universe ideally suited boards acting both master slave VMEbus system that require access systems. With Universe know that your system increases complexity, have silicon that continues provide everything need bridge. elegant design Tundra Universe some best applications engineers industry, this manual will make easy possible most sophisticated VMEbus interface.
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Universe User Manual
Past Future Universe
Past Future Universe
Universe (CA91C142) pin- software-compatible revision Universe (CA91C042). Universe developed subsequently SCV64, Tundra's interface non-PCI applications. Universe next generation Universe, been designed exceed customer expectations correct errata original Universe. rich feature performance enhancements based extensive consultation with customers. Given history, Universe offers low-risk, feature-rich, high performance solution VMEbus-based applications. Some performance enhancements offered Universe include: improved bandwidth utilization, improved register access performance, improved VMEbus slave master performance, increased FIFO depth, improved optimize transfer rate each bus, improved linked-list performance, significantly improved coupled transfer performance, reduced power consumption. Additional features include: four mailbox registers, eight semaphores, four location monitors, software interrupts, more slave images. Universe revision another example Tundra's commitment supporting VMEbus community. Tundra actively participating VMEbus, bus, CompactPCI standards vendor associations, well related SIGs. Tundra will continue propose support enhancements these specifications, while increasing both range options available customers compatibility between PCI. Please visit site keep abreast these developments: http://www.tundra.com
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About This Document
Universe User Manual
About This Document
This manual intended users Tundra Universe Because differences between Universe Universe this manual suitable users original Tundra Universe. Universe users should continue consult previous VMEbus manual (document number 9000000.MD303.01). current manual organized follows: Chapter General Information, Chapter Functional Description, Chapter Signal Description, Chapter Signals Characteristics, Appendix Registers, Appendix Performance, Appendix Typical Applications, Appendix Reliability, Appendix Cycle Mapping, Appendix Operating Storage Conditions Appendix Mechanical Ordering Information, Index. Chapter introduces Universe provides reader with information about necessary concepts conventions required manual. Chapters describe Universe function, beginning with overall functionality Chapter detailed signal descriptions Chapters Appendices reference sources necessary implementation Universe addition, Appendices contain application information user system design. Index provides means quickly access information keyword basis.
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Universe User Manual
Universe Technical Support
Universe Technical Support
Tundra dedicated providing customers with superior technical documentation support. following means support available: Universe User's Manual. This main source technical information. strive hard produce excellent documentation, this manual contains answers most customers' questions. Universe Documentation Page. This contains latest manual, application notes, FAQ, articles, device errata manual addenda. Please visit bookmark http://www.tundra.com. Designer's Resource Forum. This public discussion forum http://www.tundra.com which allows post questions read threads pertaining specifically Universe Tundra technical support staff moderate this forum promptly respond customer inquiries. support@tundra.com. also direct questions feedback Tundra using this e-mail address. Please include "Universe subject header your message. Phone support. Tundra's technical support staff reached (613) 592-1320. Please Universe technical support.
Universe Documentation
Tundra dedicated providing customers with superior technical documentation support. Universe User's Manual. This main source technical information. Universe Documentation Page. This contains latest manual, application notes, FAQ, articles, device errata manual addenda. Please visit bookmark http://www.tundra.com. documents available files. These files searchable replete with hypertext links. read documents on-line (with plug-in your browser), download them your machine. Acrobat indexes these files allow perform very rapid searches through documents. Designer's Resource Center. tailor Tundra site presented using this resource, available from http://www.tundra.com. There, also register receive automatic
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Conventions
Universe User Manual
mail notification when addendum, manual, other "resource" changed. This best ensure that always have latest Universe documentation.
1.7.1
Conventions
Signals
Signals VMEbus either active high active low. Active signals defined true (asserted) when they logic low. Similarly, active high signals defined true logic high. Signals considered asserted when active negated when inactive, irrespective voltage levels. voltage levels, indicates voltage while indicates high voltage. names Universe signals VMEbus interface start with letter (e.g., VRSYSRST#). Input signals that interface start with `VR' (e.g.,VRSYSRST#), output signals start with `VX' (e.g., VXBERR). Table shows convention denoting active signals. Table Suffixes Active Signals
Suffix Used active signals PCI, active signals VMEbus interface Universe SIGNAL* active signals VMEbus backplane Example RST# VRSYSRST# SYSRESET*
1.7.2
Symbols
Caution: This symbol alerts reader procedures operating levels which result misuse damage Universe
Note: This symbol directs reader's attention useful information suggestions.
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Universe User Manual
Conventions
1.7.3
Terminology
term "cycle" refers single data beat, while "transaction" composed more "cycles". eliminate ambiguity, expression "external master" used denote master that Universe different Universe II). capitalized expression "Master Interface" used denote Universe master. expression "external target" used denote target that Universe different Universe II). capitalized expression "Target Interface" "Slave Interface" used denote Universe target slave) bus. example Universe accesses memory chip bus, might write: "The Master Interface writes external target."
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Conventions
Universe User Manual
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VMEbus Interface Components-Universe User Manual
Functional Description
Section 2.1, "Architectural Overview", page summarizes overall architecture Universe Section 2.2, "VMEbus Interface", page presents capabilities Universe VMEbus slave VMEbus master, Section 2.3, "PCI Interface", page 2-30 presents capabilities Universe target master, Section 2.4, "Slave Image Programming", page 2-50 explains program mapping cycles from other, Section 2.5, "Bus Error Handling", page 2-58 explains Universe handles generates errors, Section 2.6, "Interrupt Generation", page 2-62 describes interrupts which Universe generate, Section 2.7, "Interrupt Handling", page 2-68 describes Universe responds interrupt conditions, Section 2.8, "DMA Controller", page 2-77 describes operation Universe II's Direct Memory Access Controller, Section 2.9, "Registers", page 2-100 gives overview Universe II's registers they accessed, Section 2.10, "Utility Functions", page 2-110 describes resets, power-up options, test modes, clocks.
This chapter organized follows.
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Architectural Overview
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Architectural Overview
This section introduces general architecture Universe This description makes frequent reference functional block diagram provided Figure page 2-3. Notice that each interfaces, VMEbus bus, there three functionally distinct modules: master module, slave module, interrupt module. These modules connected different functional channels operating Universe These channels are: VMEbus Slave Channel, Target Channel, Channel, Interrupt Channel, Register Channel. Architectural Overview organized into following sections: "VMEbus Interface", "PCI Interface", "Interrupter Interrupt Handler", "DMA Controller". These sections describe operation Universe terms different modules channels illustrated Figure 2.1.
2.1.1 2.1.1.1
VMEbus Interface Universe VMEbus Slave
Universe VMEbus Slave Channel accepts addressing data transfer modes documented VME64 specification (except those intended augment applications, i.e., MD32). Incoming write transactions from VMEbus treated either coupled posted, depending upon programming VMEbus slave image (see "VME Slave Images" page 2-50). With posted write transactions, data written Posted Write Receive FIFO (RXFIFO), VMEbus master receives data acknowledgment from Universe Write data transferred resource from RXFIFO without involvement initiating VMEbus master (see "Posted Writes" page 2-15 full explanation this operation). With coupled cycle, VMEbus master only receives data acknowledgment when transaction complete bus. This means that VMEbus unavailable other masters while transaction executed.
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Channel
Interface
bidirectional FIFO
VMEbus Interface
VMEbus Slave Channel
Master
posted writes FIFO prefetch read FIFO coupled read
Slave
Slave Channel
Slave
posted writes FIFO coupled read logic
Master
VMEbus
Interrupt Channel
Interrupts
Interrupt Handler Interrupter
Interrupts
Register Channel
Figure Architectural Diagram Universe Read transactions either prefetched coupled. enabled user, prefetched read initiated when VMEbus master requests block read transaction (BLT MBLT) this mode enabled. When Universe receives block read request, begins fill Read Data FIFO (RDFIFO) using burst transactions from resource. initiating VMEbus master then acquires block read data from RDFIFO rather than from resources directly.
2.1.1.2
Universe VMEbus Master
Universe becomes VMEbus master when VMEbus Master Interface internally requested Target Channel, Channel, Interrupt Channel. Interrupt Channel always priority over other channels. Several mechanisms available configure relative priority that Target Channel Channel have over ownership VMEbus Master Interface.
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Universe II's VMEbus Master Interface generates addressing data transfer modes documented VME64 specification (except those intended augment applications, i.e. MD32). Universe also compatible with VMEbus modules conforming pre-VME64 specifications. VMEbus master, Universe supports Read-Modify-Write (RMW), Address-Only-with-Handshake (ADOH) does accept RETRY* termination from VMEbus slave. ADOH cycle used implement VMEbus Lock command allowing master lock VMEbus resources.
2.1.2 2.1.2.1
Interface Universe Target
Read transactions from always processed coupled. Write transactions either coupled posted, depending upon setting target image (see "PCI Target Images" page 2-53). With posted write transaction, write data written Posted Write Transmit FIFO (TXFIFO) master receives data acknowledgment from Universe with zero wait-states. Meanwhile, Universe obtains VMEbus writes data VMEbus resource independent initiating master (see "Posted Writes" page 2-44 full description this operation). allow masters perform ADOH cycles, Universe provides Special Cycle Generator. Special Cycle Generator used combination with VMEbus ownership function guarantee masters exclusive access VMEbus resources over several VMEbus transactions (see "The Special Cycle Generator" page 2-45 "Using VOWN bit" page 2-48 full description this functionality).
2.1.2.2
Universe Master
Universe becomes master when Master Interface internally requested VMEbus Slave Channel Channel. There mechanisms provided which allow user configure relative priority VMEbus Slave Channel Channel.
2.1.3 2.1.3.1
Interrupter Interrupt Handler Interrupter
Universe Interrupt Channel provides flexible scheme interrupts VMEbus Interface. Interrupts generated from hardware software sources (see "Interrupt Generation" page 2-62 "Interrupt Handling" page 2-68 full description hardware software sources). Interrupt sources mapped VMEbus interrupt output pins. Interrupt sources mapped VMEbus interrupts generated VMEbus interrupt output pins VIRQ# [7:1]. When software hardware source assigned same VIRQn# pin, software source always higher priority.
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Interrupt sources mapped interrupts generated INT# [7:0] pins. fully compliant, interrupt sources must routed single INT# pin. VMEbus interrupt outputs, Universe interrupter supplies 8-bit STATUS/ID VMEbus interrupt handler during IACK cycle, optionally generates internal interrupt signal that interrupt vector been provided (see "VMEbus Interrupt Generation" page 2-65). Interrupts mapped outputs serviced interrupt controller. determines which interrupt sources active reading interrupt status register Universe source negates interrupt when been serviced (see "PCI Interrupt Generation" page 2-63).
2.1.3.2
VMEbus Interrupt Handling
VMEbus interrupt triggers Universe generate normal VMEbus IACK cycle generate specified interrupt output. When IACK cycle complete, Universe releases VMEbus interrupt vector read resource servicing interrupt output. Software interrupts ROAK, while hardware, internal interrupts RORA.
2.1.4
Controller
Universe provides internal controller high performance data transfer between VMEbus. operations between source destination decoupled through single bidirectional FIFO (DMAFIFO). Parameters transfer software configurable Universe registers (see "DMA Controller" page 2-77). principal mechanism transfers same operations either direction (PCI VMEbus, VMEbus PCI), only relative identity source destination changes. transfer, Universe gains control source reads data into DMAFIFO. Following specific rules DMAFIFO operation (see "FIFO Operation Ownership" page 2-92), then acquires destination writes data from DMAFIFO. controller programmed perform multiple blocks transfers using entries linked-list. will work through transfers linked-list following pointers each linked-list entry. Linked-list operation initiated through pointer internal Universe register, linked-list itself resides memory.
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VMEbus Interface
VMEbus Interface incorporates operations associated with VMEbus. This includes master slave functions, VMEbus configuration system controller functions. These operations covered follows: "VMEbus Requester" below, "Universe VMEbus Master" page 2-9, "Universe VMEbus Slave" page 2-13, "VMEbus Configuration" page 2-23, "Automatic Slot Identification" page 2-24, "System Controller Functions" page 2-26. "BI-Mode" page 2-28. information concerning Universe VMEbus slave images, "VME Slave Images" page 2-50.
2.2.1 2.2.1.1
VMEbus Requester Internal Arbitration VMEbus Requests
Three different internal channels within Universe require VMEbus: Interrupt Channel, Target Channel, Channel. These three channels directly request VMEbus, instead they compete internally ownership VMEbus Master Interface. Interrupt Channel (refer Figure page 2-3) always highest priority access VMEbus Master Interface. Target Channel requests handled fair manner. channel awarded VMEbus mastership maintains ownership VMEbus until `done'. definition `done' each channel given below "VMEbus Release" page 2-8. Interrupt Channel requests VMEbus master when detects enabled VMEbus interrupt line asserted needs interrupt acknowledge cycle acquire STATUS/ID. Target Channel requests VMEbus Master Interface service following conditions: TXFIFO contains complete transaction, there coupled cycle request.
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VMEbus Interface
Channel requests VMEbus Master Interface DMAFIFO bytes available reading from VMEbus) bytes FIFO writing VMEbus), block complete (see "DMA Controller" page 2-77). case Channel, user optionally Channel VMEbus-off-timer further qualify requests from this channel. VMEbus-off-timer controls long remains VMEbus before making another request (see "PCI VMEbus Transfers" page 2-92). Universe provides software mechanism VMEbus acquisition through VMEbus ownership (VOWN MAST_CTL register, Table A.81). When VMEbus ownership set, Universe acquires VMEbus sets acknowledgment (VOWN_ACK MAST_CTL register, Table A.81) optionally generates interrupt (see "VME Lock Cycles-Exclusive Access VMEbus Resources" page 2-47). Universe maintains VMEbus ownership until ownership cleared. During VMEbus tenure initiated setting ownership bit, only Target Channel Interrupt Channel access VMEbus Master Interface.
2.2.1.2
Request Modes
Request Levels Universe software configurable request VMEbus request levels: BR3*, BR2*, BR1*, BR0*. default setting level VMEbus request. request level global programming option through field MAST_CTL register (Table A.81). programmed request level used VMEbus Master Interface regardless channel (Interrupt Channel, Channel, Target Channel) currently accessing VMEbus Master Interface. Fair Demand Universe requester programmed either Fair Demand mode. request mode global programming option through bits MAST_CTL register (Table A.81). Fair mode, Universe does request VMEbus until there other VMEbus requests pending programmed level. This mode ensures that every requester equal level access bus. Demand mode (the default setting), requester asserts request regardless state BRn* line. requesting frequently, requesters down daisy chain prevented from ever obtaining ownership. This referred "starving" those requesters. Note that order achieve fairness, requesters VMEbus system must Fair mode.
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2.2.1.3
VMEbus Release
Universe VMEbus requester configured either (release when done) (release request) using VREL MAST_CTL register (Table A.81). default setting RWD. means Universe releases BBSY* only request pending from another VMEbus master once channel that current owner VMEbus Master Interface done. Ownership assumed another channel without re-arbitration there pending requests level VMEbus. When RWD, VMEbus Master Interface releases BBSY* when channel accessing VMEbus Master Interface done (see below). Note that MYBBSY status MISC_STAT register (Table A.83) while Universe asserts BBSY* output. mode, VMEbus released when channel (for example, Channel) done, even another channel request pending (for example, Target Channel). re-arbitration VMEbus required pending channel requests. Each channel rules that determine when `done' with VMEbus transaction. Interrupt Channel done when single interrupt acknowledge cycle complete. Target Channel done under following conditions: when TXFIFO empty (the TXFE Universe MISC_STAT register, Table A.83), when maximum number bytes Target Channel tenure been reached programmed with PWON field MAST_CTL register, Table A.81)1, after each posted write, PWON equal 0b1111, programmed MAST_CTL register, Table A.81 when coupled cycle complete Coupled Window Timer expired, Coupled Request Timer (page 2-42) expires before coupled cycle retried master, when VMEbus ownership acquired with VOWN MAST_CTL register then VOWN cleared other words, VMEbus acquired through VOWN bit, Universe does release BBSY* until VOWN cleared-see "VME Lock Cycles-Exclusive Access VMEbus Resources" page 2-47).
This setting overridden VOWN mechanism used.
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VMEbus Interface
Channel done under following conditions (see "FIFO Operation Ownership" page 2-92 "DMA Error Handling" page 2-96): DMAFIFO full during VMEbus transfers, DMAFIFO empty during VMEbus transfers, error encountered during operation, VMEbus Tenure Byte Counter expired, block complete. Universe does monitor BCLR* ownership VMEbus affected assertion BCLR*.
2.2.2
Universe VMEbus Master
Universe becomes VMEbus master result following chain events: master accesses Universe target image (leading VMEbus access) Channel initiates transaction, either Universe Target Channel Channel wins access VMEbus Master Interface through internal arbitration, Universe Master Interface requests obtains ownership VMEbus. Universe will also become VMEbus master VMEbus ownership (see "VME Lock Cycles-Exclusive Access VMEbus Resources" page 2-47) role VMEbus interrupt handling (see "VMEbus Interrupt Handling" page 2-68). following sections describe function Universe VMEbus master terms different phases VMEbus transaction: addressing, data transfer, cycle termination, release.
2.2.2.1
Addressing Capabilities
Depending upon programming target image (see "PCI Target Images" page 2-53), Universe generates A16, A24, A32, CR/CSR address phases VMEbus. address mode type (supervisor/non-privileged program/data) also programmed through target image. Address pipelining provided except during MBLT cycles, where VMEbus specification does permit address codes that generated Universe functions address target image programming (see "PCI Target Images" page 2-53) through programming.
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Universe generates ADdress-Only-with-Handshake (ADOH) cycles support lock commands A16, A24, spaces. ADOH cycles must generated through Special Cycle Generator (see "The Special Cycle Generator" page 2-45). There User Defined codes that programmed through USER_AM register (Table A.84). USER_AM register only used generate accept codes 0x10 through 0x1F. These codes designated USERAM codes VMEbus specification. After power-up, values USER_AM register default same VME64 user-defined code. USER_AM codes used with VMEbus Slave Interface, ensure that cycles 32-bit addressing, that only single cycle accesses used. BLTs MBLTs with USER_AM codes will lead unpredictable behavior.
2.2.2.2
Data Transfer Capabilities
data transfer between VMEbus depicted Figure page 2-12. Universe seen funnel where mouth funnel data width transaction. funnel maximum VMEbus data width programmed into target image. example, consider 32-bit transaction accessing target image with bits. data beat with byte lanes enabled will broken into 16-bit cycles VMEbus. target image also programmed with block transfers enabled, 32-bit data beat will result block transfer VMEbus. Write data unpacked VMEbus read data packed data width. data width data beat same maximum data width target image, then Universe maps data beat equivalent VMEbus cycle. example, consider 32-bit transaction accessing target image with bits. data beat with byte lanes enabled translated single 32-bit cycle VMEbus. general rule, data width less than VMEbus data width then there packing unpacking between buses. only exception this during 32-bit multi-data beat transactions target image programmed with maximum VMEbus data width bits. this case, packing/unpacking occurs make maximum full bandwidth both buses. Only aligned VMEbus transactions generated, requested data beat unaligned non-contiguous byte enables, then broken into multiple aligned VMEbus transactions wider than programmed VMEbus data width. example, consider three-byte data beat 32-bit bus) accessing target image with bits. three-byte data beat will broken into aligned VMEbus cycles: single-byte cycle double-byte cycle (the ordering cycles depends arrangement byte enables data beat). above example target image bits, then three-byte data beat will broken into three single-byte VMEbus cycles.
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VMEbus Interface
BLT/MBLT cycles initiated VMEbus target image been programmed with this capacity (see "PCI Target Images" page 2-53). length BLT/MBLT transactions VMEbus will determined initiating transaction setting PWON field MAST_CTL register (Table A.81). example, single data beat transaction queued TXFIFO results single data beat block transfer VMEbus. With PWON field, user specify transfer byte count that will dequeued from TXFIFO before VMEbus Master Interface relinquishes VMEbus. PWON field specifies minimum tenure Universe VMEbus. However, tenure extended VOWN MAST_CTL register (see "Using VOWN bit" page 2-48). During operations, Universe will attempt block transfers maximum length permitted VMEbus specification (256 bytes BLT, Kbytes MBLT) limited counter (see "DMA VMEbus Ownership" page 2-81).
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Data width transaction
Maximum data width programmed into target image Data width exceeds maximum data width target image
Data width fits with maximum data width target image
WRITE (UNPACKING)
READ (PACKING) SIDE VMEBUS SIDE
Figure Influence Transaction Data Width Target Image Data Width Data Packing/Unpacking Universe provides indivisible transactions with VMEbus lock commands VMEbus ownership (see "VME Lock Cycles-Exclusive Access VMEbus Resources" page 2-47).
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2.2.2.3
Cycle Terminations
Universe accepts BERR* DTACK* cycle terminations from VMEbus slave. does support RETRY*. assertion BERR* indicates that some type system error occurred transaction complete properly. VMEbus BERR* received Universe during coupled transaction communicated master Target-Abort. information logged Universe receives BERR* coupled transaction. error occurs during posted write VMEbus, Universe uses V_AMERR register (Table A.107) code transaction (AMERR [5:0]), state IACK* signal (IACK bit, indicate whether error occurred during IACK cycle). current transaction FIFO purged. V_AMERR register also records multiple errors have occurred (with M_ERR bit), although actual number errors given. error qualified value V_STAT bit. address errored transaction latched V_AERR register (Table A.108). When Universe receives VMEbus error during posted write, generates interrupt VMEbus and/or depending upon whether VERR LERR interrupts enabled (see "Interrupt Handling" page 2-68, Table A.60 Table A.61). DTACK* signals successful completion transaction.
2.2.3
Universe VMEbus Slave
This section describes VMEbus Slave Channel other aspects Universe VMEbus slave. following topics discussed: "Coupled Transfers" page 2-14, "Posted Writes" page 2-15, "Prefetched Block Reads" page 2-16, "VMEbus Lock Commands (ADOH Cycles)" page 2-18, "VMEbus Read-Modify-Write Cycles (RMW Cycles)" page 2-19, "Location Monitors" page 2-19 "Generating Configuration Cycles" page 2-20. Universe becomes VMEbus slave when eight programmed slave images register images accessed VMEbus master (note that Universe cannot reflect cycle VMEbus access itself). Depending upon programming slave image, different possible transaction types result (see "VME Slave Images" page 2-50 description types accesses which Universe responds).
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reads, transaction coupled prefetched. Similarly, write transactions coupled posted. type read write transaction allowed slave image depends programming that particular VMEbus slave image (see Figure below "VME Slave Images" page 2-50). ensure sequential consistency, prefetched reads, coupled reads, coupled write operations only processed once previously posted write operations have completed (i.e. RXFIFO empty).
PREFETCHED READ DATA RDFIFO
MASTER INTERFACE
COUPLED READ DATA
COUPLED WRITE DATA POSTED WRITE DATA RXFIFO
VMEbus SLAVE INTERFACE
Figure VMEbus Slave Channel Dataflow
Incoming cycles from VMEbus have data widths 8-bit, 16-bit, 32-bit, 64-bit. Although supports only port sizes (32-bit 64-bit), byte lanes individually enabled, which allows each type VMEbus transaction directly mapped data bus. order VMEbus slave image respond incoming cycle, Master Interface must enabled (bit PCI_CSR register, Table A.3). data enqueued VMEbus Slave Channel FIFO cleared, FIFO will empty additional transfers will received.
2.2.3.1
Coupled Transfers
coupled transfer means that FIFO involved transaction handshakes relayed directly through Universe Coupled mode default setting VMEbus slave images. Coupled transfers only proceed once posted write entries RXFIFO have completed (see "Posted Writes" below). coupled cycle with multiple data beats (i.e. block transfers) VMEbus side always mapped single data beat transactions bus, where each data beat VMEbus mapped single data beat transaction regardless data beat size. packing unpacking performed. only exception this when VMEbus transaction mapped bus. data width depends
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VMEbus Interface
programming VMEbus slave image (32-bit 64-bit, "VME Slave Images" page 2-50). Universe enables appropriate byte lanes required VMEbus transaction. example, VMEbus slave image programmed generate 32-bit transactions accessed VMEbus read transaction (prefetching enabled this slave image). transaction mapped single data beat 32-bit transfers with only byte lane enabled. Target-Retry from target communicated VMEbus master. transactions terminated with Target-Abort Master-Abort terminated VMEbus with BERR*. Note that Universe sets R_TA R_MA bits PCI_CS register (Table A.3) when receives Target-Abort Master-Abort.
2.2.3.2
Posted Writes
posted write involves VMEbus master writing data into Universe II's RXFIFO, rather than directly address. Write transactions from VMEbus processed posted PWEN VMEbus slave image control register (see "VME Slave Images" page 2-50). cleared (the default setting) transaction bypasses FIFO performed coupled transfer (see above). Incoming posted writes from VMEbus queued 32-entry deep RXFIFO. (The RXFIFO same structure RDFIFO. different names used FIFO's roles, only which implement once.) Each entry RXFIFO contain address bits, data bits. Each incoming VMEbus address phase, whether 16-bit, 24-bit, 32-bit, constitutes single entry RXFIFO followed subsequent data entries. address entry contains translated address space command information mapping relevant particular VMEbus slave image that been accessed (see "VME Slave Images" page 2-50). this reason, re-programming VMEbus slave image attributes will only reflected RXFIFO entries queued after re-programming. Transactions queued before re-programming delivered with VMEbus slave image attributes that were before re-programming. Incoming non-block write transactions from VMEbus require entries RXFIFO: address entry (with accompanying command information) data entry. size data entry corresponds data width VMEbus transfer. Block transfers require least entries: entry address command information, more data entries. VMEbus Slave Channel packs data received during block transfers full 64-bit width RXFIFO. example, data phase transfer bytes total) does require data entries RXFIFO. Instead, eight data phases bits data phase total bits) packed into 64-bit data entries RXFIFO. final data phases bits combined) queued next RXFIFO entry. When address entry three data entries, this VMEbus block write been stored total four RXFIFO entries.
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Unlike Target Channel (see page 2-38), VMEbus Slave Channel does retry VMEbus RXFIFO does have enough space hold incoming VMEbus write transaction. Instead, DTACK* response from VMEbus Slave Interface delayed until space becomes available RXFIFO. Since single transfers require entries RXFIFO, entries must freed before VMEbus Slave Interface asserts DTACK*. Similarly, VMEbus Slave Channel requires available RXFIFO entries before acknowledge first data phase MBLT transfer (one entry address phase first data phase). RXFIFO available space subsequent data phases block transfer, then VMEbus Slave Interface delays assertion DTACK* until single entry available next data phase block transfer. Master Interface uses transactions queued RXFIFO generate transactions bus. address phase deletion performed, length transaction corresponds length queued VMEbus transaction. Non-block transfers generated single data beat transactions. Block transfers generated more burst transactions, where length burst transaction programmed (PABS field MAST_CTL register, Table A.81). Universe always packs unpacks data from VMEbus transaction data width programmed into VMEbus slave image (with byte lanes enabled). example, consider VMEbus slave image programmed posted writes that accessed with VMEbus block write transaction. VMEbus write transaction mapped write transaction with byte lanes enabled. (However, note that single transaction from VMEbus mapped with only byte lanes enabled). During block transfers, Universe will pack data full negotiated width bus. This imply that block transfers that begin addresses aligned width different byte lanes enabled during each data beat. error occurs during posted write bus, Universe uses L_CMDERR register (Table A.32) command information transaction (CMDERR [3:0]). L_CMDERR register also records multiple errors have occurred (with M_ERR bit) although actual number given. error qualified with L_STAT bit. address errored transaction latched LAERR register (Table A.33). interrupt generated VMEbus and/or depending upon whether VERR LERR interrupts enabled (see "Bus Error Handling" page 2-58 "Interrupt Handling" page 2-68).
2.2.3.3
Prefetched Block Reads
Prefetching read data occurs VMEbus block transfers (BLT, MBLT) those slave images that have prefetch enable (PREN) (see "VME Slave Images" page 2-50). VMEbus Slave Channel, prefetching supported BLT/MBLT transfers.
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VMEbus Interface
Without prefetching, block read transactions from VMEbus master handled VMEbus Slave Channel coupled reads. This means that each data phase block transfer translated single data beat transaction bus. addition, only amount data requested during relevant data phase fetched from bus. example, block read transaction with data phases VMEbus maps transactions, where each transaction only byte lanes enabled. Note VMEbus lies idle during arbitration time required each transaction, resulting considerable performance degradation. With prefetching enabled, VMEbus Slave Channel uses 32-entry deep RDFIFO provide read data VMEbus with minimum latency. (The RXFIFO same structure RDFIFO. different names used FIFO's roles, only which implement once.) RDFIFO bits wide, with additional bits control information. VMEbus slave image programmed prefetching (see "VME Slave Images" page 2-50), then block read access that image causes VMEbus Slave Channel generate aligned burst read transactions (the size burst read transactions determined setting aligned burst size, PABS MAST_CTL register). These burst read transaction queued RDFIFO data then delivered VMEbus. Note that first data phase provided VMEbus master essentially coupled read, subsequent data phases VMEbus block read delivered from RDFIFO essentially decoupled (see "Prefetched Reads" page 2-60 impact error handling). data width transaction (32-bit 64-bit) depends setting LD64EN VMEbus slave image control register (e.g. Table A.85) capabilities accessed target. Internally, prefetched read data packed bits, regardless width data width original VMEbus block read address information stored with data). Once entry queued RDFIFO, VMEbus Slave Interface delivers data VMEbus, unpacking data necessary with data width original VMEbus block read (e.g. D16, D32). VMEbus Slave Interface continuously delivers data from RDFIFO VMEbus master performing block read transaction. Because data transfer rates exceed those VMEbus, unlikely that RDFIFO will ever unable deliver data VMEbus master. this reason, block read performance VMEbus will similar that observed with block writes. However, should RDFIFO unable deliver data VMEbus master (which happen there considerable traffic target slow response) VMEbus Slave Interface delays DTACK* assertion until entry queued available VMEbus block read. side, prefetching continues long there room another transaction RDFIFO initiating VMEbus block read still active. space required RDFIFO another burst read transaction determined setting aligned burst size (PABS MAST_CTL register, Table A.81). PABS bytes, there must four entries available RDFIFO; aligned burst size bytes, eight
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entries must available, aligned burst size bytes, there must entries available. When there insufficient room RDFIFO hold another burst read, read transactions terminated only resume room becomes available another aligned burst original VMEbus block read still active. When VMEbus block transfer terminates, remaining data RDFIFO purged. Reading side will cross 1024-byte boundary. Master Interface will release FRAME# VMEbus Slave Channel will relinquish internal ownership Master Interface when reaches this boundary. VMEbus Slave Channel will re-request internal ownership Master Interface soon possible, order continue reading from external target. described elsewhere, PABS setting determines much data must available RDFIFO before VMEbus Slave Channel continues reading.) Regardless read request, data width prefetching side full width with byte lanes enabled. request unaligned, then first data beat will have only relevant byte lanes enabled. Subsequent data beats will have full data width with byte lanes enabled. LD64EN VMEbus Slave image, Universe requests asserting REQ64# during address phase. target does respond with ACK64#, subsequent data beats D32. error occurs bus, Universe does translate error condition into BERR* VMEbus. Indeed, Universe does directly error. doing nothing, Universe forces external VMEbus error timer expire.
2.2.3.4
VMEbus Lock Commands (ADOH Cycles)
Universe supports VMEbus lock commands described VME64 specification. Under specification, ADOH cycles used execute lock command (with special code). resource locked VMEbus cannot accessed other resource during tenure VMEbus master. When Universe receives VMEbus lock command, asserts LOCK# addressed resource bus. Master Interface processes this read transfer (with data). subsequent slave VMEbus transactions coupled while Universe owns LOCK#. Note that VMEbus Slave Channel dedicated access Master Interface during locked transaction. Universe holds lock until VMEbus lock command terminated, i.e. when BBSY* negated. Universe accepts ADOH cycles slave images when Universe Master Interface enabled PCI_CSR register) images programmed transactions into Memory Space. event that Target-Abort Master-Abort occurs during locked transaction bus, Universe will relinquish ownership LOCK# accord with Specification. responsibility user verify R_MA R_TA status bits PCI_CSR status register determine whether ownership LOCK# lost.
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Once external VMEbus masters locks bus, Universe will perform transfers until unlocked.
2.2.3.5
VMEbus Read-Modify-Write Cycles (RMW Cycles)
read-modify-write (RMW) cycle allows VMEbus master read from VMEbus slave then write same resource without relinquishing tenure between operations. Each Universe slave images programmed transactions locked transactions. LLRMW enable selected VMEbus slave image control register (e.g. Table A.85), then every non-block slave read mapped coupled locked read. LOCK# will held until negated VMEbus. Every non-block slave read assumed since there possible indication from VMEbus master that single cycle read just read beginning RMW. LLRMW enable Universe receives VMEbus cycle, read write portions cycle will treated independent transactions bus: i.e., read followed write. write coupled decoupled depending state PWEN accessed slave image. Note: There adverse performance impact reads that processed through RMW-capable slave image; this accentuated LOCK# currently owned another master. cycles supported with unaligned cycles. When external VMEbus Master begins cycle, some point read cycle will appear bus. During time between when read cycle occurs when associated write cycle occurs bus, transfers will occur bus.
2.2.3.6 2.2.3.7
Register Accesses Location Monitors
"Registers" page 2-100 full description register mapping register access.
Universe four location monitors support VMEbus broadcast capability. location monitors' image 4-Kbyte image A16, space VMEbus. enabled, access location monitor causes Master Interface generate interrupt.
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Location Monitor Control Register (LM_CTL, Table A.101) controls Universe II's location monitoring. field LM_CTL register enables capability. PGM[1:0] field sets Program/Data code. SUPER[1:0] field LM_CTL register sets Supervisor/User code which Universe responds. VAS[3:0] field LM_CTL register specifies address space that monitored. BS[31:12] field location monitor Base Address Register (LM_BS, Table A.102) specifies lowest address Kbyte range that will decoded location monitor access. While Universe said have four location monitors, they share same LM_CTL LM_BS registers. address spaces A16, respective upper address bits ignored. When access location monitor detected, interrupt generated bus. VMEbus address bits [4:3] determine which Location Monitor will used, hence which four interrupts generate. (See "Location Monitors" page 2-75 details mapping interrupts from location monitor.) location monitors store write data. Read data from location monitors undefined. Location monitors support MBLT transfers. Each Universe VMEbus should programmed monitor same Kbytes addresses VMEbus. Note that Universe access location monitor. Universe accesses (enabled) location monitor, same Universe generates DTACK* VMEbus thereby terminates cycle. This removes necessity system integrator ensuring that there another card enabled generate DTACK*. generation DTACK* happens after Universe decoded responded cycle. location monitor accessed different master, Universe does respond with DTACK*.
2.2.3.8
Generating Configuration Cycles
Configuration cycles generated accessing VMEbus slave image whose Local Address Space field (LAS) Configuration Space. Both Type Type cycles generated handled through same mechanism. Once VMEbus cycle received mapped configuration cycle, Universe compares bits [23:16] incoming address with value stored MAST_CTL Register's Number field (BUS_NO[7:0] Table A.81). bits same BUS_NO field, then TYPE access generated. they same, Type configuration access generated. bus-generated address then becomes unsigned addition incoming VMEbus address VMEbus slave image translation offset.
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Generating Configuration Type Cycles Universe asserts AD[31:11] select device during configuration Type access. perform configuration Type cycle bus: Program field VSIx_CTL Configuration Space, Program VSIx_BS, VSIx_BD registers some suitable value, Program VSIx_TO register Program BUS_NO field MAST_CTL register some value. Perform VMEbus access where: VA[7:2] identifies Register Number will mapped directly AD[7:2], VA[10:8] identifies Function Number will mapped directly AD[10:8], VA[15:11] selects device will mapped AD[31:12] according Table 2.2, VA[23:16] matches BUS_NO MAST_CTL register, Other address bits irrelevant-they mapped bus.
Table Address Line Asserted Function VA[15:11]
VA[15:11]a 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 Address Line Assertedb
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Table Address Line Asserted Function VA[15:11]
VA[15:11]a 01101 01110 01111 10000 10001 10010 10011 10100 Address Line Assertedb
other values VA[15:11] defined must used. Only AD[31:11] asserted; other address lines AD[31:11] negated.
Generating Configuration Type Cycles generate configuration Type cycle VMEbus: Program field VSIx_CTL Configuration Space, Program VSIx_BS, VSIx_BD registers some suitable value, Program VSIx_TO register Program BUS_NO field MAST_CTL register some value. Perform VMEbus access where: VMEbus Address[7:2] identifies Register Number, VMEbus Address[10:8] identifies Function Number, VMEbus Address[15:11] identifies Device Number, VMEbus Address[23:16] does match BUS_NO MAST_CTL register, VMEbus Address[31:24] mapped directly through bus.
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2.2.4
VMEbus Configuration
Universe provides following functions assist initial configuration VMEbus system: First Slot Detector, Register Access Power-up, Auto Slot (two methods). These described separately below.
2.2.4.1
First Slot Detector
specified VME64 specification First Slot Detector module Universe samples BG3IN* immediately after reset determine whether Universe II's host board resides slot VMEbus specification requires that BG[3:0]* lines driven high after reset. This means that card preceded another card VMEbus system, will always sample BG3IN* high after reset. BG3IN* only sampled after reset first card system (there preceding card drive BG3IN* high). BG3IN* sampled logic immediately after reset (due Universe II's internal pull-down), then Universe II's host board slot Universe becomes SYSCON: otherwise, SYSCON module disabled. This mechanism overridden software through clearing setting SYSCON MISC_CTL register (Table A.82). Universe monitors IACK* (rather than IACKIN*) when configured SYSCON. This permits operate SYSCON VMEbus chassis slot other than slot provided there only empty slots left. slot with SYSCON becomes virtual slot
2.2.4.2
VMEbus Register Access Power-up
Universe provides VMEbus slave image that allows access Universe Control Status Registers (UCSR). base address this slave image programmed through VRAI_BS register (Table A.104). power-up, Universe program VRAI_BS VRAI_CTL (Table A.103) registers with information specifying UCSR slave image (see "Power-Up Options" page 2-115). Register access power-up would used systems where Universe II's card CPU, where register access that card needs independent local CPU.
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2.2.5
Automatic Slot Identification
Universe supports types Auto-ID functionality. type uses Auto Slot technique described VME64 specification. other type uses proprietary method developed Systems implemented Tundra SCV64. Neither system identifies geographical addressing, only relative position amongst boards present system (i.e. fourth board versus fourth slot). Auto-ID prevents need jumpers uniquely identify cards system. This can: increase speed system level repairs field, reduce possibility incorrect configurations, reduce number unique spare cards that must stocked. Both methods Auto employed Universe described below.
2.2.5.1
Auto Slot VME64 Specified
VME64 auto cycle (described VME64 Specification) requires power-up that Auto slave generate IRQ2*, negate SYSFAIL*. When Auto slave responds Monarch's IACK cycle, will enable accesses CR/CSR space, provide Status/ID Monarch indicating interrupt Auto-ID request, assert DTACK*, release IRQ2*. Universe participates VME64 auto cycle either automatic semi-automatic mode. fully automatic mode, holds SYSFAIL* asserted until SYSRST* negated. When SYSRST* negated, Universe asserts IRQ2* releases SYSFAIL*. semi-automatic mode, Universe still holds SYSFAIL* asserted until SYSRST* negated. However, when SYSRST* negated, local performs diagnostics local logic sets AUTOID MISC_CTL register (Table A.82). This asserts IRQ2* releases SYSFAIL*. After SYSFAIL* released Universe detects level IACK cycle, responds with STATUS/ID stored level STATID register (which defaults 0xFE).
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Universe programmed that will release SYSFAIL* until SYSFAIL VCSR_CLR register (Table A.125) cleared local logic (SYSFAIL* asserted SYSFAIL VCSR_SET register, Table A.126, power-up). Since system Monarch does service Auto-ID slave until after SYSFAIL* negated, clearing SYSFAIL allows Auto-ID process delayed until completes local diagnostics. Once local diagnostics complete, clears SYSFAIL Auto-ID cycle proceeds. Monarch perform CR/CSR reads writes A[23:19]= 0x00 CR/CSR space re-locate Universe II's CR/CSR base address. Universe Auto-ID Monarch power-up Auto-ID Monarch waits level IACK cycle until after SYSFAIL* goes high. After IACK cycle performed received Status/ID indicating Auto-ID request, monarch software masks IRQ2* that will service other interrupters that interrupt level until current Auto-ID cycle completed), performs access 0x00 CR/CSR space information about Auto-ID slave, moves CR/CSR base address location, unmasks IRQ2* allow service next Auto-ID slave). Universe supports monarch activity through capability level interrupt handler. other activity must handled through software residing board.
2.2.5.2
Auto-ID: Proprietary Tundra Method
Universe uses proprietary Auto-ID scheme this selected power-up option (see "Auto-ID" page 2-118). Tundra proprietary Auto-ID function identifies relative position each board system, without using jumpers on-board information. number generated Auto-ID then used determine board's base address. After system reset (assertion SYSRST*), Auto-ID logic responds first level IACK cycle VMEbus. After level IACK* signal been asserted (either through IRQ1* with synthesized version), Universe slot counts five clocks from start cycle then asserts IACKOUT* second board system (see Figure 2.4). other boards continue counting until they receive IACKIN*, then count four more clocks assert IACKOUT* next board. Finally, last board asserts IACKOUT* pauses until data transfer time-out circuit ends cycle asserting BERR*.
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SYSCLK DS0G IACKG IACKOUTG (CARD IACKOUTG (CARD IACKOUTG (CARD COUNTER VALUE
Figure Timing Auto-ID Cycle Because boards four clocks "wide", value clock counter divided four identify slot which board installed; remainder discarded. Note that since start IACK cycle synchronized SYSCLK, count variation from theoretical value board occur. However, cases value board greater than that board lower slot number. result placed DY4AUTOID [7:0] field DY4DONE (both located MISC_STAT register, Table A.83).
2.2.6
System Controller Functions
When located Slot VMEbus system (see "First Slot Detector" page 2-23), Universe assumes role SYSCON sets SYSCON status MISC_CTL register (Table A.82). accordance with VME64 specification, SYSCON Universe provides: system clock driver, arbitration module, IACK Daisy Chain Driver (DCD), timer.
2.2.6.1
System Clock Driver
Universe provides SYSCLK signal derived from CLK64 when configured SYSCON.
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2.2.6.2
VMEbus Arbiter
When Universe SYSCON, Arbitration Module enabled. Arbitration Module supports following arbitration modes: Fixed Priority Arbitration Mode (PRI), Single Level Arbitration (SGL) subset PRI), Round Robin Arbitration Mode (RRS) (default setting). These with VARB MISC_CTL register (Table A.82). Fixed Priority Arbitration Mode (PRI) this mode, order priority VRBR#[3], VRBR#[2], VRBR#[1], VRBR#[0] defined VME64 specification. Arbitration Module issues Grant (VBGO [3:0]#) highest requesting level. Request higher priority than current owner becomes asserted, Arbitration Module asserts VBCLR# until owner releases (VRBBSY# negated). Single Level Arbitration Mode (SGL) this mode, subset priority mode, requests grants made exclusively level Universe mode this mode. Round Robin Arbitration Mode (RRS) This mode arbitrates levels round robin mode, repeatedly scanning from levels Only grant issued level owner never forced from favor another requester (VBCLR# never asserted). Since only grant issued level each round robin cycle, several scans will required service queue requests level. VMEbus Arbiter Time-out Universe II's VMEbus arbiter programmed time-out requester does assert BBSY* within specified period. This allows BGOUT negated that arbiter continue with other requesters. timer programmed using VARBTO field MISC_CTL register (Table A.82), disabled. default setting timer arbitration time-out timer granularity setting timer means timer timeout little
2.2.6.3
IACK Daisy-Chain Driver Module
IACK Daisy-Chain Driver module enabled when Universe becomes system controller. This module guarantees that IACKIN* will stay high least specified rule VME64 specification.
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2.2.6.4
VMEbus Time-out
programmable timer allows users select VMEbus time-out period. time-out period programmed through VBTO field MISC_CTL register (Table A.82) 16µs, 32µs, 64µs, 1024 disabled. default setting timer VMEbus Timer module asserts VXBERR# VMEbus transaction times (indicated VMEbus data strobes remaining asserted beyond time-out period).
2.2.7
BI-Mode
BI-Mode® (Bus Isolation Mode) mechanism logically isolating Universe from VMEbus. This mechanism useful following purposes: implementing hot-standby systems. system have identically configured boards, BI-Mode. board that BI-Mode fails, BI-Mode while spare board removed from BI-Mode. system diagnostics routine maintenance, fault isolation event card failure, even spare board provided, least faulty board isolated. While BI-Mode, Universe data channels cannot used communicate between VMEbus (Universe mailboxes provide means communication). only traffic permitted Universe registers either through configuration cycles, register image, VMEbus register image, CR/CSR space. IACK cycles will generated responded activity will occur. access other images will result Target-Retry. Access other VMEbus images will ignored. Entering BI-Mode following effects. VMEbus Master Interface becomes inactive. Target Channel coupled accesses will thereafter retried. Target Channel Posted Writes FIFO will continue accept transactions will eventually fill further posted writes will accepted. FIFO will eventually empty fill further activity will take place bus. Universe VMEbus Master will service interrupts while BI-Mode. Universe will respond VMEbus slave, except accesses register image CR/CSR image. Universe will respond interrupt outstanding. VMEbus outputs from Universe will tri-stated, that Universe will driving VMEbus signals. only exception this IACK daisy chains which must remain operation before.
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There four ways cause Universe enter BI-Mode. Universe into BI-Mode: BI-Mode power-up option selected (See "Power-up Option Descriptions" page 2-117 Table 2.22 page 2-116), when SYSRST* RST# asserted time after Universe been powered-up BI-Mode, when VRIRQ# asserted, provided that ENGBI MISC_CTL register been set, when MISC_CTL register set. Note that when Universe BI-Mode, MISC_CTL register (Table A.82) set. Clearing this ends Bi-Mode. There ways remove Universe from BI-Mode: power-up Universe with BI-Mode option (see "BI-Mode" page 2-118), clear MISC_CTL register, which will effective only source BI-Mode longer active. That VRIRQ# still being asserted while ENGBI MISC_CTL register set, then attempting clear MISC_CTL register will effective.
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"PCI Cycles-Overview" below, "Universe Master" page 2-35, "Universe Target" page 2-38.
Interface organized follows:
Universe Interface electrically logically directly connected bus. information concerning different types accesses available, "PCI Target Images" page 2-53.
2.3.1
Cycles-Overview
port Universe operates compliant port with 64-bit multiplexed address/data bus. Universe Interface configured little-endian using address invariant translation when mapping between VMEbus bus. Address invariant translation preserves byte ordering data structure little-endian memory big-endian memory (see Appendix-E). Universe signals described specification with exception SBO# SDONE (since Universe does provide cache support). Universe cycles synchronous, meaning that control input signals externally synchronized clock (CLK). cycles divided into four phases: request, address phase, data transfer, cycle termination.
2.3.1.1
32-Bit Versus 64-Bit
Universe configured with 32-bit 64-bit data power-up (see "PCI Width" page 2-119 directions configure width.)
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Each Universe II's VMEbus slave images programmed that VMEbus transactions mapped 64-bit data Interface (with LD64EN bit, e.g. Table A.85). VMEbus slave image programmed with 64-bit data width Universe powered 64-bit environment, then Universe asserts REQ64# during address phase transaction. target 64-bit capable, then will respond with ACK64# Universe will pack data full width bits) bus. target 64-bit capable, then does assert ACK64# Universe will pack data 32-bit bus. Note that REQ64# will asserted LD64EN 64-bit system independent whether Universe full bits transfer. This result performance degradation because extra clocks required assert REQ64# sample ACK64#. Also, there some performance degradation when accessing 32-bit targets with LD64EN set. this unless there 64-bit targets slave image window. VMEbus slave images programmed 64-bit wide data bus, then Universe operates transparently 32-bit environment. Independent setting LD64EN bit, Universe will never attempt 64-bit cycle powered 32-bit.
2.3.1.2
Request Parking
Universe supports parking. Universe requires will assert REQ# only GNT# currently asserted. When Master Module ready begin transaction GNT# asserted, transfer begins immediately. This eliminates possible clock cycle delay before beginning transaction which would exist Universe implement parking. parking described Section 3.4.3 Specification (Rev. 2.1).
2.3.1.3
Address Phase
transactions initiated asserting FRAME# driving address command information onto bus. VMEbus Slave Channel, Universe calculates address transaction adding translation offset VMEbus address (see "Universe VMEbus Slave" page 2-13). command signals C/BE# lines) contain information about Memory space, cycle type whether transaction read write. Table below gives command type encoding implemented with Universe
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Table Command Type Encoding Transfer Type
C/BE# [3:0] PCI, C/BE# [7:4] non-multiplexed 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Command Type Interrupt Acknowledge Special Cycle Read Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write Invalidate Universe Capability Target/Master Target/Master Target/Master Target/Master Target/Master Target/Master (See Text) (See Text) (See Text)
Memory Read Multiple Memory Read Line transactions aliased Memory Read transactions when Universe accessed target with these commands. Likewise, Memory Write Invalidate aliased Memory Write. initiator, Universe generate Memory Read Multiple never Memory Read Line. targets expected assert DEVSEL# they have decoded access. During Configuration cycle, target selected particular IDSEL. target does respond with DEVSEL# within clocks, Master-Abort generated. role configuration cycles described Specification.
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2.3.1.4
Data Transfer
Acknowledgment data phase occurs first rising clock edge after both IRDY# TRDY# asserted master target, respectively. REQ64# driven during address phase indicate that master wishes initiate 64-bit transaction. target asserts ACK64# able respond 64-bit transaction. Wait cycles introduced either master target deasserting IRDY# TRDY#. write cycles, data valid first rising edge after IRDY# asserted. Data acknowledged target first rising edge with TRDY# asserted. read cycles, data transferred acknowledged first rising edge with both IRDY# TRDY# asserted. single data transfer cycle repeated every time IRDY# TRDY# both asserted. transaction only enters termination phase when FRAME# deasserted (master-initiated termination) STOP# asserted (target-initiated). When both FRAME# IRDY# deasserted (final data phase complete), defined idle.
2.3.1.5
Termination Phase
Interface permits four types terminations: Master-Abort: master negates FRAME# when target responds (DEVSEL# asserted) after clock cycles. Target-Disconnect: termination requested target (STOP# asserted) because unable respond within latency requirements specification requires address phase. Target-disconnect means that transaction terminated after data transferred. Universe will deassert REQ# least clock cycles receives STOP# from target. Target-Retry: termination requested (STOP# asserted) target because cannot currently process transaction. Retry means that transaction terminated after address phase without data transfer. Target-Abort: modified version target-disconnect where target requests termination (asserts STOP#) transaction which will never able respond during which fatal error occurred. Although there fatal error initiating application, transaction completes gracefully, ensuring normal operation other resources.
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2.3.1.6
Parity Checking
Universe both monitors generates parity information using signal. Universe monitors when accepts data master during read target during write. Universe drives when provides data target during read master during write. Universe also drives during address phase transaction when master monitors during address phase when target. both address data phases, signal provides even parity C/BE#[7:0] AD[63:0]. Universe continues with transaction independent parity error reported during transaction. Universe also programmed report address parity errors. does this asserting SERR# signal setting status registers. interrupt generated, regardless whether assertion SERR# enabled, Universe does respond errored access. powered 64-bit environment, Universe uses PAR64 same PAR, except AD[63:32] C/BE[7:4].
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2.3.2
Universe Master
Universe requests mastership through Master Interface. Master Interface available either VMEbus Slave Channel (access from remote VMEbus master) Channel. VMEbus Slave Channel makes internal request Master Interface when: RXFIFO contains complete transaction, sufficient data exists RXFIFO generate transaction length defined programmable aligned burst size (PABS), there coupled cycle request. Channel makes internal request Master Interface when: DMAFIFO room bytes read from PCI, DMAFIFO queued bytes written PCI, block completely queued during write bus. Arbitration between channels Master Interface follows round robin protocol. Each channel given access single transaction. Once that transaction completes, ownership Master Interface granted other channel requires bus. VMEbus Slave Channel Channel each have rules that determine when `done' with Master Interface. VMEbus Slave Channel done under following conditions: entire transaction greater length than programmed aligned burst size) emptied from RXFIFO, coupled cycle complete. Channel done when: boundary programmed into aligned burst size emptied from DMAFIFO during writes bus, boundary programmed into aligned burst size queued DMAFIFO during reads from bus. discussed elsewhere ("Universe VMEbus Slave" page 2-13), access from VMEbus either coupled decoupled. full description operation these data paths, "Universe VMEbus Slave" page 2-13.
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Master Interface generate following command types: Read, Write, Memory Read, Memory Read Multiple, Memory Write, Configuration Read (Type Configuration Write (Type type cycle Universe generates depends which VMEbus slave image accessed programmed. example, slave image might programmed space, another Memory space another Configuration space (see "VME Slave Images" page 2-50). When generating memory transaction, implied addressing either 32-bit 64-bit aligned, depending upon target. When generating transaction, implied addressing 32-bit aligned incoming transactions coupled.
2.3.2.1
Burst Transfers
Universe generates aligned burst transfers some maximum alignment, according programmed aligned burst size (PABS field MAST_CTL register, Table A.81). aligned burst size programmed bytes. Burst transfers will cross programmed boundaries. example, when programmed 32-byte boundaries, burst will begin XXXX_XX20, XXXX_XX40, etc. necessary, burst will begin address with programmed alignment. optimize usage, Universe always attempts transfer data aligned bursts full negotiated width bus. Universe perform 64-bit data transfer over [63:0] lines, operated 64-bit environment against 64-bit capable target initiator. LD64EN must access being made through VMEbus slave image; LD64EN must access being performed with DMA. Universe generates burst cycles emptying RXFIFO (the RXFE status MISC_STAT register when RXFIFO empties), filling RDFIFO (receives block read request from VMEbus master appropriately programmed VMEbus slave image), performing transfers other accesses treated single data beat transactions bus.
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During burst transactions, Universe dynamically enables byte lanes changing signals during each data phase.
2.3.2.2
Termination
Universe performs Master-Abort target does respond within clock cycles. Coupled transactions terminated with Target-Abort Master-Abort terminated VMEbus with BERR*. R_TA R_MA bits PCI_CS register (Table A.3) when Universe receives Target-Abort generates Master-Abort independent whether transaction coupled, decoupled, prefetched, initiated DMA. Universe receives retry from target, then relinquishes re-requests within clock cycles. other transactions processed Master Interface until retry condition cleared. Universe programmed perform maximum number retries using MAXRTRY field MAST_CTL register (Table A.81). When this number retries been reached, Universe responds same does Target-Abort bus. That Universe issue BERR* signal VMEbus. Target-Aborts discussed next paragraphs. VMEbus slave coupled transactions decoupled transactions will encounter delayed DTACK once FIFO fills until condition clears either success retry time-out. error occurs during posted write (see also "Bus Error Handling" page 2-58), Universe uses L_CMDERR register (Table A.32) command information transaction (CMDERR [3:0]) address errored transaction latched LAERR register (Table A.33). L_CMDERR register also records multiple errors occur (with M_ERR bit) although number errors given. error qualified with L_STAT bit. rest transaction will purged from RXFIFO some portion write encounters error. interrupt generated VMEbus and/or depending upon whether VERR LERR interrupts enabled (see "Interrupt Handling" page 2-68). error occurs bus, Universe does translate error condition into BERR* VMEbus. Indeed, Universe does directly error. doing nothing, Universe forces external VMEbus error timer expire.
2.3.2.3
Parity
Universe monitors when accepts data master during read drives when provides data master during write. Universe also drives during address phase transaction when master. both address data phases, signal provides even parity C/BE#[3:0] AD[31:0]. Universe powered 64-bit environment, then PAR64 provides even parity C/BE#[7:4] AD[63:32].
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PERESP PCI_CS register (Table A.3) determines whether Universe responds parity errors master. Data parity errors reported through assertion PERR# PERESP set. Regardless setting these bits, D_PE (Detected Parity Error) PCI_CS register Universe encounters parity error master. DP_D (Data Parity Detected) same register only parity checking enabled through PERESP Universe detects parity error while master (i.e. asserts PERR# during read transaction receives PERR# during write). interrupts generated Universe response parity errors reported during transaction. Parity errors reported Universe through assertion PERR# setting appropriate bits PCI_CS register. PERR# asserted Universe while master, only action takes DP_D. Universe continues with transaction independent parity errors reported during transaction. master, Universe does monitor SERR#. expected that central resource will monitor SERR# take appropriate action.
2.3.3
Universe Target
This section covers following aspects Universe target: "Overview" page 2-38, "Data Transfer" page 2-39, "Coupled Transfers" page 2-42, "Posted Writes" page 2-44, "The Special Cycle Generator" page 2-45, "Using VOWN bit" page 2-48, "Terminations" page 2-49.
2.3.3.1
Overview
Universe becomes target when eight programmed target images registers accessed master (the Universe cannot that master). Register accesses discussed elsewhere (see "Registers" page 2-100); this section describes only those accesses destined VMEbus. When target images accessed, Universe responds with DEVSEL# within clocks FRAME# (making Universe medium speed device, reflected DEVSEL field PCI_CS register).
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target, Universe responds following command types: Read, Write, Memory Read, Memory Write, Configuration Read (Type Configuration Write (Type Memory Read Multiple (aliased Memory Read), Memory Line Read (aliased Memory Read), Memory Write Invalidate (aliased Memory Write). Type Configuration accesses only made Universe II's configuration registers. target images accept Type accesses. Address parity errors reported both PERESP SERR_EN PCI_CS register (Table A.3). Address parity errors reported Universe asserting SERR# signal setting S_SERR (Signalled SERR#) PCI_CS register. Assertion SERR# disabled clearing SERR_EN PCI_CS register. interrupt generated, regardless whether assertion SERR# enabled not, Universe does respond access with DEVSEL#. Typically master transaction times with Master-Abort. Universe accessed validly with REQ64# Memory space 64-bit target, then responds with ACK64# powered 64-bit device.
2.3.3.2
Data Transfer
Read transactions always coupled opposed VMEbus slave reads, which pre-fetched; "Universe VMEbus Slave" page 2-13). Write transactions coupled posted (see Figure below "PCI Target Images" page 2-53). ensure sequential consistency, coupled operations (reads writes) only processed once previously posted write operations have completed (i.e. TXFIFO empty).
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POSTED WRITE DATA TXFIFO
SLAVE INTERFACE
COUPLED READ DATA
COUPLED WRITE DATA
VMEbus MASTER INTERFACE
Figure Target Channel Dataflow
data transfer between VMEbus perhaps best explained Figure below. Universe seen funnel where mouth funnel data width transaction. funnel maximum VMEbus data width programmed into target image (VDW target image control register). example, consider 32-bit transaction accessing target image with bits. data beat with byte lanes enabled will broken into 16-bit cycles VMEbus. target image also programmed with block transfers enabled, 32-bit data beat will result block transfer VMEbus. Write data unpacked VMEbus read data packed data width. data width data beat same maximum data width target image, then Universe maps data beat equivalent VMEbus cycle. example, consider 32-bit transaction accessing target image with bits. data beat with byte lanes enabled translated single 32-bit cycle VMEbus. general rule, data width less than VMEbus data width then there packing unpacking between buses. only exception this during 32-bit multi-data beat transactions target image programmed with maximum VMEbus data width bits. this case, packing/unpacking occurs make maximum full bandwidth both buses. Only aligned VMEbus transactions generated, requested data beat unaligned non-contiguous byte enables, then broken into multiple aligned VMEbus transactions wider than programmed VMEbus data width. example, consider three-byte data beat 32-bit bus) accessing target image with bits. three-byte data beat will broken into aligned VMEbus cycles: single-byte cycle double-byte cycle (the ordering cycles depends arrangement byte enables data beat). above example target image bits, then three-byte data beat will broken into three single-byte VMEbus cycles.
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Data width transaction
Maximum data width programmed into target image Data width exceeds maximum data width target image
Data width fits with maximum data width target image
WRITE (UNPACKING)
READ (PACKING) SIDE VMEBUS SIDE
Figure Influence Transaction Data Width Target Image Data Width Data Packing/Unpacking
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2.3.3.3
Coupled Transfers
Target Channel supports "coupled transfers". nutshell, coupled transfer through Target Channel transfer between where Universe maintains ownership VMEbus from beginning transfer (and possibly longer), where termination cycle VMEbus relayed directly initiator normal manner (i.e., Target-Abort, Target Completion), rather than through error-logging interrupts. default, target images coupled transfers. Coupled transfers typically cause Universe through three phases: Coupled Request Phase, Coupled Data-Transfer Phase, then Coupled Wait Phase. When external Master attempts data transfer through slave image programmed coupled cycles, then: Universe currently owns VMEbus, Target Channel moves directly Coupled Data-Transfer Phase; otherwise, Universe moves Coupled Request Phase. These three phases described below. Note that once Coupled Request phase begun, posted writes traverse Target Channel without affecting coupled transfers. Coupled Request Phase During Coupled Request Phase, Universe will attempt acquire VMEbus. first must empty posted writes pending TXFIFO, obtain ownership internal VMEbus Master Interface (see "VMEbus Release" page more details Universe shares VMEbus between channels.) Target Channel retries master until Target Channel obtains ownership VMEbus. Every time issues such retry, Universe restarts Coupled Request Timer, which counts down period clock cycles. Coupled Request Timer co-determines long Universe maintains VMEbus since last time Universe issued Target-Retry during Coupled Request Phase: Universe will release terminate attempt obtain) VMEbus coupled transfer attempted before Coupled Request Timer expires. Usually, external Master will attempt coupled cycle once Universe acquired VMEbus during Coupled Request Phase. this case Universe will proceed "Coupled Data-Transfer Phase". addresss matching performed verify whether current coupled cycle matches initiating coupled cycle. external Master requests transfer with illegal byte lane combination, Universe will exit "Coupled Request Phase."
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Coupled Data-Transfer Phase beginning Coupled Data-Transfer Phase, Universe latches command, byte enable, address case write) data. Regardless state FRAME#, Universe retries1 master, then performs transaction VMEbus. Universe continues signal Target-Retry external master until transfer completes (normally abnormally) VMEbus. transfer completes normally VMEbus, then case read, data transmitted master. data phase coupled transfer requires packing unpacking VMEbus, acknowledgment transfer given master until data been packed unpacked VMEbus. Successful termination signalled bus-the data beat acknowledged with Target-Disconnect, forcing multi-beat transfers into single beat. this point, Universe enters Coupled Wait Phase. error signalled VMEbus error occurs during packing unpacking, then transaction terminated with Target-Abort. also "Data Transfer" page 2-39. Coupled Wait Phase Coupled Wait Phase entered after successful completion Coupled Data-Transfer phase. Coupled Wait Phase allows consecutive coupled transactions occur without releasing VMEbus. coupled transaction attempted while Universe Coupled Wait Phase, Universe will move directly Coupled Data-Transfer Phase without re-entering Coupled Request Phase. Coupled Window Timer determines maximum duration Coupled Wait Phase. When Universe enters Coupled Wait Phase, Coupled Window Timer starts. period this timer specified clocks programmable through field LMISC register (Table A.30). this field programmed 0000, Universe will early release BBSY* during coupled transfer VMEbus will enter "Coupled Wait Phase." this case, VMEbus ownership relinquished immediately Target Channel after each coupled cycle. Once timer associated with Coupled Wait Phase expires, Universe will release VMEbus release mode RWD, release mode there pending (external) request VMEbus.
latency requirements described revision Specification) require that only clock cycles elapse between first second data beat transaction. Since Universe cannot guarantee that data acknowledgment will received from VMEbus time meet these latency requirements, Universe performs target-disconnect after first data beat every coupled write transaction.
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2.3.3.4
Posted Writes
Posted writes enabled target image setting PWEN control register target image (see "PCI Target Images" page 2-53). Write transactions relayed from VMEbus through 32-entry deep TXFIFO. TXFIFO allows each entry contain address bits (with extra bits provided command information), data bits. each posted write transaction received from bus, Target Interface queues address entry FIFO. This entry contains translated address space mapped VMEbus attributes information relevant particular target image that been accessed (see "PCI Target Images" page 2-53). this reason, re-programming target image attributes will only reflected TXFIFO entries queued after re-programming. Transactions queued before re-programming delivered VMEbus with target image attributes that were before re-programming. Caution: Care should taken before reprogramming target images from while that image being accessed from opposite bus. there chance image accessed while being reprogrammed, disable image first before changing image attributes.
Once address phase queued TXFIFO entry, Target Interface pack subsequent data beats full 64-byte width before queuing data into entries TXFIFO. 32-bit transfers Universe TXFIFO will accept single burst address phase data phases when empty. 64-bit PCI, TXFIFO will accept single burst address phase data phases when empty. improve utilization, TXFIFO does accept address phase does have room burst address phase bytes data. TXFIFO does have enough space aligned burst, then posted write transaction terminated with Target-Retry immediately after address phase. When external Master posts writes Target Channel Universe Universe will issue disconnect implied address will cross 256-byte boundary. Before transaction delivered VMEbus from TXFIFO, Target Channel must obtain ownership VMEbus Master Interface. Ownership VMEbus Master Interface granted different channels round robin basis (see "VMEbus Release" page 2-8). Once Target Channel obtains VMEbus through VMEbus Master Interface, manner which TXFIFO entries delivered depends programming VMEbus attributes target image (see "PCI Target Images" page 2-53). example, VMEbus data width programmed bits, block transfers disabled, then each data entry TXFIFO corresponds four transactions VMEbus.
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block transfers enabled target image, then each transaction queued TXFIFO, independent length, delivered VMEbus block transfer. This means that single data beat transaction queued TXFIFO, appears VMEbus single data phase block transfer. master attempting coupled transactions retried while TXFIFO contains data. posted writes continually written Target Channel, FIFO does empty, coupled transactions Target Channel will proceed will continually retried. This presents potential starvation scenario.
2.3.3.5
Special Cycle Generator
Special Cycle Generator Target Channel Universe used conjunction with Target Images generate read-modify-write (RMW) Address Only With Handshake (ADOH) cycles. address programmed into SCYC_ADDR register (Table A.26), address space specified field SCYC_CTL register (Memory I/O), must appear during address phase transfer Special Cycle Generator perform function. Whenever this address matches address SCYC_ADDR register, Universe does respond with ACK64# (since Special Cycle Generator only processes 32-bit cycles). cycle that produced VMEbus any) will attributes programmed into Image Control Register image that contains address programmed SCYC_ADDR register. Special Cycle Generator configured through register fields shown Table described below. Table Register Fields Special Cycle Generator
Field 32-bit address Address Space Special cycle 32-bit enable 32-bit compare 32-bit swap Register Bits ADDR Table A.26 Table A.25 SCYC[1:0] Table A.25 [31:0] Table A.27 [31:0] Table A.28 [31:0] Table A.29 Description specifies target image address specifies whether address specified ADDR field lies memory space disabled, ADOH mask select bits modified VMEbus read data during cycle data which compared VMEbus read data during cycle data which swapped with VMEbus read data written original address during cycle
Tundra Semiconductor Corporation
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following sections describe specific properties each transfer types: ADOH. Read-Modify-Write When SCYC field RMW, read access specified address (SCYC_ADDR register) will result cycle VMEbus (provided constraints listed below satisfied). cycles VMEbus consist single read followed single write operation. data from read portion VMEbus returned read data bus. cycles make three 32-bit registers (see Table above). enable field mask which lets user specify which bits read data compared modified cycle. This enable setting completely independent cycle data width, which determined data width initiating transaction. During RMW, VMEbus read data bitwise compared with SCYC_CMP SCYC_EN registers. valid compared enabled bits then swapped using SCYC_SWP register. Each enabled that compares true swapped with corresponding 32-bit swap field. false comparison results original being written back. Once cycle completes, VMEbus read data returned waiting master cycle terminates. Certain restrictions apply cycles. write transaction initiated VMEbus address when special cycle field (SCYC Table A.25) RMW, then standard write occurs with attributes programmed target image other words, special cycle generator used). Universe performs packing unpacking data VMEbus during operation. following constraints must also met. Special Cycle Generator will only generate accessed with 8-bit, aligned 16-bit, aligned 32-bit read cycle. Special Cycle Generator will only generate size request less than equal programmed VMEbus Maximum Datawidth. destination VMEbus address space must A16, A32. event that Special Cycle Generator accessed with read cycle that does meet three criteria described above, Universe generates Target-Abort. Thus user's responsibility ensure that Universe correctly programmed accessed with correct byte-lane information.
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Lock Cycles-Exclusive Access VMEbus Resources Lock cycle used combination with VOWN MAST_CTL register lock resources VMEbus. Lock cycle used Universe inform resource that locked cycle intended that VMEbus slave prevent accesses from other masters different bus). VOWN MAST_CTL register ensure that when Universe acquires VMEbus, only master given access (until VOWN cleared). also necessary master have locked Universe using LOCK# signal. When SCYC field Lock, write access specified VMEbus address will result Lock cycle VMEbus. Lock cycle coupled: cycle does complete until completes VMEbus. Reads specified address translate VMEbus reads standard fashion. data during writes ignored. code generated VMEbus determined target image definition specified VMEbus address (see Table 2.12 page 56). However, after Lock cycle complete, there guarantee that Universe will remain VMEbus master unless VOWN bit. Universe loses VMEbus ownership, then VMEbus resouce will longer remain locked. following procedure required lock VMEbus ADOH cycle: there more than master bus, necessary LOCK# ensure that master driving ADOH cycle sole access Universe registers VMEbus,) program VOWN MAST_CTL register value (see "Using VOWN bit" below), wait until VOWN_ACK MAST_CTL register value generate ADOH cycle with Special Cycle Generator, perform transactions locked VMEbus, release VMEbus programming VOWN MAST_CTL register value wait until VOWN_ACK MAST_CTL register value event that BERR* asserted VMEbus once Universe locked owns VMEbus, responsibility user release ownership VMEbus programming VOWN MAST_CTL register value
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