2-Port PCI-to-PCI Bridge REVISION 1.02 2380 Bering Drive, Jo
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PI7C8154
2-Port PCI-to-PCI Bridge
REVISION 1.02
2380 Bering Drive, Jose, 95131 Telephone: 1-877-PERICOM, (1-877-737-4266) Fax: 408-435-1100 Email: solutions@pericom.com Internet: http://www.pericom.com
PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
LIFE SUPPORT POLICY Pericom Semiconductor Corporation's products authorized critical components life support devices systems unless specific written agreement pertaining such intended executed between manufacturer officer PSC. Life support devices system devices systems which: intended surgical implant into body Support sustain life whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness. Pericom Semiconductor Corporation reserves right make changes products specifications time, without notice, order improve design performance supply best possible product. Pericom Semiconductor does assume responsibility circuitry described other than circuitry embodied Pericom Semiconductor product. Company makes representations that circuitry described herein free from patent infringement other rights third parties which result from use. license granted implication otherwise under patent, patent rights other rights, Pericom Semiconductor Corporation. other trademarks their respective companies. Page 2003 Revision 1.02
PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
REVISION HISTORY
Date 12/5/02 2/20/03 Revision Number 1.00 1.01 Description First Release Data Sheet Correct designation errors/omissions: page S_PAR64 should page S_REQ64_L should page S_ACK64_L should page should SM66EN page should PMEENA_L Added PMEENA_L description page Added GPIO register descriptions [31:8] offset Added Signal Types configuration register (section 12.1)
05/16/03
1.02
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TABLE CONTENTS
SIGNAL DEFINITIONS SIGNAL TYPES SIGNALS 1.2.1 PRIMARY INTERFACE SIGNALS 1.2.2 PRIMARY INTERFACE SIGNALS 64-BIT EXTENSION 1.2.3 SECONDARY INTERFACE SIGNALS 1.2.4 SECONDARY INTERFACE SIGNALS 64-BIT EXTENSION 1.2.5 CLOCK SIGNALS 1.2.6 MISCELLANEOUS SIGNALS. 1.2.7 GENERAL PURPOSE INTERFACE SIGNALS 1.2.8 JTAG BOUNDARY SCAN SIGNALS 1.2.9 POWER GROUND. LIST SIGNAL DEFINITIONS TYPES TRANSACTIONS SINGLE ADDRESS PHASE. DUAL ADDRESS PHASE. DEVICE SELECT (DEVSEL_L) GENERATION. DATA PHASE. WRITE TRANSACTIONS 2.6.1 MEMORY WRITE TRANSACTIONS. 2.6.2 MEMORY WRITE INVALIDATE 2.6.3 DELAYED WRITE TRANSACTIONS. 2.6.4 WRITE TRANSACTION ADDRESS BOUNDARIES. 2.6.5 BUFFERING MULTIPLE WRITE TRANSACTIONS. 2.6.6 FAST BACK-TO-BACK WRITE TRANSACTIONS READ TRANSACTIONS 2.7.1 PREFETCHABLE READ TRANSACTIONS. 2.7.2 NON-PREFETCHABLE READ TRANSACTIONS. 2.7.3 READ PREFECTCH ADDRESS BOUNDARIES. 2.7.4 DELAYED READ REQUESTS 2.7.5 DELAYED READ COMPLETION TARGET 2.7.6 DELAYED READ COMPLETION INITIATOR BUS. 2.7.7 FAST BACK-TO-BACK READ TRANSACTION CONFIGURATION TRANSACTIONS 2.8.1 TYPE ACCESS PI7C8154 2.8.2 TYPE TYPE CONVERSION 2.8.3 TYPE TYPE FORWARDING. 2.8.4 SPECIAL CYCLES 64-BIT OPERATION 2.9.1 64-BIT 32-BIT TRANSACTIONS INITIATED PI7C8154. 2.9.2 64-BIT TRANSACTIONS ADDRESS PHASE 2.9.3 64-BIT TRANSACTIONS DATA PHASE. 2.9.4 64-BIT TRANSACTIONS RECEIVED PI7C8154 2.9.5 64-BIT TRANSACTIONS SUPPORT DURING RESET 2.10 TRANSACTION FLOW THROUGH. 2.11 TRANSACTION TERMINATION. 2.11.1 MASTER TERMINATION INITIATED PI7C8154. 2.11.2 MASTER ABORT RECEIVED PI7C8154. Page 2003 Revision 1.02
PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 2.11.3 2.11.4 TARGET TERMINATION RECEIVED PI7C8154 TARGET TERMINATION INITIATED PI7C8154
ADDRESS DECODING. ADDRESS RANGES ADDRESS DECODING 3.2.1 BASE LIMIT ADDRESS REGISTER. 3.2.2 MODE. MEMORY ADDRESS DECODING. 3.3.1 MEMORY-MAPPED BASE LIMIT ADDRESS REGISTERS 3.3.2 PREFETCHABLE MEMORY BASE LIMIT ADDRESS REGISTERS 3.3.3 PREFETCHABLE MEMORY 64-BIT ADDRESSING REGISTERS. SUPPORT 3.4.1 MODE. 3.4.2 SNOOP MODE.
TRANSACTION ORDERING. TRANSACTIONS GOVERNED ORDERING RULES GENERAL ORDERING GUIDELINES. ORDERING RULES DATA SYNCHRONIZATION
ERROR HANDLING. ADDRESS PARITY ERRORS DATA PARITY ERRORS. 5.2.1 CONFIGURATION WRITE TRANSACTIONS CONFIGURATION SPACE. 5.2.2 READ TRANSACTIONS 5.2.3 DELAYED WRITE TRANSACTIONS. 5.2.4 POSTED WRITE TRANSACTIONS. DATA PARITY ERROR REPORTING SUMMARY SYSTEM ERROR (SERR_L) REPORTING
EXCLUSIVE ACCESS CONCURRENT LOCKS ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8154. 6.2.1 LOCKED TRANSACTIONS DOWNSTREAM DIRECTION 6.2.2 LOCKED TRANSACTION UPSTREAM DIRECTION ENDING EXCLUSIVE ACCESS
ARBITRATION. PRIMARY ARBITRATION. SECONDARY ARBITRATION 7.2.1 SECONDARY ARBITRATION USING INTERNAL ARBITER. 7.2.2 PREEMPTION 7.2.3 SECONDARY ARBITRATION USING EXTERNAL ARBITER. 7.2.4 PARKING.
GENERAL PURPOSE INTERFACE. GPIO CONTROL REGISTERS SECONDARY CLOCK CONTROL. LIVE INSERTION PRIMARY SECONDARY CLOCK INPUTS Page 2003 Revision 1.02
CLOCKS
PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 11.1 11.2 11.3 SECONDARY CLOCK OUTPUTS. POWER MANAGEMENT RESET. PRIMARY INTERFACE RESET SECONDARY INTERFACE RESET CHIP RESET CONFIGURATION REGISTERS.
12.1 CONFIGURATION REGISTER. 12.1.1 SIGNAL TYPES 12.1.2 VENDOR REGISTER OFFSET 00h. 12.1.3 DEVICE REGISTER OFFSET 12.1.4 COMMAND REGISTER OFFSET 04h. 12.1.5 STATUS REGISTER OFFSET 12.1.6 REVISION REGISTER OFFSET 12.1.7 CLASS CODE REGISTER OFFSET 08h. 12.1.8 CACHE LINE SIZE REGISTER OFFSET 12.1.9 PRIMARY LATENCY TIMER REGISTER OFFSET 12.1.10 HEADER TYPE REGISTER OFFSET 0Ch. 12.1.11 PRIMARY NUMBER REGISTSER OFFSET 18h. 12.1.12 SECONDARY NUMBER REGISTER OFFSET 12.1.13 SUBORDINATE NUMBER REGISTER OFFSET 18h. 12.1.14 SECONDARY LATENCY TIMER REGISTER OFFSET 12.1.15 BASE ADDRESS REGISTER OFFSET 12.1.16 LIMIT ADDRESS REGISTER OFFSET 12.1.17 SECONDARY STATUS REGISTER OFFSET 1Ch. 12.1.18 MEMORY BASE ADDRESS REGISTER OFFSET 12.1.19 MEMORY LIMIT REGISTER OFFSET 20h. 12.1.20 PEFETCHABLE MEMORY BASE ADDRESS REGISTER OFFSET 12.1.21 PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER OFFSET 12.1.22 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER OFFSET 12.1.23 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER OFFSET 2Ch. 12.1.24 BASE ADDRESS UPPER 16-BITS REGISTER OFFSET 12.1.25 LIMIT ADDRESS UPPER 16-BITS REGISTER OFFSET 30h. 12.1.26 POINTER REGISTER OFFSET 34h. 12.1.27 INTERRUPT LINE REGISTER OFFSET 12.1.28 INTERRUPT REGISTER OFFSET 3Ch. 12.1.29 BRIDGE CONTROL REGISTER OFFSET 12.1.30 DIAGNOSTIC CHIP CONTROL REGISTER OFFSET 40h. 12.1.31 ARBITER CONTROL REGISTER OFFSET 40h. 12.1.32 EXTENDED CHIP CONTROL REGISTER OFFSET 48h. 12.1.33 SECONDARY ARBITER PREEMPTION CONTROL REGISTER OFFSET 12.1.34 P_SERR_L EVENT DISABLE REGISTER OFFSET 64h. 12.1.35 GPIO DATA REGISTER OFFSET 64h. 12.1.36 GPIO CONTROL REGISTER OFFSET 12.1.37 SECONDARY CLOCK CONTROL REGISTER OFFSET 12.1.38 P_SERR_L STATUS REGISTER OFFSET 12.1.39 PORT OPTION REGISTER OFFSET 12.1.40 RETRY COUNTER REGISTER OFFSET Page 2003 Revision 1.02
PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 12.1.41 12.1.42 12.1.43 12.1.44 12.1.45 12.1.46 12.1.47 12.1.48 PRIMARY MASTER TIMEOUT COUNTER OFFSET SECONDARY MASTER TIMEOUT COUNTER OFFSET CAPABILITY REGISTER OFFSET DCh. NEXT ITEM POINTER REGISTER OFFSET POWER MANAGEMENT CAPABILITIES REGISTER OFFSET POWER MANAGEMENT DATA REGISTER OFFSET E0h. SUPPORT EXTENSIONS REGISTER OFFSET E2h. DATA REGISTER OFFSET E3h.
BRIDGE BEHAVIOR.
13.1 BRIDGE ACTIONS VARIOUS CYCLE TYPES. 13.2 ABNORMAL TERMINATION (INITIATED BRIDGE MASTER). 13.2.1 MASTER ABORT. 13.2.2 PARITY ERROR REPORTING 13.2.3 REPORTING PARITY ERRORS 13.2.4 SECONDARY IDSEL MAPPING IEEE 1149.1 COMPATIBLE JTAG CONTROLLER. 14.1 BOUNDARY SCAN ARCHITECTURE 14.1.1 PINS 14.1.2 INSTRUCTION REGISTER 14.2 BOUNDARY SCAN INSTRUCTION 14.3 TEST DATA REGISTERS 14.4 BYPASS REGISTER 14.5 BOUNDARY-SCAN REGISTER. 14.6 CONTROLLER 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 16.1 16.2 ELECTRICAL TIMING SPECIFICATIONS. MAXIMUM RATINGS SPECIFICATIONS SPECIFICATIONS 66MHZ SIGNALING TIMING. 33MHZ SIGNALING TIMING. RESET TIMING. GPIO TIMING (66MHZ 33MHZ) JTAG TIMING POWER CONSUMPTION. PACKAGE INFORMATION. 304-BALL PBGA PACKAGE DIAGRAM. ORDERING INFORMATION.
LIST TABLES
Table Table Table Table Table Table Table Table LIST 304-BALL PBGA. TRANSACTIONS WRITE TRANSACTION FORWARDING WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES. READ PREFETCH ADDRESS BOUNDARIES READ TRANSACTION PREFETCHING. DEVICE NUMBER IDSEL S_AD MAPPING DELAYED WRITE TARGET TERMINATION RESPONSE. Page 2003 Revision 1.02
PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Table RESPONSE POSTED WRITE TARGET TERMINATION Table RESPONSE DELAYED READ TARGET TERMINATION Table SUMMARY TRANSACTION ORDERING Table SETTING PRIMARY INTERFACE DETECTED PARITY ERROR (bit Offset 04h) Table SETTING SECONDARY INTERFACE DETECTED PARITY ERROR Table SETTING PRIMARY INTERFACE DATA PARITY DETECTED (bit Offset 04h) Table SETTING SECONDARY INTERFACE DATA PARITY DETECTED Table ASSERTION P_PERR_L. Table ASSERTION S_PERR_L Table ASSERTION P_SERR_L DATA PARITY ERRORS. Table GPIO OPERATION Table GPIO SERIAL DATA FORMAT. Table 10-1 POWER MANAGEMENT TRANSITIONS Table 12-1 CONFIGURATION SPACE Table 14-1 PINS Table 14-2 JTAG BOUNDARY REGISTER ORDER
LIST FIGURES
Figure SECONDARY ARBITER EXAMPLE Figure 14-1 TEST ACCESS PORT BLOCK DIAGRAM. Figure 15-1 SIGNAL TIMING MEASUREMENT CONDITIONS Figure 16-1 304-BALL PBGA PACKAGE OUTLINE.
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
SIGNAL DEFINITIONS
SIGNAL TYPES
Signal Type Description Input Only Output Only Power Tri-State bi-directional Sustained Tri-State. Active signal must pulled HIGH cycle when deasserting. Open Drain
SIGNALS
Note: Signal names that with "_L" active LOW.
1.2.1
PRIMARY INTERFACE SIGNALS
Name P_AD[31:0] AA1, AA3, AB3, AA4, AB8, AA8, AC9, AB9, AA9, AC10, AA10, Y11, AB11, AA11, AA12, AB12, AB13, AA13, Y13, AA14 Type Description Primary Address Data: Multiplexed address data bus. Address indicated P_FRAME_L assertion. Write data stable valid when P_IRDY_L asserted read data stable valid when P_TRDY_L asserted. Data transferred rising clock edges when both P_IRDY_L P_TRDY_L asserted. During idle, PI7C8154 drives P_AD[31:0] valid logic level when P_GNT_L asserted. Primary Command/Byte Enables: Multiplexed command field byte enable field. During address phase, initiator drives transaction type these pins. After that, initiator drives byte enables during data phases. During idle, PI7C8154 drives P_CBE[3:0] valid logic level when P_GNT_L asserted. Primary Parity. P_PAR even parity P_AD[31:0] P_CBE[3:0] (i.e. even number 1's). P_PAR valid stable cycle after address phase (indicated assertion P_FRAME_L) address parity. write data phases, P_PAR valid clock after P_IRDY_L asserted. read data phase, P_PAR valid clock after P_TRDY_L asserted. Signal P_PAR tristated cycle after P_AD lines tristated. During idle, PI7C8154 drives P_PAR valid logic level when P_GNT_L asserted.
P_CBE[3:0]
AB4, AA7, AC11
P_PAR
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name P_FRAME_L Type Description Primary FRAME (Active LOW). Driven initiator transaction indicate beginning duration access. deassertion P_FRAME_L indicates final data phase requested initiator. Before being tri-stated, driven de-asserted state cycle. Primary IRDY (Active LOW). Driven initiator transaction indicate ability complete current data phase primary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven de-asserted state cycle. Primary TRDY (Active LOW). Driven target transaction indicate ability complete current data phase primary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven de-asserted state cycle. Primary Device Select (Active LOW). Asserted target indicating that device accepting transaction. master, PI7C8154 waits assertion this signal within cycles P_FRAME_L assertion; otherwise, terminate with master abort. Before tri-stated, driven de-asserted state cycle. Primary STOP (Active LOW). Asserted target indicating that target requesting initiator stop current transaction. Before tri-stated, driven de-asserted state cycle. Primary LOCK (Active LOW). Asserted initiator, clock cycle after first address phase transaction, attempting perform operation that take more than transaction complete. Primary Select. Used chip select line Type configuration access PI7C8154 configuration space. Primary Parity Error (Active LOW). Asserted when data parity error detected data received primary interface. Before being tri-stated, driven deasserted state cycle. Primary System Error (Active LOW). driven device indicate system error condition. PI7C8154 drives this Address parity error Posted write data parity error target Secondary S_SERR_L asserted Master abort during posted write transaction Target abort during posted write transaction Posted write transaction discarded Delayed write request discarded Delayed read request discarded Delayed transaction master timeout This signal requires external pull-up resistor proper operation.
P_IRDY_L
P_TRDY_L
P_DEVSEL_L
P_STOP_L
P_LOCK_L
P_IDSEL P_PERR_L
P_SERR_L
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name P_REQ_L Type Description Primary Request (Active LOW): This asserted PI7C8154 indicate that wants start transaction primary bus. PI7C8154 de-asserts this least clock cycles before asserting again. Primary Grant (Active LOW): When asserted, PI7C8154 access primary bus. During idle P_GNT_L asserted, PI7C8154 will drive P_AD, P_CBE, P_PAR valid logic levels. Primary RESET (Active LOW): When P_RESET_L active, signals should asynchronously tri-stated. Primary Interface 66MHz Operation. This input used specify PI7C8154 capable running 66MHz. 66MHz operation Primary bus, this signal should pulled "HIGH". 33MHz operation Primary bus, this signal should pulled "LOW". this condition, S_M66EN will driven "LOW", forcing secondary 33MHz also.
P_GNT_L
P_RESET_L P_M66EN
AB10
1.2.2
PRIMARY INTERFACE SIGNALS 64-BIT EXTENSION
Name P_AD[63:32] AA16, AB16, AA17, AB17, Y17, AB18, AC18, AA18, AC19, AA19, AB20, Y19, AA20, AB21, AC21, AA21, Y20, AA23, Y21, W20, Y23, W21, W23, W22, V21, V23, V22, U23, U20, U22, T23, Type Description Primary Upper 32-bit Address Data: Multiplexed address data providing additional bits primary. When dual address command used P_REQ64_L asserted, initiator drives upper bits 64-bit address. Otherwise, these bits undefined driven valid logic levels. During data phase transaction, initiator drives upper bits 64-bit write data, target drives upper bits 64-bit read data, when P_REQ64_L P_ACK64_L both asserted. Otherwise, these bits pulled valid logic level through external resistors. Primary Upper 32-bit Command/Byte Enables: Multiplexed command field byte enable field. During address phase, when dual address command used P_REQ64_L asserted, initiator drives transaction type these pins. Otherwise, these bits undefined, initiator drives valid logic level onto pins. read write transactions, initiator drives these bits P_AD[63:32] data bits when P_REQ64_L P_ACK64_L both asserted. When driven, these bits pulled valid logic level through external resistors.
P_CBE[7:4]
AA15, AB15, Y15, AC15
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name P_PAR64 Type Description Primary Upper 32-bit Parity: P_PAR64 carries even parity P_AD[63:32] P_CBE[7:4] both address data phases. P_PAR64 driven initiator valid cycle after first address phase when dual address command used P_REQ64_L asserted. P_PAR64 valid clock cycle after second address phase dual address transaction when P_REQ64_L asserted. P_PAR64 valid cycle after valid data driven when both P_REQ64_L P_ACK64_L asserted that data phase. P_PAR64 driven device driving read write data cycle after P_AD lines driven. P_PAR64 tri-stated cycle after P_AD lines tri-stated. Devices receive data sample P_PAR64 input check possible parity errors during 64-bit transactions. When driven, P_PAR64 pulled valid logic level through external resistors. Primary 64-bit Transfer Request: P_REQ64_L asserted initiator indicate that initiator requesting 64-bit data transfer. P_REQ64_L same timing P_FRAME_L. When P_REQ64_L asserted during reset, 64-bit data path supported. When P_REQ64_L HIGH during reset, PI7C8154 drives P_AD[63:32], P_CBE[7:4], P_PAR64 valid logic levels. When deasserting, P_REQ64_L driven deasserted state cycle then sustained external pull-up resistor. Primary 64-bit Transfer Acknowledge: P_ACK64_L asserted target only when P_REQ64_L asserted initiator indicate target's ability transfer data using bits. P_ACK64_L same timing P_DEVSEL_L. When deasserting, P_ACK64_L driven deasserted state cycle then sustained external pull-up resistor.
P_REQ64_L
AC14
P_ACK64_L
AB14
1.2.3
SECONDARY INTERFACE SIGNALS
Name S_AD[31:0] C13, B13, A13, D13, C14, B14, C15, B15, C16, B16, C17, B17, D17, A17, B18, Type Description Secondary Address/Data: Multiplexed address data bus. Address indicated S_FRAME_L assertion. Write data stable valid when S_IRDY_L asserted read data stable valid when S_IRDY_L asserted. Data transferred rising clock edges when both S_IRDY_L S_TRDY_L asserted. During idle, PI7C8154 drives S_AD[31:0] valid logic level when S_GNT_L asserted respectively.
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name S_CBE[3:0] C12, Type Description Secondary Command/Byte Enables: Multiplexed command field byte enable field. During address phase, initiator drives transaction type these pins. initiator then drives byte enables during data phases. During idle, PI7C8154 drives S_CBE[3:0] valid logic level when internal grant asserted. Secondary Parity: S_PAR even parity S_AD[31:0] S_CBE[3:0] (i.e. even number 1's). S_PAR valid stable cycle after address phase (indicated assertion S_FRAME_L) address parity. write data phases, S_PAR valid clock after S_IRDY_L asserted. read data phase, S_PAR valid clock after S_TRDY_L asserted. Signal S_PAR tristated cycle after S_AD lines tristated. During idle, PI7C8154 drives S_PAR valid logic level when internal grant asserted. Secondary FRAME (Active LOW): Driven initiator transaction indicate beginning duration access. deassertion S_FRAME_L indicates final data phase requested initiator. Before being tri-stated, driven de-asserted state cycle. Secondary IRDY (Active LOW): Driven initiator transaction indicate ability complete current data phase secondary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven deasserted state cycle. Secondary TRDY (Active LOW): Driven target transaction indicate ability complete current data phase secondary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven deasserted state cycle. Secondary Device Select (Active LOW): Asserted target indicating that device accepting transaction. master, PI7C8154 waits assertion this signal within cycles S_FRAME_L assertion; otherwise, terminate with master abort. Before tri-stated, driven deasserted state cycle. Secondary STOP (Active LOW): Asserted target indicating that target requesting initiator stop current transaction. Before tri-stated, driven de-asserted state cycle. Secondary LOCK (Active LOW): Asserted initiator, clock cycle after first address phase transaction, when propagating locked transaction downstream. PI7C8154 does propagate locked transactions upstream. Secondary Parity Error (Active LOW): Asserted when data parity error detected data received secondary interface. Before being tri-stated, driven deasserted state cycle.
S_PAR
S_FRAME_L
S_IRDY_L
S_TRDY_L
S_DEVSEL_L
S_STOP_L
S_LOCK_L
S_PERR_L
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name S_SERR_L S_REQ_L[8:0] Type Description Secondary System Error (Active LOW): driven device indicate system error condition. Secondary Request (Active LOW): This asserted external device indicate that wants start transaction secondary bus. input externally pulled through resistor VDD. Secondary Grant (Active LOW): PI7C8154 asserts these pins allow external masters access secondary bus. PI7C8154 de-asserts these pins least clock cycles before asserting again. During idle S_GNT_L deasserted, PI7C8154 will drive S_AD, S_CBE, S_PAR. Secondary RESET (Active LOW): Asserted when following conditions met: Signal P_RESET_L asserted. Secondary reset bridge control register configuration space set. chip reset chip control register configuration space set. When asserted, control signals tri-stated zeroes driven S_AD, S_CBE, S_PAR, S_PAR64. Secondary Interface 66MHz Operation: This input used specify PI7C8154 capable running 66MHz secondary side. When HIGH, Secondary 66MHz. When LOW, Secondary only 33MHz. P_M66EN pulled LOW, S_M66EN driven LOW. Secondary Central Function Control Pin: When tied LOW, enables internal arbiter. When tied HIGH, external arbiter must used. S_REQ_L[0] reconfigured secondary grant input, S_GNT_L[0] reconfigured secondary request output.
S_GNT_L[8:0]
S_RESET_L
S_M66EN
I/OD
S_CFN_L
1.2.4
SECONDARY INTERFACE SIGNALS 64-BIT EXTENSION
Name S_AD[63:32] C20, A21, D20, C21, C23, C22, D21, E20, D22, E21, E23, F21, F23, F22, G20, G22, G21, H23, H22, H21, J23, J20, J22, K23, K22, K21, L23, L21, L22, M22, M23, Type Description Secondary Upper 32-bit Address/Data: Multiplexed address data bus. Address indicated S_FRAME_L assertion. Write data stable valid when S_IRDY_L asserted read data stable valid when S_IRDY_L asserted. Data transferred rising clock edges when both S_IRDY_L S_TRDY_L asserted. During idle, PI7C8154 drives S_AD valid logic level when S_GNT_L asserted respectively. Secondary Upper 32-bit Command/Byte Enables: Multiplexed command field byte enable field. During address phase, initiator drives transaction type these pins. initiator then drives byte enables during data phases. During idle, PI7C8154 drives S_CBE[7:0] valid logic level when internal grant asserted.
S_CBE[7:4]
A19, C19, A20,
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name S_PAR64 Type Description Secondary Upper 32-bit Parity: S_PAR64 carries even parity S_AD[63:32] S_CBE[7:4] both address data phases. S_PAR64 driven initiator valid cycle after first address phase when dual address command used S_REQ64_L asserted. S_PAR64 valid clock cycle after second address phase dual address transaction when S_REQ64_L asserted. S_PAR64 valid cycle after valid data driven when both S_REQ64_L S_ACK64_L asserted that data phase. S_PAR64 driven device driving read write data cycle after S_AD lines driven. S_PAR64 tri-stated cycle after S_AD lines tri-stated. Devices receive data sample S_PAR64 input check possible parity errors during 64-bit transactions. When driven, S_PAR64 pulled valid logic level through external resistors. Secondary 64-bit Transfer Request: S_REQ64_L asserted initiator indicate that initiator requesting 64-bit data transfer. S_REQ64_L same timing S_FRAME_L. When S_REQ64_L asserted during reset, 64-bit data path supported. When S_REQ64_L HIGH during reset, PI7C8154 drives S_AD[63:32], S_CBE[7:4], S_PAR64 valid logic levels. When deasserting, S_REQ64_L driven deasserted state cycle then sustained external pull-up resistor. Secondary 64-bit Transfer Acknowledge: S_ACK64_L asserted target only when S_REQ64_L asserted initiator indicate target's ability transfer data using bits. S_ACK64_L same timing S_DEVSEL_L. When deasserting, S_ACK64_L driven deasserted state cycle then sustained external pull-up resistor.
S_REQ64_L
S_ACK64_L
1.2.5
CLOCK SIGNALS
Name P_CLK S_CLKIN S_CLKOUT[9:0] Type Description Primary Clock Input: Provides timing transactions primary interface. Secondary Clock Input: Provides timing transactions secondary interface. Secondary Clock Output: Provides secondary clocks phase synchronous with P_CLK. When these clocks used, clock outputs must back S_CLKIN. Unused outputs disabled Writing secondary clock disable bits configuration space Using serial disable mask using GPIO pins MSK_IN Terminating them electrically.
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
1.2.6
MISCELLANEOUS SIGNALS
Name MSK_IN Type Description Secondary Clock Disable Serial Input: This used PI7C8154 disable secondary clock outputs. serial stream received MSK_IN, starting when P_RESET detected deasserted S_RESET_L detected being asserted. serial data used selectively disabling secondary clock outputs shifted into secondary clock control configuration register. This tied enable secondary clock outputs tied HIGH drive secondary clock outputs HIGH. Primary Voltage: This used determine either 3.3V signaling primary bus. P_VIO must tied 3.3V only when devices primary 3.3V signaling. Otherwise, P_VIO tied Secondary Voltage: This used determine either 3.3V signaling secondary bus. S_VIO must tied 3.3V only when devices secondary 3.3V signaling. Otherwise, S_VIO tied Bus/Power Clock Control Management Pin: When this tied HIGH PI7C8154 placed D3HOT power state, enables PI7C8154 place secondary power state. secondary clocks disabled driven When this tied LOW, there effect secondary clocks when PI7C8154 enters D3HOT power state. 66MHz Configuration: This indicates PI7C8154 capable running 66MHz operation. HIGH [21] offset status register. Power Management Enable Support: This sets bits [31:27] offset Power Management Capabilities Register. When tied LOW, bits [31:27] offset 11111 indicate that secondary devices capable asserting PME_L. When this tied HIGH, bits [31:27] offset 00000 indicate that PI7C8154 does support PME_L pin.
P_VIO
S_VIO
BPCCE
CONFIG66
PMEENA_L
1.2.7
GENERAL PURPOSE INTERFACE SIGNALS
Name GPIO[3:0] Type Description General Purpose Data Pins: general-purpose signals programmable either input-only bi-directional signals writing GPIO output enable control register configuration space.
1.2.8
JTAG BOUNDARY SCAN SIGNALS
Name Type Description
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name TRST_L Type Description Test Clock. Used clock state information data into PI7C8154 during boundary scan. Test Mode Select. Used control state Test Access Port controller. Test Data Output. Used serial output test instructions data from test logic. Test Data Input. Serial input JTAG instructions test data. Test Reset. Active signal reset Test Access Port (TAP) controller into initialized state.
1.2.9
POWER GROUND
Name A22, B20, B23, D10, D11, D14, D15, D18, E22, H20, J21, M20, R23, T20, Y10, Y14, Y18, Y22, AB1, AB19, AB23, AC2, AC3, AC8, AC12, AC16, AC22 A12, A16, A23, B21, B22, D12, D16, D23, F20, G23, K20, L20, P20, U21, V20, Y12, Y16, AA2, AA22, AB2, AB22, AC1, AC4, AC13, AC17, AC20, AC23 Type Description Power: +3.3V Digital power.
Ground: Digital ground.
LIST
Table LIST 304-BALL PBGA
BALL LOCATION NAME S_AD[30] S_AD[22] S_AD[16] S_LOCK_L S_AD13] S_CBE[0] S_AD[2] S_CBE[7] S_AD[62] S_AD[29] S_AD[24] S_AD[20] S_FRAME_L TYPE BALL LOCATION NAME S_AD[27] S_AD[23] S_AD[19] S_TRDY_L SM66EN S_AD[0] S_CBE[5] S_AD[26] S_AD[18] S_DEVSEL_L TYPE I/OD
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
BALL LOCATION NAME S_SERR_L S_AD[14] S_AD[8] S_AD[4] S_REQ64_L S_REQ_L[1] S_AD[31] S_AD[25] S_IRDY_L S_PERR_L S_AD[15] S_AD[9] S_AD[5] S_CBE[6] S_AD[60] S_AD[59] S_REQ_L[5] S_REQ_[3] S_AD[21] S_CBE[2] PMEENA_L S_AD[12] S_AD[3] S_CBE[4] S_AD[57] S_REQ_L[8] S_REQ_L[7] S_AD[54] S_AD[53] S_GNT_L[2] S_GNT_L[1] S_AD[52] S_AD[51] S_GNT_L[4] S_GNT_L[7] S_AD[47] S_GNT_L[8] S_AD[44] S_AD[46] S_AD[43] S_CFN_L GPIO[2] S_AD[38] S_AD[40] GPIO[0] TYPE BALL LOCATION NAME S_PAR S_AD[10] S_AD[6] S_AD[1] S_REQ_L[2] S_AD[28] S_CBE[3] S_AD[17] S_STOP_L S_CBE[1] S_AD[11] S_AD[7] S_ACK64_L S_AD[63] S_AD[58] S_REQ_L[6] S_REQ_L[0] S_AD[61] S_AD[55] S_GNT_L[0] S_REQ_L[4] S_AD[56] S_GNT_L[3] S_AD[50] S_GNT_L[6] S_GNT_L[5] S_AD[49] S_AD[48] S_RESET_L S_AD[45] S_CLKIN S_AD[42] S_AD[41] GPIO[3] S_AD[39] S_CLKOUT[0] TYPE
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
BALL LOCATION
NAME S_CLKOUT[1] S_AD[36] S_AD[37] S_CLKOUT[3] S_CLKOUT[2] S_AD[32] S_AD[33] S_CLKOUT[6] S_CLKOUT[5] S_PAR64 TRST_L S_CLKOUT[9] S_CLKOUT[7] P_RESET_L MSK_IN P_CLK P_PAR64 P_AD[33] P_AD[29] P_REQ_L P_AD[36] P_AD[27] P_AD[26] P_AD[39] P_AD[38] P_AD[24] P_AD[42] P_AD[41] P_IDSEL P_AD[22] P_AD[16] P_SERR_L P_AD[8] P_AD[1] P_CBE[5] P_AD[59] P_AD[52] P_AD[45] P_AD[43] P_AD[21] P_AD[20] P_FRAME_L
TYPE
BALL LOCATION
NAME GPIO[1] S_AD[35] S_CLKOUT[4] S_AD[34] S_VIO S_CLKOUT[8] P_GNT_L BPCCE P_VIO CONFIG66 P_AD[32] P_AD[31] P_AD[30] P_AD[35] P_AD[34] P_AD[28] Reserved1 P_AD[37] P_AD[25] P_AD[23] P_AD[44] P_AD[40] P_CBE[3] P_AD[19] Reserved2 P_AD[47] P_AD[17] P_DEVSEL_L
TYPE
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BALL LOCATION AA11 AA13 AA15 AA17 AA19 AA21 AA23 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AC11 AC13 AC15 AC17 AC19 AC21 AC23 NAME P_CBE[1] P_AD[11] P_AD[6] P_AD[2] P_CBE[7] P_AD[61] P_AD[54] P_AD[48] P_AD[46] P_AD[18] P_TRDY_L P_PAR P_AD[12] P_AD[7] P_AD[3] P_CBE[6] P_AD[60] P_AD[50] P_IRDY_L P_PERR_L P_AD[13] P_CBE[0] P_CBE[4] P_AD[55] P_AD[49] TYPE BALL LOCATION AA10 AA12 AA14 AA16 AA18 AA20 AA22 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC10 AC12 AC14 AC16 AC18 AC20 AC22 NAME P_AD[14] P_AD[9] P_AD[5] P_AD[0] P_AD[63] P_AD[56] P_AD[51] P_CBE[2] P_LOCK_L P_AD[15] P_M66EN P_AD[4] P_ACK64_L P_AD[62] P_AD[58] P_AD[53] P_STOP_L P_AD[10] P_REQ64_L P_AD[57] TYPE
SIGNAL DEFINITIONS
This Chapter offers information about transactions, transaction forwarding across PI7C8154, transaction termination. PI7C8154 128-byte buffers read data buffering upstream downstream transactions. Also, PI7C8154 128-byte buffers write data buffering upstream downstream transactions.
TYPES TRANSACTIONS
This section provides summary transactions performed PI7C8154. Table lists command code name each transaction. Master Target columns indicate support each transaction when PI7C8154 initiates transactions master, primary secondary buses, when PI7C8154 responds transactions target, primary secondary buses. Table TRANSACTIONS
Types Transactions 0000 Interrupt Acknowledge Initiates Master Primary Secondary Responds Target Primary Secondary
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Types Transactions 0001 Special Cycle 0010 Read 0011 Write 0100 Reserved 0101 Reserved 0110 Memory Read 0111 Memory Write 1000 Reserved 1001 Reserved 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1101 Dual Address Cycle 1110 Memory Read Line 1111 Memory Write Invalidate Initiates Master (Type only) Responds Target (Type only)
indicated Table 2-1, following commands supported PI7C8154: PI7C8154 never initiates transaction with reserved command code and, target, PI7C8154 ignores reserved command codes. PI7C8142 does generate interrupt acknowledge transactions. PI7C8154 ignores interrupt acknowledge transactions target. PI7C8154 does respond special cycle transactions. PI7C8154 cannot guarantee delivery special cycle transaction downstream buses because broadcast nature special cycle command inability control transaction target. generate special cycle transactions other buses, either upstream downstream, Type configuration write must used. PI7C8154 neither generates Type configuration transactions primary responds Type configuration transactions secondary bus.
SINGLE ADDRESS PHASE
32-bit address uses single address phase. This address driven P_AD[31:0], command driven P_CBE[3:0]. PI7C8154 supports linear increment address mode only, which indicated when lowest address bits equal zero. either lowest address bits nonzero, PI7C8154 automatically disconnects transaction after first data transfer.
DUAL ADDRESS PHASE
64-bit address uses address phases. first address phase denoted asserting edge FRAME_L. second address phase always follows next clock cycle. 32-bit interface, first address phase contains dual address command code CBE[3:0] lines, address bits AD[31:0] lines. second address phase consists specific memory transaction command code CBE[3:0] lines, high address bits AD[31:0] lines. this way, 64-bit addressing supported 32-bit buses.
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PCI-to-PCI Bridge Architecture Specification supports dual address transactions prefetchable memory range only. Section 3.3.3 discussion prefetchable address space. PI7C8154 supports dual address transactions both upstream downstream direction. PI7C8154 supports programmable 64-bit address range prefetchable memory downstream forwarding dual address transactions. Dual address transactions falling outside prefetchable address range forwarded upstream, downstream. Prefetching posting performed manner consistent with guidelines given this document each type memory transaction prefetchable memory space.
DEVICE SELECT (DEVSEL_L) GENERATION
PI7C8154 always performs positive address decoding (medium decode) when accepting transactions either primary secondary buses. PI7C8154 never does subtractive decode.
DATA PHASE
address phase transaction followed more data phases. data phase completed when IRDY_L either TRDY_L STOP_L asserted. transfer data occurs only when both IRDY_L TRDY_L asserted during same clock cycle. last data phase transaction indicated when FRAME_L de-asserted both TRDY_L IRDY_L asserted, when IRDY_L STOP_L asserted. Section 2.11for further discussion transaction termination. Depending command type, PI7C8154 support multiple data phase transactions. detailed descriptions PI7C8154 imposes disconnect boundaries, Section 2.6.4for write address boundaries Section 2.7.3 read address boundaries.
WRITE TRANSACTIONS
Write transactions treated either posted write delayed write transactions. Table shows method forwarding used each type write operation. Table WRITE TRANSACTION FORWARDING
Type Transaction Memory Write Memory Write Invalidate Memory Write memory Write Type Configuration Write Type Forwarding Posted (except memory) Posted Delayed Delayed Delayed
2.6.1
MEMORY WRITE TRANSACTIONS
Posted write forwarding used "Memory Write" "Memory Write Invalidate" transactions.
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION When PI7C8154 determines that memory write transaction forwarded across bridge, PI7C8154 asserts DEVSEL_L with medium decode timing TRDY_L next cycle, provided that enough buffer space available posted memory write queue address least DWORD data. Under this condition, PI7C8154 accepts write data without obtaining access target bus. PI7C8154 accept DWORD write data every clock cycle. That target wait state inserted. write data stored internal posted write buffers subsequently delivered target. PI7C8154 continues accept write data until following events occurs: initiator terminates transaction de-asserting FRAME_L IRDY_L. internal write address boundary reached, such cache line boundary aligned boundary, depending transaction type. posted write data buffer fills
When last events occurs, PI7C8154 returns target disconnect requesting initiator this data phase terminate transaction. Once posted write data moves head posted data queue, PI7C8154 asserts request target bus. This occur while PI7C8154 still receiving data initiator bus. When grant target received target detected idle condition, PI7C8154 asserts FRAME_L drives stored write address target bus. following cycle, PI7C8154 drives first DWORD write data continues transfer write data until write data corresponding that transaction delivered, until target termination received. long write data exists queue, PI7C8154 drive DWORD write data each clock cycle; that master wait states inserted. write data flowing through PI7C8154 initiator stalls, PI7C8154 will signal last data phase current transaction target queue empties. PI7C8154 will restart follow-on transactions queue data. PI7C8154 ends transaction target when following conditions met: posted write data been delivered target. target returns target disconnect target retry (PI7C8154 starts another transaction deliver rest write data). target returns target abort (PI7C8154 discards remaining write data). master latency timer expires, PI7C8154 longer target grant (PI7C8154 starts another transaction deliver remaining write data).
Section 2.11.3.2 provides detailed information about PI7C8154 responds target termination during posted write transactions.
2.6.2
MEMORY WRITE INVALIDATE
Posted write forwarding used Memory Write Invalidate transactions.
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C8154 disconnects Memory Write Invalidate commands aligned cache line boundaries. cache line size value cache line size register gives number DWORD cache line. value cache line size register does meet memory write invalidate conditions, PI7C8154 returns target disconnect initiator cache line boundary.
2.6.3
DELAYED WRITE TRANSACTIONS
Delayed write forwarding used write transactions Type configuration write transactions. delayed write transaction guarantees that actual target response returned back initiator without holding initiating wait states. delayed write transaction limited single DWORD data transfer. When write transaction first detected initiator bus, PI7C8154 forwards delayed transaction, PI7C8154 claims access asserting DEVSEL_L returns target retry initiator. During address phase, PI7C8154 samples command, address, address parity cycle later. After IRDY_L asserted, PI7C8154 also samples first data DWORD, byte enable bits, data parity. This information placed into delayed transaction queue. transaction queued only other existing delayed transactions have same address command, delayed transaction queue full. When delayed write transaction moves head delayed transaction queue ordering constraints with posted data satisfied. PI7C8154 initiates transaction target bus. PI7C8154 transfers write data target. PI7C8154 receives target retry response write transaction target bus, continues repeat write transaction until data transfer completed, until error condition encountered. PI7C8154 unable deliver write data after (default) (maximum) attempts, PI7C8154 will report system error. PI7C8154 also asserts P_SERR_L primary SERR_L enable command register. Section 5.4for information assertion P_SERR_L. When initiator repeats same write transaction (same command, address, byte enable bits, data), completed delayed transaction head queue, PI7C8154 claims access asserting DEVSEL_L returns TRDY_L initiator, indicate that write data transferred. initiator requests multiple DWORD, PI7C8154 also asserts STOP_L conjunction with TRDY_L signal target disconnect. Note that only those bytes write data with valid byte enable bits compared. byte enable bits turned (driven HIGH), corresponding byte write data compared. initiator repeats write transaction before data been transferred target, PI7C8154 returns target retry initiator. PI7C8154 continues return target retry initiator until write data delivered target, until error condition encountered. When write transaction repeated, PI7C8154 does make entry into delayed transaction queue. Section 2.11.3.1 provides detailed information about PI7C8154 responds target termination during delayed write transactions.
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C8154 implements discard timer that starts counting when delayed write completion head delayed transaction completion queue. initial value this timer retry counter register offset 78h. initiator does repeat delayed write transaction before discard timer expires, PI7C8154 discards delayed write completion from delayed transaction completion queue. PI7C8154 also conditionally asserts P_SERR_L (see Section 5.4).
2.6.4
WRITE TRANSACTION ADDRESS BOUNDARIES
PI7C8154 imposes internal address boundaries when accepting write data. aligned address boundaries used prevent PI7C8154 from continuing transaction over device address boundary provide upper limit maximum latency. PI7C78154 returns target disconnect initiator when reaches aligned address boundaries under conditions shown Table 2-3. Table WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES
Type Transaction Delayed Write Posted Memory Write Posted Memory Write Posted Memory Write Invalidate Posted Memory Write Invalidate Condition Memory write disconnect control 0(1) Memory write disconnect control 1(1) Cache line size Cache line size Aligned Address Boundary Disconnects after data transfer aligned address boundary Disconnects cache line boundary aligned address boundary Cache line boundary posted memory write data FIFO does have enough space next cache line 16-DWORD aligned address boundary
Posted Memory Write Cache line size Invalidate Note Memory write disconnect control chip control register offset configuration space.
2.6.5
BUFFERING MULTIPLE WRITE TRANSACTIONS
PI7C8154 continues accept posted memory write transactions long space least DWORD data posted write data buffer remains. posted write data buffer fills before initiator terminates write transaction, PI7C8154 returns target disconnect initiator. Delayed write transactions accepted long least open entry delayed transaction queue exists. Therefore, several posted delayed write transactions exist data buffers same time. Chapter information about multiple posted delayed write transactions ordered.
2.6.6
FAST BACK-TO-BACK WRITE TRANSACTIONS
PI7C8154 capable decoding forwarding fast back-to-back write transactions. When PI7C8154 cannot accept second transaction because buffer space limitations, returns target retry initiator. fast back-to-back enable must command
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION register upstream write transactions, bridge control register downstream write transactions.
READ TRANSACTIONS
Delayed read forwarding used read transactions crossing PI7C8154. Delayed read transactions treated either prefetchable non-prefetchable. Table shows read behavior, prefetchable non-prefetchable, each type read operation.
2.7.1
PREFETCHABLE READ TRANSACTIONS
prefetchable read transaction read transaction where PI7C8154 performs speculative DWORD reads, transferring data from target before requested from initiator. This behavior allows prefetchable read transaction consist multiple data transfers. However, byte enable bits cannot forwarded data phases done single data phase non-prefetchable read transaction. prefetchable read transactions, PI7C8154 forces byte enable bits data phases. Prefetchable behavior used memory read line memory read multiple transactions, well memory read transactions that fall into prefetchable memory space. amount data that prefetched depends type transaction. amount prefetching also affected amount free buffer space available PI7C8154, read address boundaries encountered. Prefetching should used those read transactions that have side effects target device, that control status registers, FIFO's, target device's base address register registers indicate memory address region prefetchable.
2.7.2
NON-PREFETCHABLE READ TRANSACTIONS
non-prefetchable read transaction read transaction where PI7C8154 requests only DWORD from target disconnects initiator after delivery first DWORD read data. Unlike prefetchable read transactions, PI7C8154 forwards read byte enable information data phase. Non-prefetchable behavior used configuration read transactions, well memory read transactions that fall into non-prefetchable memory space. extra read transactions could have side effects, example, when accessing FIFO, non-prefetchable read transactions those locations. Accordingly, important retain value byte enable bits during data phase, non-prefetchable read transactions. these locations mapped memory space, memory read command target into non-prefetchable (memory-mapped I/O) memory space nonprefetching behavior.
2.7.3
READ PREFECTCH ADDRESS BOUNDARIES
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C8154 imposes internal read address boundaries read prefetched data. When read transaction reaches these aligned address boundaries, PI7C8154 stops pre-fetched data, unless target signals target disconnect before read prefetched boundary reached. When PI7C8154 finishes transferring this read data initiator, returns target disconnect with last data transfer, unless initiator completes transaction before pre-fetched read data delivered. leftover pre-fetched data discarded. Prefetchable read transactions flow-through mode pre-fetch nearest aligned address boundary, until initiator de-asserts FRAME_L. Section 2.7.6 describes flowthrough mode during read operations. Table READ PREFETCH ADDRESS BOUNDARIESshows read pre-fetch address boundaries read transactions during non-flow-through mode. Table READ PREFETCH ADDRESS BOUNDARIES
Type Transaction Configuration Read Read Memory Read Memory Read Memory Read Memory Read Line Address Space Non-Prefetchable Prefetchable Prefetchable Cache Line (CLS) Size Prefetch Aligned Address Boundary DWORD prefetch) DWORD prefetch) DWORD prefetch) 16-DWORD aligned address boundary Cache line address boundary 16-DWORD aligned address boundary Cache line boundary Queue full Second cache line boundary
Memory Read Line Memory Read Multiple Memory Read Multiple does matter prefetchable non-prefetchable don't care
Table READ TRANSACTION PREFETCHING
Read Behavior Prefetching never allowed Prefetching never allowed Downstream: Prefetching used address prefetchable space Memory Read Upstream: Prefetching used programmable Memory Read Line Prefetching always used Memory Read Multiple Prefetching always used Section detailed information about prefetchable non-prefetchable address spaces. Type Transaction Read Configuration Read
2.7.4
DELAYED READ REQUESTS
PI7C8154 treats read transactions delayed read transactions, which means that read request from initiator posted into delayed transaction queue. Read data from target placed read data queue directed toward initiator interface transferred initiator when initiator repeats read transaction. PI7C8154 accepts delayed read request, sampling read address, read command, address parity. When IRDY_L asserted, PI7C8154 then samples byte enable bits first data phase. This information entered into delayed transaction queue. PI7C8154 terminates transaction signaling target retry initiator. Upon reception target retry, initiator required continue repeat same read
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION transaction until least data transfer completed, until target response (target abort master abort) other than target retry received.
2.7.5
DELAYED READ COMPLETION TARGET
When delayed read request reaches head delayed transaction queue, PI7C8154 arbitrates target initiates read transaction only previously queued posted write transactions have been delivered. PI7C8154 uses exact read address read command captured from initiator during initial delayed read request initiate read transaction. read transaction non-prefetchable read, PI7C8154 drives captured byte enable bits during next cycle. transaction prefetchable read transaction, drives byte enable bits zero data phases. PI7C8154 receives target retry response read transaction target bus, continues repeat read transaction until least data transfer completed, until error condition encountered. transaction terminated normal master termination target disconnect after least data transfer been completed, PI7C8154 does initiate further attempts read more data. PI7C8154 unable obtain read data from target after (default) (maximum) attempts, PI7C8154 will report system error. number attempts programmable. PI7C8154 also asserts P_SERR_L primary SERR_L enable command register. Section information assertion P_SERR_L. Once PI7C8154 receives DEVSEL_L TRDY_L from target, transfers data read opposite direction read data queue, pointing toward opposite inter-face, before terminating transaction. example, read data response downstream read transaction initiated primary placed upstream read data queue. PI7C8154 accept DWORD read data each clock cycle; that master wait states inserted. number DWORD's transferred during delayed read transaction matches prefetch address boundary given Table READ PREFETCH ADDRESS BOUNDARIES (assuming disconnect received from target).
2.7.6
DELAYED READ COMPLETION INITIATOR
When transaction been completed target bus, delayed read data head read data queue, ordering constraints with posted write transactions have been satisfied, PI7C8154 transfers data initiator when initiator repeats transaction. memory read transactions, PI7C8154 aliases memory read line memory read multiple commands memory read when matching command transaction command delayed transaction queue bit[3] offset `1'. PI7C8154 returns target disconnect along with transfer last DWORD read data initiator. PI7C8154 initiator terminates transaction before read data been transferred, remaining read data left data buffers discarded. When master repeats transaction starts transferring prefetchable read data from data buffers while read transaction target still progress before read boundary reached target bus, read transaction starts operating flow-through mode. Because data flowing through data buffers from target initiator, long read bursts then sustained. this case, read transaction allowed continue until initiator terminates transaction, until aligned address boundary reached, until buffer fills, whichever comes first. When buffer empties, PI7C8154 Page 2003 Revision 1.02
PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION reflects stalled condition initiator disconnecting initiator with data. initiator retry transaction later data needed. initiator does need more data, initiator will continue disconnected transaction. this case, PI7C8154 will start master timeout timer. remaining read data will discarded after master timeout timer expires. provide better latency, there other pending data other transactions (Read Data Buffer), remaining read data will discarded even though master timeout timer expired. PI7C8154 implements master timeout timer that starts counting when delayed read completion head delayed transaction queue, read data head read data queue. initial value this timer programmable through configuration transaction. initiator does repeat read transaction before master timeout timer expires (215 default), PI7C8154 discards read transaction read data from queues. PI7C8154 also conditionally asserts P_SERR_L (see Section 5.4). PI7C8154 capability post multiple delayed read requests, maximum four each direction. initiator starts read transaction that matches address read command read transaction that already queued, current read command posted already contained delayed transaction queue. Section discussion delayed read transactions ordered when crossing PI7C8154.
2.7.7
FAST BACK-TO-BACK READ TRANSACTION
PI7C8154 capable decoding fast back-to-back read transactions both primary secondary. Also, PI7C8154 cannot generate fast back-to-back read transactions secondary primary even though bit[23] offset bit[9] offset `1'.
CONFIGURATION TRANSACTIONS
Configuration transactions used initialize system. Every device configuration space that accessed configuration commands. registers accessible configuration space only. addition accepting configuration transactions initialization configuration space, PI7C8154 also forwards configuration transactions device initialization hierarchical systems, well special cycle generation. support hierarchical systems, types configuration transactions specified: Type Type Type configuration transactions issued when intended target resides same initiator. Type configuration transaction identified configuration command lowest bits address 00b. Type configuration transactions issued when intended target resides another bus, when special cycle generated another bus. Type configuration command identified configuration command lowest address bits 01b. Page 2003 Revision 1.02
PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
register number found both Type Type formats gives DWORD address configuration register accessed. function number also included both Type Type formats indicates which function multifunction device accessed. single-function devices, this value decoded. addresses Type configuration transaction include 5-bit field designating device number that identifies device target that accessed. addition, number Type transactions specifies which transaction targeted.
2.8.1
TYPE ACCESS PI7C8154
configuration space accessed Type configuration transaction primary interface. configuration space cannot accessed from secondary bus. PI7C8154 responds Type configuration transaction asserting P_DEVSEL_L when following conditions during address phase: command configuration read configuration write transaction. Lowest address bits P_AD[1:0] must 00b. Signal P_IDSEL must asserted. PI7C8154 limits configuration access single DWORD data transfer returns target-disconnect with first data transfer additional data phases requested. Because read transactions configuration space have side effects, bytes requested DWORD returned, regardless value byte enable bits. Type configuration write read transactions data buffers; that these transactions completed immediately, regardless state data buffers. PI7C8154 ignores Type transactions initiated secondary interface.
2.8.2
TYPE TYPE CONVERSION
Type configuration transactions used specifically device configuration hierarchical system. PCI-to-PCI bridge only type device that should respond Type configuration command. Type configuration commands used when configuration access intended device that resides other than where Type transaction generated. PI7C8154 performs Type Type translation when Type transaction generated primary intended device attached directly secondary bus. PI7C8154 must convert configuration command Type format that secondary device respond Type Type translations performed only downstream direction; that PI7C8154 generates Type transaction only secondary bus, never primary bus. PI7C8154 responds Type configuration transaction translates into Type transaction secondary when following conditions during address phase: lowest address bits P_AD[1:0] 01b. Page 2003 Revision 1.02
PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
number address field P_AD[23:16] equal value secondary number register configuration space. command P_CBE[3:0] configuration read configuration write transaction.
When PI7C8154 translates Type transaction Type transaction secondary interface, performs following translations address: Sets lowest address bits S_AD[1:0] Decodes device number drives pattern specified Table 2-6on S_AD[31:16] purpose asserting device's IDSEL signal. Sets S_AD[15:11] Leaves unchanged function number register number fields.
PI7C8154 asserts unique address line based device number. These address lines used secondary IDSEL signals. mapping address lines depends device number Type address bits P_AD[15:11]. Table presents mapping that PI7C8154 uses. Table DEVICE NUMBER IDSEL S_AD MAPPING
Device Number P_AD[15:11] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 11110 11111 Secondary IDSEL S_AD[31:16] 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 Generate special cycle (P_AD[7:2] 00h) 0000 0000 0000 0000 (P_AD[7:2] 00h) S_AD
PI7C8154 assert unique address lines used IDSEL signals devices secondary bus, device numbers ranging from through Because electrical loading constraints bus, more than IDSEL signals should necessary. However, device numbers greater than desired, some external method generating IDSEL lines must used, upper address bits then asserted. configuration transaction still translated passed from primary secondary bus. IDSEL asserted secondary device, transaction ends master abort.
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C8154 forwards Type Type configuration read write transactions delayed transactions. Type Type configuration read write transactions limited single 32-bit data transfer.
2.8.3
TYPE TYPE FORWARDING
Type Type transaction forwarding provides hierarchical configuration mechanism when more levels PCI-to-PCI bridges used. When PI7C8154 detects Type configuration transaction intended downstream from secondary bus, PI7C8154 forwards transaction unchanged secondary bus. Ultimately, this transaction translated Type configuration command special cycle transaction downstream PCI-to-PCI bridge. Downstream Type Type forwarding occurs when following conditions during address phase: lowest address bits equal 01b. number falls range defined lower limit (exclusive) secondary number register upper limit (inclusive) subordinate number register. command configuration read write transaction.
PI7C8154 also supports Type Type forwarding configuration write transactions upstream support upstream special cycle generation. Type configuration command forwarded upstream when following conditions met: lowest address bits equal 01b. number falls outside range defined lower limit (inclusive) secondary number register upper limit (inclusive) subordinate number register. device number address bits AD[15:11] equal 11111b. function number address bits AD[10:8] equal 111b. command configuration write transaction.
PI7C8154 forwards Type Type configuration write transactions delayed transactions. Types Type configuration write transactions limited single data transfer.
2.8.4
SPECIAL CYCLES
Type configuration mechanism used generate special cycle transactions hierarchical systems. Special cycle transactions ignored acting target forwarded across bridge. Special cycle transactions generated from Type configuration write transactions either upstream down-stream direction.
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C8154 initiates special cycle target when Type configuration write transaction being detected initiating following conditions during address phase: lowest address bits AD[1:0] equal 01b. device number address bits AD[15:11] equal 11111b. function number address bits AD[10:8] equal 111b. register number address bits AD[7:2] equal 000000b. number equal value secondary number register configuration space downstream forwarding equal value primary number register configuration space upstream forwarding. command configuration write command.
When PI7C8154 initiates transaction target interface, command changed from configuration write special cycle. address data for-warded unchanged. Devices that special cycles ignore address decode only command. data phase contains special cycle message. transaction forwarded delayed transaction, this case target response forwarded back (because special cycles result master abort). Once transaction completed target bus, through detection master abort condition, PI7C8154 responds with TRDY_L next attempt con-figuration transaction from initiator. more than data transfer requested, PI7C8154 responds with target disconnect operation during first data phase.
64-BIT OPERATION
Both primary secondary interfaces PI7C8154 support 32-bit operation 64bit operation. This chapter describes 64-bit operations well conditions that along with
2.9.1
64-BIT 32-BIT TRANSACTIONS INITIATED PI7C8154
64-bit transactions requested asserting P_REQ64_L primary S_REQ64_L secondary during address phase. REQ64_L asserted deasserted during same cycles FRAME_L. Under certain conditions, PI7C8154 does 64-bit extension when initiating transactions. this case, REQ64_L asserted. REQ64_L asserted, transaction initiated 32-bit transaction when following conditions met: P_REQ64_L asserted primary during reset (64-bit extension supported primary) upstream transactions only PI7C8154 initiating transaction PI7C8154 initiating special cycle transaction
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C8154 initiating configuration transaction PI7C8154 initiating nonprefetchable memory read transaction address QUADWORD aligned address near cache line single DWORD read transaction being performed single two-DWORD memory write transaction being performed PI7C8154 resuming memory write transaction after target disconnect, ACK64_L asserted target previous transaction does apply when previous target termination target retry
2.9.2
64-BIT TRANSACTIONS ADDRESS PHASE
When transaction using primary 64-bit extension single address cycle, upper 32-bits address, AD[63:32], assumed CBE[7:4] defined driven valid logic levels during address phase. When transaction using primary 64-bit extension dual address cycle, upper 32-bit address, AD[63:32], contain upper 32-bits address CBE[7:4] contain memory command during both address phases. 64-bit target then opportunity decode entire 64-bit address command after first address phase. 32-bit target needs both address phases decode full address command.
2.9.3
64-BIT TRANSACTIONS DATA PHASE
PI7C8154 asserts REQ64_L indicate initiating 64-bit transfer during memory write transactions. During data phase, PI7C8154 asserts following: bits data AD[31:0] bits CBE[3:0] high bits data AD[63:32] high bits CBE[7:4]
Every data phase will consist bits byte enable bits when PI7C8154 detects ACK64#_L asserted target same time detects DEVSEL_L. write transactions, PI7C8154 redirects write data that AD[63:32] AD[31:0] during second data phase does detect ACK64_L asserted same time that detects DEVSEL_L asserted. Also, CBE[7:4] redirected CBE[3:0] during second data phase.
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 64-bit memory write transactions that DWORD boundary, PI7C8154 drives byte enable bits during last data phase. AD[63:32] then unpredictable driven valid logic level. read transactions, PI7C8154 drives bits byte enables CBE[7:0] when asserted REQ64_L. CBE[7:0] always because only read transactions that 64bit extension prefetchable memory reads. special redirection needed based target's assertion lack assertion ACK64_L. When target asserts ACK64_L same time that asserts DEVSEL_L, read data transfers consist bits target asserts PAR64, which covers AD[63:32] CBE[7:4]. data phase consist 32-bit transactions when target does assert ACK64_L asserts DEVSEL_L.
2.9.4
64-BIT TRANSACTIONS RECEIVED PI7C8154
PI7C8154 does things when target transaction REQ64_L asserted. PI7C8154 either asserts ACK64_L same time asserts DEVSEL_L indicate ability perform 64-bit data transfers, does 64-bit extension target does assert ACK64_L. PI7C8154 does assert ACK64_L under following conditions: REQ64_L asserted initiator PI7C8154 responding nonprefetchable memory read transaction PI7C8154 responding transaction PI7C8154 responding configuration transaction Only DWORD data read from target
PI7C8154 target 64-bit memory write transaction, able accept bits data during each data phase. PI7C8154 target memory read transaction, delivers bits read data during each data phase drives PAR64 corresponding AD[63:32] CBE[7:4] each data phase. number DWORDS read from target PI7C8154 asserted ACK64_L when returning read data initiator, PI7C8154 disconnects before last DWORD returned. PI7C8154 have read number DWORD's because either target disconnect master latency timer expiration during 32-bit data transfers opposite interface.
2.9.5
64-BIT TRANSACTIONS SUPPORT DURING RESET
PI7C8154 checks P_REQ64_L while P_RESET_L asserted determine whether 64bit extensions connected. P_REQ64_L HIGH, PI7C8154 knows that 64-bit extension signals connected always drives 64-bit extension outputs have valid logic levels inputs. PI7C8154 will then treat transactions primary 32-bit. P_REQ64_L LOW, 64-bit signals should connected pull-up resistors board PI7C8154 does perform input biasing. PI7C8154 then treat memory write prefetchabel memory read transactions 64-bit transactions primary.
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C8154 always asserts S_REQ64_L during S_RESET_L indicate that 64-bit extension supported secondary bus. Individual pull-up resistors must always supplied S_AD[63:32], S_CBE[7:4], S_PAR64.
2.10
TRANSACTION FLOW THROUGH
Transaction flow through refers data being removed from read/write buffers concurrently data still being written buffer. reads, flow through occurs when initiator repeats delayed transaction while some read data buffer, transaction still ongoing target bus. read flow through occur, there other reads writes previously posted same direction. writes, flow through occurs when PI7C8154 able arbitrate target bus, initiate transaction receive TRDY_L from target, while receiving data from same transaction initiator bus. Flow through only occur writes that were previously posted same direction completed.
2.11
TRANSACTION TERMINATION
This section describes PI7C8154 returns transaction termination conditions back initiator. initiator terminate transactions with following types termination: Normal termination Normal termination occurs when initiator de-asserts FRAME_L beginning last data phase, de-asserts IRDYL last data phase conjunction with either TRDY_L STOP_L assertion from target. Master abort master abort occurs when target response detected. When initiator does detect DEVSEL_L from target within five clock cycles after asserting FRAME_L, initiator terminates transaction with master abort. FRAME_L still asserted, initiator de-asserts FRAME_L next cycle, then de-asserts IRDY_L following cycle. IRDY_L must asserted same cycle which FRAME_L deasserts. FRAME_L already deasserted, IRDY_L deasserted next clock cycle following detection master abort condition. target terminate transactions with following types termination: Normal termination TRDY_L DEVSEL_L asserted conjunction with FRAME_L deasserted IRDY_L asserted. Target retry STOP_L DEVSEL_L asserted with TRDY_L deasserted during first data phase. data transfers occur during transaction. This transaction must repeated. Target disconnect with data transfer Page 2003 Revision 1.02
PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION STOP_L, DEVSEL_L TRDY_L asserted. signals that this last data transfer transaction. Target disconnect without data transfer STOP_L DEVSEL_L asserted with TRDY_L de-asserted after previous data transfers have been made, indicating that more data transfers will made during this transaction. Target abort STOP_L asserted with DEVSEL_L TRDY_L de-asserted. Indicates that target will never able complete this transaction. DEVSEL_L must asserted least cycle during transaction before target abort signaled.
2.11.1
MASTER TERMINATION INITIATED PI7C8154
PI7C8154, initiator, uses normal termination DEVSEL_L returned target within five clock cycles PI7C8154's assertion FRAME_L target bus. initiator, PI7C8154 terminates transaction when following conditions met: During delayed write transaction, single DWORD delivered. During non-prefetchable read transaction, single DWORD transferred from target. During prefetchable read transaction, pre-fetch boundary reached. posted write transaction, write data transaction transferred from data buffers target. burst transfer, with exception "Memory Write Invalidate" transactions, master latency timer expires PI7C8154's grant de-asserted. target terminates transaction with retry, disconnect, target abort.
PI7C8154 delivering posted write data when terminates transaction because master latency timer expires, initiates another transaction deliver remaining write data. address transaction updated reflect address current DWORD delivered. PI7C8154 pre-fetching read data when terminates transaction because master latency timer expires, does repeat transaction obtain more data.
2.11.2
MASTER ABORT RECEIVED PI7C8154
initiator initiates transaction target does detect DEVSEL_L returned target within five clock cycles assertion FRAME_L, PI7C8154 terminates transaction with master abort. This sets received-master-abort status register corresponding target bus. delayed read write transactions, PI7C8154 able reflect master abort condition back initiator. When PI7C8154 detects master abort response delayed transaction, when initiator repeats transaction, PI7C8154 does Page 2003 Revision 1.02
PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION respond transaction with DEVSEL_L, which induces master abort condition back initiator. transaction then removed from delayed transaction queue. When master abort received response posted write transaction, PI7C8154 discards posted write data makes more attempts deliver data. PI7C8154 sets received-master-abort status register when master abort received primary bus, sets received master abort secondary status register when master abort received secondary interface. When master abort detected posted write transaction with both master-abort-mode (bit[5] bridge control register) SERR_L enable (bit command register secondary bus) set, PI7C8154 asserts P_SERR_L master-abort-on-posted-write set. master-abort-on-posted-write P_SERR_L event disable register (offset 64h). Note: When PI7C8154 performs Type special cycle conversion, master abort expected termination special cycle target bus. this case, master abort received set, Type configuration transaction disconnected after first data phase.
2.11.3
TARGET TERMINATION RECEIVED PI7C8154
When PI7C8154 initiates transaction target target responds with DEVSEL_L, target transaction with following types termination: Normal termination (upon de-assertion FRAME_L) Target retry Target disconnect Target abort
PI7C8154 handles these terminations different ways, depending type transaction being performed. 2.11.3.1 DELAYED WRITE TARGET TERMINATION RESPONSE When PI7C8154 initiates delayed write transaction, type target termination received from target passed back initiator. Table shows response each type target termination that occurs during delayed write transaction. PI7C8154 repeats delayed write transaction until following conditions met: PI7C8154 completes least data transfer. PI7C8154 receives master abort. PI7C8154 receives target abort.
PI7C8154 makes (default) (maximum) write attempts resulting response target retry.
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Table DELAYED WRITE TARGET TERMINATION RESPONSE
Target Termination Normal Target Retry Target Disconnect Target Abort Response Returning disconnect initiator with first data transfer only multiple data phases requested. Returning target retry initiator. Continue write attempts target Returning disconnect initiator with first data transfer only multiple data phases requested. Returning target abort initiator. received target abort target interface status register. signaled target abort initiator interface status register.
After PI7C8154 makes (default) attempts same delayed write trans-action target bus, PI7C8154 asserts P_SERR_L SERR_L enable (bit command register secondary bus) delayed-write-non-delivery set. delayed-write-non-delivery P_SERR_L event disable register (offset 64h). PI7C8154 will report system error. Section description system error conditions. 2.11.3.2 POSTED WRITE TARGET TERMINATION RESPONSE When PI7C8154 initiates posted write transaction, target termination cannot passed back initiator. Table shows response each type target termination that occurs during posted write transaction. Table RESPONSE POSTED WRITE TARGET TERMINATION
Target Termination Normal Target Retry Target Disconnect Target Abort Repsonse additional action. Repeating write transaction target. Initiate write transaction delivering remaining posted write data. received-target-abort target interface status register. Assert P_SERR# enabled, signaled-system-error primary status register.
Note that when target retry target disconnect returned posted write data associated with that transaction remains write buffers, PI7C8154 initiates another write transaction attempt deliver rest write data. there target retry, exact same address will driven initial write trans-action attempt. target disconnect received, address that driven subsequent write transaction attempt will updated reflect address current DWORD. initial write transaction Memory-Write-and-Invalidate transaction, partial delivery write data target performed before target disconnect received, PI7C8154 will memory write command deliver rest write data. because incomplete cache line will transferred subsequent write transaction attempt. After PI7C8154 makes (default) write transaction attempts fails deliver posted write data associated with that transaction, PI7C8154 asserts P_SERR_L primary SERR_L enable (bit command register secondary bus) postedwrite-non-delivery set. posted-write-non-delivery P_SERR_L event disable register (offset 64h). PI7C8154 will report system error. Section discussion system error conditions. 2.11.3.3 DELAYED READ TARGET TERMINATION RESPONSE
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION When PI7C8154 initiates delayed read transaction, abnormal target responses passed back initiator. Other target responses depend much data initiator requests. Table shows response each type target termination that occurs during delayed read transaction. PI7C8154 repeats delayed read transaction until following conditions met: PI7C8154 completes least data transfer. PI7C8154 receives master abort. PI7C8154 receives target abort.
PI7C8154 makes (default) read attempts resulting response target retry. Table RESPONSE DELAYED READ TARGET TERMINATION
Target Termination Normal Target Retry Target Disconnect Target Abort Response prefetchable, target disconnect only initiator requests more data than read from target. non-prefetchable, target disconnect first data phase. Re-initiate read transaction target initiator requests more data than read from target, return target disconnect initiator. Return target abort initiator. received target abort target interface status register. signaled target abort initiator interface status register.
After PI7C8154 makes 224(default) attempts same delayed read transaction target bus, PI7C8154 asserts P_SERR_L primary SERR_L enable (bit command register secondary bus) delayed-write-non-delivery set. delayed-write-non-delivery P_SERR_L event disable register (offset 64h). PI7C8154 will report system error. Section description system error conditions.
2.11.4
TARGET TERMINATION INITIATED PI7C8154
PI7C8154 return target retry, target disconnect, target abort initiator reasons other than detection that condition target interface.
2.11.4.1
TARGET RETRY PI7C8154 returns target retry initiator when cannot accept write data return read data result internal conditions. PI7C8154 returns target retry initiator when following conditions met: DELAYED WRITE TRANSACTIONS: transaction being entered into delayed transaction queue. Transaction already been entered into delayed transaction queue, target response been received.
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Target response been received progressed head return queue. delayed transaction queue full, transaction cannot queued. transaction with same address command been queued. locked sequence being propagated across PI7C8154, write transaction locked transaction. target locked write transaction locked transaction. more than clocks accept this transaction.
DELAYED READ TRANSACTIONS: transaction being entered into delayed transaction queue. read request already been queued, read data available. Data been read from target, head read data queue posted write transaction precedes delayed transaction queue full, transaction cannot queued. delayed read request with same address command already been queued. locked sequence being propagated across PI7C8154, read transaction locked transaction. PI7C78154 currently discarding previously pre-fetched read data. target locked write transaction locked transaction. more than clocks accept this transaction.
POSTED WRITE TRANSACTIONS: posted write data buffer does have enough space address least DWORD write data. locked sequence being propagated across PI7C8154, write transaction locked transaction. When target retry returned initiator delayed transaction, initiator must repeat transaction with same address command well data write transaction, within time frame specified master timeout value. Otherwise, transaction discarded from buffers.
2.11.4.2
TARGET DISCONNECT
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C8154 returns target disconnect initiator when following conditions met: PI7C8154 hits internal address boundary. PI7C8154 cannot accept more write data. PI7C8154 more read data deliver.
Section 2.6.4 description write address boundaries, Section 2.7.3 description read address boundaries. 2.11.4.3 TARGET ABORT PI7C8154 returns target abort initiator when following conditions met: PI7C8154 returning target abort from intended target. When PI7C8154 returns target abort initiator, sets signaled target abort status register corresponding initiator interface.
ADDRESS DECODING
PI7C8154 uses three address ranges that control memory transaction forwarding. These address ranges defined base limit address registers configuration space. This chapter describes these address ranges, well ISA-mode VGAaddressing support.
ADDRESS RANGES
PI7C8154 uses following address ranges that determine which memory transactions forwarded from primary secondary bus, from secondary primary bus: 32-bit address ranges 32-bit memory-mapped (non-prefetchable memory) ranges 32-bit prefetchable memory address ranges
Transactions falling within these ranges forwarded downstream from primary secondary bus. Transactions falling outside these ranges forwarded upstream from secondary primary bus. address translation required PI7C8154. addresses that marked downstream always forwarded upstream.
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
ADDRESS DECODING
PI7C8154 uses following mechanisms that defined configuration space specify address space downstream upstream forwarding: base limit address registers enable mode snoop
This section provides information address registers mode Section provides information modes. enable downstream forwarding transactions, enable must command register configuration space. transactions initiated primary will ignored enable set. enable upstream forwarding transactions, master enable must command register. master-enable set, PI7C8154 ignores memory transactions initiated secondary bus. master-enable also allows upstream forwarding memory transactions set. CAUTION configuration state affecting transaction forwarding changed configuration write operation primary same time that transactions ongoing secondary bus, PI7C8154 response secondary transactions predictable. Configure base limit address registers, enable bit, mode bit, snoop before setting enable master enable bits, change them subsequently only when primary secondary buses idle.
3.2.1
BASE LIMIT ADDRESS REGISTER
PI7C8154 implements base limit address registers configuration space that define address range port downstream forwarding. PI7C8154 supports 32-bit addressing, which allows addresses downstream PI7C8154 mapped anywhere address space. transactions with addresses that fall inside range defined base limit registers forwarded downstream from primary secondary bus. transactions with addresses that fall outside this range forwarded upstream from secondary primary bus. range turned setting base address value greater than that limit address. When range turned off, trans-actions forwarded upstream, transactions forwarded downstream. range minimum granularity aligned boundary. maximum range size. base register consists 8-bit field configuration address 1Ch, 16bit field address 30h. bits 8-bit field define bits [15:12] base Page 2003 Revision 1.02
PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION address. bottom bits read only indicate that PI7C8154 supports 32-bit addressing. Bits [11:0] base address assumed which naturally aligns base address boundary. bits contained base upper bits register configuration offset define AD[31:16] base address. bits read/write. After primary reset chip reset, value base address initialized 0000 0000h. limit register consists 8-bit field configuration offset 16-bit field offset 32h. bits 8-bit field define bits [15:12] limit address. bottom bits read only indicate that 32-bit addressing supported. Bits [11:0] limit address assumed FFFh, which naturally aligns limit address address block. bits contained limit upper bits register configuration offset define AD[31:16] limit address. bits read/write. After primary reset chip reset, value limit address reset 0000 0FFFh. Note: initial states base limit address registers define range 0000 0000h 0000 0FFFh, which bottom space. Write these registers with their appropriate values before setting either enable master enable command register configuration space.
3.2.2
MODE
PI7C8154 supports mode providing enable bridge control register configuration space. mode modifies response PI7C8154 inside address range order support mapping space presence system. This only affects response PI7C8154 when transaction falls inside address range defined base limit address registers, only when this address also falls inside first 64KB space (address bits [31:16] 0000h). When enable set, PI7C8154 does forward downstream transactions addressing bytes each aligned block. Only those transactions addressing bottom bytes aligned block inside base limit address range forwarded downstream. Transactions above 64KB address boundary forwarded defined address range defined base limit registers. Accordingly, enable set, PI7C8154 forwards upstream those transactions addressing bytes each aligned block within first 64KB space. master enable command configuration register must also enable upstream forwarding. other transactions initiated secondary forwarded upstream only they fall outside address range. When enable set, devices downstream PI7C8154 have space mapped into first bytes each chunk below 64KB boundary, anywhere space above 64KB boundary.
MEMORY ADDRESS DECODING
PI7C8154 three mechanisms defining memory address ranges forwarding memory transactions:
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Memory-mapped base limit address registers Prefetchable memory base limit address registers mode
This section describes first mechanisms. Section 3.4.1 describes mode. enable downstream forwarding memory transactions, memory enable must command register configuration space. enable upstream forwarding memory transactions, master-enable must command register. master-enable also allows upstream forwarding transactions set. CAUTION configuration state affecting memory transaction forwarding changed configuration write operation primary same time that memory transactions ongoing secondary bus, response secondary memory transactions predictable. Configure memory-mapped base limit address registers, prefetchable memory base limit address registers, mode before setting memory enable master enable bits, change them subsequently only when primary secondary buses idle.
3.3.1
MEMORY-MAPPED BASE LIMIT ADDRESS REGISTERS
Memory-mapped also referred non-prefetchable memory. Memory addresses that cannot automatically pre-fetched that conditionally pre-fetched based command type should mapped into this space. Read transactions non-prefetchable space exhibit side effects; this space have non-memory-like behavior. PI7C8154 prefetches this space only memory read line memory read multiple commands used; transactions using memory read command limited single data transfer. memory-mapped base address memory-mapped limit address registers define address range that PI7C8154 uses determine when forward memory commands. PI7C8154 forwards memory transaction from primary secondary interface transaction address falls within memory-mapped address range. PI7C8154 ignores memory transactions initiated secondary interface that fall into this address range. transactions that fall outside this address range ignored primary interface forwarded upstream from secondary interface (provided that they fall into prefetchable memory range forwarded downstream mechanism). memory-mapped range supports 32-bit addressing only. PCI-to-PCI Bridge Architecture Specification does provide 64-bit addressing memory-mapped space. memory-mapped address range granularity alignment 1MB. maximum memory-mapped address range 4GB. memory-mapped address range defined 16-bit memory-mapped base address register configuration offset 16-bit memory-mapped limit address register offset 22h. bits each these registers correspond bits [31:20] memory address. bits hardwired lowest bits memory-mapped base address assumed 0000h, which results natural alignment boundary. lowest bits memory-mapped limit address assumed FFFFFh, which results alignment block. Page 2003 Revision 1.02
PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Note: initial state memory-mapped base address register 0000 0000h. initial state memory-mapped limit address register 000F FFFFh. Note that initial states these registers define memory-mapped range bottom block memory. Write these registers with their appropriate values before setting either memory enable master enable command register configuration space. turn memory-mapped address range, write memory-mapped base address register with value greater than that memory-mapped limit address register.
3.3.2
PREFETCHABLE MEMORY BASE LIMIT ADDRESS REGISTERS
Locations accessed prefetchable memory address range must have true memory-like behavior must exhibit side effects when read. This means that extra reads prefetchable memory location must have side effects. PI7C8154 pre-fetches types memory read commands this address space. prefetchable memory base address prefetchable memory limit address registers define address range that PI7C8154 uses determine when forward memory commands. PI7C8154 forwards memory transaction from primary secondary interface transaction address falls within prefetchable memory address range. PI7C8154 ignores memory transactions initiated secondary interface that fall into this address range. PI7C8154 does respond transactions that fall outside this address range primary interface forwards those transactions upstream from secondary interface (provided that they fall into memory-mapped range forwarded mechanism). prefetchable memory range supports 64-bit addressing provides additional registers define upper bits memory address range, prefetchable memory base address upper bits register, prefetchable memory limit address upper bits register. address comparison, single address cycle (32-bit address) prefetchable memory transaction treated like 64-bit address transaction where upper bits address equal This upper 32-bit value compared prefetchable memory base address upper bits register prefetchable memory limit address upper bits register. prefetchable memory base address upper bits register must pass single address cycle transactions downstream. Prefetchable memory address range granularity alignment 1MB. Maximum memory address range when 32-bit addressing being used. Prefetchable memory address range defined 16-bit prefetchable memory base address register configuration offset 16-bit prefetchable memory limit address register offset 26h. bits each these registers correspond bits [31:20] memory address. lowest bits hardwired lowest bits prefetchable memory base address assumed 0000h, which results natural alignment boundary. lowest bits prefetchable memory limit address assumed FFFFFh, which results alignment block. Note: initial state prefetchable memory base address register 0000 0000h. initial state prefetchable memory limit address register 000F FFFFh. Note that initial states these registers define prefetchable memory range bottom block Page 2003 Revision 1.02
PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION memory. Write these registers with their appropriate values before setting either memory enable master enable command register configuration space. turn prefetchable memory address range, write prefetchable memory base address register with value greater than that prefetchable memory limit address register. entire base value must greater than entire limit value, meaning that upper bits must considered. Therefore, disable address range, upper bits registers both same value, while lower base register greater than lower limit register. Otherwise, upper 32-bit base must greater than upper 32bit limit.
3.3.3
PREFETCHABLE MEMORY 64-BIT ADDRESSING REGISTERS
PI7C8154 supports 64-bit memory address decoding forwarding dual address memory transactions. Dual address cycle used 64-bit addressing. first address phase dual address cycle contains bits address second address phase contains high bits. high bits must never during dual address cycle. prefetchable memory address range defined implementing prefetchable memory base address upper bits register prefetchable memory limit address upper bits register. prefetchable address space defined either: Residing entirely first memory Residing entirely above first memory Crossing first memory boundary
prefetchable memory space secondary resides entirely first memory, both upper register must PI7C8154 then ignores dual address cycles initiated primary interface forwards dual address transactions initiated secondary interface upstream. prefetchable memory space secondary resides entirely above first memory, both prefetchable memory base address upper register prefetchable memory limit address upper register must initialized nonzero values. PI7C8154 ignores single address memory transactions initiated primary forwards single address memory transactions initiated secondary upstream, unless memory falls within memory mapped memory range. dual address memory transaction forwarded downstream from primary falls within address range defined prefetchable memory base address, prefetchable memory base address upper bits, prefetchable memory limit address, prefetchable memory limit address upper bits. dual address cycle initiated secondary falls outside this address range, forwarded upstream primary. PI7C8154 does respond dual address cycle initiated primary that falls outside this address range, dual address cycle initiated secondary that falls within address range. prefetchable memory space secondary resides boundary, prefetchable memory base address upper register prefetchable memory limit address upper register initialized nonzero value. Single address cycle memory transactions compared prefetchable memory base address register only. transaction initiated primary forwarded downstream address Page 2003 Revision 1.02
PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION greater than equal base address. transaction initiated secondary forwarded upstream address less than base address. Dual address cycles compared prefetchable memory limit address prefetchable memory limit address upper register. address dual address cycle less than equal limit, transaction forwarded downstream from primary ignored secondary. address dual address cycle greater than this limit, transaction ignored primary forwarded upstream from secondary. prefetchable memory base address upper register located offset configuration register prefetchable memory limit address upper register located offset 2Ch. Both registers reset
SUPPORT
PI7C8154 provides modes support: mode, supporting VGA-compatible addressing snoop mode, supporting palette forwarding
3.4.1
MODE
When VGA-compatible device exists downstream from PI7C8154, mode bridge control register configuration space enable mode. When PI7C8154 operating mode, forwards downstream those transactions addressing frame buffer memory registers, regardless values base limit address registers. PI7C8154 ignores transactions initiated secondary interface addressing these locations. frame buffer consists following memory address range: 000A 0000h-000B FFFFh Read transactions frame buffer memory treated non-prefetchable. PI7C8154 requests only single data transfer from target, read byte enable bits forwarded target bus. addresses range 3B0h-3BBh 3C0h-3DFh I/O. These addresses aliases every throughout first 64KB space. This means that address bits [5:10] decoded value, while address bits [31:16] must 0's. BIOS addresses starting C0000h decoded mode.
3.4.2
SNOOP MODE
PI7C8154 provides snoop mode, allowing palette write transactions forwarded downstream. This mode used when graphics device downstream from PI7C8154 needs snoop respond palette write transactions. enable mode, snoop command register configuration space. Note that
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C8154 claims palette write transactions asserting DEVSEL_L snoop mode. When snoop set, PI7C8154 forwards downstream transactions within 3C6h, 3C8h 3C9h addresses space. Note that these addresses also forwarded part compatibility mode previously described. Again, address bits [15:10] decoded, while address bits [31:16] must equal which means that these addresses aliases every throughout first 64KB space. Note: both mode snoop set, PI7C8154 behaves same only mode were set.
TRANSACTION ORDERING
maintain data coherency consistency, PI7C8154 complies with ordering rules forth Local Specification, Revision 2.2, transactions crossing bridge. This chapter describes ordering rules that control transaction forwarding across PI7C8154.
TRANSACTIONS GOVERNED ORDERING RULES
Ordering relationships established following classes transactions crossing PI7C8154: Posted write transactions, comprised memory write memory write invalidate transactions. Posted write transactions complete source before they complete destination; that data written into intermediate data buffers before reaches target. Delayed write request transactions, comprised write configuration write transactions. Delayed write requests terminated target retry initiator queued delayed transaction queue. delayed write transaction must complete target before completes initiator bus. Delayed write completion transactions, comprised write configuration write transactions. Delayed write completion transactions complete target bus, target response queued buffers. delayed write completion transaction proceeds direction opposite that original delayed write request; that delayed write completion transaction proceeds from target initiator bus. Delayed read request transactions, comprised memory read, read, configuration read transactions. Delayed read requests terminated target retry initiator queued delayed transaction queue. Delayed read completion transactions, comprised memory read, read, configuration read transactions.
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Delayed read completion transactions complete target bus, read data queued read data buffers. delayed read completion transaction proceeds direction opposite that original delayed read request; that delayed read completion transaction proceeds from target initiator bus. PI7C8154 does combine merge write transactions: PI7C8154 does combine separate write transactions into single write transaction-this optimization best implemented originating master. PI7C8154 does merge bytes separate masked write transactions same DWORD address-this optimization also best implemented originating master. PI7C8154 does collapse sequential write transactions same address into single write transaction-the Local Specification does permit this combining transactions.
GENERAL ORDERING GUIDELINES
Independent transactions primary secondary buses have relationship only when those transactions cross PI7C8154. following general ordering guidelines govern transactions crossing PI7C8154: ordering relationship transaction with respect other transactions determined when transaction completes, that when transaction ends with termination other than target retry. Requests terminated with target retry accepted completed order with respect other transactions that have been terminated with target retry. order completion delayed requests important, initiator should start second delayed transaction until first been completed. more than delayed transaction initiated, initiator should repeat delayed transaction requests, using some fairness algorithm. Repeating delayed transaction cannot contingent completion another delayed transaction. Otherwise, deadlock occur. Write transactions flowing direction have ordering requirements with respect write transactions flowing other direction. PI7C8154 accept posted write transactions both interfaces same time, well initiate posted write transactions both interfaces same time. acceptance posted memory write transaction target never contingent completion non-locked, non-posted transaction master. This true PI7C8154 must also true other agents. Otherwise, deadlock occur. PI7C8154 accepts posted write transactions, regardless state completion delayed transactions being forwarded across PI7C8154.
ORDERING RULES
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PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Table shows ordering relationships transactions refers number ordering rules that follow. Table SUMMARY TRANSACTION ORDERING
Pass Posted Write Delayed Read Request Delayed Write Request Delayed Read Completion Delayed Write Completion Posted Write Delayed Read Request Yes5 Delayed Write Request Yes5 Delayed Read Completion Yes5 Delayed Write Completion Yes5
Note: superscript accompanying some table entries refers applicable ordering rule listed this section. Many entries governed these ordering rules; therefore, implementation choose whether transactions pass each other. entries without superscripts reflect PI7C8154's implementation choices. following ordering rules describe transaction relationships. Each ordering rule followed explanation, ordering rules referred number Table 4-1. These ordering rules apply posted write transactions, delayed write read requests, delayed write read completion transactions crossing PI7C8154 same direction. Note that delayed completion transactions cross PI7C8154 direction opposite that corresponding delayed requests. Posted write transactions must complete target order which they were received initiator bus. subsequent posted write transaction setting flag that covers data first posted write transaction; second transaction were complete before first transaction, device checking flag could subsequently consume stale data. delayed read request traveling same direction previously queued posted write transaction must push posted write data ahead posted write transaction must complete target before delayed read request attempted target bus. read transaction same location write data, read transaction were pass write transaction, would return stale data. delayed read completion must ``pull'' ahead previously queued posted write data traveling same direction. this case, read data traveling same direction write data, initiator read transaction same side PI7C8154 target write transaction. posted write transaction must complete target before read data returned initiator. read transaction reading status register initiator posted write data therefore should complete until write transaction complete. Delayed write requests cannot pass previously queued posted write data. posted memory write transactions, delayed write transaction flag that covers data posted write transaction. delayed write request were complete before earlier posted write transaction, device checking flag could subsequently consume stale data. Posted write transactions must given opportunities pass delayed read write requests completions. Otherwise, deadlocks occur when some bridges which support delayed transactions other bridges which support delayed transactions Page 2003 Revision 1.02
PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION being used same system. fairness algorithm used arbitrate between posted write queue delayed transaction queue.
DATA SYNCHRONIZATION
Data synchronization refers relationship between interrupt signaling data delivery. Local Specification, Revision 2.2, provides following alternative methods synchronizing data interrupts: device signaling interrupt performs read data just written (software). device driver performs read operation register interrupting device before accessing data written device (software). System hardware guarantees that write buffers flushed before interrupts forwarded.
PI7C8154 does have hardware mechanism guarantee data synchronization posted write transactions. Therefore, posted write transactions must followed read operation, either from device location just written some other location along same path), from device driver device registers.
ERROR HANDLING
PI7C8154 checks, forwards, generates parity both primary secondary interfaces. maintain transparency, PI7C8154 always tries forward existing parity condition other bus, along with address data. PI7C8154 always attempts transparent when reporting errors, this always possible, given presence posted data delayed transactions. support error reporting bus, PI7C8154 implements following: PERR_L SERR_L signals both primary secondary interfaces Primary status secondary status registers device-specific P_SERR_L event disable register
This chapter provides detailed information about PI7C8154 handles errors. also describes error status reporting error operation disabling.
ADDRESS PARITY ERRORS
PI7C8154 checks address parity transactions both buses, address commands. When PI7C8154 detects address parity error primary interface, following events occur: parity error response command register, PI7C8154 does claim transaction with P_DEVSEL_L; this allow transaction terminate Page 2003 Revision 1.02
PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION master abort. parity error response set, PI7C8154 proceeds normally accepts transaction directed across PI7C8154. PI7C8154 sets detected parity error status register. PI7C8154 asserts P_SERR_L sets signaled system error status register, both following conditions met: SERR_L enable command register. parity error response command register.
When PI7C8154 detects address parity error secondary interface, following events occur: parity error response bridge control register, PI7C8154 does claim transaction with S_DEVSEL_L; this allow transaction terminate master abort. parity error response set, PI7C8154 proceeds normally accepts transaction directed across PI7C8154. PI7C8154 sets detected parity error secondary status register. PI7C8154 asserts P_SERR_L sets signaled system error status register, both following conditions met: SERR_L enable command register. parity error response bridge control register.
DATA PARITY ERRORS
When forwarding transactions, PI7C8154 attempts pass data parity condition from interface other unchanged, whenever possible, allow master target devices handle error condition. following sections describe, each type transaction, sequence events that occurs when parity error detected which parity condition forwarded across PI7C8154.
5.2.1
CONFIGURATION WRITE TRANSACTIONS CONFIGURATION SPACE
When PI7C8154 detects data parity error during Type configuration write transaction PI7C8154 configuration space, following events occur: parity error response command register, PI7C8154 asserts P_TRDY_L writes data configuration register. PI7C8154 also asserts P_PERR_L. parity error response set, PI7C8154 does assert P_PERR_L. PI7C8154 sets detected parity error status register, regardless state parity error response bit. Page 2003 Revision 1.02
PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
5.2.2
READ TRANSACTIONS
When PI7C8154 detects parity error during read transaction, target drives data data parity, initiator checks parity conditionally asserts PERR_L. downstream transactions, when PI7C8154 detects read data parity error secondary bus, following events occur: PI7C8154 asserts S_PERR_L cycles following data transfer, secondary interface parity error response bridge control register. PI7C8154 sets detected parity error secondary status register. PI7C8154 sets data parity detected secondary status register, secondary interface parity error response bridge control register. PI7C8154 forwards parity with data back initiator primary bus. data with parity pre-fetched read initiator primary bus, data discarded data with parity returned initiator. PI7C8154 completes transaction normally.
upstream transactions, when PI7C8154 detects read data parity error primary bus, following events occur: PI7C8154 asserts P_PERR_L cycles following data transfer, primary interface parity error response command register. PI7C8154 sets detected parity error primary status register. PI7C8154 sets data parity detected primary status register, primary interface parity-error-response command register. PI7C8154 forwards parity with data back initiator secondary bus. data with parity pre-fetched read initiator secondary bus, data discarded data with parity returned initiator. PI7C8154 completes transaction normally.
PI7C8154 returns initiator data parity that received from target. When initiator detects parity error this read data enabled report initiator asserts PERR_L cycles after data transfer occurs. assumed that initiator takes responsibility handling parity error condition; therefore, when PI7C8154 detects PERR_L asserted while returning read data initiator, PI7C8154 does take further action completes transaction normally.
5.2.3
DELAYED WRITE TRANSACTIONS
Page 2003 Revision 1.02
PI7C8154 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION When PI7C8154 detects data parity error during delayed write transaction, initiator drives data data parity, target checks parity conditionally asserts PERR_L. delayed write transactions, parity error occur following times: During original delayed write request transaction When initiator repeats delayed write request transaction When PI7C8154 completes delayed write transaction target
When delayed write transaction normally queued, address, command, address parity, data, byte enable bits, data parity captured target retry returned initiator. When PI7C8154 detects parity error write data initial delayed write request transaction, following events occur: parity-error-response corresponding initiator set, PI7C8154 asserts TRDY_L initiator transaction queued. multiple data phases requested, STOP_L also asserted cause target disconnect. cycles after data transfer, PI7C8154 also asserts PERR_L. parity-error-response set, PI7C8154 returns target retry. queues transaction usual. PI7C8154 does assert PERR_L. this case, initiator repeats transaction. PI7C8154 sets detected-parity-error status register corresponding initiator bus, regardless state parity-error-response bit.
Note: parity checking turned data parity errors have occurred queued subsequent delayed write tra
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