Interface Master 3.02 two-wire, bi-directional serial that provid

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Interface Master 3.02 two-wire, bi-directional serial that provid

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DI2CM
Interface Master 3.02
two-wire, bi-directional serial that provides simple efficient method data transmission over short distance between many devices. DI2CM core provides interface between microprocessor microcontroller bus. work master transmitter master receiver depending working mode determined microprocessor/microcontroller. DI2CM core incorporates features required latest specification including clock synchronization, arbitration, multi-master systems High-speed transmission mode. Built-in timer allows operation from wide range frequencies. Build-in 8-bit timer data transfers speed adjusting Host side interface dedicated User-defined timing (data setup, start setup, start hold, etc.) Fully synthesizable Static synchronous design with positive edge clocking synchronous reset internal tri-states Scan test ready
APPLICATIONS
Embedded microprocessor boards Consumer professional audio/video Home automotive radio Low-power applications Communication systems Cost-effective reliable automotive systems
FEATURES
Conforms v.2.1 specification Master operation
Master transmitter Master receiver
Support transmission speeds
Standard kb/s) Fast kb/s) High Speed Mb/s)
DELIVERABLES
Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, plain text EDIF netlist VHDL VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes
http://www.dcd.pl
Arbitration clock synchronization Support multi-master systems Support both 7-bit 10-bit addressing formats Interrupt generation
trademarks mentioned this document trademarks their respective owners.
Copyright 1999-2004 Digital Core Design. Rights Reserved.
core specification Datasheet Synthesis scripts Example application Technical support Core implementation support months maintenance Delivery Core updates, minor major versions changes Delivery documentation updates Phone email support
SYMBOL
datai(7:0) address(1:0) sclhs sclo sdao datao(7:0)
scli sdai
LICENSING
Comprehensible clearly defined licensing methods without royalty fees make using Core easy simply. Single Design license allows Core single FPGA bitstream ASIC implementation. Unlimited Designs, Year licenses allow Core unlimited number FPGA bitstreams ASIC implementations. cases number Core instantiations within design, number manufactured chips unlimited. There time restriction except Year license where time limited months.
PINS DESCRIPTION
address(1:0) scli sdai datai(7:0) datao(7:0) sclo sclhs sdao
TYPE
input input input input input input input input input output output output output output
DESCRIPTION
Global clock Global reset Processor address lines Chip select Processor write strobe Processor read strobe clock line (input) data line (input) Processor data (input) Processor data (output) clock line (output) High-speed clock line (output) data line (output) Processor interrupt line
Single Design license
VHDL, Verilog source code called Source Encrypted, plain text EDIF called Netlist
Year license
Encrypted Netlist only
Unlimited Designs license
Source Netlist
Upgrade from
Source Netlist Single Design Unlimited Designs
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2004 Digital Core Design. Rights Reserved.
BLOCK DIAGRAM
Figure below shows DI2CM Core block diagram.
address(1:0) datai(7:0) datao(7:0)
IMPLEMENTATION
Figures below show typical DI2CM implementations system with Standard/Fast High-speed devices.
sdai
Slave Address Shift Register Send Data Receive Data
Input Filter Output Register
Interface
sdao
Control Register Status Register
Control Logic
Arbitration Logic
sdai sdao
open drain
Clock Synchronization Timer
Input Filter Output Register Output Register
scli sclo
DI2CM
Slave device
Clock Generator
scli
sclhs
sclo
open drain
sclhs
Interface Performs interface functions between DI2CM internal blocks microprocessor. Allows easy connection core microprocessor/microcontroller system. Control Logic Manages execution commands sent interface. Synchronizes internal data flow. Shift Register Controls line, performs data address shifts during data transmission reception. Control Register Contains five control bits used performing types transmissions. Status Register Contains seven status bits that indicates state DI2CM core. Clock Generator Performs generation serial clock. Input Filter Performs spike filtering. Clock Synchronization Performs clock synchronization. Arbitration Logic Performs arbitration during operations multi-master systems. Timer Allows operation from wide range input frequencies. programmed user before transmission reprogrammed change frequency.
trademarks mentioned this document trademarks their respective owners.
DI2CM implementation I2C-bus system with Standard/Fast devices only
sdai sdao
open drain
DI2CM
Slave device
scli sclo
open drain
sclhs
current-source pull-up
DI2CM implementation I2C-bus system with High-speed devices
http://www.dcd.pl
Copyright 1999-2004 Digital Core Design. Rights Reserved.
PERFORMANCE
following table gives survey about Core area performance ALTERA® devices after Place Route (all features have been included):
Device MERCURY STRATIX Speed Logic Cells grade Fmax
CYCLONE APEX APEX20KC APEX20KE APEX20K ACEX1K FLEX10KE 7000AE 3000A Core performance ALTERA® devices
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2004 Digital Core Design. Rights Reserved.
main features each Digital Core Design compliant cores have been summarized table below. gives briefly member characterization helping user select most suitable Core application.
High-speed mode 10-bit addressing Master operation specification version 7-bit addressing Clock synchronization Slave operation Standard mode Passive device interface
interface
DI2CM DI2CS DI2CSB
Arbitration
Design
cores summary table
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2004 Digital Core Design. Rights Reserved.
Spike filtering
User defined timing
Fast mode
Interrupt generation
CONTACTS
modification special request please contact Digital Core Design local distributors. Headquarters: Wroclawska 41-902 Bytom, POLAND e-mail: iinffo@dcd.pll o@dcd tel.
Distributors: Please check
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.pl
Copyright 1999-2004 Digital Core Design. Rights Reserved.

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