2-Port PCI-to-PCI Bridge REVISION 1.04 3545 North First Stre
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PI7C8148A
2-Port PCI-to-PCI Bridge
REVISION 1.04
3545 North First Street, Jose, 95134 Telephone: 1-877-PERICOM, (1-877-737-4266) Fax: 408-435-1100 Email: solutions@pericom.com Internet: http://www.pericom.com
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
LIFE SUPPORT POLICY Pericom Semiconductor Corporation's products authorized critical components life support devices systems unless specific written agreement pertaining such intended executed between manufacturer officer PSC. Life support devices system devices systems which: intended surgical implant into body Support sustain life whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness. Pericom Semiconductor Corporation reserves right make changes products specifications time, without notice, order improve design performance supply best possible product. Pericom Semiconductor does assume responsibility circuitry described other than circuitry embodied Pericom Semiconductor product. Company makes representations that circuitry described herein free from patent infringement other rights third parties which result from use. license granted implication otherwise under patent, patent rights other rights, Pericom Semiconductor Corporation. other trademarks their respective companies.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
REVISION HISTORY
DATE 11-13-2003 03-25-2004 04-26-2004 05-10-2004 REVISION NUMBER 0.01 0.02 0.03 1.00 DESCRIPTION First Draft Datasheet First release preliminary datasheet Revisions/changes GPIO EEPROM references Revisions EEPROM references Revisions ordering information, correction package codes Further modifications EEPROM information Changed type "Data Select" 15.2.41 from Added power consumptions data section 16.6 Added TDELAY data sections 16.4 16.5 Revised descriptions sections 15.2.39, 15.2.47, 15.2.48. Added register descriptions (section 15.2.50 15.2.53)
05-17-2004 05-19-2004 06-11-2004 06-14-2004
1.01 1.02 1.03 1.04
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TABLE CONTENTS
SIGNAL DEFINITIONS.13 SIGNAL TYPES.13 SIGNALS 1.2.1 PRIMARY INTERFACE SIGNALS 1.2.2 SECONDARY INTERFACE SIGNALS 1.2.3 CLOCK SIGNALS 1.2.4 MISCELLANEOUS SIGNALS 1.2.5 GENERAL PURPOSE INTERFACE SIGNALS 1.2.6 POWER GROUND.17 LIST 160-PIN LFBGA.18 OPERATION.19 TYPES TRANSACTIONS SINGLE ADDRESS PHASE.20 DEVICE SELECT (DEVSEL#) GENERATION DATA PHASE.20 WRITE TRANSACTIONS.20 2.5.1 MEMORY WRITE TRANSACTIONS.21 2.5.2 MEMORY WRITE INVALIDATE 2.5.3 DELAYED WRITE TRANSACTIONS 2.5.4 WRITE TRANSACTION BOUNDARIES.23 2.5.5 BUFFERING MULTIPLE WRITE TRANSACTIONS.23 2.5.6 FAST BACK-TO-BACK TRANSACTIONS READ TRANSACTIONS 2.6.1 PREFETCHABLE READ TRANSACTIONS 2.6.2 DYNAMIC PREFETCHING CONTROL.24 2.6.3 NON-PREFETCHABLE READ TRANSACTIONS 2.6.4 READ PREFETCH ADDRESS BOUNDARIES 2.6.5 DELAYED READ REQUESTS 2.6.6 DELAYED READ COMPLETION WITH TARGET 2.6.7 DELAYED READ COMPLETION INITIATOR BUS.26 2.6.8 FAST BACK-TO-BACK READ TRANSACTIONS CONFIGURATION TRANSACTIONS.27 2.7.1 TYPE ACCESS PI7C8148A.28 2.7.2 TYPE TYPE CONVERSION 2.7.3 TYPE TYPE FORWARDING 2.7.4 SPECIAL CYCLES.30 TRANSACTION TERMINATION.30 2.8.1 MASTER TERMINATION INITIATED PI7C8148A 2.8.2 MASTER ABORT RECEIVED PI7C8148A 2.8.3 TARGET TERMINATION RECEIVED PI7C8148A 2.8.4 TARGET TERMINATION INITIATED PI7C8148A.34 ADDRESS DECODING.36 ADDRESS RANGES ADDRESS DECODING.36 3.2.1 BASE LIMIT ADDRESS REGISTER 3.2.2 MODE MEMORY ADDRESS DECODING 3.3.1 MEMORY-MAPPED BASE LIMIT ADDRESS REGISTERS 3.3.2 PREFETCHABLE MEMORY BASE LIMIT ADDRESS REGISTERS Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION SUPPORT 3.4.1 MODE 3.4.2 SNOOP MODE TRANSACTION ORDERING TRANSACTIONS GOVERNED ORDERING RULES GENERAL ORDERING GUIDELINES ORDERING RULES DATA SYNCHRONIZATION
ERROR HANDLING ADDRESS PARITY ERRORS.44 DATA PARITY ERRORS.45 5.2.1 CONFIGURATION WRITE TRANSACTIONS CONFIGURATION SPACE 5.2.2 READ TRANSACTIONS 5.2.3 DELAYED WRITE TRANSACTIONS 5.2.4 POSTED WRITE TRANSACTIONS DATA PARITY ERROR REPORTING SUMMARY.49 SYSTEM ERROR (SERR#) REPORTING
ARBITRATION PRIMARY ARBITRATION SECONDARY ARBITRATION.53 6.2.1 PREEMPTION 6.2.2 PARKING
CLOCKS PRIMARY CLOCK INPUTS SECONDARY CLOCK OUTPUTS CLOCKRUN GPIO CONTROL REGISTERS
GENERAL PURPOSE INTERFACE.55 EEPROM INTERFACE AUTO MODE EEPROM ACCESS EEPROM MODE RESET.56 EEPROM DATA STRUCTURE EEPROM SPACE ADDRESS MAP.56 9.4.1 EEPROM CONTENT.56
12.1 12.2 12.3 13.1 13.2
COMPACT SWAP.58 POWER MANAGEMENT RESET PRIMARY INTERFACE RESET.59 SECONDARY INTERFACE RESET CHIP RESET SUPPORTED COMMANDS PRIMARY INTERFACE SECONDARY INTERFACE
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION BRIDGE BEHAVIOR.62
14.1 BRIDGE ACTIONS VARIOUS CYCLE TYPES.62 14.2 ABNORMAL TERMINATION (INITIATED BRIDGE MASTER) 14.2.1 MASTER ABORT 14.2.2 PARITY ERROR REPORTING 14.2.3 REPORTING PARITY ERRORS.63 14.2.4 SECONDARY IDSEL MAPPING.63 CONFIGURATION REGISTERS.64 15.1 REGISTER TYPES 15.2 CONFIGURATION REGISTER.64 15.2.1 VENDOR REGISTER OFFSET 15.2.2 DEVICE REGISTER OFFSET 00h.65 15.2.3 COMMAND REGISTER OFFSET 15.2.4 PRIMARY STATUS REGISTER OFFSET 15.2.5 REVISION REGISTER OFFSET 08h.67 15.2.6 CLASS CODE REGISTER OFFSET 15.2.7 CACHE LINE REGISTER OFFSET 15.2.8 PRIMARY LATENCY TIMER REGISTER OFFSET 0Ch.67 15.2.9 HEADER TYPE REGISTER OFFSET 15.2.10 PRIMARY NUMBER REGISTER OFFSET 15.2.11 SECONDARY NUMBER REGISTER OFFSET 15.2.12 SUBORDINATE NUMBER REGISTER OFFSET 15.2.13 SECONDARY LATENCY TIMER REGISTER OFFSET 15.2.14 BASE ADDRESS REGISTER OFFSET 1Ch.68 15.2.15 LIMIT ADDRESS REGISTER OFFSET 15.2.16 SECONDARY STATUS REGISTER OFFSET 1Ch.69 15.2.17 MEMORY BASE ADDRESS REGISTER OFFSET 15.2.18 MEMORY LIMIT ADDRESS REGISTER OFFSET 15.2.19 PREFETCHABLE MEMORY BASE ADDRESS REGISTER OFFSET 24h.70 15.2.20 PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER OFFSET 15.2.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER OFFSET 15.2.22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER OFFSET 15.2.23 BASE ADDRESS UPPER 16-BITS REGISTER OFFSET 15.2.24 LIMIT ADDRESS UPPER 16-BITS REGISTER OFFSET 15.2.25 CAPABILITY POINTER REGISTER OFFSET 15.2.26 INTERRUPT LINE REGISTER OFFSET 15.2.27 INTERRUPT REGISTER OFFSET 15.2.28 BRIDGE CONTROL REGISTER OFFSET 15.2.29 DIAGNOSTIC/CHIP CONTROL REGISTER OFFSET 15.2.30 ARBITER CONTROL REGISTER OFFSET 15.2.31 EXTENDED CHIP CONTROL REGISTER OFFSET 15.2.32 SECONDARY ARBITER PREEMPTION CONTROL REGISTER OFFSET 15.2.33 P_SERR# EVENT DISABLE REGISTER OFFSET 15.2.34 SECONDARY CLOCK CONTROL REGISTER OFFSET 15.2.35 P_SERR# STATUS REGISTER OFFSET 68h.77 15.2.36 CLKRUN REGISTER OFFSET 15.2.37 PORT OPTION REGISTER OFFSET 74h.78 15.2.38 CAPABILITY REGISTER OFFSET 15.2.39 NEXT ITEM POINTER REGISTER OFFSET 15.2.40 POWER MANAGEMENT CAPABILITIES REGISTER OFFSET Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 15.2.41 15.2.42 15.2.43 15.2.44 15.2.45 15.2.46 15.2.47 15.2.48 15.2.49 15.2.50 15.2.51 15.2.52 15.2.53 15.2.54 15.2.55 15.2.56 15.2.57 15.2.58 15.2.59 15.2.60 15.2.61 16.1 16.2 16.3 16.4 16.5 16.6 17.1 17.2 POWER MANAGEMENT DATA REGISTER OFFSET 84h.81 SUPPORT EXTENSIONS OFFSET DATA REGISTER OFFSET 84h.81 PRIMARY MASTER TIMEOUT COUNTER REGISTER OFFSET 88h.82 SECONDARY MASTER TIMEOUT COUNTER REGISTER OFFSET CAPABILITY REGISTER OFFSET NEXT ITEM POINTER REGISTER OFFSET SWAP CAPABILITY STRUCTURE REGISTER OFFSET SWAP SWITCH REGISTER OFFSET CAPABILITY REGISTER OFFSET A0h.83 NEXT ITEM POINTER REGISTER OFFSET REGISTER OFFSET DATA REGISTER OFFSET A4h.84 MISCELLANEOUS CONTROL REGISTER OFFSET GPIO CONTROL REGISTER OFFSET EEPROM CONTROL REGISTER OFFSET EEPROM ADDRESS REGISTER OFFSET C8h.85 EEPROM DATA REGISTER OFFSET EEPROM TEST REGISTER OFFSET SUBSYSTEM VENDOR REGISTER OFFSET SUBSYSTEM OFFSET F0h.87
ELECTRICAL TIMING SPECIFICATIONS MAXIMUM RATINGS.87 SPECIFICATIONS SPECIFICATIONS 66MHZ TIMING 33MHZ TIMING POWER CONSUMPTION.89 PACKAGE INFORMATION.90 160-PIN LFBGA PACKAGE OUTLINE PART NUMBER ORDERING INFORMATION
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
LIST TABLES
TABLE 2-1. TRANSACTIONS TABLE 2-2. WRITE TRANSACTION FORWARDING TABLE 2-3. WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES TABLE 2-4. READ PREFETCH ADDRESS BOUNDARIES TABLE 2-5. READ TRANSACTION PREFETCHING TABLE 2-6. DEVICE NUMBER IDSEL S_AD MAPPING TABLE 2-7. DELAYED WRITE TARGET TERMINATION RESPONSE TABLE 2-8. RESPONSE POSTED WRITE TARGET TERMINATION TABLE 2-9. RESPONSE DELAYED READ TARGET TERMINATION TABLE 4-1. SUMMARY TRANSACTION ORDERING.43 TABLE 5-1. SETTING PRIMARY INTERFACE DETECTED PARITY ERROR TABLE 5-2. SETTING SECONDARY INTERFACE DETECTED PARITY ERROR TABLE 5-3. SETTING PRIMARY INTERFACE MASTER DATA PARITY ERROR DETECTED TABLE 5-4. SETTING SECONDARY INTERFACE MASTER DATA PARITY ERROR DETECTED BIT.50 TABLE 5-5. ASSERTION P_PERR# TABLE 5-6. ASSERTION S_PERR# TABLE 5-7. ASSERTION P_SERR# DATA PARITY ERRORS TABLE 11-1. POWER MANAGEMENT TRANSITIONS
LIST FIGURES
FIGURE 16-1 SIGNAL TIMING MEASUREMENT CONDITIONS FIGURE 17-1 160-PIN LFBGA PACKAGE OUTLINE
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
INTRODUCTION
Product Description
PI7C8148A Pericom Semiconductor's PCI-to-PCI Bridge, designed fully compliant with 32-bit, 66MHz implementation Local Specification, Revision 2.2. PI7C8148A supports synchronous transactions between devices Primary Secondary Buses operating 66MHz. Both primary secondary buses must operate same frequency. primary secondary buses also operate concurrent mode, resulting added increase system performance.
Product Features
32-bit Primary Secondary Ports 66MHz Compliant with Local Specification, Revision Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.1. memory commands Type Type configuration conversion Type Type configuration forwarding Type configuration write special cycle conversion Compliant with Advanced Configuration Power Interface (ACPI) Compliant with Power Management Specification, Revision Compliant with Mobile Design Guide, Revision Provides internal arbitration four secondary masters Programmable 2-level priority arbiter Supports serial EEPROM interface register auto-load access Supports posted write buffers directions Dynamic Prefetching Control Four byte FIFO's delay transactions byte FIFO's posted memory transactions Enhanced address decoding 32-bit address range 32-bit memory-mapped address range 64-bit prefetchable address range Extended commercial temperature range 85°C 3.3V signaling 160-pin LFBGA package
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SIGNAL DEFINITIONS
SIGNAL TYPES
SIGNAL TYPE DESCRIPTION Input only Output only Power Tri-state bi-directional Sustained tri-state. Active signal must pulled HIGH cycle when deasserting. Open Drain
SIGNALS
Signals that with active LOW.
1.2.1
PRIMARY INTERFACE SIGNALS
Name P_AD[31:0] Number P10, N10, M10, P11, N11, M11, P12, N12, M14, L12, L13, L14, K12, K13, K14, J12, E14, E13, E12, D14, D13, D12, C13, B14, B12, A12, C11, B11, A11, C10, A10, P14, J13, F12, Type Description Primary Address Data: Multiplexed address data bus. Address indicated P_FRAME# assertion. Write data stable valid when P_IRDY# asserted read data stable valid when P_TRDY# asserted. Data transferred rising clock edges when both P_IRDY# P_TRDY# asserted. During idle, PI7C8148A drives P_AD valid logic level when P_GNT# asserted. Primary Command/Byte Enables: Multiplexed command field byte enable field. During address phase, initiator drives transaction type these pins. After that, initiator drives byte enables during data phases. During idle, PI7C8148A drives P_CBE#[3:0] valid logic level when P_GNT# asserted. Primary Parity. Parity even across P_AD[31:0], P_CBE#[3:0], P_PAR (i.e. even number 1's). P_PAR input valid stable cycle after address phase (indicated assertion P_FRAME#) address parity. write data phases, P_PAR input valid clock after P_IRDY# asserted. read data phase, P_PAR output valid clock after P_TRDY# asserted. Signal P_PAR tri-stated cycle after P_AD lines tri-stated. During idle, PI7C8148A drives P_PAR valid logic level when P_GNT# asserted. Primary FRAME (Active LOW). Driven initiator transaction indicate beginning duration access. de-assertion P_FRAME# indicates final data phase requested initiator. Before being tri-stated, driven de-asserted state cycle. Primary IRDY (Active LOW). Driven initiator transaction indicate ability complete current data phase primary side. Once asserted data phase, deasserted until data phase. Before tri-stated, driven de-asserted state cycle.
P_CBE#[3:0]
P_PAR
P_FRAME#
P_IRDY#
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name P_TRDY# Number Type Description Primary TRDY (Active LOW). Driven target transaction indicate ability complete current data phase primary side. Once asserted data phase, deasserted until data phase. Before tri-stated, driven de-asserted state cycle. Primary Device Select (Active LOW). Asserted target indicating that device accepting transaction. master, PI7C8148A waits assertion this signal within cycles P_FRAME# assertion; otherwise, terminate with master abort. Before tri-stated, driven de-asserted state cycle. Primary STOP (Active LOW). Asserted target indicating that target requesting initiator stop current transaction. Before tri-stated, driven de-asserted state cycle. Primary Select. Used chip select line Type configuration access PI7C8148A configuration space. Primary Parity Error (Active LOW). Asserted when data parity error detected data received primary interface. Before being tri-stated, driven de-asserted state cycle. Primary System Error (Active LOW). driven device indicate system error condition. PI7C8148A drives this Address parity error Posted write data parity error target Secondary S_SERR# asserted Master abort during posted write transaction Target abort during posted write transaction Posted write transaction discarded Delayed write request discarded Delayed read request discarded Delayed transaction master timeout This signal requires external pull-up resistor proper operation. Primary Request (Active LOW): This asserted PI7C8148A indicate that wants start transaction primary bus. PI7C8148A de-asserts this least clock cycles before asserting again. Primary Grant (Active LOW): When asserted, PI7C8148A access primary bus. During idle P_GNT# asserted, PI7C8148A will drive P_AD, P_CBE, P_PAR valid logic levels. Primary RESET (Active LOW): When P_RST# active, signals should asynchronously tri-stated.
P_DEVSEL#
P_STOP#
P_IDSEL P_PERR#
P_SERR#
P_REQ#
P_GNT#
P_RST#
1.2.2
SECONDARY INTERFACE SIGNALS
Name S_AD[31:0] Number Type Description Secondary Address/Data: Multiplexed address data bus. Address indicated S_FRAME# assertion. Write data stable valid when S_IRDY# asserted read data stable valid when S_TRDY# asserted. Data transferred rising clock edges when both S_IRDY# S_TRDY# asserted. During idle, PI7C8148A drives S_AD valid logic level when S_GNT# asserted respectively. Secondary Command/Byte Enables: Multiplexed command field byte enable field. During address phase, initiator drives transaction type these pins. initiator then drives byte enables during data phases. During idle, PI7C8148A drives S_CBE#[3:0] valid logic level when internal grant asserted.
S_CBE#[3:0]
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Name S_PAR Number Type Description Secondary Parity: Parity even across S_AD[31:0], S_CBE#[3:0], S_PAR (i.e. even number 1's). S_PAR input valid stable cycle after address phase (indicated assertion S_FRAME#) address parity. write data phases, S_PAR input valid clock after S_IRDY# asserted. read data phase, S_PAR output valid clock after S_TRDY# asserted. Signal S_PAR tri-stated cycle after S_AD lines tri-stated. During idle, PI7C8148A drives S_PAR valid logic level when internal grant asserted. Secondary FRAME (Active LOW): Driven initiator transaction indicate beginning duration access. de-assertion S_FRAME# indicates final data phase requested initiator. Before being tri-stated, driven de-asserted state cycle. Secondary IRDY (Active LOW): Driven initiator transaction indicate ability complete current data phase secondary side. Once asserted data phase, deasserted until data phase. Before tri-stated, driven de-asserted state cycle. Secondary TRDY (Active LOW): Driven target transaction indicate ability complete current data phase secondary side. Once asserted data phase, deasserted until data phase. Before tri-stated, driven de-asserted state cycle. Secondary Device Select (Active LOW): Asserted target indicating that device accepting transaction. master, PI7C8148A waits assertion this signal within cycles S_FRAME# assertion; otherwise, terminate with master abort. Before tri-stated, driven de-asserted state cycle. Secondary STOP (Active LOW): Asserted target indicating that target requesting initiator stop current transaction. Before tri-stated, driven de-asserted state cycle. Secondary Parity Error (Active LOW): Asserted when data parity error detected data received secondary interface. Before being tri-stated, driven de-asserted state cycle. Secondary System Error (Active LOW): driven device indicate system error condition. Secondary Request (Active LOW): This asserted external device indicate that wants start transaction secondary bus. input externally pulled through resistor VDD. Secondary Grant (Active LOW): PI7C8148A asserts these pins allow external masters access secondary bus. PI7C8148A de-asserts these pins least clock cycles before asserting again. During idle S_GNT# deasserted, PI7C8148A will drive S_AD, S_CBE, S_PAR. Secondary RESET (Active LOW): Asserted when following conditions met: Signal P_RST# asserted. Secondary reset bridge control register configuration space set. When asserted, control signals tri-stated zeroes driven S_AD, S_CBE, S_PAR.
S_FRAME#
S_IRDY#
S_TRDY#
S_DEVSEL#
S_STOP#
S_PERR#
S_SERR# S_REQ#[3:0]
S_GNT#[3:0]
S_RST#
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1.2.3
CLOCK SIGNALS
Name P_CLK S_CLKIN S_CLKOUT[4:0] Number Type Description Primary Clock Input: Provides timing transactions primary interface. Secondary Clock Input: Provides timing transactions secondary interface. Secondary Clock Output: Provides secondary clocks phase synchronous with P_CLK. clock outputs must back S_CLKIN. Unused outputs disabled Writing secondary clock disable bits configuration space Terminating them electrically. Primary Clock Run: Allows main system stop primary clock based specifications Mobile Design Guide, Revision 1.0. unused, this should tied ground signify that P_CLK always running. Secondary Clock Run: Allows main system slow down stop secondary clock controlled primary bit[4] offset 6Fh. secondary devices support CLKRUN, this should pulled resistor.
P_CLKRUN#
S_CLKRUN#
1.2.4
MISCELLANEOUS SIGNALS
Name ENUM# Number Type Description Swap Status Indicator: output ENUM# indicates system that insertion occurred that extraction about occur. Swap LED: output this lights indicate insertion removal ready status. This also used input detect pin. Every 500us, tri-states primary clock cycles sample status. Swap Switch. When driven LOW, this signal indicates that board ejector handle indicates insertion impending extraction board. EEPROM Clock: Clock signal EEPROM interface EEPROM Data: Serial data interface EEPROM Primary Voltage: This used determine either 3.3V signaling primary bus. P_VIO must tied 3.3V only when devices primary 3.3V signaling. Otherwise, P_VIO tied Secondary Voltage: This used determine either 3.3V signaling secondary bus. S_VIO must tied 3.3V only when devices secondary 3.3V signaling. Otherwise, S_VIO tied Full-Scan Test Mode Enable: normal operation, pull SCAN_TM# HIGH. Manufacturing test pin. Full-Scan Enable Control: normal operation, SCAN_TM# should pulled HIGH SCAN_EN becomes output with logic Manufacturing test pin. Bus/Power Clock Control Management Pin: When this tied HIGH PI7C8148A placed D3HOT power state, enables PI7C8148A place secondary power state. secondary clocks disabled driven When this tied LOW, there effect secondary clocks when PI7C8148A enters D3HOT power state.
EJECT EECLK EEPD P_VIO
S_VIO
SCAN_TM# SCAN_EN BPCEE
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1.2.5
GENERAL PURPOSE INTERFACE SIGNALS
Name GPIO[3:0] Number M13, P13, Type Description General Purpose Data Pins: general-purpose signals programmable either input-only bi-directional signals writing GPIO output enable control register configuration space.
1.2.6
POWER GROUND
Name Number F11, G11, H11, J11, B13, C12, D10, D11, E11, K11, L10, L11, M12, Type Description Power: 3.3V power
Ground
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LIST 160-PIN LFBGA
Number Name BPCEE S_AD[15] S_AD[10] S_AD[5] S_AD[1] P_AD[3] P_CBE#[0] S_PAR S_CLKRUN# S_AD[11] S_AD[6] S_AD[0] P_AD[4] S_PERR# S_AD[12] S_AD[7] P_AD[0] P_AD[5] P_AD[9] S_TRDY# S_STOP# P_AD[11] EEPD S_IRDY# P_AD[14] S_AD[17] S_CBE#[2] P_PAR S_AD[20] S_AD[18] EECLK S_AD[21] S_AD[23] P_TRDY# S_CBE#[3] S_AD[25] P_CBE#[2] S_AD[26] S_AD[27] P_AD[18] S_AD[28] S_AD[30] P_AD[21] Type Number Name S_CBE#[1] S_AD[13] S_CBE#[0] S_AD[4] P_AD[1] P_AD[6] P_CLKRUN# ENUM# S_AD[8] S_AD[3] P_AD[7] P_AD[8] S_SERR# S_AD[14] S_AD[9] S_AD[2] P_AD[2] EJECT S_DEVSEL# P_AD[10] P_AD[12] S_FRAME# P_AD[13] P_AD[15] S_AD[16] P_CBE#[1] P_SERR# S_AD[19] P_PERR# P_STOP# S_AD[22] P_IRDY# P_DEVSEL# S_AD[24] P_AD[16] P_FRAME# GPIO[0] P_AD[19] P_AD[17] S_AD[29] P_AD[22] P_AD[20] Type
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Number Name S_AD[31] S_CLKIN S_CLKOUT[4] P_REQ# P_AD[26] GPIO[3] S_REQ#[1] S_GNT#[0] S_VIO SCAN_EN P_GNT# P_AD[27] S_REQ#[2] S_GNT#[1] S_CLKOUT[0] SCAN_TM# P_VIO P_AD[28] GPIO[2] Type Number Name S_REQ#[0] S_GNT#[2] S_CLKOUT[1] P_CLK P_AD[29] P_AD[23] S_GNT#[3] S_CLKOUT[2] GPIO[1] P_AD[30] P_AD[24] P_IDSEL S_REQ#[3] S_RST# S_CLKOUT[3] P_RST# P_AD[31] P_AD[25] P_CBE#[3] Type
OPERATION
This Chapter offers information about transactions, transaction forwarding across bridge, transaction termination. bridge 128-byte FIFO's buffering upstream downstream transactions. These hold addresses, data, commands, byte enables that used write transactions. bridge also additional four 128-byte FIFO's that hold addresses, data, commands, byte enables read transactions.
TYPES TRANSACTIONS
This section provides summary transactions performed bridge. Table lists command code name each transaction. Master Target columns indicate support each transaction when bridge initiates transactions master, primary secondary buses, when bridge responds transactions target, primary secondary buses. Table 2-1. Transactions
Types Transactions 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Interrupt Acknowledge Special Cycle Read Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Initiates Master Primary (Type only) Secondary Responds Target Primary Secondary (Type only)
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Types Transactions 1101 1110 1111 Dual Address Cycle Memory Read Line Memory Write Invalidate Initiates Master Primary Responds Target Primary Secondary
Secondary
indicated Table 2-1, following commands supported bridge: bridge never initiates transaction with reserved command code and, target, bridge ignores reserved command codes. bridge does generate interrupt acknowledge transactions. bridge ignores interrupt acknowledge transactions target. bridge does respond special cycle transactions. bridge cannot guarantee delivery special cycle transaction downstream buses because broadcast nature special cycle command inability control transaction target. generate special cycle transactions other buses, either upstream downstream, Type configuration write must used. bridge neither generates Type configuration transactions primary responds Type configuration transactions secondary buses.
SINGLE ADDRESS PHASE
32-bit address uses single address phase. This address driven P_AD[31:0], command driven P_CBE[3:0]. bridge supports linear increment address mode only, which indicated when lowest address bits equal zero. either lowest address bits nonzero, bridge automatically disconnects transaction after first data transfer.
DEVICE SELECT (DEVSEL#) GENERATION
bridge always performs positive address decoding (medium decode) when accepting transactions either primary secondary buses. bridge never does subtractive decode.
DATA PHASE
address phase transaction followed more data phases. data phase completed when IRDY# either TRDY# STOP# asserted. transfer data occurs only when both IRDY# TRDY# asserted during same clock cycle. last data phase transaction indicated when FRAME# de-asserted both TRDY# IRDY# asserted, when IRDY# STOP# asserted. Section further discussion transaction termination. Depending command type, bridge support multiple data phase transactions. detailed descriptions bridge imposes disconnect boundaries, Section 2.5.4 write address boundaries Section 2.6.4 read address boundaries.
WRITE TRANSACTIONS
Write transactions treated either posted write delayed write transactions. Table shows method forwarding used each type write operation. Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Table 2-2. Write Transaction Forwarding
Type Transaction Memory Write Memory Write Invalidate Memory Write memory Write Type Configuration Write Type Forwarding Posted (except memory) Posted Delayed Delayed Delayed
2.5.1
MEMORY WRITE TRANSACTIONS
Posted write forwarding used "Memory Write" "Memory Write Invalidate" transactions. When bridge determines that memory write transaction forwarded across bridge, bridge asserts DEVSEL# with medium timing TRDY# next cycle, provided that enough buffer space available posted memory write queue address least DWORD data. Under this condition, bridge accepts write data without obtaining access target bus. bridge accept DWORD write data every clock cycle. That target wait state inserted. write data stored internal posted write buffers subsequently delivered target. bridge continues accept write data until following events occurs: initiator terminates transaction de-asserting FRAME# IRDY#. internal write address boundary reached, such cache line boundary aligned boundary, depending transaction type. posted write data buffer fills
When last events occurs, bridge returns target disconnect requesting initiator this data phase terminate transaction. Once posted write data moves head posted data queue, bridge asserts request target bus. This occur while bridge still receiving data initiator bus. When grant target received target detected idle condition, bridge asserts FRAME# drives stored write address target bus. following cycle, bridge drives first DWORD write data continues transfer write data until write data corresponding that transaction delivered, until target termination received. long write data exists queue, bridge drive DWORD write data each clock cycle; that master wait states inserted. write data flowing through bridge initiator stalls, bridge will signal last data phase current transaction target queue empties. bridge will restart follow-on transactions queue data. bridge ends transaction target when following conditions met: posted write data been delivered target. target returns target disconnect target retry (the bridge starts another transaction deliver rest write data). target returns target abort (the bridge discards remaining write data). master latency timer expires, bridge longer target grant (the bridge starts another transaction deliver remaining write data).
Section 2.8.3.2 provides detailed information about bridge responds target termination during posted write transactions.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
2.5.2
MEMORY WRITE INVALIDATE
Posted write forwarding used Memory Write Invalidate transactions. offset bits [8:7] bridge disconnects Memory Write Invalidate commands aligned cache line boundaries. cache line size value cache line size register gives number DWORD cache line. offset bits [8:7] bridge converts Memory Write Invalidate transactions Memory Write transactions destination. value cache line size register does meet memory write invalidate conditions, bridge returns target disconnect initiator cache line boundary.
2.5.3
DELAYED WRITE TRANSACTIONS
Delayed write forwarding used write transactions Type configuration write transactions. delayed write transaction guarantees that actual target response returned back initiator without holding initiating wait states. delayed write transaction limited single DWORD data transfer. When write transaction first detected initiator bus, bridge forwards delayed transaction, bridge claims access asserting DEVSEL# returns target retry initiator. During address phase, bridge samples command, address, address parity cycle later. After IRDY# asserted, bridge also samples first data DWORD, byte enable bits, data parity. This information placed into delayed transaction queue. transaction queued only other existing delayed transactions have same address command, delayed transaction queue full. When delayed write transaction moves head delayed transaction queue ordering constraints with posted data satisfied. bridge initiates transaction target bus. bridge transfers write data target. bridge receives target retry response write transaction target bus, continues repeat write transaction until data transfer completed, until error condition encountered. bridge unable deliver write data after (default) (maximum) attempts, bridge will report system error. bridge also asserts P_SERR# primary SERR# enable command register. Section information assertion P_SERR#. When initiator repeats same write transaction (same command, address, byte enable bits, data), completed delayed transaction head queue, bridge claims access asserting DEVSEL# returns TRDY# initiator, indicate that write data transferred. initiator requests multiple DWORD, bridge also asserts STOP# conjunction with TRDY# signal target disconnect. Note that only those bytes write data with valid byte enable bits compared. byte enable bits turned (driven HIGH), corresponding byte write data compared. initiator repeats write transaction before data been transferred target, bridge returns target retry initiator. bridge continues return target retry initiator until write data delivered target, until error condition encountered. When write transaction repeated, bridge does make entry into delayed transaction queue. Section 2.8.3.1 provides detailed information about bridge responds target termination during delayed write transactions.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION bridge implements discard timer that starts counting when delayed write completion head delayed transaction completion queue. initial value this timer retry counter register offset 88h. initiator does repeat delayed write transaction before discard timer expires, bridge discards delayed write completion from delayed transaction completion queue. bridge also conditionally asserts P_SERR# (see Section 5.4).
2.5.4
WRITE TRANSACTION BOUNDARIES
bridge imposes internal address boundaries when accepting write data. aligned address boundaries used prevent bridge from continuing transaction over device address boundary provide upper limit maximum latency. bridge returns target disconnect initiator when reaches aligned address boundaries under conditions shown Table 2-3. Table 2-3. Write Transaction Disconnect Address Boundaries
Type Transaction Delayed Write Posted Memory Write Posted Memory Write Posted Memory Write Invalidate Posted Memory Write Invalidate Condition Memory write disconnect control 0(1) Memory write disconnect control 1(1) Cache line size Cache line size Aligned Address Boundary Disconnects after data transfer aligned address boundary Disconnects cache line boundary aligned address boundary
Cache line boundary posted memory write data FIFO does have enough space cache line Note Memory write disconnect control chip control register offset configuration space.
2.5.5
BUFFERING MULTIPLE WRITE TRANSACTIONS
bridge continues accept posted memory write transactions long space least DWORD data posted write data buffer remains. posted write data buffer fills before initiator terminates write transaction, bridge returns target disconnect initiator. Delayed write transactions posted long least open entry delayed transaction queue exists. Therefore, several posted delayed write transactions exist data buffers same time. Chapter information about multiple posted delayed write transactions ordered.
2.5.6
FAST BACK-TO-BACK TRANSACTIONS
bridge recognize post fast back-to-back write transactions. When bridge cannot accept second transaction because buffer space limitations, returns target retry initiator. fast back-to-back enable must command register upstream write transactions, bridge control register downstream write transactions.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
READ TRANSACTIONS
Delayed read forwarding used read transactions crossing bridge. Delayed read transactions treated either prefetchable non-prefetchable. Table shows read behavior, prefetchable non-prefetchable, each type read operation.
2.6.1
PREFETCHABLE READ TRANSACTIONS
prefetchable read transaction read transaction where bridge performs speculative DWORD reads, transferring data from target before requested from initiator. This behavior allows prefetchable read transaction consist multiple data transfers. However, byte enable bits cannot forwarded data phases done single data phase non-prefetchable read transaction. prefetchable read transactions, bridge forces byte enable bits turned data phases. Prefetchable behavior used memory read line memory read multiple transactions, well memory read transactions that fall into prefetchable memory space. amount data that pre-fetched depends type transaction. amount pre-fetching also affected amount free buffer space available bridge, read address boundaries encountered. Pre-fetching should used those read transactions that have side effects target device, that control status registers, FIFO's, target device's base address register registers indicate memory address region prefetchable.
2.6.2
DYNAMIC PREFETCHING CONTROL
prefetchable reads described previous section, prefetching length normally predefined cannot changed once set. This cause some inefficiency prefetching length determined could larger smaller than actual data being prefetched. make prefetching more efficient, PI7C8148A incorporates dynamic prefetching control logic. This logic regulates different memory read commands memory read, memory read line, memory read multiple) improve memory read burst performance. bridge tracks every memory read burst transaction tallies status. using status information, bridge determine increase, reduce, keep same cache line length prefetched. Over time, bridge better match correct cache line setting length data being requested. dynamic prefetching control logic with bits[3:2] offset 48h.
2.6.3
NON-PREFETCHABLE READ TRANSACTIONS
non-prefetchable read transaction read transaction where bridge requests only DWORD from target disconnects initiator after delivery first DWORD read data. Unlike prefetchable read transactions, bridge forwards read byte enable information data phase. Non-prefetchable behavior used configuration read transactions, well memory read transactions that fall into non-prefetchable memory space. Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
extra read transactions could have side effects, example, when accessing FIFO, nonprefetchable read transactions those locations. Accordingly, important retain value byte enable bits during data phase, non-prefetchable read transactions. these locations mapped memory space, memory read command target into non-prefetchable (memory-mapped I/O) memory space non-prefetching behavior.
2.6.4
READ PREFETCH ADDRESS BOUNDARIES
bridge imposes internal read address boundaries read pre-fetched data. When read transaction reaches these aligned address boundaries, bridge stops pre-fetched data, unless target signals target disconnect before read pre-fetched boundary reached. When bridge finishes transferring this read data initiator, returns target disconnect with last data transfer, unless initiator completes transaction before pre-fetched read data delivered. leftover prefetched data discarded. Prefetchable read transactions flow-through mode pre-fetch nearest aligned address boundary, until initiator de-asserts FRAME_L. Section 2.6.7 describes flow-through mode during read operations. Table shows read prefetch address boundaries read transactions during non-flow-through mode. Table 2-4. Read Prefetch Address Boundaries
Cache Line Size (CLS) Configuration Read Read Memory Read Non-Prefetchable Memory Read Prefetchable Memory Read Prefetchable Memory Read Line Memory Read Line Memory Read Multiple Memory Read Multiple does matter prefetchable non-prefetchable don't care Type Transaction Address Space Prefetch Aligned Address Boundary DWORD prefetch) DWORD prefetch) DWORD prefetch) 16-DWORD aligned address boundary Cache line address boundary 16-DWORD aligned address boundary Cache line boundary 32-DWORD aligned address boundary cache line boundary
Table 2-5. Read Transaction Prefetching
Read Behavior Prefetching never allowed Prefetching never allowed Downstream: Prefetching used address prefetchable space Memory Read Upstream: Prefetching used programmable Memory Read Line Prefetching always used Memory Read Multiple Prefetching always used Section detailed information about prefetchable non-prefetchable address spaces. Type Transaction Read Configuration Read
2.6.5
DELAYED READ REQUESTS
bridge treats read transactions delayed read transactions, which means that read request from initiator posted into delayed transaction queue. Read data from target placed Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION read data queue directed toward initiator interface transferred initiator when initiator repeats read transaction. When bridge accepts delayed read request, first samples read address, read command, address parity. When IRDY# asserted, bridge then samples byte enable bits first data phase. This information entered into delayed transaction queue. bridge terminates transaction signaling target retry initiator. Upon reception target retry, initiator required continue repeat same read transaction until least data transfer completed, until target response (target abort master abort) other than target retry received.
2.6.6
DELAYED READ COMPLETION WITH TARGET
When delayed read request reaches head delayed transaction queue, bridge arbitrates target initiates read transaction only previously queued posted write transactions have been delivered. bridge uses exact read address read command captured from initiator during initial delayed read request initiate read transaction. read transaction non-prefetchable read, bridge drives captured byte enable bits during next cycle. transaction prefetchable read transaction, drives byte enable bits zero data phases. bridge receives target retry response read transaction target bus, continues repeat read transaction until least data transfer completed, until error condition encountered. transaction terminated normal master termination target disconnect after least data transfer been completed, bridge does initiate further attempts read more data. bridge unable obtain read data from target after (default) (maximum) attempts, bridge will report system error. number attempts programmable. bridge also asserts P_SERR# primary SERR# enable command register. Section information assertion P_SERR#. Once bridge receives DEVSEL# TRDY# from target, transfers data read opposite direction read data queue, pointing toward opposite inter-face, before terminating transaction. example, read data response downstream read transaction initiated primary placed upstream read data queue. bridge accept DWORD read data each clock cycle; that master wait states inserted. number DWORD's transferred during delayed read transaction depends conditions given Table (assuming disconnect received from target).
2.6.7
DELAYED READ COMPLETION INITIATOR
When transaction been completed target bus, delayed read data head read data queue, ordering constraints with posted write transactions have been satisfied, bridge transfers data initiator when initiator repeats transaction. memory read transactions, bridge aliases memory read, memory read line, memory read multiple commands when matching command transaction command delayed transaction queue. bridge returns target disconnect along with transfer last DWORD read data initiator. bridge initiator terminates transaction before read data been transferred, remaining read data left data buffers discarded. When master repeats transaction starts transferring prefetchable read data from data buffers while read transaction target still progress before read boundary reached target bus, read transaction starts operating flow-through mode. Because data flowing Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION through data buffers from target initiator, long read bursts then sustained. this case, read transaction allowed continue until initiator terminates transaction, until aligned address boundary reached, until buffer fills, whichever comes first. When buffer empties, bridge reflects stalled condition initiator disconnecting initiator with data. initiator retry transaction later data needed. initiator does need more data, initiator will continue disconnected transaction. this case, bridge will start master timeout timer. remaining read data will discarded after master timeout timer expires. provide better latency, there other pending data other transactions (Read Data Buffer), remaining read data will discarded even though master timeout timer expired. bridge implements master timeout timer that starts counting when delayed read completion head delayed transaction queue, read data head read data queue. initial value this timer programmable through configuration register. initiator does repeat read transaction before master timeout timer expires (215 default), bridge discards read transaction read data from queues. bridge also conditionally asserts P_SERR# (see Section 5.4). bridge capability post multiple delayed read requests, maximum four each direction. initiator starts read transaction that matches address read command read transaction that already queued, current read command posted already contained delayed transaction queue. Section discussion delayed read transactions ordered when crossing bridge.
2.6.8
FAST BACK-TO-BACK READ TRANSACTIONS
bridge recognize fast back-to-back read transactions.
CONFIGURATION TRANSACTIONS
Configuration transactions used initialize system. Every device configuration space that accessed configuration commands. registers accessible configuration space only. addition accepting configuration transactions initialization configuration space, bridge also forwards configuration transactions device initialization hierarchical systems, well special cycle generation. support hierarchical systems, types configuration transactions specified: Type Type Type configuration transactions issued when intended target resides same initiator. Type configuration transaction identified configuration command lowest bits address 00b. Type configuration transactions issued when intended target resides another bus, when special cycle generated another bus. Type configuration command identified configuration command lowest address bits 01b.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION register number found both Type Type formats gives DWORD address configuration register accessed. function number also included both Type Type formats indicates which function multifunction device accessed. single-function devices, this value decoded. addresses Type configuration transaction include 5-bit field designating device number that identifies device target that accessed. addition, number Type transactions specifies which transaction targeted.
2.7.1
TYPE ACCESS PI7C8148A
configuration space accessed Type configuration transaction primary interface. configuration space cannot accessed from secondary bus. bridge responds Type configuration transaction asserting P_DEVSEL# when following conditions during address phase: command configuration read configuration write transaction. Lowest address bits P_AD[1:0] must 00b. Signal P_IDSEL must asserted.
bridge limits configuration access single DWORD data transfer returns targetdisconnect with first data transfer additional data phases requested. Because read transactions configuration space have side effects, bytes requested DWORD returned, regardless value byte enable bits. Type configuration write read transactions data buffers; that these transactions completed immediately, regardless state data buffers. bridge ignores Type transactions initiated secondary interface.
2.7.2
TYPE TYPE CONVERSION
Type configuration transactions used specifically device configuration hierarchical system. PCI-to-PCI bridge only type device that should respond Type configuration command. Type configuration commands used when configuration access intended device that resides other than where Type transaction generated. bridge performs Type Type translation when Type transaction generated primary intended device attached directly secondary bus. bridge must convert configuration command Type format that secondary device respond Type Type translations performed only downstream direction; that bridge generates Type transaction only secondary bus, never primary bus. bridge responds Type configuration transaction translates into Type transaction secondary when following conditions during address phase: lowest address bits P_AD[1:0] 01b. number address field P_AD[23:16] equal value secondary number register configuration space. command P_CBE[3:0] configuration read configuration write transaction. When bridge translates Type transaction Type transaction secondary interface, performs following translations address: Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Sets lowest address bits S_AD[1:0]. Decodes device number drives pattern specified Table S_AD[31:16] purpose asserting device's IDSEL signal. Sets S_AD[15:11] Leaves unchanged function number register number fields.
bridge asserts unique address line based device number. These address lines used secondary IDSEL signals. mapping address lines depends device number Type address bits P_AD[15:11]. presents mapping that bridge uses. Table 2-6. Device Number IDSEL S_AD Mapping
Device Number P_AD[15:11] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 11110 11111 Secondary IDSEL S_AD[31:16] 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 Generate special cycle (P_AD[7:2] 00h) 0000 0000 0000 0000 (P_AD[7:2] 00h) S_AD
bridge assert unique address lines used IDSEL signals devices secondary bus, device numbers ranging from through Because electrical loading constraints bus, more than IDSEL signals should necessary. However, device numbers greater than desired, some external method generating IDSEL lines must used, upper address bits then asserted. configuration transaction still translated passed from primary secondary bus. IDSEL asserted secondary device, transaction ends master abort. bridge forwards Type Type configuration read write transactions delayed transactions. Type Type configuration read write transactions limited single 32-bit data transfer.
2.7.3
TYPE TYPE FORWARDING
Type Type transaction forwarding provides hierarchical configuration mechanism when more levels PCI-to-PCI bridges used. When bridge detects Type configuration transaction intended downstream from secondary bus, bridge forwards transaction unchanged secondary bus. Ultimately, this transaction translated Type configuration command special cycle transaction downstream PCI-to-PCI bridge. Downstream Type Type forwarding occurs when following conditions during address phase: lowest address bits equal 01b. Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION number falls range defined lower limit (exclusive) secondary number register upper limit (inclusive) subordinate number register. command configuration read write transaction.
bridge also supports Type Type forwarding configuration write transactions upstream support upstream special cycle generation. Type configuration command forwarded upstream when following conditions met: lowest address bits equal 01b. number falls outside range defined lower limit (inclusive) secondary number register upper limit (inclusive) subordinate number register. device number address bits AD[15:11] equal 11111b. function number address bits AD[10:8] equal 111b. command configuration write transaction.
bridge forwards Type Type configuration write transactions delayed transactions. Type Type configuration write transactions limited single data transfer.
2.7.4
SPECIAL CYCLES
Type configuration mechanism used generate special cycle transactions hierarchical systems. Special cycle transactions ignored acting target forwarded across bridge. Special cycle transactions generated from Type configuration write transactions either upstream down-stream direction. birdge initiates special cycle target when Type configuration write transaction being detected initiating following conditions during address phase: lowest address bits AD[1:0] equal 01b. device number address bits AD[15:11] equal 11111b. function number address bits AD[10:8] equal 111b. register number address bits AD[7:2] equal 000000b. number equal value secondary number register configuration space downstream forwarding equal value primary number register configuration space upstream forwarding. command CBE# configuration write command.
When bridge initiates transaction target interface, command changed from configuration write special cycle. address data for-warded unchanged. Devices that special cycles ignore address decode only command. data phase contains special cycle message. transaction forwarded delayed transaction, this case target response forwarded back (because special cycles result master abort). Once transaction completed target bus, through detection master abort condition, bridge responds with TRDY# next attempt con-figuration transaction from initiator. more than data transfer requested, bridge responds with target disconnect operation during first data phase.
TRANSACTION TERMINATION
This section describes bridge returns transaction termination conditions back initiator. initiator terminate transactions with following types termination: Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Normal termination Normal termination occurs when initiator de-asserts FRAME# beginning last data phase, de-asserts IRDY# last data phase conjunction with either TRDY# STOP# assertion from target. Master abort master abort occurs when target response detected. When initiator does detect DEVSEL# from target within five clock cycles after asserting FRAME#, initiator terminates transaction with master abort. FRAME# still asserted, initiator de-asserts FRAME# next cycle, then de-asserts IRDY# following cycle. IRDY# must asserted same cycle which FRAME# de-asserts. FRAME# already de-asserted, IRDY# de-asserted next clock cycle following detection master abort condition.
target terminate transactions with following types termination: Normal termination TRDY# DEVSEL# asserted conjunction with FRAME# de-asserted IRDY# asserted. Target retry STOP# DEVSEL# asserted with TRDY# de-asserted during first data phase. data transfers occur during transaction. This transaction must repeated. Target disconnect with data transfer STOP#, DEVSEL# TRDY# asserted. signals that this last data transfer transaction. Target disconnect without data transfer STOP# DEVSEL# asserted with TRDY# de-asserted after previous data transfers have been made. Indicates that more data transfers will made during this transaction. Target abort STOP# asserted with DEVSEL# TRDY# de-asserted. Indicates that target will never able complete this transaction. DEVSEL# must asserted least cycle during transaction before target abort signaled.
2.8.1
MASTER TERMINATION INITIATED PI7C8148A
bridge, initiator, uses normal termination DEVSEL# returned target within five clock cycles bridge's assertion FRAME# target bus. initiator, bridge terminates transaction when following conditions met: During delayed write transaction, single DWORD delivered. During non-prefetchable read transaction, single DWORD transferred from target. During prefetchable read transaction, pre-fetch boundary reached. posted write transaction, write data transaction transferred from data buffers target. burst transfer, with exception "Memory Write Invalidate" transactions, master latency timer expires bridge's grant de-asserted. target terminates transaction with retry, disconnect, target abort.
bridge delivering posted write data when terminates transaction because master latency timer expires, initiates another transaction deliver remaining write data. address transaction updated reflect address current DWORD delivered. bridge pre-fetching read data when terminates transaction because master latency timer expires, does repeat transaction obtain more data. Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
2.8.2
MASTER ABORT RECEIVED PI7C8148A
initiator initiates transaction target does detect DEVSEL# returned target within five clock cycles assertion FRAME#, bridge terminates transaction with master abort. This sets received-master-abort status register corresponding target bus. delayed read write transactions, bridge able reflect master abort condition back initiator. When bridge detects master abort response delayed transaction, when initiator repeats transaction, bridge does respond transaction with DEVSEL#, which induces master abort condition back initiator. transaction then removed from delayed transaction queue. When master abort received response posted write transaction, bridge discards posted write data makes more attempts deliver data. bridge sets received-master-abort status register when master abort received primary bus, sets received master abort secondary status register when master abort received secondary interface. When master abort detected posted write transaction with both master-abort-mode (bit bridge control register) SERR# enable (bit command register secondary bus) set, bridge asserts P_SERR# master-abort-on-posted-write set. master-abort-on-posted-write P_SERR# event disable register (offset 64h). Note: When bridge performs Type special cycle conversion, master abort expected termination special cycle target bus. this case, master abort received set, Type configuration transaction disconnected after first data phase.
2.8.3
TARGET TERMINATION RECEIVED PI7C8148A
When bridge initiates transaction target target responds with DEVSEL#, target transaction with following types termination: Normal termination (upon de-assertion FRAME#) Target retry Target disconnect Target abort
bridge handles these terminations different ways, depending type transaction being performed. 2.8.3.1 DELAYED WRITE TARGET TERMINATION RESPONSE When bridge initiates delayed write transaction, type target termination received from target passed back initiator. Table shows response each type target termination that occurs during delayed write transaction. bridge repeats delayed write transaction until following conditions met: Bridge completes least data transfer. Bridge receives master abort. Bridge receives target abort.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION bridge makes (default) (maximum) write attempts resulting response target retry. Table 2-7. Delayed Write Target Termination Response
Target Termination Normal Target Retry Target Disconnect Target Abort Response Returning disconnect initiator with first data transfer only multiple data phases requested. Returning target retry initiator. Continue write attempts target Returning disconnect initiator with first data transfer only multiple data phases requested. Returning target abort initiator. received target abort target interface status register. signaled target abort initiator interface status register.
After bridge makes (default) attempts same delayed write trans-action target bus, bridge asserts P_SERR# SERR# enable (bit command register secondary bus) delayed-write-non-delivery set. delayed-write-non-delivery P_SERR# event disable register (offset 64h). bridge will report system error. Section description system error conditions. 2.8.3.2 POSTED WRITE TARGET TERMINATION RESPONSE When bridge initiates posted write transaction, target termination cannot passed back initiator. Table shows response each type target termination that occurs during posted write transaction. Table 2-8. Response Posted Write Target Termination
Target Termination Normal Target Retry Target Disconnect Target Abort Repsonse additional action. Repeating write transaction target. Initiate write transaction delivering remaining posted write data. received-target-abort target interface status register. Assert P_SERR# enabled, signaled-system-error primary status register.
Note that when target retry target disconnect returned posted write data associated with that transaction remains write buffers, bridge initiates another write transaction attempt deliver rest write data. there target retry, exact same address will driven initial write trans-action attempt. target disconnect received, address that driven subsequent write transaction attempt will updated reflect address current DWORD. initial write transaction Memory-Write-and-Invalidate transaction, partial delivery write data target performed before target disconnect received, bridge will memory write command deliver rest write data. because incomplete cache line will transferred subsequent write transaction attempt. After bridge makes (default) write transaction attempts fails deliver posted write data associated with that transaction, bridge asserts P_SERR# primary SERR# enable (bit command register secondary bus) posted-write-non-delivery set. postedwrite-non-delivery P_SERR# event disable register (offset 64h). bridge will report system error. Section discussion system error conditions.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
2.8.3.3 DELAYED READ TARGET TERMINATION RESPONSE When bridge initiates delayed read transaction, abnormal target responses passed back initiator. Other target responses depend much data initiator requests. Table shows response each type target termination that occurs during delayed read transaction. bridge repeats delayed read transaction until following conditions met: Bridge completes least data transfer. Bridge receives master abort. Bridge receives target abort.
bridge makes (default) read attempts resulting response target retry. Table 2-9. Response Delayed Read Target Termination
Target Termination Normal Target Retry Target Disconnect Target Abort Response prefetchable, target disconnect only initiator requests more data than read from target. non-prefetchable, target disconnect first data phase. Re-initiate read transaction target initiator requests more data than read from target, return target disconnect initiator. Return target abort initiator. received target abort target interface status register. signaled target abort initiator interface status register.
After bridge makes 224(default) attempts same delayed read transaction target bus, bridge asserts P_SERR# primary SERR# enable (bit command register secondary bus) delayed-write-non-delivery set. delayed-write-non-delivery P_SERR# event disable register (offset 64h). bridge will report system error. Section description system error conditions.
2.8.4
TARGET TERMINATION INITIATED PI7C8148A
bridge return target retry, target disconnect, target abort initiator reasons other than detection that condition target interface.
2.8.4.1 TARGET RETRY bridge returns target retry initiator when cannot accept write data return read data result internal conditions. bridge returns target retry initiator when following conditions met: delayed write transactions: transaction being entered into delayed transaction queue. Transaction already been entered into delayed transaction queue, target response been received. Target response been received progressed head return queue. delayed transaction queue full, transaction cannot queued. transaction with same address command been queued. locked sequence being propagated across bridge, write transaction locked transaction. target locked write transaction locked transaction. Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION more than clocks accept this transaction.
delayed read transactions: transaction being entered into delayed transaction queue. read request already been queued, read data available. Data been read from target, head read data queue posted write transaction precedes delayed transaction queue full, transaction cannot queued. delayed read request with same address command already been queued. locked sequence being propagated across bridge, read transaction locked transaction. bridge currently discarding previously pre-fetched read data. target locked write transaction locked transaction. more than clocks accept this transaction.
posted write transactions: posted write data buffer does have enough space address least DWORD write data. locked sequence being propagated across bridge, write transaction locked transaction. When target retry returned initiator delayed transaction, initiator must repeat transaction with same address command well data write transaction, within time frame specified master timeout value. Otherwise, transaction discarded from buffers.
2.8.4.2 TARGET DISCONNECT bridge returns target disconnect initiator when following conditions met: Bridge hits internal address boundary. Bridge cannot accept more write data. Bridge more read data deliver.
Section 2.5.4 description write address boundaries, Section 2.6.4 description read address boundaries. 2.8.4.3 TARGET ABORT bridge returns target abort initiator when following conditions met: bridge returning target abort from intended target. When bridge returns target abort initiator, sets signaled target abort status register corresponding initiator interface.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
ADDRESS DECODING
bridge uses three address ranges that control memory transaction forwarding. These address ranges defined base limit address registers configuration space. This chapter describes these address ranges, well ISA-mode VGA-addressing support.
ADDRESS RANGES
bridge uses following address ranges that determine which memory transactions forwarded from primary secondary bus, from secondary primary bus: 32-bit address ranges 32-bit memory-mapped (non-prefetchable memory) ranges 32-bit prefetchable memory address ranges
Transactions falling within these ranges forwarded downstream from primary secondary bus. Transactions falling outside these ranges forwarded upstream from secondary primary bus. address translation required bridge. addresses that marked downstream always forwarded upstream.
ADDRESS DECODING
bridge uses following mechanisms that defined configuration space specify address space downstream upstream forwarding: base limit address registers enable mode snoop
This section provides information address registers mode. Section provides information modes. enable downstream forwarding transactions, enable must command register configuration space. transactions initiated primary will ignored enable set. enable upstream forwarding transactions, master enable must command register. master-enable set, bridge ignores memory transactions initiated secondary bus. master-enable also allows upstream forwarding memory transactions set. CAUTION configuration state affecting transaction forwarding changed configuration write operation primary same time that transactions ongoing secondary bus, bridge response secondary transactions predictable. Configure base limit address registers, enable bit, mode bit, snoop before setting enable Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION master enable bits, change them subsequently only when primary secondary buses idle.
3.2.1
BASE LIMIT ADDRESS REGISTER
bridge implements base limit address registers configuration space that define address range port downstream forwarding. bridge supports 32-bit addressing, which allows addresses downstream bridge mapped anywhere address space. transactions with addresses that fall inside range defined base limit registers forwarded downstream from primary secondary bus. transactions with addresses that fall outside this range forwarded upstream from secondary primary bus. range turned setting base address value greater than that limit address. When range turned off, trans-actions forwarded upstream, transactions forwarded downstream. range minimum granularity aligned boundary. maximum range size. base register consists 8-bit field configuration address 1Ch, 16-bit field address 30h. bits 8-bit field define bits [15:12] base address. bottom bits read only indicate that bridge supports 32-bit addressing. Bits [11:0] base address assumed which naturally aligns base address boundary. bits contained base upper bits register configuration offset define AD[31:16] base address. bits read/write. After primary reset chip reset, value base address initialized 0000 0000h. limit register consists 8-bit field configuration offset 16-bit field offset 32h. bits 8-bit field define bits [15:12] limit address. bottom bits read only indicate that 32-bit addressing supported. Bits [11:0] limit address assumed FFFh, which naturally aligns limit address address block. bits contained limit upper bits register configuration offset define AD[31:16] limit address. bits read/write. After primary reset chip reset, value limit address reset 0000 0FFFh. Note: initial states base limit address registers define range 0000 0000h 0000 0FFFh, which bottom space. Write these registers with their appropriate values before setting either enable master enable command register configuration space.
3.2.2
MODE
bridge supports mode providing enable bridge control register configuration space. mode modifies response bridge inside address range order support mapping space presence system. This only affects response bridge when transaction falls inside address range defined base limit address registers, only when this address also falls inside first 64KB space (address bits [31:16] 0000h). When enable set, bridge does forward downstream transactions addressing bytes each aligned block. Only those transactions addressing bottom bytes aligned block inside base limit address range forwarded downstream. Transactions above 64KB address boundary forwarded defined address range defined base limit registers.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Accordingly, enable set, bridge forwards upstream those transactions addressing bytes each aligned block within first 64KB space. master enable command configuration register must also enable upstream forwarding. other transactions initiated secondary forwarded upstream only they fall outside address range. When enable set, devices downstream bridge have space mapped into first bytes each chunk below 64KB boundary, anywhere space above 64KB boundary.
MEMORY ADDRESS DECODING
bridge three mechanisms defining memory address ranges forwarding memory transactions: Memory-mapped base limit address registers Prefetchable memory base limit address registers mode
This section describes first mechanisms. Section 3.4.1 describes mode. enable downstream forwarding memory transactions, memory enable must command register configuration space. enable upstream forwarding memory transactions, masterenable must command register. master-enable also allows upstream forwarding transactions set. CAUTION configuration state affecting memory transaction forwarding changed configuration write operation primary same time that memory transactions ongoing secondary bus, response secondary memory transactions predictable. Configure memorymapped base limit address registers, prefetchable memory base limit address registers, mode before setting memory enable master enable bits, change them subsequently only when primary secondary buses idle.
3.3.1
MEMORY-MAPPED BASE LIMIT ADDRESS REGISTERS
Memory-mapped also referred non-prefetchable memory. Memory addresses that cannot automatically pre-fetched that conditionally pre-fetched based command type should mapped into this space. Read transactions non-prefetchable space exhibit side effects; this space have non-memory-like behavior. bridge prefetches this space only memory read line memory read multiple commands used; transactions using memory read command limited single data transfer. memory-mapped base address memory-mapped limit address registers define address range that bridge uses determine when forward memory commands. bridge forwards memory transaction from primary secondary interface transaction address falls within memory-mapped address range. bridge ignores memory transactions initiated secondary interface that fall into this address range. transactions that fall outside this address range ignored primary interface forwarded upstream from secondary interface (provided that they fall into prefetchable memory range forwarded downstream mechanism).
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION memory-mapped range supports 32-bit addressing only. PCI-to-PCI Bridge Architecture Specification does provide 64-bit addressing memory-mapped space. memorymapped address range granularity alignment 1MB. maximum memory-mapped address range 4GB. memory-mapped address range defined 16-bit memory-mapped base address register configuration offset 16-bit memory-mapped limit address register offset 22h. bits each these registers correspond bits [31:20] memory address. bits hardwired lowest bits memory-mapped base address assumed 0000h, which results natural alignment boundary. lowest bits memory-mapped limit address assumed FFFFFh, which results alignment block. Note: initial state memory-mapped base address register 0000 0000h. initial state memory-mapped limit address register 000F FFFFh. Note that initial states these registers define memory-mapped range bottom block memory. Write these registers with their appropriate values before setting either memory enable master enable command register configuration space. turn memory-mapped address range, write memory-mapped base address register with value greater than that memory-mapped limit address register.
3.3.2
PREFETCHABLE MEMORY BASE LIMIT ADDRESS REGISTERS
Locations accessed prefetchable memory address range must have true memory-like behavior must exhibit side effects when read. This means that extra reads prefetchable memory location must have side effects. bridge prefetches types memory read commands this address space. prefetchable memory base address prefetchable memory limit address registers define address range that bridge uses determine when forward memory commands. bridge forwards memory transaction from primary secondary interface transaction address falls within prefetchable memory address range. bridge ignores memory transactions initiated secondary interface that fall into this address range. bridge does respond transactions that fall outside this address range primary interface forwards those transactions upstream from secondary interface (provided that they fall into memory-mapped range forwarded mechanism). prefetchable memory range supports 64-bit addressing provides additional registers define upper bits memory address range, prefetchable memory base address upper bits register, prefetchable memory limit address upper bits register. address comparison, single address cycle (32-bit address) prefetchable memory transaction treated like 64-bit address transaction where upper bits address equal This upper 32-bit value compared prefetchable memory base address upper bits register prefetchable memory limit address upper bits register. prefetchable memory base address upper bits register must pass single address cycle transactions downstream. Prefetchable memory address range granularity alignment 1MB. Maximum memory address range when 32-bit addressing being used. Prefetchable memory address range defined 16-bit prefetchable memory base address register configuration offset 16bit prefetchable memory limit address register offset 26h. bits each these registers correspond bits [31:20] memory address. lowest bits hardwired lowest bits prefetchable memory base address assumed 0000h, which results natural Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION alignment boundary. lowest bits prefetchable memory limit address assumed FFFFFh, which results alignment block. Note: initial state prefetchable memory base address register 0000 0000h. initial state prefetchable memory limit address register 000F FFFFh. Note that initial states these registers define prefetchable memory range bottom block memory. Write these registers with their appropriate values before setting either memory enable master enable command register configuration space. turn prefetchable memory address range, write prefetchable memory base address register with value greater than that prefetchable memory limit address register. entire base value must greater than entire limit value, meaning that upper bits must considered. Therefore, disable address range, upper bits registers both same value, while lower base register greater than lower limit register. Otherwise, upper 32-bit base must greater than upper 32-bit limit.
SUPPORT
bridge provides modes support: mode, supporting VGA-compatible addressing snoop mode, supporting palette forwarding
3.4.1
MODE
When VGA-compatible device exists downstream from bridge, mode bridge control register configuration space enable mode. When bridge operating mode, forwards downstream those transactions addressing frame buffer memory registers, regardless values base limit address registers. bridge ignores transactions initiated secondary interface addressing these locations. frame buffer consists following memory address range: 000A 0000h-000B FFFFh Read transactions frame buffer memory treated non-prefetchable. bridge requests only single data transfer from target, read byte enable bits forwarded target bus. addresses range 3B0h-3BBh 3C0h-3DFh I/O. These addresses aliases every throughout first 64KB space. This means that address bits <15:10> decoded value, while address bits [31:16] must 0's. BIOS addresses starting C0000h decoded mode.
3.4.2
SNOOP MODE
bridge provides snoop mode, allowing palette write transactions forwarded downstream. This mode used when graphics device downstream from bridge needs snoop respond palette write transactions. enable mode, snoop command
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION register configuration space. Note that bridge claims palette write transactions asserting DEVSEL# snoop mode. When snoop set, bridge forwards downstream transactions within 3C6h, 3C8h 3C9h addresses space. Note that these addresses also forwarded part compatibility mode previously described. Again, address bits <15:10> decoded, while address bits <31:16> must equal which means that these addresses aliases every throughout first 64KB space. Note: both mode snoop set, bridge behaves same only mode were set.
TRANSACTION ORDERING
maintain data coherency consistency, bridge complies with ordering rules forth Local Specification, Revision 2.2, transactions crossing bridge. This chapter describes ordering rules that control transaction forwarding across bridge.
TRANSACTIONS GOVERNED ORDERING RULES
Ordering relationships established following classes transactions crossing bridge: Posted write transactions, comprised memory write memory write invalidate transactions. Posted write transactions complete source before they complete destination; that data written into intermediate data buffers before reaches target. Delayed write request transactions, comprised write configuration write transactions. Delayed write requests terminated target retry initiator queued delayed transaction queue. delayed write transaction must complete target before completes initiator bus. Delayed write completion transactions, comprised write configuration write transactions. Delayed write completion transactions complete target bus, target response queued buffers. delayed write completion transaction proceeds direction opposite that original delayed write request; that delayed write completion transaction proceeds from target initiator bus. Delayed read request transactions, comprised memory read, read, configuration read transactions. Delayed read requests terminated target retry initiator queued delayed transaction queue. Delayed read completion transactions, comprised memory read, read, configuration read transactions. Delayed read completion transactions complete target bus, read data queued read data buffers. delayed read completion transaction proceeds direction opposite that original delayed read request; that delayed read completion transaction proceeds from target initiator bus. Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
bridge does combine merge write transactions: bridge does combine separate write transactions into single write transaction-this optimization best implemented originating master. bridge does merge bytes separate masked write transactions same DWORD address-this optimization also best implemented originating master. bridge does collapse sequential write transactions same address into single write transaction-the Local Specification does permit this combining transactions.
GENERAL ORDERING GUIDELINES
Independent transactions primary secondary buses have relationship only when those transactions cross bridge. following general ordering guidelines govern transactions crossing bridge: ordering relationship transaction with respect other transactions determined when transaction completes, that when transaction ends with termination other than target retry. Requests terminated with target retry accepted completed order with respect other transactions that have been terminated with target retry. order completion delayed requests important, initiator should start second delayed transaction until first been completed. more than delayed transaction initiated, initiator should repeat delayed transaction requests, using some fairness algorithm. Repeating delayed transaction cannot contingent completion another delayed transaction. Otherwise, deadlock occur. Write transactions flowing direction have ordering requirements with respect write transactions flowing other direction. bridge accept posted write transactions both interfaces same time, well initiate posted write transactions both interfaces same time. acceptance posted memory write transaction target never contingent completion non-locked, non-posted transaction master. This true bridge must also true other agents. Otherwise, deadlock occur. bridge accepts posted write transactions, regardless state completion delayed transactions being forwarded across bridge.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
ORDERING RULES
Table shows ordering relationships transactions refers number ordering rules that follow. Table 4-1. Summary Transaction Ordering
Pass Posted Write Delayed Read Request Delayed Write Request Delayed Read Completion Delayed Write Completion Posted Write Delayed Read Request Yes5 Delayed Write Request Yes5 Delayed Read Completion Yes5 Delayed Write Completion Yes5
Note: superscript accompanying some table entries refers applicable ordering rule listed this section. Many entries governed these ordering rules; therefore, implementation choose whether transactions pass each other. entries without superscripts reflect bridge's implementation choices. following ordering rules describe transaction relationships. Each ordering rule followed explanation, ordering rules referred number Table 4-1. These ordering rules apply posted write transactions, delayed write read requests, delayed write read completion transactions crossing bridge same direction. Note that delayed completion transactions cross bridge direction opposite that corresponding delayed requests. Posted write transactions must complete target order which they were received initiator bus. subsequent posted write transaction setting flag that covers data first posted write transaction; second transaction were complete before first transaction, device checking flag could subsequently consume stale data. delayed read request traveling same direction previously queued posted write transaction must push posted write data ahead posted write transaction must complete target before delayed read request attempted target bus. read transaction same location write data, read transaction were pass write transaction, would return stale data. delayed read completion must ``pull'' ahead previously queued posted write data traveling same direction. this case, read data traveling same direction write data, initiator read transaction same side bridge target write transaction. posted write transaction must complete target before read data returned initiator. read transaction reading status register initiator posted write data therefore should complete until write transaction complete. Delayed write requests cannot pass previously queued posted write data. posted memory write transactions, delayed write transaction flag that covers data posted write transaction. delayed write request were complete before earlier posted write transaction, device checking flag could subsequently consume stale data. Posted write transactions must given opportunities pass delayed read write requests completions. Otherwise, deadlocks occur when some bridges which support delayed transactions other bridges which support delayed transactions being used same system.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION fairness algorithm used arbitrate between posted write queue delayed transaction queue.
DATA SYNCHRONIZATION
Data synchronization refers relationship between interrupt signaling data delivery. Local Specification, Revision 2.2, provides following alternative methods synchronizing data interrupts: device signaling interrupt performs read data just written (software). device driver performs read operation register interrupting device before accessing data written device (software). System hardware guarantees that write buffers flushed before interrupts forwarded.
bridge does have hardware mechanism guarantee data synchronization posted write transactions. Therefore, posted write transactions must followed read operation, either from device location just written some other location along same path), from device driver device registers.
ERROR HANDLING
bridge checks, forwards, generates parity both primary secondary interfaces. maintain transparency, bridge always tries forward existing parity condition other bus, along with address data. bridge always attempts transparent when reporting errors, this always possible, given presence posted data delayed transactions. support error reporting bus, bridge implements following: PERR# SERR# signals both primary secondary interfaces Primary status secondary status registers device-specific P_SERR# event disable register
This chapter provides detailed information about bridge handles errors. also describes error status reporting error operation disabling.
ADDRESS PARITY ERRORS
bridge checks address parity transactions both buses, address commands. When bridge detects address parity error primary interface, following events occur: parity error response command register, bridge does claim transaction with P_DEVSEL#; this allow transaction terminate master abort. parity error response set, bridge proceeds normally accepts transaction directed across bridge. bridge sets detected parity error status register. bridge asserts P_SERR# sets signaled system error status register, both following conditions met: SERR# enable command register. Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION parity error response command register.
When bridge detects address parity error secondary interface, following events occur: parity error response bridge control register, bridge does claim transaction with S_DEVSEL#; this allow transaction terminate master abort. parity error response set, bridge proceeds normally accepts transaction directed across bridge. bridge sets detected parity error secondary status register. bridge asserts P_SERR# sets signaled system error status register, both following conditions met: SERR# enable command register. parity error response bridge control register.
DATA PARITY ERRORS
When forwarding transactions, bridge attempts pass data parity condition from interface other unchanged, whenever possible, allow master target devices handle error condition. following sections describe, each type transaction, sequence events that occurs when parity error detected which parity condition forwarded across bridge.
5.2.1
CONFIGURATION WRITE TRANSACTIONS CONFIGURATION SPACE
When bridge detects data parity error during Type configuration write transaction bridge configuration space, following events occur: parity error response command register, bridge asserts P_TRDY# writes data configuration register. bridge also asserts P_PERR#. parity error response set, bridge does assert P_PERR#. bridge sets detected parity error status register, regardless state parity error response bit.
5.2.2
READ TRANSACTIONS
When bridge detects parity error during read transaction, target drives data data parity, initiator checks parity conditionally asserts PERR#. downstream transactions, when bridge detects read data parity error secondary bus, following events occur: Bridge asserts S_PERR# cycles following data transfer, secondary interface parity error response bridge control register. Bridge sets detected parity error secondary status register. Bridge sets data parity detected secondary status register, secondary interface parity error response bridge control register.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Bridge forwards parity with data back initiator primary bus. data with parity pre-fetched read initiator primary bus, data discarded data with parity returned initiator. Bridge completes transaction normally.
upstream transactions, when bridge detects read data parity error primary bus, following events occur: Bridge asserts P_PERR# cycles following data transfer, primary interface parity error response command register. Bridge sets detected parity error primary status register. Bridge sets data parity detected primary status register, primary interface parityerror-response command register. Bridge forwards parity with data back initiator secondary bus. data with parity pre-fetched read initiator secondary bus, data discarded data with parity returned initiator. Bridge completes transaction normally.
bridge returns initiator data parity that received from target. When initiator detects parity error this read data enabled report initiator asserts PERR# cycles after data transfer occurs. assumed that initiator takes responsibility handling parity error condition; therefore, when bridge detects PERR# asserted while returning read data initiator, bridge does take further action completes transaction normally.
5.2.3
DELAYED WRITE TRANSACTIONS
When bridge detects data parity error during delayed write transaction, initiator drives data data parity, target checks parity conditionally asserts PERR#. delayed write transactions, parity error occur following times: During original delayed write request transaction When initiator repeats delayed write request transaction When bridge completes delayed write transaction target
When delayed write transaction normally queued, address, command, address parity, data, byte enable bits, data parity captured target retry returned initiator. When bridge detects parity error write data initial delayed write request transaction, following events occur: parity-error-response corresponding initiator set, bridge asserts TRDY# initiator transaction queued. multiple data phases requested, STOP# also asserted cause target disconnect. cycles after data transfer, bridge also asserts PERR#. parity-error-response set, bridge returns target retry. queues transaction usual. bridge does assert PERR#. this case, initiator repeats transaction. bridge sets detected-parity-error status register corresponding initiator bus, regardless state parity-error-response bit.
Note: parity checking turned data parity errors have occurred queued subsequent delayed write transactions initiator bus, possible that initiator's re-attempts write transaction match original queued delayed write information contained delayed Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION transaction queue. this case, master timeout condition occur, possibly resulting system error (P_SERR# assertion). downstream transactions, when bridge delivering data target secondary S_PERR# asserted target, following events occur: bridge sets secondary interface data parity detected secondary status register, secondary parity error response bridge control register. bridge captures parity error condition forward back initiator primary bus.
Similarly, upstream transactions, when bridge delivering data target primary P_PERR# asserted target, following events occur: bridge sets primary interface data-parity-detected status register, primary parity-error-response command register. bridge captures parity error condition forward back initiator secondary bus.
delayed write transaction completed initiator when initiator repeats write transaction with same address, command, data, byte enable bits delayed write command that head posted data queue. Note that parity compared when determining whether transaction matches those delayed transaction queues. cases must considered: When parity error detected initiator subsequent re-attempt transaction detected target When parity error forwarded back from target
downstream delayed write transactions, when parity error detected initiator bridge write status return, following events occur: Bridge first asserts P_TRDY# then asserts P_PERR# cycles later, primary interface parity-error-response command register. Bridge sets primary interface parity-error-detected status register. Because there exact data parity match, write status returned transaction remains queue.
Similarly, upstream delayed write transactions, when parity error detected initiator bridge write status return, following events occur: Bridge first asserts S_TRDY# then asserts S_PERR# cycles later, secondary interface parity-error-response bridge control register (offset 3Ch). Bridge sets secondary interface parity-error-detected secondary status register. Because there exact data parity match, write status returned transaction remains queue.
downstream transactions, where parity error being passed back from target parity error condition originally detected initiator bus, following events occur: Bridge asserts P_PERR# cycles after data transfer, following both true: parity-error-response command register primary interface. parity-error-response bridge control register secondary interface. Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Bridge completes transaction normally.
upstream transactions, when parity error being passed back from target parity error condition originally detected initiator bus, following events occur: Bridge asserts S_PERR# cycles after data transfer, following both true: parity error response command register primary interface. parity error response bridge control register secondary interface. Bridge completes transaction normally.
5.2.4
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when bridge responds target, detects data parity error initiator (primary) following events occur: Bridge asserts P_PERR# cycles after data transfer, parity error response command register primary interface. Bridge sets parity error detected status register primary interface. Bridge captures forwards parity condition secondary bus. Bridge completes transaction normally.
Similarly, during upstream posted write transactions, when bridge responds target, detects data parity error initiator (secondary) bus, following events occur: Bridge asserts S_PERR# cycles after data transfer, parity error response bridge control register secondary interface. Bridge sets parity error detected status register secondary interface. Bridge captures forwards parity condition primary bus. Bridge completes transaction normally.
During downstream write transactions, when data parity error reported target (secondary) target's assertion S_PERR#, following events occur: Bridge sets data parity detected status register secondary interface, parity error response bridge control register secondary interface. Bridge asserts P_SERR# sets signaled system error status register, following conditions met: SERR# enable command register. posted write parity error P_SERR# event disable register set. parity error response bridge control register secondary interface. parity error response command register primary interface. Bridge detected parity error primary (initiator) which parity error forwarded from primary secondary bus.
During upstream write transactions, when data parity error reported target (primary) target's assertion P_PERR#, following events occur: Bridge sets data parity detected status register, parity error response command register primary interface. Bridge asserts P_SERR# sets signaled system error status register, following conditions met: Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
SERR# enable command register. parity error response bridge control register secondary interface. parity error response command register primary interface. Bridge detected parity error secondary (initiator) bus, which parity error forwarded from secondary primary bus.
Assertion P_SERR# used signal parity error condition when initiator does know that error occurred. Because data already been delivered with errors, there other signal this information back initiator. parity error forwarded from initiating target bus, P_SERR# will asserted.
DATA PARITY ERROR REPORTING SUMMARY
previous sections, responses bridge data parity errors presented according type transaction progress. This section organizes responses bridge data parity errors according status bits that bridge sets signals that asserts. Table shows setting detected parity error status register, corresponding primary interface. This when bridge detects parity error primary interface. Table 5-1. Setting Primary Interface Detected Parity Error
Primary Detected Parity Error don't care Transaction Type Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write Direction Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Where Error Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary/ Secondary Parity Error Response Bits
Table shows setting detected parity error secondary status register, corresponding secondary interface. This when bridge detects parity error secondary interface. Table 5-2. Setting Secondary Interface Detected Parity Error
Secondary Detected Parity Error Transaction Type Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Direction Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Where Error Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Primary/ Secondary Parity Error Response Bits
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Secondary Detected Parity Error don't care Transaction Type Delayed Write Direction Upstream Where Error Detected Secondary Primary/ Secondary Parity Error Response Bits
Table shows setting data parity detected primary interface's status register. This under following conditions: Bridge must master primary bus. parity error response command register, corresponding primary interface, must set. P_PERR# signal detected asserted parity error detected primary bus.
Table 5-3. Setting Primary Interface Master Data Parity Error Detected
Primary Data Parity don't care Transaction Type Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write Direction Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Where Error Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Parity Error Response Bits
Table shows setting data parity detected status register secondary interface. This under following conditions: bridge must master secondary bus. parity error response must bridge control register secondary interface. S_PERR# signal detected asserted parity error detected secondary bus.
Table 5-4. Setting Secondary Interface Master Data Parity Error Detected
Secondary Detected Parity Detected don't care Transaction Type Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write Direction Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Where Error Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Parity Error Response Bits
Table shows assertion P_PERR#. This signal under following conditions:
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION bridge either target write transaction initiator read transaction primary bus. parity-error-response must command register primary interface. bridge detects data parity error primary detects S_PERR# asserted during completion phase downstream delayed write transaction target (secondary) bus.
Table 5-5. Assertion P_PERR#
P_PERR# Transaction Type Direction Where Error Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary/ Secondary Parity Error Response Bits
(de-asserted) Read Downstream Read Downstream (asserted) Read Upstream Read Upstream Posted Write Downstream Posted Write Downstream Posted Write Upstream Posted Write Upstream Delayed Write Downstream Delayed Write Downstream Delayed Write Upstream Delayed Write Upstream don't care parity error detected target (secondary) initiator (primary) bus.
Table shows assertion S_PERR# that under following conditions: bridge either target write transaction initiator read transaction secondary bus. parity error response must bridge control register secondary interface. Bridge detects data parity error secondary detects P_PERR# asserted during completion phase upstream delayed write transaction target (primary) bus.
Table 5-6. Assertion S_PERR#
S_PERR# Transaction Type Direction Where Error Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary/ Secondary Parity Error Response Bits
(de-asserted) Read Downstream (asserted) Read Downstream Read Upstream Read Upstream Posted Write Downstream Posted Write Downstream Posted Write Upstream Posted Write Upstream Delayed Write Downstream Delayed Write Downstream Delayed Write Upstream Delayed Write Upstream don't care parity error detected target (secondary) initiator (primary) bus.
Table shows assertion P_SERR#. This signal under following conditions: bridge detected P_PERR# asserted upstream posted write transaction S_PERR# asserted downstream posted write transaction. bridge detect parity error target posted write transaction. parity error response command register parity error response bridge control register must both set. Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION SERR# enable must command register.
Table 5-7. Assertion P_SERR# Data Parity Errors
P_SERR# Transaction Type Direction Where Error Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Parity Error Response Bits
(de-asserted) Read Downstream Read Downstream Read Upstream Read Upstream Posted Write Downstream (asserted) Posted Write Downstream Posted Write Upstream Posted Write Upstream Delayed Write Downstream Delayed Write Downstream Delayed Write Upstream Delayed Write Upstream don't care parity error detected target (secondary) initiator (primary) bus. parity error detected target (primary) initiator (secondary) bus.
SYSTEM ERROR (SERR#) REPORTING
bridge uses P_SERR# signal report conditionally number system error conditions addition special case parity error conditions described Section 5.2.3. Whenever assertion P_SERR# discussed this document, assumed that following conditions apply: bridge assert P_SERR# reason, SERR# enable must command register. Whenever bridge asserts P_SERR#, bridge must also signaled system error status register.
compliance with PCI-to-PCI Bridge Architecture Specification, bridge asserts P_SERR# when detects secondary SERR# input, S_SERR#, asserted SERR# forward enable bridge control register. addition, bridge also sets received system error secondary status register. bridge also conditionally asserts P_SERR# following reasons: Target abort detected during posted write transaction Master abort detected during posted write transaction Posted write data discarded after (default) attempts deliver (224 target retries received) Parity error reported target during posted write transaction (see previous section) Delayed write data discarded after (default) attempts deliver (224 target retries received) Delayed read data cannot transferred from target after (default) attempts (224 target retries received) Master timeout delayed transaction
device-specific P_SERR# status register reports reason assertion P_SERR#. Most these events have additional device-specific disable bits P_SERR# event disable register that make possible mask P_SERR# assertion specific events. master timeout condition
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION SERR# enable that event bridge control register therefore does have devicespecific disable bit.
ARBITRATION
bridge must arbitrate primary when forwarding upstream transactions. Also, must arbitrate secondary when forwarding downstream transactions. arbiter primary resides external bridge, typically motherboard. secondary bus, bridge implements internal arbiter. This arbiter disabled, external arbiter used instead. This chapter describes primary secondary arbitration.
PRIMARY ARBITRATION
bridge implements request output pin, P_REQ#, grant input pin, P_GNT#, primary arbitration. bridge asserts P_REQ# when forwarding transactions upstream; that acts initiator primary bus. long least pending transaction resides queues upstream direction, either posted write data delayed transaction requests, bridge keeps P_REQ# asserted. However, target retry, target disconnect, target abort received response transaction initiated bridge primary bus, bridge de-asserts P_REQ# clock cycles. cycles through bridge, P_REQ# asserted until transaction request been completely queued. When P_GNT# asserted primary arbiter after bridge asserted P_REQ#, bridge initiates transaction primary during next clock cycle. When P_GNT# asserted bridge when P_REQ# asserted, bridge parks P_AD, P_CBE, P_PAR driving them valid logic levels. When primary parked bridge bridge transaction initiate primary bus, bridge starts transaction P_GNT# asserted during previous cycle.
SECONDARY ARBITRATION
bridge implements internal secondary arbiter. This arbiter supports four external masters secondary addition PI7C8148A. secondary arbiter supports programmable 2-level rotating algorithm. bridge detects that initiator failed assert S_FRAME# after cycles both grant assertion secondary idle condition, arbiter deasserts grant. prevent contention, secondary idle, arbiter never asserts grant signal same cycle which de-asserts another. de-asserts grant asserts next grant, earlier than clock cycle later. secondary busy, that S_FRAME# S_IRDY# asserted, arbiter de-asserted grant asserted another grant during same clock cycle.
6.2.1
PREEMPTION
Preemption programmed either off, with default (offset 4Ch, [31:28]). Time-to-preempt programmed (default clocks. current Page JUNE 2004 Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION master occupies other masters waiting, current master will preempted removing grant (GNT#) after next master waits time-to-preempt.
6.2.2
PARKING
parking refers driving AD[31:0], CBE[3:0], lines known value while idle. general, device implementing arbiter responsible parking assigning another device park bus. device parks when idle, grant asserted, device's request asserted. signals should driven first, with signal driven cycle later. bridge parks primary only when P_GNT# asserted,
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