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SM3 ULTRA MINIATURE STRATUM 3 MODULE

· Small Package Size, 1.45 x

SM3 ULTRA MINIATURE STRATUM 3 MODULE
2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com
Application
Features
· Small Package Size, 1.45 x
1.0 x 0.25 inches
· Four Auto Select Input
References, 8 kHz - 77.76 MHz
· Frequency Qualification and
Loss of Reference detection for each input
· Hitless Reference Switching · Master / Slave Operation with
Phase Adjustment
· Manual / Autonomous
Operation
· Bi-Directional SPI Port
Control
· Three CMOS Frequency
Bulletin Page Revision Date Issued By
TM052 1 of 34 01 14 JAN 05 MBatts
Outputs - Output1 from 12.96 - 77.76 MHz, M / S Output @ 8kHz, BITS @2.048 MHz or 1.544 MHz
· 3.3V operation
General Description
Functional Block Diagram
Figure 1
Data Sheet #: TM052
Page 2 of 34
Rev: 01
Specifications for Ultra Miniature Stratum 3
Table 1 Parameter
Specification
Pin Description
Table 2
JTAG pins do not require pull up or pull down resistors
Data Sheet #: TM052
Page 3 of 34 Rev: 01
Pin Diagram
Figure 2
(TOP VIEW)
Register Map
Table 3 Address
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c
Reg Name
Description
Data Sheet #: TM052
Page 4 of 34
Rev: 01
Register Map Continued
Data Sheet #: TM052
Page 5 of 34 Rev: 01
Detailed Description
The SM3 can accept up to 4 external references from 8 kHz to 77.76 MHz and each is monitored for signal presence and frequency offset. Additionally, a cross-couple reference input is provided for master / slave operation. Reference selection may be manual or automatic, according to pre-programmed priorities. All reference switches are performed in a hitless manner, and frequency ramp controls ensure smooth output signal transitions. When references are switched, the device provides an automatic phase build-out to minimize phase transitions in the output clocks. Three output signals are provided, the first up to 77.76 MHz , the second fixed at 8 kHz for use as a Frame Sync signal as well as a cross-couple reference for master / slave operation. The third output is a BITS clock, selectable as either 1.544 MHz or 2.048 MHz. Device operation may be in Free Run, locked, or Hold Over modes. In Free Run, the clock frequencies are simply determined by the accuracy of the calibrated internal clock. In locked mode, the SM3 phase locks to the selected input reference. While locked, a frequency history is accumulated. In Hold Over mode, the output frequencies are generated according to this history. The Digital Phase Locked Loop provides the critical filtering and frequency / phase control that meet or exceed all requirements in critical jitter and accuracy performance parameters. Filter bandwidth may be configured to suit applications requirements. Control functions are provided via standard SPI bus register interface. Register access provides visibility into a variety of registered information as well as providing extensive programmable control capability.
Operating Modes: The SM3 Operates in Either Free Run, Locked, or Hold Over Mode:
Data Sheet #: TM052
Page 6 of 34
Rev: 01
Detailed Description continued
Furthermore, under register access control, a backup holdover history register is provided. It may be loaded from the active holdover history or restored to the active holdover history. The active holdover history may also be flushed. Holdover mode may be entered at any time. If there is no holdover history available, the prior output frequency will be maintained. When in holdover, the application may read (via register access) the time since holdover was enterred.
Master / Slave Operation
Pairs of SM3 devices may be operated in a master / slave configuration for redundant timing source applications. A typical configuration is shown below.:
Master / Slave Configuration Figure 3
REFS1-4 M / S REF
M / S OUTPUT / OUTPUT1 / BITS
REFS1-4
M / S OUTPUT / OUTPUT1 / BITS
Data Sheet #: TM052
Page 7 of 34 Rev: 01
Detailed Description continued
Serial Communication
The user can control the operation of the SM3 module through the SPI port. Timing diagrams are shown below. This interface is only for point-to-point applications.
Serial Interface Timing, Read Access
Figure 4
tRWs tRWh A0
tCH A2 A3
tDRDY D0
Serial Interface Timing, Write Access
Figure 5
tCH A2 A3 tCL A4 A5 A6 1
tRWh A0
Data Sheet #: TM052
Page 8 of 34
Rev: 01
Detailed Description continued
Serial Interface Timing
Table 4 Symbol
tCS tCH tCL tRWs tRWh tDRDY tHLD tCSTRI tCSMIN
Parameter
Minimum
Nominal
Maximum
Units
Notes
Minimum delay between successive accesses 300
Note: The SPI port should not be accessed until 1200ms after reset has transitioned from low to a high state.
Reference Input Quality Monitoring
Reference Input Selection, Frequencies, and Mode Selection
Data Sheet #: TM052
Page 9 of 34 Rev: 01
Detailed Description continued
The automatic reference selection is shown in the following state diagram:
Automatic Reference Selection
Figure 6
Ref n returns, Ref m marked "revertive"
Ref n returns, Ref m marked "non-revertive"
Locked on Ref n
Loss of Ref n
Select & Lock on Ref m
The operational mode is according to the following state diagram:
No available reference and no Hold Over history Ref loss w / no good Hold Over history and no other available reference
Automatic Operational Mode Selection
Figure 7
Reference Available (Select highest priority) Higher priority Ref return with prior reference marked "revertive" Locked Ref loss w / no good hold over history and no other available reference Ref Return Free Run Ref Return Hold Over Ref Loss w / good hold over history and no alternate reference available Ref Loss w / alternate reference available
No available reference and no hold over history
Data Sheet #: TM052
Page 10 of 34
Rev: 01
Detailed Description continued
Output Signals and Frequency
Interrupts
Interrupts and Reference Change in Autonomous Mode
Data Sheet #: TM052
Page 11 of 34 Rev: 01
Register Descriptions and Operation
Low byte of chip ID: 0x12
High byte of chip ID: 0x30
Chip revision number: Chip revision number is subject to change.
Reserved
Reserved 0:Default
Bandwidth Selection in Hz: 0000: 0.025 0001: 0.025 0010: 0.025 0011: 0.025 0100: 0.025 0101: 0.025 0110: 0.049 0111: 0.098(Reset Default) 1000: 0.20 1001: 0.39 1010: 0.78 1011 - 1111: 1.6
BITS 3 - 0 select the phase lock loop bandwidth in Hertz. The reset default is 0.098 Hz.
Reserved
Default: 0
Data Sheet #: TM052
Page 12 of 34
Rev: 01
Register Descriptions and Operation continued
Reserved
Master or Slave Mode 1: Master 0: Slave (Read Only)
Free Run, Locked, or Hold Over: 0000: Free Run mode 0001: Locked on Ref1 0010: Locked on Ref2 0011: Locked on Ref3 0100: Locked on Ref4 0101 - 1000: Not Used 1001 - 1111: Hold Over
Reserved
Cross reference activity 0000: No signal 0001: 8kHz 0010:1.544 MHz 0011:2.048MHz 0100: 12.96MHz 0101: 19.44MHz 0110: 25.92MHz 0111: 38.88MHz 1000: 51.84MHz 1001: 77.76MHz 1010-1111: Reserved
Indicates signal presence and auto-detected frequency for the M / S REF input.
0: off
ref4 activity 1: on 0: off
ref3 activity 1: on 0: off
ref2 activity 1: on 0: off
ref1 activity 1: on 0: off
Each bit indicates the presence of a signal for that reference.
Data Sheet #: TM052
Page 13 of 34 Rev: 01
Register Descriptions and Operation continued
0: Default
ref2 sts 1: in range 0: out range register.
ref1 sts 1: in range 0: out range
0: Default
ref2 avail: 1: avail. 0: not avail.
ref1 avail: 1: avail. 0: not
Data Sheet #: TM052
Page 14 of 34
Rev: 01
Register Descriptions and Operation continued
Calibration, 0x0f (R / W)
Bit 7 ~ Bit4
Reserved
Bit 7 ~Bit 5
Reserved
Hold Over Build Complete 1: Complete 0: Incomplete
Hold Over Available 1: Avail. 0: Not avail.
Locked 1: Locked 0: Not locked
Loss of Lock 1: Loss of Lock 0: No loss of lock
Loss of Signal 1: No activity on active reference 0: Active reference signal present
NOTE: Only references 1 - 4 are used with this model
Data Sheet #: TM052
Page 15 of 34 Rev: 01
Register Descriptions and Operation continued
Loss of Lock
Loss of Signal
Active reference change
DPLL Mode status change
M / S Ref Change from no activity to activity
M / S Ref Change from activity to no activity
Enable Interrupt event 7: 1: Enable 0: Disable Default: 0
Enable Interrupt event 6: 1: Enable 0: Disable Default: 0
Enable Interrupt event 5: 1: Enable 0: Disable Default: 0
Enable Interrupt event 4: 1: Enable 0: Disable Default: 0
Enable Interrupt event 3: 1: Enable 0: Disable Default: 0
Enable Interrupt event 2: 1: Enable 0: Disable Default: 0
Enable Interrupt event 1: 1: Enable 0: Disable Default: 0
Enable Interrupt event 0: 1: Enable 0: Disable Default: 0
Data Sheet #: TM052
Page 16 of 34
Rev: 01
Register Descriptions and Operation continued
Enable / Revertivity Priority Disable 1: Enable 0: Highest Reserved 1: Enable 0: Disable 3: Lowest 0: Disable Default: 0 Default: 0 Default: 0 non-revertive Free Run may be treated like a reference. When it is enabled, Free Run will be entered when all references of higher priority are lost or masked. If or when a higher priority reference retur ns, it is switched to if Free Run is set as "revertive". When disabled, Free Run will be entered only if manually selected or all references fail without an available Hold Over history. For equal priority value, Free Run will be treated as lower priority.
Reference Switch Hold Over Hisory Policy Reserved 0: Rebuild 1: Continue Bit 0 determines if Hold Over is retained or rebuilt when a reference switch occurs. See Application Notes, Holdover History Accumulation and Management section.
Bit 1-0
Hold Over Histroy Commands 01: Save active history to backup history Reserved 10: Restore active histor y from backup 11: Flush the active history and accumulation register 00: No command Bits 0-1 are written to save a holdover history to the backup history, restore the active holdover history from the backup, or flush the active history. The default value of the register is 00. The last command is latched and may be read by the application. A flush does not affect the backup history. See Application Notes, Holdover History Accumulation and Management section.
Indicates the time since entering the Hold Over state. from 0-255, one bit per hour. Zero in non-Hold Over state and stops at 255.
Cfgdata, 0x30 (R / W)
Configuration data write register. Configuration data is written to this register. Internal use only.
Configuration data write counter low byte. Low order byte of configuration data write counter. Internal use only.
Data Sheet #: TM052
Page 17 of 34 Rev: 01
Register Descriptions and Operation continued
Configuration data write counter high byte. High order byte of configuration data write counter. Internal use only.
Chksum, 0x33 (R / W)
Configuration Data Checksum pass / fail indicator 0: Fail 1: Pass
Reserved Checksum verification register for configuration data. Internal use only.
Reserved EEPROM write enable register.
EEPROM Write Enable 0: Disable 1: Enable
Reserved
EEPROM read / write page number, 0x00 to 0x9f (0 - 159) EEPROM read / write page number register. EEPROM consist of 160 pages.
EEPROM read / write FIFO data. EEPROM read / write FIFO port register. EEPROM data is written to / read from this location.
Data Sheet #: TM052
Page 18 of 34
Rev: 01
Performance Specifications
Performance Definitions
SM3 Performance
Input Jitter Tolerance - Input jitter tolerance is the amount of jitter at its input a clock can tolerate before generating an indication of improper operation. GR-1244 and ITU-813 requirements specify jitter amplitude v.s. jitter frequency for jitter tolerance. The SM3 device provides jitter tolerance that meets the specified requirements. Input Wander Tolerance - Input wander tolerance is the amount of wander at its input a clock can tolerate before generating an indication of improper operation. GR-1244 and ITU-813 requirements specify input wander TDEV vs. Integration Time as shown below.
Integration Time, (seconds)
TDEV (ns)
The SM3 device provides wander tolerance that meets these requirements. Phase Transient Tolerance - GR-1244 specifies maximum reference input phase transients that a clock system must tolerate without generating an indication of improper operation. The phase transient tolerance is specified in MTIE(nS) v.s. observation time from .001 to 100 seconds, as shown below.
Observation time S (Seconds)
MTIE (ns)
61, 000 x S 925 + 4600 x S 10, 000
The SM3 will tolerate all reference input transients within the GR-1244 specification. Free Run Frequency Accuracy - Free Run frequency accuracy is the maximum fractional frequency offset while in Free Run mode. It is determined by the accuracy of the internal clock. Hold Over Frequency Stability - Hold Over frequency stability is the maximum fractional frequency offset while in Hold Over mode. It is determined by the stability of the internal clock.
Data Sheet #: TM052
Page 19 of 34 Rev: 01
Performance Specifications continued
Wander Generation Characteristics - MTIE
GR-1244-CORE, R5-5
MTIE (ns)
Observation Time (sec)
Wander Generation Characteristics - TDEV
GR-1244-CORE, R5-4
TDEV (ns)
Integration Time (sec)
Data Sheet #: TM052
Page 20 of 34
Rev: 01
Performance Specifications continued
Wander Transfer - Wander transfer is the degree to which input wander is attenuated (or amplified) from input to output of a clock. The GR-1244 requirements for wander transfer limits are shown below.
Integration time, (seconds)
Stratum 3 TDEV (nanoseconds)
0.5 32.2 x 0.5
The SM3, when configured for the appropriate stratum 3 bandwidth frequency, meets the stratum 3 requirements, Jitter Generation - Jitter generation is the process whereby jitter appears at the output of a clock in the absence of input jitter. The device jitter generation performance is as shown below:
Jitter
Broadband (10 Hz - 2 MHz) SONET Band
19.44 MHz
8 ps Typical (rms) (12 kHz -2MHz) 5 ps Typical (rms)
77.76 MHz
8 ps Typical (rms) (12 kHz -20MHz) 1.5 ps Typical (rms)
Jitter Transfer - Jitter transfer is the degree to which input jitter is attenuated (or amplified) from input to output of a clock. It is a function of the selected bandwidth. Phase Transients - A phase transient is an unusual step or change in the phase-time of a signal over a relatively short time period. This may be due to switching between equipment, reference switching, diagnostics, entry or exit to / from Hold Over, or input reference transients. The SM3 performance for reference switches is shown below:
Phase Transients - MTIE
GR-1244-CORE, R5-14
MTIE (ns)
Observation Time (sec)
Data Sheet #: TM052
Page 21 of 34 Rev: 01
Performance Specifications continued
Capture range and Hold range - Capture range and Hold range are the maximum frequency errors on the reference input within which the phase locked loop is able to achieve lock and hold lock, respectively. The SM3 stratum 3 performance is shown below:
Characteristic
Capture range Hold range
Requirement
GR-1244-CORE, Sec 3.4 GR-1244-CORE, Sec 3.4
Characteristic
Master / Slave phase skew Reference switch settling time
Requirement
SM3 Initialization:
I. The unit starts up in Free Run and operates in Manual mode. Here are the steps that need to be taken to lock the unit to a reference in Manual mode. 1. 2. 3. 4. 5. 6. Apply signal to the reference inputs. Set the appropriate pull in range by writing to address 0x06. Set Bandwidth to 0.0016Hz and enable phase build out by writing 00010001 to address 0x03. A value of 0001xxxx, depending on which (Ref 1-8) reference to lock to, should be written to address 0x05. Enable Reference mask for appropriate references by writing a 1 to the reference bit in address 0x0b. Enable all Interrupts by writing 11111111 to address 0x13.
Data Sheet #: TM052
Page 22 of 34
Rev: 01
IV RESET Parameters: 1. 2. The reset pin should be held low for a minimum of 10 milliseconds to ensure a complete reset occurs. The SPI interface should not be accessed for a minimum of 1 second after the reset pin is de-asserted.
Switching Master / Slave designations:
Data Sheet #: TM052
Page 23 of 34 Rev: 01
Data Sheet #: TM052
Page 24 of 34
Rev: 01
Application Notes
Master / Slave Configuration
Figure 8
SM3 #1
REF4 STC3500
Master / Slave output Synchronized clock output BITS clock output
SM3 #2
Data Sheet #: TM052
Page 25 of 34 Rev: 01
Application Notes continued
Hold Over History Accumulation Register
Active Hold Over History
Backup Hold Over History
Once lock has been achieved, holdover history is compiled in the accumulation register. It is transferred to the Active holdover history when it is ready (typically in about 15 minutes). The "Holdover Available" bit and output pin are set to "1". From then on, the Active holdover history is continually updated and kept in sync with the holdover history accumulation register. (See Figure 11).
Data Sheet #: TM052
Page 26 of 34
Rev: 01
Application Notes continued Hold Over History access and Control Registers
Table 5 Register
0x25 0x26 0x27 0x11
Register Name
Description
Sets policy for Hold Over history accumulation: "Rebuild" or "Continue" Save, restore, and flush commands for Hold Over history Indicates the time since entering the Hold Over state Bits 3 and 4: Hold Over Available" and "Hold Over Build Complete"
Hold Over History and Status States
Figure 9
Flush
History Build Complete
Reference Switch History Build Complete, Replace Active Hold Over History
Reference Switch
History Restored from backup, re-start the building procedure.
Data Sheet #: TM052
Page 27 of 34 Rev: 01
Application Notes continued
Control Modes
Data Sheet #: TM052
Page 28 of 34
Rev: 01
Application Notes continued Mechanical Dimensions
Figure10
1.450 36.83mm MAX.
0.075 1.91mm
1.000 25.40mm MAX.
0.850 21.59mm
0.250 6.35mm MAX.
0.070 1.78mm
0.125 3.18mm
0.018 0.45mm
0.100 2.54mm
Footprint Dimensions
Figure 11
TOP VIEW
HOLE / PAD SIZE (28 PLACES):
CUSTOMER COMPONENT KEEP OUT AREA
1. UNSOCKETED MODULE: 0.028" DIA. PLATED HOLE WITH 0.060" DIA. PAD. 2. SOCKETED MODULE: 0.038" DIA. PLATED HOLE WITH 0.070" DIA. PAD. NOTE: For compatibllity with both the unsocketed and socketed modules, Connor-Winfield recommends using a 0.038" DIA. plated hole with 0.070" DIA. pad
Data Sheet #: TM052
Page 29 of 34 Rev: 01
Application Notes continued Required External Components
PCB Layout Recommendations
1. 2. 3. 4. 5. 6. Orient module so airflow is parallel along the header strips (pins). Place de-coupling and / or filter components as close to module pins as possible. Do not place any components directly beneath the module on the topside of the host PCB. Ensure that only clean and well-regulated power is supplied to the module. Isolate power and ground inputs to the module from noisy sources. Provide power and ground connections through a 0.050" wide trace (minimum) using 1-oz. Cu or equivalent copper feature (i.e. internal plane, copper area fill, etc.). 7. Keep module signals away from sensitive or noisy analog and digital circuitry. 8. Avoid split ground planes as high-frequency return currents may be affected. 9. Allow extra spacing between traces of high-frequency inputs and outputs. 10.Keep all traces as shor t as possible - avoid meandering trace paths. 11.Avoid routing signals directly beneath the module on the topside of the host PCB. 12.If possible, provide a copper area directly beneath the module on the topside of the host PCB. Connect this copper area to ground. 13.It is recommended that the connections of the JTAG, VPP and VPN pins be routed to pads as shown in Figure 14. No external pull-up or pull-down resistors are to be used on the JTAG pins.
Optional Socket Mounting Recommendations
Mating sockets may be used if permanent installation of the SM3 module is not desired. Two possible sources for these sockets include: 1. Samtec, "Low Profile Socket Strips", SL Series, PN SL-114-G-19. (http://www.samtec.com / ) 2. Mill-Max, "Single-In-Line Sockets", 315 Series, PN 315-xx-114-41-001. (http://www.mill-max.com / ) The SM3 requires two 14-pin sockets. The optional dual footprint configuration shown in Figure 13 requires one 14-pin and two 16pin sockets.
Data Sheet #: TM052
Page 30 of 34
Rev: 01
Application Notes continued Optional SM3 / SM3E Dual Footprint
A dual footprint configuration may be used when designing a host circuit board containing the Connor Winfield SM3 or SM3E modules. The smaller SM3 contains a subset of the signal pins found on the larger SM3E in locations which allow for a simple dual footprint arrangement like the one shown in Figure 13.
(TOP VIEW)
Figure 12
Data Sheet #: TM052
Page 31 of 34 Rev: 01
SM3 Reference Design
Figure 13
C1 10uF C2 0.01uF
Data Sheet #: TM052
Page 32 of 34
Rev: 01
Optional Programing Header Reference Design
Figure 14
J2 1 3 5 7 9 11 13 15 17 19 21 23 25 NC NC NC GND GND GND NC NC GND GND NC NC NC VDDP VDDP VPP VPN GND TCK TDI TDO TMS RCK TRST VDD VDD 2 4 6 8 10 12 14 16 18 20 22 24 26 + GND
4.7uF C5 + VPP VPN GND TCK TDO TDI TMS TRST
4.7uF C6
FTSH-113-01-L-D-K
SAMTEC
The programming header is optional. It provides a means for re-programming the chip on board if necessary. The SAMTEC header has a notch and should be laid out in such a way that the notch is on the pin1 side. The header specified here is a thru-hole part and surface mount versions are available. Please refer to www.samtec.com for more information on the header.
Ordering Information
SM3-XXX.XXM Replace XXX.XX with one of the following available frequencies, 012.96MHz, 019.44MHz, 025.92MHz, 038.88MHz, 051.84MHz or 077.76MHz. Please contact Connor-Winfield for other frequencies that may be available. Similar Products from Connor-Winfield SM3-8R-XXX.XXM - Stratum 3 module with 8 input references. SM3-IT-XXX.XXM - Industrial temperature rated Stratum 3 module with 4 input references. SM3E-XXX.XXM - Stratum 3E module with 8 input references.
Data Sheet #: TM052
Page 33 of 34 Rev: 01
2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com
Revision
Revision Date
Final Release Added Initialization Information pg.22