Memory Subsystem Device Architecture Flash density: 128-, 256-Mbi
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Intel PXA27x Processor Family
Memory Subsystem
Device Architecture Flash density: 128-, 256-Mbit LPSDRAM density: 256-Mbit Flash LPDRAM Combo (x16) Flash Flash Combo (x32) Device Voltage Core: (Typ) I/O: VCCQ (Typ) Device Packaging Ball count: balls Area: 14x14 Height: 1.55 SDRAM Architecture Performance Clock rate: Four internal banks Burst Length: full page Quality Reliability Extended Temp: Minimum flash block erase cycle 0.13 ETOX VIII flash technology
Flash Architecture Read-While-Write Erase Asymmetrical blocking structure 8-Mbit partition sizes (128-Mbit die) 16-Mbit partition sizes (256-Mbit die) 16-KWord parameter blocks (Bottom) 64-KWord main blocks 2-Kbit One-Time Programmable (OTP) Protection Register Zero-latency block locking Absolute write protection with block lock down using F-VPP F-WP# Flash Performance initial access async page-mode read sync read (tCHQV) Buffered Enhanced Factory Programming (Buffered EFP): µs/Byte (Typ) Buffered programming µs/Byte (Typ) Flash Software Intel FDI, Intel PSM, Intel Common Flash Interface (CFI) Basic/Extended Command
Intel® PXA27x Processor Family Memory Subsystem stacked device combining highperformance Intel StrataFlash® memory with without low-power SDRAM Intel® Stacked package. flash memory features low-power operations with flexible multipartitions, dual operation Read-While-Write Read-While-Erase, asynchronous synchronous reads 0.13 ETOXVIII flash technology. LPSDRAM memory features low-power operation MHz. PXA27x processor memory subsystem stacked Intel® PXA27x Processor optimized small form-factor package solution cellular applications.
Notice: This document contains preliminary information products production. specifications subject change without notice. Verify with your local Intel sales office that have latest datasheet before finalizing design.
301855-001 July 2004
INFORMATION THIS DOCUMENT PROVIDED CONNECTION WITH INTEL® PRODUCTS. LICENSE, EXPRESS IMPLIED, ESTOPPEL OTHERWISE, INTELLECTUAL PROPERTY RIGHTS GRANTED THIS DOCUMENT. EXCEPT PROVIDED INTEL'S TERMS CONDITIONS SALE SUCH PRODUCTS, INTEL ASSUMES LIABILITY WHATSOEVER, INTEL DISCLAIMS EXPRESS IMPLIED WARRANTY, RELATING SALE AND/OR INTEL PRODUCTS INCLUDING LIABILITY WARRANTIES RELATING FITNESS PARTICULAR PURPOSE, MERCHANTABILITY, INFRINGEMENT PATENT, COPYRIGHT OTHER INTELLECTUAL PROPERTY RIGHT. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Intel® PXA27x Processor Family Memory Subsystem contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2004. rights reserved. *Other names brands claimed property others.
Intel® PXA27x Processor Family Memory Subsystem
Contents
Contents
Part Electrical, Mechanical, Thermal Specifications (EMTS)
Introduction
Nomenclature Acronyms Conventions.10 Intel StrataFlash® Memory Die.13 Device Description Intel® PXA27x Processor Memory Subsystem Block Diagram Package Mechanical Information.23 Ballout Diagrams Signal Descriptions Absolute Maximum Ratings Operating Conditions Flash Current Characteristics Flash Voltage Characteristics LPSDRAM Characteristics Test Conditions.41 Flash Read Specifications Flash Write Specifications Flash Program Erase Characteristics LPSDRAM Capacitance LPSDRAM Characteristics.52 Flash Power-Up Power-Down Flash Output Disable Flash Standby.55 Flash Reset.55 Flash Power Supply Decoupling Flash Automatic Power Saving LPSDRAM Power-up Sequence Initialization
Device Overview
Package Information
Ballout Signal Descriptions.27
Maximum Ratings Operating Conditions
Electrical Specifications
Characteristics
Power Reset Specifications
Intel® PXA27x Processor Family Memory Subsystem
Contents
Part Flash Device Operations
Device Operations Overview
Flash LPSDRAM Operations. Flash Operations Flash Command Definitions. Flash Asynchronous Page-Mode Read Flash Synchronous Burst-Mode Read. 10.2.1 Flash Burst Suspend Flash Read Configuration Register. 10.3.1 Flash Read Mode 10.3.2 Flash Latency Count. 10.3.3 Flash Burst Sequence 10.3.4 Flash Clock Edge. 10.3.5 Flash Burst Wrap 10.3.6 Flash Burst Length. Flash Word Programming. 11.1.1 Flash Factory Word Programming. Flash Buffered Programming. Flash Buffered Enhanced Factory Programming. 11.3.1 Flash Buffered Requirements Considerations 11.3.2 Flash Buffered Setup Phase. 11.3.3 Flash Buffered Program/Verify Phase 11.3.4 Flash Buffered Exit Phase Flash Program Suspend Flash Program Resume. Flash Program Protection Flash Block Erase. Flash Erase Suspend Flash Erase Resume Flash Erase Protection Flash Block Locking. 13.1.1 Flash Lock Block. 13.1.2 Flash Unlock Block 13.1.3 Flash Lock-Down Block 13.1.4 Flash Block Lock Status 13.1.5 Flash Block Locking During Suspend Flash One-Time Programmable Protection Registers 13.2.1 Flash Reading Protection Registers 13.2.2 Flash Programming Protection Registers 13.2.3 Flash Locking Protection Registers
Flash Read Operations
10.1 10.2 10.3
Flash Programming Operations
11.1 11.2 11.3
11.4 11.5 11.6
Flash Erase Operations
12.1 12.2 12.3 12.4
Flash Security Modes
13.1
13.2
Contents
Flash Dual-Operation Considerations
14.1 14.2 Flash Partitioning Flash Read-While-Write Command Sequences 14.2.1 Simultaneous Flash Operation Details.90 14.2.2 Flash Write Flash Asynchronous Read Transition.90 14.2.3 Flash Write Flash Synchronous Read Operation Transition.90 14.2.4 Flash Write with Clock Active.90 14.2.5 Flash Read During Flash Buffered Programming Simultaneous Flash Operation Restrictions.91 Flash Read Status Register 15.1.1 Flash Clear Status Register Flash Read Device Identifier.95 Query
14.3
Special Flash Read States
15.1 15.2 15.3
Part LPSDRAM Operations
LSDRAM Register Definition.99
16.1 16.2 Mode Register LPSDRAM Extended Mode Register LPSDRAM Operation LPSDRAM Deselect. LPSDRAM Active.101 LPSDRAM Read Command LPSDRAM Write Command LPSDRAM Power-Down .102 LPSDRAM Deep Power-Down .103 LPSDRAM Clock Suspend LPSDRAM Precharge LPSDRAM Auto Precharge LPSDRAM Concurrent Auto Precharge. LPSDRAM Burst Terminate LPSDRAM Auto Refresh LPSDRAM Self Refresh.
LPSDRAM Command Operation.
17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 17.9 17.10 17.11 17.12 17.13
Appendix Appendix Appendix Appendix Appendix
Flash Flowcharts Common Flash Interface Intel® PXA27x Processor Memory Subsystem Type .133 Additional Information Ordering Introduction .137
Intel® PXA27x Processor Family Memory Subsystem
Contents
Revision History
Date 07/04 Revision -001 Description Initial product document release.
Part Electrical, Mechanical, Thermal Specifications (EMTS)
Intel® PXA27x Processor Family Memory Subsystem
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Introduction
Introduction
This document contains information pertaining PXA27x processor memory subsystem products Intel® PXA27x Processor Family. Intel® PXA27x Processor Family memory subsystem stacked device combining high- performance Intel StrataFlash® memory with without low-power SDRAM Intel® Stacked package. flash memory features lowpower operations with flexible multi-partitions, dual operation Read-While-Write Read-WhileErase, asynchronous synchronous reads 0.13 ETOXVIII flash technology. LPSDRAM memory features low-power operation MHz. PXA27x processor memory subsystem stacked Intel® PXA27x Processor optimized small form-factor package solution cellular applications.
Nomenclature
Volt Core Volt Asserted Block Bottom parameter (memory subsystem core) voltage range VCCQ (memory subsystem I/O) voltage range Signal with logical voltage level VIL, enabled. Group cells, bits, bytes words within flash memory array that erased with erase instruction. Previously referred bottom-boot flash, device with flash parameter partition located lowest physical address memory processor system boot Signal with logical voltage level VIH, disabled. specific memory type stacked flash LPSDRAM memory density configuration combination within memory subsystem product family. Individual flash LPSDRAM used stacked package memory subsystem device. High Impedance Signal Driven bus. 64-KWord flash array block. flash partition containing only main blocks. Flash reads which return flash Device Identifier, Query, Protection Register Status Register information. 16-KWord flash array block. flash partition containing parameter main blocks.
Deasserted Device High-Z Low-Z Main block Main partition Non-Array Reads Parameter block Parameter partition
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Introduction
Partition Program Write
group flash blocks that shares common status register read state. operation Write data flash array LPSDRAM. cycle operation inputs flash LPSDRAM die, which command data sent flash array LPSDRAM.
Acronyms
Buffered technology Automatic Power Savings Buffered Enhanced Factory Programming Common Flash Interface Chip Scale Package Command User Interface Multi-Level Cell technology One-Time Programmable Protection Lock Register Protection Register Read Configuration Register Reserved Future (Unused active signals package ballout) Read-While-Write Read-While-Erase Status Register Write State Machine
Conventions
Byte Clear DQ[15:0] F-CE# Denotes element signal group, this case address Binary unit, valid range [0,1]. Eight bits, valid range [0x00 0xFF]. Logical zero (0). Denotes group similarly named signals, such data bus. Denotes Chip Enable flash die, where denote flash specific signal suffix "CE#" root signal name flash die. denote LPSDRAM type signal.
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Introduction
Gbit Kbit KByte KWord Mbit MByte SR.4 Word
1,073,741,824 bits. 1024 bits. 1024 bytes (8,192 bits). 1024 words (16,384 bits). 1,048,576 bits. 1,048,576 bytes (8,388,608 bits). Hexadecimal number prefix. Binary number prefix. Logical (1). flash status register bit, this case status register SR[7:0]. Signal voltage connection. Signal voltage level. Denotes global power signal stacked device, common memory dies within stacked memory device. bytes sixteen bits, valid range [0x0000 0xFFFF].
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Introduction
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Device Overview
Device Overview
PXA27x processor memory subsystem device combines 128- 256-Mbit Intel StrataFlash® memory with without 256-Mbit low-power SDRAM Intel stacked package. following section describes PXA27x processor memory subsystem features, operation, characteristics flash LPSDRAM devices.
Intel StrataFlash® Memory
flash provides read-while-write read-while-erase capability with density upgrades 256-Mbit increments. flash provides high-performance voltage 16-bit data individually erasable memory blocks sized optimum code data storage. flash contains parameter partition several main partitions. flash memory arrays grouped into multiple 8-Mbit partition 128-Mbit flash die, 16-Mbit partitions 256-Mbit flash die. dividing flash memory into partitions, program erase operations take place simultaneously read operation. Although each partition write, erase, burst read capabilities, simultaneous operations limited write erase partition while reading another partition. Burst reads across partition boundaries allow, burst reads allow cross into partition that busy programming erasing mode, across flash dies within PXA27x processor memory subsystem. burst read operation must initiated when crossing these bondaries. Upon initial power return from reset, flash defaults asynchronous page-mode read. Configuring Read Configuration Register (RCR) enables flash synchronous burst-mode reads. synchronous burst-mode, output data synchronized with memory clock signal. addition enhanced architecture interface, flash incorporates technology that enables fast factory program erase operations. Designed low-voltage systems, flash supports read operations with F-VCC volt, erase program operations with F-VPP Buffered Enhanced Factory Programming (Buffered EFP) provides fastest flash array programming performance with F-VPP volt, which increases factory throughput. With F-VPP F-VCC F-VPP tied together simple, ultra-low power design. addition voltage flexibility, dedicated F-VPP connection provides complete data protection when F-VPP less than VPPLK. flash Command User Interface (CUI) interface between PXA27x processor internal operations each selected flash die. internal flash Write State Machine (WSM) automatically executes, example, algorithms timings necessary block erase program. Status Register indicates erase program completion errors that have occurred. industry-standard flash command sequence invokes program erase automation. Each erase operation erases block time. Erase Suspend feature allows system interrupt pause erase cycle read program data another block another partition. Program Suspend allows system interrupt pause programming read other locations. flash array programmed 16-bits increments.
Intel® PXA27x Processor Family Memory Subsystem
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Device Overview
flash offers power savings through Automatic Power Savings (APS) mode standby mode. individual flash automatically enters mode following read-cycle completion. Standby initiated when PXA27x processor deselects flash deasserting F-CE# asserting FRST#. Combined, these features significantly reduce power consumption. security requirement, each flash features 2048-bits One-Time Protection (OTP) register allows unique flash identification that used increase system security. addition, individual flexible Block Lock feature provides zero-latency block locking unlocking.
Device Description
PXA27x processor memory subsystem device combines high-performance Intel StrataFlash® memory with low-power SDRAM 16-bit Intel StrataFlash® memory only dies 32-bit operations Intel stacked package. Table "PXA27x Processor Memory Subsystem Signals 16-bit Interface" Table "PXA27x Processor Memory Subsystem Signals 32bit Interface" page provide signal relationships between Intel® PXA27x Processor device (bottom package) signal names with PXA27x processor memory subsystem (top package) device respectively interfaces.
Table Intel® PXA27x Processor Memory Subsystem Signals 16-bit Interface (Sheet
Ball# Type Input Input Input Input Input Input Input Input Input Input Input Input Input Input Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Ball Name DQM<0> DQM<1> DQM<2> DQM<3> NCS<0> NSDCS<0> NSDCAS NSDRAS SDCLK<3> SDCLK<1> SDCKE NF_WP<0> MD<15> MD<14> MD<13> MD<12> MD<11> MD<10> MD<9> MD<8> SDRAM D-DM[1] D-DM[0] D-CS# D-CAS# D-RAS# R-CLK D-CKE Flash F-CE# ADV# F-CLK F-WP# DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 PXA27x DQM<0> DQM<1> DQM<2> DQM<3> nCS<0> nSDCS<0> nSDCAS nSDRAS SDCLK<3> SDCLK<1> SDCKE MD<15> MD<14> MD<13> MD<12> MD<11> MD<10> MD<9> MD<8>
Intel® PXA27x Processor Family Memory Subsystem
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Device Overview
Table Intel® PXA27x Processor Memory Subsystem Signals 16-bit Interface (Sheet
Ball# Type Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Supply Ball Name MD<7> MD<6> MD<5> MD<4> MD<3> MD<2> MD<1> MD<0> MA<25> MA<24> MA<23> MA<22> MA<21> MA<20> MA<19> MA<18> MA<17> MA<16> MA<15> MA<14> MA<13> MA<12> MA<11> MA<10> MA<9> MA<8> MA<7> MA<6> MA<5> MA<4> MA<3> MA<2> MA<1> MA<0> NF_RST F_VPP SDRAM DQ11 DQ10 DQ13 DQ12 DQ15 DQ14 D-BA1 D-BA0 Flash
PXA27x MD<7> MD<6> MD<5> MD<4> MD<3> MD<2> MD<1> MD<0> MA<25> MA<24> MA<23> MA<22> MA<21> MA<20> MA<19> MA<18> MA<17> MA<16> MA<15> MA<14> MA<13> MA<12> MA<11> MA<10> MA<9> MA<8> MA<7> MA<6> MA<5> MA<4> MA<3> MA<2> MA<1> MA<0>
F-RST# F-VPP
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Device Overview
Table Intel® PXA27x Processor Memory Subsystem Signals 16-bit Interface (Sheet
Ball# V10/ V11/ V12/ V14/ V16/ V17/ R19/ N20/ P20/ Y10/ Y11/ Y12/ Y13/ Y16/ Y20/ U19/ N18/ P18/ U10/ U11/ U12/ U14/ U16/ W11/ A18/ A19/ A20/ B20/ C20/ C15/ Type Ball Name SDRAM Flash PXA27x
PXA27x processor memory subsystem Core Supply
VCC_MEM
D-VCC
F-VCC
VCC_MEM
PXA27x processor memory subsystem Supply
VSS_MEM
VSSQ
VSSQ
VSS_MEM
Supply
Intel® PXA27x Processor Family Memory Subsystem
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Device Overview
Table Intel® PXA27x Processor Memory Subsystem Signals 16-bit Interface (Sheet
Ball# W12/ W13/ W16/ Y15/ Type Ball Name SDRAM Flash PXA27x
Input
NF_WP<1>1
Notes: NF_WP<1> reserved stacked data-core flash memory write protect (not available current PXA27x processor configurations), package. Address signals shifted 16-bit flash align PXA27x processor memory subsystem with processor system design requirements.
Table Intel® PXA27x Processor Memory Subsystem Signals 32-bit Interface (Sheet
Ball# Type Input Input Input Input Input Input Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Ball Name NCS<0> NSDCAS SDCLK<3> NF_WP<0> MD<31> MD<30> MD<29> MD<28> MD<27> MD<26> MD<25> MD<24> MD<23> MD<22> MD<21> MD<20> MD<19> MD<18> MD<17> MD<16> MD<15> MD<14> MD<13> MD<12> Flash F-CE# ADV# F-CLK F-WP# DQ15 DQ14 DQ13 DQ12 Flash F-CE# ADV# F-CLK F-WP# DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 PXA27x nCS<0> nSDCAS SDCLK<3> MD<31> MD<30> MD<29> MD<28> MD<27> MD<26> MD<25> MD<24> MD<23> MD<22> MD<21> MD<20> MD<19> MD<18> MD<17> MD<16> MD<15> MD<14> MD<13> MD<12>
Intel® PXA27x Processor Family Memory Subsystem
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Device Overview
Table Intel® PXA27x Processor Memory Subsystem Signals 32-bit Interface (Sheet
Ball# Type Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Ball Name MD<11> MD<10> MD<9> MD<8> MD<7> MD<6> MD<5> MD<4> MD<3> MD<2> MD<1> MD<0> MA<25> MA<24> MA<23> MA<22> MA<21> MA<20> MA<19> MA<18> MA<17> MA<16> MA<15> MA<14> MA<13> MA<12> MA<11> MA<10> MA<9> MA<8> MA<7> MA<6> MA<5> MA<4> MA<3> MA<2> MA<1> MA<0> Flash DQ11 DQ10
Flash
PXA27x MD<11> MD<10> MD<9> MD<8> MD<7> MD<6> MD<5> MD<4> MD<3> MD<2> MD<1> MD<0> MA<25> MA<24> MA<23> MA<22> MA<21> MA<20> MA<19> MA<18> MA<17> MA<16> MA<15> MA<14> MA<13> MA<12> MA<11> MA<10> MA<9> MA<8> MA<7> MA<6> MA<5> MA<4> MA<3> MA<2> MA<1> MA<0>
Intel® PXA27x Processor Family Memory Subsystem
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Device Overview
Table Intel® PXA27x Processor Memory Subsystem Signals 32-bit Interface (Sheet
Ball# V10/ V11/ V12/ V14/ V16/ V17/ R19/ N20/ P20/ Y10/ Y11/ Y12/ Y13/ Y16/ Y20/ U19/ N18/ P18/ U10/ U11/ U12/ U14/ U16/ W11/ A18/ A19/ A20/ B20/ C20/ C15/ Type Input Supply Ball Name NF_RST F_VPP Flash F-RST# F-VPP Flash F-RST# F-VPP PXA27x
PXA27x processor memory subsystem Core Supply
VCC_MEM
D-VCC
F-VCC
VCC_MEM
PXA27x processor memory subsystem Supply
VSS_MEM
VSSQ
VSSQ
VSS_MEM
Supply
Intel® PXA27x Processor Family Memory Subsystem
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Device Overview
Table Intel® PXA27x Processor Memory Subsystem Signals 32-bit Interface (Sheet
Ball# W12/ W13/ W16/ Y15/ Type Ball Name Flash Flash PXA27x
Input
NF_WP<1>1
NOTES: NF_WP<1> reserved stacked data-core flash memory write protect (not available current PXA27x processor configurations), package. Address signals stacked datasheet shifted 32-bit flash align PXA27x processor memory subsystem with processor system design requirements.
Intel® PXA27x Processor Memory Subsystem Block Diagram
Intel® PXA27x Processor Memory Subsystem (x16) Device Block Diagram1
Figure
Memory Subsystem
MA[24:1]
A[23:0] D-BA[1:0] DQ[15:0] F-CE# D-CS# F-CLK ADV#
MD[15:0] nCS0
nSDCS0
Intel StrataFlash Memory 256-Mbit
Intel PXA27x Processor
SDCLK0
nSDCAS
nRESET_OUT SDCKE1
F-RST# D-CKE R-CLK D-RAS# D-CAS# D-DM[1:0]
LPSDRAM 256-Mbit
SDCLK1
nSDRAS
DQM[1:0]
Note: Connections shown operation.
Note:
PXA271 PXA27x 256-Mbit Flash 256-Mbit LPSDRAM (x16 configuration) device
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Device Overview
Figure
Intel® PXA27x Processor Memory Subsystem (x32) Device Block Diagram1,2
MA[25:2]
A[23:0] DQ[31:0] F-CE# F-CLK ADV#
MD[31:0] nCS0
Intel StrataFlash Memory 256-Mbit
PXA27x Processor (x32)
Intel®
SDCLK0 nSDCAS
nRESET_OUT
F-RST#
Intel StrataFlash Memory 256-Mbit
Note: Connections shown operation.
Notes: PXA272 PXA27x 128-Mbit Flash 128-Mbit Flash (x32 configuration) device. PXA273 PXA27x 256-Mbit Flash 256-Mbit Flash (x32 configuration) device.
Intel® PXA27x Processor Family Memory Subsystem
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Device Overview
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Package Information
Package Information
This section provides package mechanical specifications Intel® PXA27x Processor with PXA27x processor memory subsystem device. Intel® PXA27x Processor with PXA27x processor memory subsystem device provided 336-pin, 0.650 FS-CSP molded matrix array package, shown Figure Figure Table "Intel® PXA27x Processor with Memory Subsystem Dimensions" page
Figure
Package Mechanical Information
Intel® PXA27x Processor with Memory Subsystem Mechanical Details View
Ball Corner View Bottom Package Ball side down Complete Mark Shown
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Package Information
Figure
Intel® PXA27x Processor with Memory Subsystem Mechanical Details Side View
Seating Plane
Table
Intel® PXA27x Processor with Memory Subsystem Dimensions
Dimension Pacakge Height Ball Height Package Body Thickness Ball (Lead) Width Bottom Package Body Width Bottom Package Body Length Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along Corner Ball Distance Along Symbol 0.825 0.825 0.180 1.121 0.350 13.9 13.9 10.9 12.9 0.650 0.150 1.195 0.450 14.1 14.1 11.1 13.1 Typical 1.55
NOTE: mechanical dimensions milimeters (mm).
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Package Information
Figure
Intel® PXA27x Processor with Memory Subsystem Package Marking
PXA271FC0416 FPO# INTEL
Level Name Intel Legal
ALT# Flash PHILIPPINES
Pkg.
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Package Information
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Ballout Signal Descriptions
Ballout Signal Descriptions
This section provides ballout diagrams signal descriptions Intel® PXA27x Processor with Memory Subsystem device.
Figure
Ballout Diagrams
Intel® PXA27x Processor with Memory Subsystem Ball Map, Left Quarter
VCC_USB
VCC_USB
GPIO<89>
GPIO<42>
USBH_N<1> USBH_P<1>
GPIO<90>
GPIO<61>
GPIO<65>
GPIO<71>
GPIO<118> GPIO<119>
GPIO<88>
GPIO<43>
GPIO<115>
VCC_CORE
VCC_LCD
VCC_CORE
GPIO<70>
VSS_CORE
USBC_N
GPIO<120> GPIO<116> GPIO<114>
VCC_USIM
GPIO<91>
GPIO<63>
GPIO<64>
GPIO<69>
VCC_USB
USBC_P
GPIO<44>
GPIO<39>
GPIO<41>
VSS_IO
GPIO<58>
GPIO<59>
VSS_IO
GPIO<68>
VCC_CORE GPIO<117>
GPIO<35>
VSS_IO
GPIO<109>
GPIO<16>
VSS_CORE
GPIO<62>
GPIO<66>
VSS_CORE
GPIO<45>
GPIO<34>
GPIO<32>
GPIO<110> GPIO<111>
GPIO<25>
GPIO<22>
GPIO<60>
VSS_CORE
GPIO<67>
GPIO<112>
GPIO<92>
GPIO<17>
GPIO<36>
GPIO<37>
GPIO<30>
GPIO<23>
GPIO<24>
GPIO<26>
GPIO<27>
GPIO<38>
GPIO<46>
VCC_IO
VSS_IO
GPIO<40>
GPIO<31>
VSS_CORE
GPIO<11>
GPIO<28>
GPIO<29>
VCC_CORE GPIO<113>
GPIO<47>
VSS_CORE
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Part EMTS
Ballout Signal Descriptions
Figure
Intel® PXA27x Processor with Memory Subsystem Ball Map, Right Quarter
VCC_LCD
VCC_CORE
TESTCLK
GPIO<9>
GPIO<0>
NRESET
TXTAL_OUT
VCC_CORE
GPIO<14>
VSS_IO
GPIO<4>
PWR_EN
TXTAL_IN
BOOT_SEL
NRESET_O
GPIO<86>
GPIO<75>
NTRST
GPIO<3>
NVDD_FAUL NBATT_FAU PWR_CAP<
GPIO<87>
GPIO<76>
GPIO<77>
GPIO<10>
GPIO<1>
SYS_EN
PWR_CAP<
PWR_OUT
GPIO<72>
VSS_IO
GPIO<74>
CLK_REQ
PWR_CAP< PWR_CAP< VCC_BATT
PXTAL_IN
PXTAL_OUT
VSS_CORE
GPIO<73>
VSS_CORE
GPIO<19>
GPIO<97>
GPIO<94>
GPIO<96>
VCC_PLL
VSS_PLL
VSS_IO
VSS_IO
GPIO<100>
GPIO<99>
GPIO<98>
GPIO<93>
GPIO<95>
VSS_CORE GPIO<106> GPIO<104> GPIO<101> GPIO<102>
VCC_IO
GPIO<51>
GPIO<108> GPIO<107> GPIO<105> VCC_CORE GPIO<103>
GPIO<81>
VSS_BB
GPIO<50>
GPIO<52>
GPIO<53>
GPIO<54>
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Ballout Signal Descriptions
Figure
Intel® PXA27x Processor with Memory Subsystem Ball Map, Bottom Left Quarter
VCC_IO VSS_IO GPIO<12> GPIO<13> MD<30> MD<29>
GPIO<49>
GPIO<18>
VCC_SRAM
RDNWR
MD<31>
MD<14>
VCC_MEM
VSS_MEM
VCC_SRAM VSS_CORE
MA<6>
MD<15>
GPIO<80>
MA<18>
GPIO<79>
MA<10>
MA<9>
MA<3>
VCC_MEM
VCC_CORE VCC_SRAM
MA<19>
MA<15>
MA<7>
MA<4>
MD<13>
MD<12>
MD<11>
VSS_MEM
VCC_MEM
GPIO<33>
MA<20>
MA<16>
MA<12>
MA<8>
MA<2>
MD<28>
MD<27>
VCC_CORE VSS_CORE VCC_SRAM VSS_CORE
VSS_MEM
MA<13>
VSS_MEM
VSS_MEM
VSS_MEM
VSS_MEM
GPIO<15>
MA<25>
VSS_CORE
GPIO<78>
VCC_MEM
MA<14>
VCC_MEM
VCC_MEM
VCC_MEM
VCC_MEM
NCS<0>
MA<24>
MA<0>
MA<23>
MA<21>
MA<17>
MA<11>
MA<5>
F_VPP
VSS_CORE
VSS_MEM
MA<1>
MA<22>
VSS_MEM
VCC_MEM
VCC_MEM
NF_RST
VSS_MEM
VCC_MEM
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Ballout Signal Descriptions
Figure
Intel® PXA27x Processor with Memory Subsystem Ball Map, Bottom Right Quarter
GPIO<85>
GPIO<55>
GPIO<57>
GPIO<48>
VCC_CORE
VCC_BB
MD<5>
MD<4>
MD<1>
GPIO<56>
GPIO<83>
GPIO<84>
MD<21>
MD<17>
MD<16>
VSS_MEM
GPIO<82>
VCC_MEM
MD<23>
MD<2>
DQM<1>
VSS_MEM
SDCLK<1>
VCC_MEM
MD<26>
MD<25>
VSS_CORE
MD<8>
MD<22>
VSS_CORE NSDCS<1>
GPIO<21>
VCC_MEM
VCC_CORE
MD<10>
MD<9>
VCC_CORE
MD<6>
VCC_CORE
MD<18>
DQM<2>
SDCKE
SDCLK<2>
GPIO<20>
VSS_MEM
VSS_MEM
MD<24>
VSS_MEM
MD<19>
VSS_MEM
MD<0>
VSS_CORE
VSS_MEM
NSDCAS
VCC_MEM
VCC_MEM
MD<7>
VCC_MEM
MD<3>
VCC_MEM
VCC_MEM
NSDCS<0>
SDCLK<3>
SDCLK<0>
VSS_MEM
MD<20>
NF_WP<0>
DQM<3>
DQM<0>
VCC_MEM
VCC_MEM
VCC_MEM
NF_WP<1>
VCC_MEM
VSS_MEM
NSDRAS
VCC_MEM
Note:
"RFU" means "Reserved Future Use." Please contact your local Intel representative recommendations what designers with RFUs.
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Ballout Signal Descriptions
Signal Descriptions
Table describes active signals PXA27x processor memory subsystem.
Table Intel® PXA27x Processor Memory Subsystem Signal Descriptions (Sheet
Symbol Type Name Function ADDRESS: Global device signals. Share inputs memory addresses during read write operations.
16-bit operations, A[24:1] signal balls used, while 32-bit operations, A[25:2] used. This PXA27x processor addresses shift compare flash LPSDRAM die. A[MAX:MIN] Input Flash addressability: A[23:0] 256-Mbit die; A[22:0] 128-Mbit die. 256-Mbit LPSDRAM die: A[13:1] A[9:1] column addresses. LPSDRAM Address inputs also provide op-code during Mode Register Special Mode Register command. defines Auto Precharge. During LPSDRAM Precharge command, sampled determine banks precharged (A11 HIGH).
DQ[MAX:0]
Input/ Output
DATA INPUT/OUTPUTS: Global device signals. Inputs data commands during write cycles, outputs data during read cycles. Data signals float when device output deselected. Data internally latched during writes device.
DQ[15:0] used 16-bit operations. DQ[31:0] used 32-bit operations.
ADDRESS VALID: Low-true input.
ADV# Input During synchronous flash read operations, addresses latched rising edge ADV#, next valid F-CLK edge, whichever occurs first. asynchronous flash read operation, addresses latched rising edge ADV#, continuously flow-through when ADV# kept asserted.
FLASH CHIP ENABLE: Low-true input.
F-CE# Input F-CE# selects associated flash memory die. F-CE# high deselects associated flash die. When deasserted, associated flash deselected, power reduced standby levels, data outputs placed high-Z state.
CLOCK: Synchronizes selected memory PXA27x memory clock synchronous operations.
F-CLK, R-CLK Input F-CLK flash signal. Synchronizes flash PXA27x memory frequency synchronous operations. R-CLK LPSDRAM input signal. Synchronizes LPSDRAM PXA27x memory clock. LPSDRAM sampled positive edge R-CLK. R-CLK also increments internal burst counter controls output registers.
OUTPUT ENABLE: Low-true input.
Input enables output drivers selected flash die. high places flash output drivers selected high-Z.
FLASH RESET: Low-true input.
F-RST# Input F-RST# resets internal operations inhibits write operations. F-RST# high enables normal operation. Exit from reset places flash device asynchronous read array mode.
DEVICE WAIT: Flash configurable Low-True High-True output.
Indicates data valid synchronous array non-array sync flash reads. Configuration Register (CR.10, determines polarity when asserted. With F-CE# VIL, WAIT's active output VOH. WAIT high-Z F-CE# VIH. synchronous array non-array flash read modes, WAIT indicates invalid data when asserted valid data when deasserted. asynchronous flash page read, flash write modes, WAIT deasserted.
WAIT
Output
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Ballout Signal Descriptions
Table Intel® PXA27x Processor Memory Subsystem Signal Descriptions (Sheet
Symbol Type Name Function WRITE ENABLE: Global device signal. Low-true input.
Input flash operation, selects associated memory write operation. high deselect associated memory die, data placed high-Z state. LPSDRAM operation, latched positive clock edge conjunction with D-RAS# D-CAS# signals. input used select Bank Activate Precharge command Read Write command.
FLASH WRITE PROTECT: Low-true input.
F-WP# Input F-WP# enables Lock-Down flash mechanism. Blocks lock-down state cannot unlocked with Unlock command. F-WP# high overrides Lock-Down function, enabling locked-down blocks unlocked with Unlock command.
LPSDRAM Clock Enable: High-true input
D-CKE synchronously with clock, internal clock suspended from next clock cycle. D-CKE Input state outputs burst address halted. When banks idle state, DCKE high, LPDRAM enters into Power-Down Self Refresh modes. D-CKE synchronous except after device enters Power-Down Self Refresh modes, where D-CKE becomes asynchronous until exiting same mode. input buffers, including R-CLK, disabled during Power-Down Self Refresh modes, providing standby power.
LPSDRAM Bank Select: Low-true input.
D-BA[1:0] Input D-BA0 D-BA1 defines which bank Bank Activate, Read, Write, Bank Pre-charge command being applied. bank address D-BA0 D-BA1 used latched mode register set.
LPSDRAM Address Strobe: Low-true input.
D-RAS# signal defines operation commands, with D-CAS# signals. D-RAS# Input D-RAS# latched rising edges R-CLK. When D-RAS# D-CS# asserted D-CAS# deasserted, either Bank Activate command Precharge command selected signal. deasserted, Bank Activate command selected bank designated D-BA[1:0] turned active state.
LPSDRAM Column Address Strobe: Low-true input.
D-CAS# Input D-CAS# signal defines operation commands conjunction with D-RAS# signals latched rising edges R-CLK. D-RAS# deasserted D-CS# asserted, column access started asserting D-CAS#. Read Write command then selected asserting high.
LPSDRAM Chip Select: Low-true input.
D-CS# Input D-CS# selects associated LPSDRAM memory die. commands masked when D-CS# high. D-CS# provides external bank selection systems with multiple banks. considered part command code.
LPSDRAM Data Input/Output Mask: Data Input Mask.
D-DM[1:0] Input D-DM[1:0] byte selects. Input data masked when D-DM[1:0] sampled HIGH during write cycle. D-DM1 masks DQ[15-8], D-DM0 masks DQ[7-0]. D-DM[1:0] latency Read Clocks Write Clocks.
FLASH ERASE/ PROGRAM VOLTAGE: Flash specific signal.
F-VPP Power Valid F-VPP voltage this ball allows flash block erase program functions. Flash memory array contents cannot altered when F-VPP VPPLK. Flash block erase program invalid F-VPP voltage should attempted.
FLASH CORE VOLTAGE LEVEL: Flash specific signals.
F-VCC Power Flash core source voltage. Flash operations inhibited when F-VCC VLKO. Operations invalid F-VCC voltage should attempted.
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Ballout Signal Descriptions
Table Intel® PXA27x Processor Memory Subsystem Signal Descriptions (Sheet
Symbol
VCCQ D-VCC F-VCC RFU2
Type
Power Power Power Power
Name Function OUTPUT VOLTAGE LEVEL: Global device signals. Device input/output-driver source voltage within operatng voltage range. LPSDRAM POWER SUPPLY: Supplies power LPSDRAM die.
D-VCC supplies power LPSDRAM operation.
FLASH POWER SUPPLY: Supplies power Flash die.
F-VCC supplies power Flash operation.
GROUND: Global ground reference device memory core type voltages. USE: This ball must left floating. This ball should connected power supplies, signals, other balls. RESERVED FUTURE USE: Reserved Intel future device functionality enhancements.
Notes: Connect system ground. float connections. Please contact your local Intel representative details.
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Ballout Signal Descriptions
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Maximum Ratings Operating Conditions
Maximum Ratings Operating Conditions
Warning:
Absolute Maximum Ratings
Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Table
Table Intel® PXA27x Processor Memory Subsystem Absolute Maximum Ratings
Parameter
Case Temperature under bias Storage temperature Voltage flash signals (except F-VCC, F-VPP) relative Voltage LPSDRAM signals F-VPP voltage F-VCC D-VCC voltage VCCQ voltage Flash Output short circuit current LPSDRAM Output short circuit current
-0.5 -0.5 -0.2 -0.2 -0.2
Unit
Notes
+125 +3.8 +2.6 +2.45 +2.45
Notes: specified voltages relative VSS. Minimum voltage -0.5 input/output pins -0.2 F-VCC, D-VCC, F-VPP pins. During transitions, this level undershoot -2.5 periods which, during transitions, overshoot F-VCC D-VCC periods Maximum voltage F-VPP overshoot +9.0 periods Output shorted more than second. more than output shorted time.
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Maximum Ratings Operating Conditions
Warning: Table
Symbol
F-VCC D-VCC VCCQ VPPL VPPH
Operating Conditions
Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" adversely affect device reliability. Memory Subsystem Operating Conditions
Parameter
Case Operating Temperature Flash Supply Core Voltage LPSDRAM Supply Core Voltage Supply Voltage option Flash Progarmming Voltage Supply (Logic Level) Flash Factory Programming (Elevated Voltage) Maximum Hours Elevated Voltage Flash Main Parameter Blocks
Condition
F-VPP VPPH F-VPP F-VCC F-VPP VPPH F-VPP =VPPH
1.71 100,000
1000 2500
Unit
tPPH Flash Block Erase Cycles
Hours
Flash Main Blocks Flash Parameter Blocks Note:
Cycles
F-VPP program voltage normally VPPL. Maximum F-VPP F-VPPH 1000 cycles main blocks 2500 cycles parameter blocks during flash program erase.
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Electrical Specifications
Electrical Specifications
Note:
PXA27x processor memory subsystem device power active non-active currents.
Flash Current Characteristics
flash current characteristics shown Table individual flash within PXA27x processor memory subsystem device.
Table
Flash Current Characteristics (Sheet
Parameter
Unit
Test Conditions
F-VCC F-VCC VCCQ VCCQ VCCQ F-VCC F-VCC VCCQ VCCQ F-VCC F-VCC VCCQ VCCQ F-CE# F-RST# F-WP# F-VCC F-VCC VCCQ VCCQ F-CE# F-RST# 1-Word Read 4-Word Read Burst length Burst length F-VCC F-VCC F-CE# Inputs: F-VCC F-VCC F-CE# Inputs:
Notes
Input Load Current
Output Leakage Current
ICCS
Standby
ICCAPS Automatic Power Saving (APS) Asynchronous Single-Word F-CLK) ICCR Page-Mode Read F-CLK) Synchronous Burst Read MHz,
ICCR
ICCW, ICCE ICCWS, ICCES IPPS, IPPES IPPR
F-VPP Program Current, F-VPP Erase Current F-VPP Program Suspend Current, F-VPP Erase Suspend Current F-VPP Standby Current,
F-VPP VPPL, program/erase progress F-VPP VPPH, program/erase progress F-CE# VIL, suspend progress
1,3,4,7 1,3,5,7 1,6,3
IPPWS, F-VPP Program Suspend Current, F-VPP Erase Suspend Current F-VPP Read
F-VPP F-VPPL, suspend progress F-VPP F-VCC
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Electrical Specifications
Table
IPPW
Flash Current Characteristics (Sheet
Parameter
0.05
0.10
Unit
Test Conditions
F-VPP VPPL, program progress F-VPP VPPH, program progress
Notes
F-VPP Program Current 0.05 F-VPP Erase Current 0.10
IPPE
F-VPP VPPL, erase progress F-VPP VPPH, erase progress
NOTES: currents unless noted. Typical values typical F-VCC ICCS average current measured over time interval after F-CE# deasserted. Sampled, 100% tested. Flash read program current ICCR ICCW currents. Flash read erase current ICCR ICCE currents. ICCES specified with flash deselected. flash read-while-erase suspend, flash current ICCES ICCR. ICCW, ICCE measured over typical times specified Section 7.4, "Flash Program Erase Characteristics" page
Table
Flash Voltage Characteristics
Flash Voltage Characteristics
VPPLK VLKO VLKOQ
Parameter
Input Voltage Input High Voltage Output Voltage Output High Voltage F-VPP Lock-Out Voltage F-VCC Lock Voltage VCCQ Lock Voltage
VCCQ VCCQ
VCCQ
Unit
Test Condition
Notes
F-VCC F-VCC VCCQ VCCQ
Notes: undershoot -0.4 overshoot VCCQ durations F-VPP VPPLK inhibits erase program operations. VPPL VPPH outside their valid ranges.
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Electrical Specifications
LPSDRAM Characteristics
NOTICE: Characteristics PXA27x processor memory subsystem need considered accordingly, depending device operation.
Table
LPSDRAM Characteristics (Sheet
Parameter D-VCC Description
Voltage Range tCK_MIN D-CKE D-CS# tCK_MIN D-CKE D-CS# tCK_MIN D-CKE tCK_MIN
Test Conditions
Unit
Notes
Operating Current ICC1 (One Bank cycle time Active) Burst Length Precharge Standby Current: PowerDown Mode (All banks idle) Precharge Standby Current: Non-PowerDown Mode (All banks idle) Active Standby Current PowerDown Mode (All banks active) Active Standby Current: Non-PowerDown Mode (All banks active) Operating Current Page Burst Mode Auto Refresh Current Self Refresh Current
ICC2P
ICC2N
ICC3P
ICC3N
D-CKE tCK_MIN tCK_MIN tRC_MIN Address Data toggling cycle time Address Data toggling cycle time -100 VCCQmin
ICC4 Banks active) ICC5 ICC6
ICC7
Deep Power-Down Current Output High Voltage Output Voltage Input High Voltage
VCCQ 0.15 -0.1 VCCQ
VCCQ
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Electrical Specifications
Table
LPSDRAM Characteristics (Sheet
Input Voltage Input Leakage Current -0.2 VCCQ -0.2 -1.5 +1.5
Notes: Input leakage currents include High-Z output leakage bi-directional buffers with tri-state outputs. Input signals toggled frequency simulate PXA27x processor memory subsystem operating condition, where another device active. accesses progress. below Table "LPSDRAM Self Refresh Current".
Table
LPSDRAM Self Refresh Current
Banks Parameter Description Test Condition Temperature
Banks Refreshed
Bank Refreshed
Bank Refreshed
Unit
ICC6
Self Refresh Current (All Banks Refreshed)
D-CKE Infinity
Note:
Other than ICC6 Banks 85°C, Self Refresh currents verified during device characterization 100% tested.
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Characteristics
Characteristics
Test Conditions
Figure Intel® PXA27x Processor Memory Subsystem Input/Output Reference Waveform
VCCQ
Input CCQ/2
Test Points
VCCQ/2 Output
NOTE: test inputs driven Logic Logic "0." Input/output timing begins ends VCCQ/2. Input rise fall times (10% 90%) Worst case speed occurs F-VCC F-VCC MIN.
Figure Intel® PXA27x Processor Memory Subsystem Transient Equivalent Testing Load Circuit
Output
Ohms
Ohms VCCQ/2
Notes: Test configuration component value worst case speed conditions. includes capacitance.
30pf
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Characteristics
Table
Number
Flash Read Specifications
Flash Read Specifications (Sheet
Symbol parameter Range Units Notes
Asynchronous Specifications
tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tEHEL F-CE# output valid output valid F-RST# high output valid F-CE# output low-Z output low-Z F-CE# high output high-Z high output high-Z Output hold from first occurring address, F-CE#, change F-CE# pulse width high Address output valid Read cycle time
F-VCC F-VCC F-VCC F-VCC F-VCC F-VCC
1,2,3
Latching Specifications
R101 R102 R103
tAVVH tELVH tVLQV
Address setup ADV# high F-CE# ADV# high ADV# output valid ADV# pulse width ADV# pulse width high Address hold from ADV# high Page address access F-RST# high ADV# high
F-VCC F-VCC
R104 R105 R106 R108 R111
tVLVH tVHVL tVHAX tAPA tPHVH
Clock Specifications
R200 R201 R202 R203
fF-CLK tF-CLK tCH/CL tF-CLK
F-CLK frequency F-CLK period F-CLK high time F-CLK fall rise time
19.2
Synchronous Specifications
R301 R302 R303
tAVCH/tAVCL tVLCH/tVLCL tELCH/tELCL
Address setup F-CLK ADV# setup F-CLK F-CE# setup F-CLK
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Characteristics
Table
Number
Flash Read Specifications (Sheet
Symbol parameter Range
Units
Notes
R304 R305 R306 R311
tCHQV/tCLQV tCHQX tCHAX tCHVL
F-CLK output valid Output hold from F-CLK Address hold from F-CLK F-CLK Valid ADV# Setup
1,4,5
NOTES: Figure "PXA27x Processor Memory Subsystem Input/Output Reference Waveform" page timing measurements allowable input slew rate. delayed tELQV tGLQV after F-CE#'s falling edge without impact tELQV. Sampled, 100% tested. Address hold synchronous burst mode tCHAX tVHAX, whichever timing specification satisfied first. Applies only subsequent synchronous reads.
Figure
Flash Asynchronous Single-Word Read with ADV#
Address ADV# F-CE# Data [D/Q] F-RST#
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Characteristics
Figure
Flash Asynchronous Single-Word Read with ADV# Latch
Addres [MAX:MIN+2] A[1:0] R106 R101 R105 ADV# F-CE# Data [D/Q]
NOTE: A[1:0] must held constant.
Figure
Flash Asynchronous Page-Mode Read Timing
Address [MAX:MIN+2] A[1:0] R101 R105 ADV# F-CE# DATA [D/Q] R108 R108 R108
R106
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Characteristics
Figure
Flash Synchronous Single-Word Array Non-array Read Timing
Latency Count R301 R306
F-CLK Address R101 R105 R104 ADV# R303 R102 F-CE# R304 Data [D/Q] R305 R106
Note:
This diagram illustrates case where n-word burst initiated flash memory array terminated F-CE# deassertion after first word burst.
Figure
Flash Synchronous Burst-Mode Eight-Word Read Timing
Latency Count R301 R302 R306
F-CLK Address R101 R105 R102 ADV# R303 F-CE# Data [D/Q] R304 R304 R305 R106
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Characteristics
Figure
Flash Burst Suspend Timing
R304 F-CLK
R305
R305
Address R101 R105 ADV# F-CE# DATA [D/Q] R304 R304
R106
Note:
F-CLK stopped either high state.
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Characteristics
Flash Write Specifications
Table Intel® PXA27x Flash Write Specifications
Number Symbol Parameter Unit Notes
tPHWL tELWL tWLWH tDVWH tAVWH tWHEH tWHDX tWHAX tWHWL tVPWH tQVVL tQVBL tBHWH tWHGL tWHQV
F-RST# high recovery F-CE# setup write pulse width Data setup high Address setup high F-CE# hold from high Data hold from high Address hold from high pulse width high F-VPP setup high F-VPP hold from Status read F-WP# hold from Status read F-WP# setup high high high read valid
tAVQV
1,2,3 1,2,3 1,2,4 1,2,5 1,2,3,7
1,2,3,7 1,2,9 1,2,3,6,10
Write Asynchronous Read Specifications
tWHAV
high Address valid
1,2,3,6
Write Synchronous Read Specifications
tWHCH/L tWHVH
high Flash Clock valid high ADV# high
1,2,3,6,10
Write Specifications with Clock Active
tVHWL tCHWL
ADV# high Flash Clock high
1,2,3,11
NOTES: Write timing characteristics during erase suspend same write-only operations. write operation terminated with either F-CE# WE#. Sampled, 100% tested. Write pulse width (tWLWH tELEH) defined from F-CE# (whichever occurs last) FCE# high (whichever occurs first). Write pulse width high (tWHWL tEHEL) defined from F-CE# high (whichever occurs first) F-CE# (whichever occurs last). tWHVH tWHCH/L must when transitioning from write cycle synchronous burst read. F-VPP F-WP# should valid level until erase program success determined. This specification only applicable when transitioning from write cycle asynchronous read. spec synchronous read. When doing Read Status operation following command that alters Status Register, write operations results block lock status change, subsequent read operation reflect this change. These specs required only when device synchronous mode clock active during address setup phase.
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Characteristics
Figure
Flash Write Flash Write Timing
Address ADV# F-CE# Data [D/Q] F-RST#
Figure
Flash Asynchronous Read Flash Write Timing
Address F-CE# Data [D/Q] F-RST#
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Characteristics
Figure
Flash Write Flash Asynchronous Read Timing
Addres F-CE# Data [D/Q] F-RST#
Figure
Flash Synchronous Read Flash Write Timing
Latency Count R301 R302 R306
F-CLK R101 Addres R105 R102 ADV# R303 F-CE# R304 Data [D/Q] R305 R106 R104
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Characteristics
Figure
Flash Write Flash Synchronous Read Timing
Latency Count R302 R301
F-CLK Addres R106 R104 ADV# F-CE# Data [D/Q] F-RST# R304 R305 R304 R303 R306
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Characteristics
Flash Program Erase Characteristics
Table Intel® PXA27x Flash Program Erase Characteristics
VPPL Number. Symbol Parameter Conventional Word Programming VPPH Units Notes
W200
tPROG/W
Program Time
Single Word Single Cell
Buffered Programming
W200 W201
tPROG/Word tPROG/Buffer
Program Time
Single Word Buffer (32-words)
Buffered Enhanced Factory Programming
W451 W452
tBEFP/Word tBEFP/Setup
Single Word Program Buffered Setup
Erasing Suspending
W500 W501 W600 W601
tERS/Buffer tERS/Main Block tSUSP/Prog Susp tSUSP/Erase
Susp
Erase Time
16-KWord Parameter 64-KWord Main Program Suspend
Suspend Latency Erase Suspend
Notes: Typical values measured nominal voltages. Excludes system overhead. Sampled, 100% tested. Averaged programming time over entire flash arrays.
Table
LPSDRAM Capacitance
LPSDRAM Capacitance
Symbol Parameter Unit Condition
COUT
Input Capacitance Output Capacitance
VOUT
NOTE: Sampled, 100% tested. MHz.
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Characteristics
Table
LPSDRAM Characteristics
256-Mbit LPSDRAM Characteristics-Read-Only Operations
Symbol Parameter Test Condition Unit Notes
tCKH tCKL tCKEH tCKES tCMH tCMS tRAS tRCD tREF tRFC tSREX
Clock Cycle Time Clock High Level Pulse Width Clock Level Pulse Width Transition Time D-CKE Hold Time D-CKE Setup Time Address Hold Time Address Setup Time Data Input Hold Time Data Input Setup Time
R-CLK
100K
D-CS#, D-RAS#, D-CAS#, WE#, D-DM Hold Time D-CS#, D-RAS#, D-CAS#, WE#, D-DM Setup Time Clock valid output delay (positive edge clock) Data Hold Time Clock Output Low-Z Clock Output High-Z
28.5 28.5
Active time (Active Precharge command) Cycle time (Active Active command same bank) column delay (Active Read/Write) Precharge Time Refresh Period (4096 rows) Auto Refresh Period Self Refresh Exit Time (Self refresh Active)
Notes: minimum number clock cycles determined dividing minimum time required clock cycle time. LPSDRAM specs guaranteed only when normal output driver strength used. Table "LPSDRAM Configurable Output Driver Strength" page 100.
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Characteristics
Table
Symbol
256-Mbit LPSDRAM Characteristics-Write Operations1,2
Parameter Test Condition Unit
tRRD tDAL tCDL tBDL tCCD tDQW tDQZ tMRD tPHZ tINI
Write Recovery Time Active bank Active Bank command Last data input Active Delay Last data input Read/Write command Last data input Burst Terminate command Read/Write command Read/Write command D-DM write mask latency D-DM data mask latency Load Mode Register command Active/Refresh command Write Recovery Time Data High from Precharge command Initialization Delay
Notes: minimum number clock cycles determined dividing minimum time required clock cycle time. LPSDRAM specs guaranteed only when normal output driver strength used. Table "LPSDRAM Configurable Output Driver Strength" page 100.
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Characteristics
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Power Reset Specifications
Power Reset Specifications
Flash Power-Up Power-Down
Power supply sequencing required F-VCC, VCCQ, F-VPP connected together. VCCQ and/or F-VPP connected F-VCC supply, then F-VCC should reach F-VCC before applying VCCQ F-VPP. Device inputs should driven before supply voltage equals F-VCC MIN. Power supply transitions should only occur when F-RST# low. This protects device from accidental programming erasure during power transitions.
Flash Output Disable
When deasserted, flash outputs DQ[MAX:0] disabled placed Hign-Z.
Flash Standby
When F-CE# deasserted flash deselected placed standby, substantially reducing power consumption. standby, data outputs placed High-Z, independent level placed OE#. Standby current, ICCS, average current measured over time interval, after F-CE# deasserted. When flash deselected (while F-CE# deasserted) during program erase operation, continues consume active power until program erase operation completed.
Flash Reset
When PXA27x processor reset occurs with flash memory reset, improper processor initialization occur because flash memory providing status information rather than array data. F-RST# should controlled same low-true reset signal that resets PXA27x processor. After initial power-up reset, flash defaults asynchronous Read Array, Status Register 0x80. minimum delay required before initial read access write cycle initiated. After this wake-up interval passes, normal operation restored. Table Figure page details about flash reset timing.
Note:
F-RST# asserted during program erase operation, operation terminated memory contents aborted location (for program) block (for erase) longer valid, because data have been only partially written erased.
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Power Reset Specifications
Table
Flash Reset Timing
Nbr. Symbol Parameter Unit Notes
tPLPH tPLRH tVCCPH
F-RST# pulse width F-RST# device reset during erase F-RST# device reset during program F-VCC Power valid F-RST# de-assertion (high)
1,2,3,5 3,4,5 3,4,5 1,3,5
NOTES: device reset tPLPH tPLPH MIN, this guaranteed. F-RST# tied F-VCC supply, flash will ready until tVCCPH after F-VCC F-VCC MIN. F-RST# tied signal with VCCQ voltage levels, F-RST# input voltage must exceed F-VCC until F-VCC F-VCC MIN. Reset completes within tPLPH F-RST# asserted while erase program operation executing. Sampled, 100% tested.
Figure
Flash Reset Operation Waveforms
Reset during read mode
F-RST#
Abort Complete
Reset during program block erase Reset during program block erase
F-RST# F-RST#
Abort Complete
F-VCC Power-up F-RST# high
F-VCC
F-VCC
Flash Power Supply Decoupling
Flash memory device require careful power supply decoupling. Three basic power supply current considerations require: Standby current levels, Active current levels, Transient peaks produced when F-CE# asserted deasserted. When flash accessed, many internal conditions change. Transient current magnitudes depend device outputs' capacitive inductive loading. Two-line control correct decoupling capacitor selection suppress transient voltage peaks. Because Intel StrataFlash® memory draws power from F-VCC, F-VPP, VCCQ, therefore each power connection should have ceramic capacitor connected corresponding ground connection (e.g.,VCCQ VSS). Highfrequency, inherently low-inductance capacitors should placed close possible package leads. recommended, every eight devices used system, electrolytic capacitor should placed between power ground close devices. bulk capacitor meant overcome voltage droop caused trace inductance.
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Power Reset Specifications
Flash Automatic Power Saving
Automatic Power Saving (APS) provides power operation during read's active state. During APS, ICCAPS average current measured over time interval, after F-CE# deasserted. APS, same time interval after following events: There internal read, program, erase operations. F-CE# asserted. address lines quiescent VCCQ. also driven during APS.
LPSDRAM Power-up Sequence Initialization
LPSDRAM must powered initialized predefined manner. Once power applied D-VCC VCCQ simultaneously, clock stable, LPSDRAM requires tINI delay prior issuing command other than command. command should applied least once during tINI delay. After tINI delay, Precharge command should applied precharge banks. This must followed back back Auto Refresh cycles. After Auto Refresh cycles complete, Mode registers must programmed. Mode Register will power unknown state. Mode Register Extended Mode Register should loaded prior issuing operational commands.
Intel® PXA27x Processor Family Memory Subsystem
Part EMTS
Power Reset Specifications
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations
PXA27x Processor Memory Subsystem
PXA27x Processor Memory Subsystem
Part Flash Device Operations Device Operations Overview
Device Operations Overview
Flash LPSDRAM Operations
operations PXA27x processor memory subsystem device involve control flash LPSDRAM inputs. operations shown from Table Table Fully synchronous operations performed flash LPSDRAM latch commands positive edges F-CLK R-CLK respectively
Table
Device
Flash LPSDRAM Operations (Sheet
D-DM[1:0] D-BA[1:0] D-CKEn-1 Address D-RAS# D-CAS# D-CKEn F-RST# D-CS# F-VPP F-CE# Notes ADV# Data
Mode
Sync Read Async Read
Flash
VPPL/ VPPH
Address Addr LPSDRAM mode allowed LPSDRAM outputs must High-Z
Flash DQOUT Flash DQOUT Flash DQIN Flash High-Z Flash High-Z Flash High-Z LPSDRAM DQOUT LPSDRAM DQOUT LPSDRAM DQIN LPSDRAM High-Z LPSDRAM High-Z LPSDRAM High-Z LPSDRAM High-Z LPSDRAM High-Z
1,2,3,4, 1,2,3,4, 1,2,4,15 4,15 4,15 4,15 5,6,7
Write Output Disable Standby Reset Active Read With Auto Precharge Write With Auto Precharge
5,6,7,13
Flash outputs must High-Z
5,6,8
LPSDRAM
Burst Stop Precharge Bank Banks Auto Refresh Self Refresh Entry Self Refresh Exit Flash outputs must High-Z Flash must High-Z
flash mode allowed
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Device Operations Overview
Table
Device
Flash LPSDRAM Operations (Sheet
D-DM[1:0] D-BA[1:0] D-CKEn-1 Address D-RAS# D-CAS# D-CKEn F-RST# D-CS# F-VPP F-CE# Notes ADV# Data
Mode
Load Mode Register Input/ Output Enable Input Inhibit/ Output High-Z Clock Suspend Entry Clock Suspend Exit Power Down Entry Power Down Exit Deep Power Down Entry Deep Power Down Exit Device Deselect (NOP) Operation (NOP)
Notes:
Flash outputs must High-Z
Operand Code
LPSDRAM High-Z LPSDRAM High-Z LPSDRAM High-Z LPSDRAM High-Z LPSDRAM High-Z LPSDRAM High-Z LPSDRAM High-Z LPSDRAM High-Z LPSDRAM High-Z LPSDRAM High-Z LPSDRAM High-Z
10,11
flash mode allowed
flash mode allowed Flash outputs must High-Z flash mode allowed Flash outputs must High-Z flash mode allowed Flash outputs must High-Z
6,13
LPSDRAM
6,14
6,14
6,14
flash mode allowed Flash outputs must High-Z
should never asserted simultaneously. inputs. Flash query status register accesses DQ[7:0] only, other reads DQ[15:0]. states sequences shown illegal reserved. Valid. A[13:1] provide address LPSDRAM. A[9:1] provide column address LPSDRAM. Select bank column address, start Read. High enables auto precharge. Select bank column address, start Write. High enables auto precharge. Activate deactivate data during Writes with zero-clock delay during Reads with two-clock delay. D-DM0 corresponds DQ[7:0], D-DM1 corresponds DQ[15:8]. A[11:1] define DRAM operand code register Extended mode register programmed setting D-BA1 D-BA0 Mode register programming, D-BA1 D-BA0 banks must precharged before issuing Auto-refresh command. Clock suspend mode occurs when Column access burst progress Power-Down occurs when accesses progress. Flash only stacked combination, operations equivalent flash operations.
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Device Operations Overview
Table
Current State
LPSDRAM Functional Mode Description: Current State bank Command Bank
D-CS# D-RAS# D-CAS# Command Action Notes
Idle Active Read (without Auto precharge) Write (without Auto precharge)
Operation Operation Active Auto refresh Load Mode register Precharge Read Write Precharge Read Write Prechard Burst Terminate Read Write Precharge Burst Terminate
Continue previous Operation Continue previous Operation Select activate Auto refresh Mode register Select Column start read burst Select Column start write burst Deactivate bank banks) Truncate Read start Read burst Truncate Read start Write burst Truncate Read, start Precharge Burst terminate Truncate Write start Read burst Truncate Write& start Write burst Truncate Write, start Precharge Burst terminate
1,2,4 1,2,4 1,2,3,4 1,2,5 1,2,5 1,2,5 1,2,5
Notes: table applies when both D-CKEn-1 D-CKEn high. states sequences shown illegal reserved. This command bank specific. banks being precharged, they must valid state precharging. command other than Operation (NOP), should issued same bank while Read Write Burst with auto precharge enabled. Read Write command could auto precharge enabled auto precharge disabled.
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Device Operations Overview
Table
Current State
LPSDRAM Functional Mode Description: Current State bank Command Bank
D-CS# D-RAS# D-CAS# Command Action Notes
Idle Activating, Active, Precharging Read with Auto Precharge disabled Write with Auto precharge disabled Read with Auto Precharge Write with Auto precharge
Operation Operation Active Read Write Precharge Active Read Write Precharge Active Read Write Precharge Active Read Write Precharge Active Read Write Precharge
Continue previous Operation Continue previous Operation command allowed bank Activate Start Read burst Start Write burst Precharge Activate Start Read burst Start Write burst Precharge Activate Start Read burst Start Write burst Precharge Activate Start Read burst Start Write burst Precharge Activate Start Read burst Start Write burst Precharge
Notes: table applies when both D-CKEn-1 D-CKEn high. states sequences shown illegal reserved.
Flash Operations
F-CE# F-RST# high enable device read operations. flash device internally decodes upper address inputs determine accessed partition. ADV# opens internal address latches. activates outputs gates selected data onto bus. asynchronous mode, addresses latched when ADV# goes high continuously flows through ADV# held low. synchronous burst-mode, addresses latched first rising edge ADV#, next valid F-CLK edge with ADV# (WE# F-RST# must high, F-CE# must low).
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Device Operations Overview
Table
Mode
Flash Command Cycles
Command Cycles First Cycle Oper Addr1 Data2 Second Cycle Oper Addr1 Data2
Read Array Read Device Identifier Read Query Read Status Register Clear Status Register Word Program Program Buffered Program3 Buffered Enhanced Factory Program (Buffered EFP)4 Erase Suspend Program/Erase Resume Block Locking/ Unlocking Lock Block Unlock Block Lock-down Block Program Protection Register Protection Program Lock Register Configuration Program Read Configuration Register Block Erase Program/Erase Suspend
Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write
0xFF 0x90 0x98 0x70 0x50 0x40/ 0x10 0xE8 0x80 0x20 0xB0 0xD0 0x60 0x60 0x60 0xC0 0xC0 0x60
Read Read Read Write Write Write Write Write Write Write Write Write Write
PBA+IA PnA+QA
0xD0 0xD0 0x01 0xD0 0x2F 0x03
Notes: First command cycle address should same operation's target address. Address within partition. Partition base address. Identification code address offset. Query address offset. Address within block. Word address memory location written. Protection Register address. Lock Register address. valid address within flash. Identifier data. Query data DQ[15:0]. Status Register data. Word data. Word count data loaded into write buffer. Protection Register data. Protection Register data. Lock Register data. Read Configuration Register data A[15:0]. A[MAX:16] select partition. second cycle Buffered Program Command word count data loaded into write buffer. This followed 32-words data.Then confirm command (0xD0) issued, triggering array programming operation. confirm command (0xD0) followed buffer data.
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Device Operations Overview
Table
Mode
Flash Command Definitions
Flash Command Codes Definitions (Sheet
Code Device Mode Description
0xFF Read Array 0x70 Read Status Register Read Device Configuration Register Read Query Clear Status Register
Read
0x90 0x98 0x50
0x40
Word Program Setup
Places addressed partition Read Array mode. Array data output DQ[15:0]. Places addressed partition Read Status Register mode. partition enters this mode after program erase command issued. Status Register data output DQ[7:0]. Places addressed partition Read Device Identifier mode. Subsequent reads from addresses within partition outputs manufacturer/device codes, Configuration Register data, Block Lock status, Protection Register data DQ[15:0]. Places addressed partition Read Query mode. Subsequent reads from partition addresses output Common Flash Interface information DQ[7:0]. only Status Register error bits. Clear Status Register command used clear error bits. First cycle 2-cycle programming command; prepares write operation. next write cycle, address data latched executes programming algorithm addressed location. During program operations, partition responds only Read Status Register Program Suspend commands. F-CE# must toggled update Status Register asynchronous read. F-CE# ADV# must toggled update Status Register Data synchronous Non-array read. Read Array command must issued read array data after programming finished. Equivalent Word Program Setup command, 0x40.
0x10 Write 0xE8 0xD0
Alternate Word Program Setup Buffered Program
0x80
0xD0
0x20
Erase 0xD0
0xB0 Suspend 0xD0
This command loads variable number bytes buffer size 32-words onto program buffer. confirm command Issued after data streaming writing into buffer Buffered Program done. This instructs perform Buffered Program algorithm, writing Confirm data from buffer flash memory array. First cycle 2-cycle command; initiates Buffered Enhanced Factory Program mode Buffered Enhanced (Buffered EFP). then waits Buffered Confirm command, 0xD0, Factory that initiates Buffered algorithm. other commands ignored when Programming Setup Buffered mode begins. Buffered previous command Buffered Setup (0x80), latches address Confirm data, prepares flash Buffered mode. First cycle 2-cycle command; prepares block-erase operation. performs erase algorithm block addressed Erase Confirm Block Erase Setup command. next command Erase Confirm (0xD0) command, sets Status Register bits SR.4 SR.5, places addressed partition read status register mode. first command Block Erase Setup (0x20), latches address data, erases addressed block. During block-erase operations, partition responds only Read Status Register Erase Suspend commands. FBlock Erase Confirm must toggled update Status Register asynchronous read. FCE# ADV# must toggled update Status Register Data synchronous Non-array read. This command issued flash address initiates suspend currentlyexecuting program block erase operation. Status Register indicates successful Program Erase suspend operation setting either SR.2 (program suspended) SR.6 (erase Suspend suspended), along with SR.7 (ready). Write State Machine remains suspend mode regardless control signal states (except F-RST# asserted). This command issued flash address resumes suspended program blockSuspend Resume erase operation.
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Device Operations Overview
Table
Mode
Flash Command Codes Definitions (Sheet
Code Device Mode Description
0x60 Block Locking/ 0x01 Unlocking 0xD0 0x2F Protection 0xC0
0x60 Configuration 0x03
First cycle 2-cycle command; prepares block lock configuration changes. next command Block Lock (0x01), Block Unlock (0xD0), Block Lock Block Setup Lock-Down (0x2F), sets Status Register bits SR.4 SR.5, indicating command sequence error. Lock Block previous command Block Lock Setup (0x60), addressed block locked. previous command Block Lock Setup (0x60), addressed block Unlock Block unlocked. addressed block lock-down state, operation effect. previous command Block Lock Setup (0x60), addressed block locked Lock-Down Block down. First cycle 2-cycle command; prepares flash Protection Register Lock Program Protection Register program operation. second cycle latches register address data, Register Setup starts programming algorithm. First cycle 2-cycle command; prepares flash read configuration. Read Configuration Read Configuration Register command (0x03) next command, Register Setup sets Status Register bits SR.4 SR.5, indicating command sequence error. previous command Read Configuration Register Setup (0x60), Read Configuration latches address writes A[15:0] Read Configuration Register. Following Register Configure Read Configuration Register command, subsequent read operations access array data.
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Device Operations Overview
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Flash Read Operations
Flash Read Operations
flash supports read modes: asynchronous page-mode synchronous burst-mode. Asynchronous page-mode default read mode after flash power-up reset. Read Configuration Register must configured enable synchronous burst reads flash memory array (see Section 10.3, "Flash Read Configuration Register" page 70). perform read operation, F-RST# must deasserted while F-CE# asserted. F-CE# flash-select control. When asserted, enables flash memory. data-output control. When asserted, addressed flash memory data driven onto bus. Section 10.3, "Flash Read Configuration Register" page details available read modes, Section "Special Flash Read States" page details regarding available read states. Automatic Power Savings (APS) feature provides power operation following reads during active mode. After data read from memory array address lines quiescent, automatically places flash into standby. APS, flash current reduced ICCAPS (see Section 6.1, "Flash Current Characteristics" page 37). Each partition flash four read states: Read Array, Read Identifier, Read Status Read Query. Upon power-up, after reset, partitions flash default Read Array. change partition's read state, appropriate read command must written flash (see Section 9.3, "Flash Command Definitions" page 66).
10.1
Flash Asynchronous Page-Mode Read
Following flash power-up reset, asynchronous page-mode default flash read mode partitions Read Array. However, perform array reads after other flash operation (e.g. write operation), Read Array command must issued order read from flash memory array.
Note:
Asynchronous page-mode reads only performed when Read Configuration Register RCR.15 (see Section 10.3, "Flash Read Configuration Register" page 70). perform asynchronous page-mode read, address driven onto A[MAX:MIN], F-CE# ADV# asserted. F-RST# must already have been deasserted. ADV# driven high latch address, must held throughout read cycle. F-CLK used asynchronous page-mode reads, ignored. only asynchronous reads performed, F-CLK should tied valid level, ADV# must tied ground. Flash array data driven onto DQ[15:0] after initial access time tAVQV delay. (see Section 7.2, "Flash Read Specifications" page 42). asynchronous page-mode, four-data words "sensed" simultaneously from flash memory array loaded into internal page buffer. buffer word corresponding initial address A[MAX:MIN] driven onto DQ[15:0] after initial access delay. Address bits A[MAX:MIN+2] select 4-word page. Address bits A[MIN+1:MIN] determine which word 4-word page output from data buffer given time.
Note:
AMIN 16-bit operations while 32-bit operations, AMIN package ballout.
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Flash Read Operations
10.2
Flash Synchronous Burst-Mode Read
Read Configuration register bits RCR[15:0] must before flash synchronous burst operation performed. Synchronous burst mode performed both array non-array reads such Read Read Status Read Query. (See Section 10.3, "Flash Read Configuration Register" page details). Synchronous burst-mode outputs 16-, continuouswords. perform synchronous burst- read, initial address driven onto A[MAX:MIN], F-CE# ADV# asserted. F-RST# must already have been deasserted. ADV# asserted, then deasserted latch address. Alternately, ADV# remain asserted throughout burst access, which case address latched next valid F-CLK edge while ADV# asserted. During synchronous array non-array read modes, first word output from data buffer next valid F-CLK edge after initial access latency delay (see Section 10.3.2, "Flash Latency Count" page 72). Subsequent data output valid F-CLK edges following minimum delay. However, synchronous non-array read, same word data will output successive clock edges until burst length requirements satisfied.
10.2.1
Flash Burst Suspend
Burst Suspend feature flash reduce eliminate initial access latency incurred when system software needs suspend burst sequence that progress order retrieve data from another device same system bus. PXA27x processor resume burst sequence later. Burst suspend provides maximum benefit non-cache systems. Burst accesses suspended during initial access latency (before data received) after flash output data. When burst access suspended, internal array sensing continues previously latched internal data retained. burst sequence suspended resumed without limit long flash operation conditions met. Burst Suspend occurs when F-CE# asserted, current address been latched (either ADV# rising edge valid F-CLK edge), F-CLK halted, deasserted. F-CLK halted when VIL. resume burst access, reasserted, F-CLK restarted. Subsequent F-CLK edges resume burst sequence.
10.3
Flash Read Configuration Register
flash Read Configuration Register (RCR) used select read mode (synchronous asynchronous), defines synchronous burst characteristics flash. modify settings, Configure Read Configuration Register command (see Section 9.2, "Flash Operations" page 64). contents examined using Read Device Identifier command, then reading from <partition base address> 0x05 offset. Section 15.2, "Flash Read Device Identifier" page shown Table page
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Flash Read Operations
Table
Flash Read Configuration Register Description Read Configuration Register (RCR)
Read Mode Latency Count Data Hold Burst F-CLK Edge Burst Wrap Burst Length
LC[2:0]
BL[2:0]
Name
Description
Read Mode (RM) Reserved
Synchronous burst-mode read Asynchronous page-mode read (default) Reserved bits should cleared =Code =Code =Code =Code =Code =Code (default) Other settings reserved. Default active high =Data held 1-clock data cycle =Data held 2-clock data cycle (default) Default active high =Reserved =Linear (default) Falling edge Rising edge (default) Reserved bits should cleared =Wrap; Burst accesses wrap within burst length BL[2:0] Wrap; Burst accesses wrap within burst length (default) =Reserved =8-word burst =16-word burst =Reserved (default) Other settings reserved.
13:11
Latency Count (LC[2:0])
Reserved Data Hold (DH) Reserved Burst Sequence (BS) Clock Edge (CE) Reserved Burst Wrap (BW)
Burst Length (BL[2:0])
10.3.1
Flash Read Mode
flash Read Mode (RM) selects synchronous burst-mode asynchronous page-mode operation flash. When set, asynchronous page-mode selected (default). When cleared, synchronous burst-mode selected.
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Flash Read Operations
10.3.2
Flash Latency Count
Latency Count bits, LC[2:0], tell flash many clock cycles must elapse from rising edge ADV# from first valid clock edge after ADV# asserted) until first data word driven onto DQ[15:0]. input clock frequency used determine this value. Table page shows data output latency different settings LC[2:0]. Refer Table "Flash Frequency Support" page Latency Code Settings example.
Figure
F-CLK
Flash First-Access Latency Count
Address
Valid Address
ADV# Code (Reserved) DATA [D/Q]
Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output
Code (Reserved) DATA [D/Q] Code
Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output
DATA [D/Q]
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Code DATA [D/Q] Code DATA [D/Q] Code DATA [D/Q] Code (Reserved) Code (Reserved) DATA [D/Q]
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
DATA [D/Q]
Valid Output
Valid Output
Valid Output
Table
Flash Frequency Support
Latency Count Settings Frequency Support (MHz)
NOTE: based tAVQV tCHQV
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Flash Read Operations
Figure
Example Flash Latency Count Setting
tDATA
F-CLK F-CE# ADV#
Address Code DATA [D/Q]
Valid Address
High
Valid Output
Valid Output
R103
10.3.3
Flash Burst Sequence
Burst Sequence (BS) selects linear-burst sequence (default). Only linear-burst sequence supported. Table shows synchronous burst sequence burst lengths supported PXA27x processor.
Table
Flash Burst Sequence Word Ordering
Start Addr. Burst Wrap (DEC) (RCR.3) Burst Addressing Sequence (DEC) 8-Word Burst (BL[2:0] 0x010) 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 16-Word Burst (BL[2:0] 0x011) 0-1-2-3-4.14-15 1-2-3-4-5.15-0 2-3-4-5-6.15-0-1 3-4-5-6-7.15-0-1-2 4-5-6-7-8.15-0-1-2-3 5-6-7-8-9.15-0-1-2-3-4 6-7-8-9-10.15-0-1-2-3-4-5 7-8-9-10.15-0-1-2-3-4-5-6 14-15-0-1-2.12-13 15-0-1-2-3.13-14 0-1-2-3-4.14-15 1-2-3-4-5.15-16 2-3-4-5-6.16-17 3-4-5-6-7.17-18 4-5-6-7-8.18-19 5-6-7-8-9.19-20 6-7-8-9-10.20-21 7-8-9-10-11.21-22 14-15-16-17-18.28-29 15-16-17-18-19.29-30
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Flash Read Operations
10.3.4
Flash Clock Edge
Clock Edge (CE) selects either rising (default) falling clock edge F-CLK. This clock edge used start burst cycle, output synchronous data, assert/deassert WAIT.
10.3.5
Flash Burst Wrap
Burst Wrap (BW) determines whether 8-word, 16-word burst length accesses wrap within selected word-length boundaries cross word-length boundaries. When set, burst wrapping does occur (default). When cleared, burst wrapping occurs.
10.3.6
Flash Burst Length
Burst Length (BL[2:0]) selects linear burst length synchronous burst reads flash memory array. burst lengths 8-word 16-word.
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Flash Programming Operations
Flash Programming Operations
flash supports three programming methods: Single-word programming (0x40/0x10), Buffered Programming (0xE8, 0xD0), Buffered Enhanced Factory Programming (Buffered EFP) (0x80, 0xD0). Section 9.3, "Flash Command Definitions" page details various programming commands issued flash. perform write operation, both F-CE# asserted while F-RST# deasserted. During write operation, address data latched rising edge F-CE#, whichever occurs first. Table "Flash Command Cycles" page shows cycle sequence each supported flash commands, while Table "Flash Command Codes Definitions" page describes each command. Section 7.3, "Flash Write Specifications" page signal-timing details. Warning: Write operations with invalid F-VCC and/or F-VPP voltages produce spurious results should attempted. Successful programming requires addressed block unlocked. block locked down, F-WP# must deasserted block must unlocked before attempting program block. Attempting program locked block causes program error (SR.4 SR.1 set) termination operation. Section "Flash Security Modes" page details locking unlocking blocks.
11.1
Flash Word Programming
Word programming operations initiated writing Word Program Setup command flash (see Section 9.2, "Flash Operations" page 64). This followed second write flash with address data programmed. partition accessed during both write cycles outputs Status Register data when read. partition accessed during second cycle (the data cycle) program command sequence location where data written. Figure "Flash Word Program Flowchart" page 113. Programming occur only partition time; other partitions must read state erase suspend. F-VPP must above VPPLK, within specified VPPL value. During programming, flash Write State Machine (WSM) executes sequence internallytimed events that program desired data bits addressed location, verifies that bits sufficiently programmed. Programming flash memory array changes "ones" "zeros." Flash array bits that zeros changed ones only erasing block. Section "Flash Erase Operations" page flash Status Register examined programming progress errors reading address within partition that being programmed. partition remains Read Status Register state until another command written that partition. Issuing Read Status Register command another partition address sets that partition Read Status Register state, allowing programming progress monitored that partition's address.
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Flash Programming Operations
Status Register SR.7 indicates programming status while sequence executes. Commands that issued programming partition during programming Program Suspend, Read Status Register, Read Device Identifier, Query, Read Array (this returns unknown data). When programming finished, SR.4 (when set) indicates programming failure. SR.3 set, could perform word programming operation because F-VPP outside acceptable limits. SR.1 set, word programming operation attempted program locked block, causing operation abort. Before issuing command, Status Register contents should examined then cleared using Clear Status Register command. valid command follow, when word programming completed.
11.1.1
Flash Factory Word Programming
Factory word programming similar word programming that uses same commands programming algorithms. However, factory word programming enhances programming performance with F-VPP VPPH. This enable faster programming times during factory manufacturing processes. Factory word programming intended extended use. Section 5.2, "Operating Conditions" page limitations when F-VPP VPPH.
Note:
When F-VPP VPPL, flash draws programming current from F-VCC supply. F-VPP driven logic signal, VPPL must remain above VPPL program flash. When F-VPP VPPH, flash draws programming current from F-VPP supply. Figure "Example F-VPP Supply Connections" page shows examples flash power supply configurations.
11.2
Flash Buffered Programming
flash features 32-word buffer enable optimum programming performance. Buffered Programming, data first written on-chip write buffer. Then buffer data programmed into flash memory array buffer-size increments. This improve system programming performance significantly over non-buffered programming. When Buffered Programming Setup command issued. Section 9.3, "Flash Command Definitions" page Status Register information updated reflects availability write buffer. SR.7 indicates buffer availability: set, buffer available; cleared, write buffer available. retry, issue Buffered Programming Setup command again, recheck SR.7. When SR.7 set, buffer ready loading. Figure "Flash Buffer Program Flowchart" page 115. next write, word count written flash buffer address. This tells flash many data words will written buffer, maximum size buffer. next write, flash start address given along with first data written flash memory array. Subsequent writes provide additional flash addresses data. data addresses must within start address plus word count. Optimum programming performance lower power usage obtained aligning starting address beginning 32-word boundary (A[4:0] 0x00). Crossing 32-word boundary during programming will result doubling total programming time refilling buffer region.
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Flash Programming Operations
After last data written buffer, Buffered Programming Confirm command must issued original block address. begins program buffer contents flash memory array. command other than Buffered Programming Confirm command written flash, command sequence error occurs SR[7,5,4] set. error occurs while writing array, flash stops programming, SR[7,4] set, indicating programming failure. Reading from another partition allowed while data being programmed into array from write buffer. Section "Flash Dual-Operation Considerations" page When Buffered Programming completed, additional buffer writes initiated issuing another Buffered Programming Setup command repeating buffered program sequence. Buffered programming performed with F-VPP VPPL F-VPP VPPH. Section 5.2, "Operating Conditions" page limitations when operating flash with F-VPP VPPH. attempt made program past erase-block boundary using Buffered Program command, flash aborts operation. This generates command sequence error, SR[5,4] set. Buffered programming attempted while F-VPP VPPLK, SR[4,3] set. errors detected that have Status Register bits, Status Register should cleared using Clear Status Register command.
11.3
Flash Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (Buffered EFP) design speed flash programming today's beat-rate-sensitive manufacturing environments. enhanced programming algorithm used Buffered eliminates traditional programming elements that drive overhead flash programmer systems. Buffered consists three phases: Setup, Program/Verify, Exit. Figure "Flash Buffered Flowchart" page 116. uses write buffer spread program performance across 32-words. Verification occurs same phase programming accurately program flash memory cell correct state. single two-cycle command sequence programs entire block data. This enhancement eliminates three write cycles buffer: commands word count each 32-words. Host programmer cycles fill flash write buffer followed status check. SR.0 indicates when data from buffer been programmed into sequential flash memory array locations. Following buffer-to-flash array programming sequence, Write State Machine (WSM) increments internal addressing automatically select next 32-word array boundary. This aspect Buffered saves host programming equipment address-bus setup overhead. With adequate continuity testing, programming equipment rely WSM's internal verification ensure that flash programmed properly. This eliminates external postprogram verification associated overhead.
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Flash Programming Operations
11.3.1
Flash Buffered Requirements Considerations
Buffered requirements:
Case temperature: F-VCC within specified operating range. F-VPP driven VPPH. Target block unlocked before issuing Buffered Setup Confirm commands. first-word address (WA0) block programmed must held constant from setup phase through data streaming into target block, until transition exit phase desired.
must align with start array buffer boundary1.
Buffered considerations:
optimum performance, cycling must limited below erase cycles block2. Buffered programs block time; buffer data must fall within single block3. Buffered cannot suspended. Programming flash memory array occur only when buffer full4. Read operation while performing Buffered supported.
Notes: Word buffer boundaries array determined A[4:0] (0x00 through 0x1F). alignment start point A[4:0] 0x00. Some degradation performance occur this limit exceeded, flash will continue work properly. internal address counter increments beyond block's maximum address, addressing wraps around beginning block. number words less than remaining locations must filled with 0xFFFF.
11.3.2
Flash Buffered Setup Phase
After receiving Buffered Setup Confirm command sequence, SR.7 (Ready) cleared, indicating that busy with Buffered algorithm startup. delay before checking SR.7 required allow enough time perform setups checks (BlockLock status, F-VPP level, etc.). error detected, SR.4 Buffered operation terminates. block found locked, SR.1 also set. SR.3 error occurred incorrect F-VPP level.
Note:
Reading from flash after Buffered Setup Confirm command sequence outputs Status Register data. issue Read Status Register command; will interpreted data loaded into buffer.
11.3.3
Flash Buffered Program/Verify Phase
After Buffered Setup Phase completed, host programming system must check SR[7,0] determine availability write buffer data streaming. SR.7 cleared indicates flash busy Buffered program/verify phase activated. SR.0 indicates write buffer available.
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Flash Programming Operations
basic sequences repeat this phase: loading write buffer, followed buffer data programming array. Buffered EFP, count value buffer loading always maximum buffer size 32-words. During buffer-loading sequence, data stored sequential buffer locations starting address 0x00. Programming buffer contents flash memory array starts soon buffer full. number words less than remaining buffer locations must filled with 0xFFFF. Caution: buffer must completely filled programming occur. Supplying address outside current block's range during buffer-fill sequence causes algorithm exit immediately. data previously loaded into buffer during fill cycle programmed into array. starting address data entry must buffer size aligned, Buffered algorithm will aborted program fail (SR.4) flag will set. Data words from write buffer directed sequential memory locations flash memory array; programming continues from where previous buffer sequence ended. host programming system must poll SR.0 determine when buffer program sequence completes. SR.0 cleared indicates that buffer data been transferred flash array; SR.0 indicates that buffer available next fill cycle. host system check full status errors time, only necessary block basis after Buffered exit. After buffer fill cycle, write cycles should issued flash until SR.0 flash ready next buffer fill. Note: spurious writes ignored after buffer fill operation when internal program proceeding. host programming system continues Buffered algorithm providing next group data words written buffer. Alternatively, terminate this phase changing block address outside current block's range. Program/Verify phase concludes when programmer writes different block address; data supplied must 0xFFFF. Upon Program/Verify phase completion, flash enters Buffered Exit phase.
11.3.4
Flash Buffered Exit Phase
When SR.7 set, flash returned normal operating conditions. full status check should performed partition being programmed this time ensure entire block programmed successfully. When exiting Buffered algorithm with block address change, read mode both programmed addressed partition will change. After Buffered exit, valid command issued flash.
11.4
Flash Program Suspend
Issuing Program Suspend command while programming suspends programming operation. This allows data accessed from memory locations other than being programmed. Program Suspend command issued flash address; corresponding partition affected. program operation suspended perform reads only. Additionally, program operation that running during erase suspend suspended perform read operation. Figure "Flash Program Suspend/Resume Flowchart" page 114.
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Flash Programming Operations
When programming operation executing, issuing Program Suspend command requests suspend programming algorithm predetermined points. partition that suspended continues output after Program Suspend command issued. Programming suspended when SR[7,2] set. Suspend latency specified Section 7.4, "Flash Program Erase Characteristics" page read data from blocks within suspended partition, Read Array command must issued that partition. Read Array, Read Status Register, Read Device Identifier, Query, Program Resume valid commands during program suspend. program operation does need suspended order read data from block another partition that programming. other partition already Read Array, Read Device Identifier, Query state, issuing valid address returns corresponding read data. other partition read mode, read commands must issued partition before data read. During program suspend, deasserting F-CE# places flash standby, reducing active current. F-VPP must remain programming level, F-WP# must remain unchanged while program suspend. F-RST# asserted, flash reset.
11.5
Flash Program Resume
Resume command instructs flash continue programming, automatically clears Status Register bits SR[7,2]. This command written partition. When read partition that's programming, flash outputs data corresponding partition's last state. error bits set, Status Register should cleared before issuing next instruction. F-RST# must remain deasserted. Figure "Flash Program Suspend/Resume Flowchart" page 114.
11.6
Flash Program Protection
When F-VPP VIL, absolute hardware write protection provided flash blocks. F-VPP below VPPLK, programming operations halt SR.3 indicating F-VPP-level error. Block lock registers affected voltage level F-VPP; they still programmed read, even F-VPP VPPLK.
Figure
Example F-VPP Supply Connections
F-VCC F-VPP
F-VCC F-VPP
F-VCC Prot# (logic signal)
F-VCC F-VPP
F-VPPH fast programming Absolute write protection with F-VPP VPPLK F-VCC (Note F-VPP F-VPP
F-VPPL in-system programming Absolute write protection logic signal
F-VCC
F-VCC
F-VCC F-VPP
F-VPPL in-system programming F-VPPH fast factory programming
F-VPPL in-system programming
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Flash Erase Operations
Flash Erase Operations
Flash erasing performed individual block basis. entire block erased each time erase command sequence issued, only block erased time. When block erased, bits within that block read logical ones. following sections describe block erase operations detail.
12.1
Flash Block Erase
Block erase operations initiated writing Block Erase Setup command address target block erased. Section 9.3, "Flash Command Definitions" page Next, Block Erase Confirm command written address block erased. Erasing occur only partition time; other partitions must read state. flash placed standby (F-CE# deasserted) during erase operation, flash continues complete erase operation before entering standby.
Note:
F-VPP VPPLK block must unlocked (see Figure "Flash Block Erase Flowchart" page 117). During block erase, flash Write State Machine (WSM) executes sequence internallytimed events that conditions, erases, verifies bits within block. Erasing flash memory array changes "logical-zeros" "logical-ones." Memory array bits changed zeros only programming block (see Section "Flash Programming Operations" page 75). Status Register examined block erase progress errors reading address within partition that being erased. partition remains Read Status Register state until another command written that partition. Issuing Read Status Register command another partition address sets that partition Read Status Register state, allowing erase progress monitored that partition's address. SR.0 indicates whether addressed partition another partition erasing. partition's Status Register SR.7 upon erase completion. SR.7 indicates block erase status while sequence executes. When erase operation finished, Status Register SR.5 indicates erase failure set. SR.3 would indicate that could perform erase operation because F-VPP outside acceptable limits. SR.1 indicates that erase operation attempted erase locked block, causing operation abort. Before issuing command, Status Register contents should examined then cleared using Clear Status Register command. valid command follow once block erase operation completed.
12.2
Flash Erase Suspend
Issuing Erase Suspend command while erasing suspends block erase operation. This allows data accessed from memory locations other than being erased. Erase Suspend command issued flash address; corresponding partition affected. block
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Flash Erase Operations
erase operation suspended perform word buffer program operation, read operation within block except block that erase suspended. Figure "Flash Program Suspend/Resume Flowchart" page 114. When block erase operation executing, issuing Erase Suspend command requests suspend erase algorithm predetermined points. partition that suspended continues output after Erase Suspend command issued. Block erase suspended when SR[7,6] set. Suspend latency specified Section 7.4, "Flash Program Erase Characteristics" page During Erase Suspend, Program command issued block other than erasesuspended block. Block erase cannot resume until program operations initiated during erase suspend complete. Read Array, Read Status Register, Read Device Identifier, Query, Erase Resume valid commands during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Block Lock, Block Unlock, Block Lock-Down valid commands during Erase Suspend. During erase suspend, deasserting F-CE# places flash standby, reducing active current. F-VPP must remain valid level, F-WP# must remain unchanged while erase suspend. F-RST# asserted, flash reset.
12.3
Flash Erase Resume
Erase Resume command instructs flash continue erasing, automatically clears status register bits SR[7,6]. This command written partition. When read partition that's erasing, flash outputs data corresponding partition's last state. status register error bits set, Status Register should cleared before issuing next instruction. F-RST# must remain deasserted (see Figure "Flash Program Suspend/Resume Flowchart" page 114).
12.4
Flash Erase Protection
When F-VPP VIL, absolute hardware erase protection provided flash blocks. F-VPP VPPLK, erase operations halt SR.3 indicating F-VPP level error.
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Flash Security Modes
Flash Security Modes
flash features security modes used protect code data information stored flash memory array. following sections describe each security mode detail.
13.1
Flash Block Locking
Individual instant block locking used protect user code and/or data within flash memory array. blocks power locked state protect array data from being altered during power transitions. block locked unlocked with latency. Locked blocks cannot programmed erased; they only read. Software-controlled security implemented using Block Lock Block Unlock commands. Hardware-controlled security implemented using Block Lock-Down command along with asserting F-WP#.
13.1.1
Flash Lock Block
lock block, issue Lock Block Setup command. next command must Lock Block command issued desired block's address (see Section 9.3, "Flash Command Definitions" page Figure "Flash Block Lock Operations Flowchart" page 119). Read Configuration Register command issued after Block Lock Setup command, flash configures instead. Block lock unlock operations affected voltage level F-VPP. block lock bits modified and/or read even F-VPP VPPLK.
13.1.2
Flash Unlock Block
Unlock Block command used unlock blocks (see Section 9.3, "Flash Command Definitions" page 66). Unlocked blocks read, programmed, erased. Unlocked blocks return locked state when flash reset powered down. block lock-down state, must deasserted before unlocked (see Figure "Flash Block Locking State Diagram" page 84).
13.1.3
Flash Lock-Down Block
locked unlocked block locked-down writing Lock-Down Block command sequence (see Section 9.3, "Flash Command Definitions" page 66). Blocks lock-down state cannot programmed erased; they only read. However, unlike locked blocks, their locked state cannot changed software commands alone. locked-down block only unlocked issuing Unlock Block command with F-WP# deasserted. return unlocked block locked-down state, Lock-Down command must issued prior changing F-WP# VIL. Locked-down blocks revert locked state upon reset power flash (see Figure "Flash Block Locking State Diagram" page 84).
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Flash Security Modes
13.1.4
Flash Block Lock Status
Read Device Identifier command used determine block's lock status (see Section 15.2, "Flash Read Device Identifier" page 95). Data bits DQ[1:0] display addressed block's lock status; addressed block's lock bit, while addressed block's lock-down bit.
Figure
Flash Block Locking State Diagram
Power-Up/Reset
Locked [X01]
LockedDown4,5 [011]
Hardware Locked5 [011]
F-WP# Hardware Control
Unlocked [X00]
Software Locked [111]
Unlocked [110]
Software Block Lock (0x60/0x01) Software Block Unlock (0x60/0xD0) Software Block Lock-Down (0x60/0x2F) F-WP# hardware control
Notes:
[a,b,c] represents [F-WP#, D0]. Don't Care. indicates block Lock-down status. `0', Lock-down been issued this block. `1', Lock-down been issued this block. indicates block lock status. `0', block unlocked. `1', block locked. Locked-down Hardware Software locked. [011] states should tracked system software determine difference between Hardware Locked Locked-Down states.
13.1.5
Flash Block Locking During Suspend
Block lock unlock changes performed during erase suspend. change block locking during erase operation, first issue Erase Suspend command. Monitor Status Register until SR.7 SR.6 set, indicating flash suspended ready accept another command. Next, write desired lock command sequence block, which changes lock state that block. After completing block lock unlock operations, resume erase operation using Erase Resume command.
Note:
Lock Block Setup command followed command other than Lock Block, Unlock Block, Lock-Down Block produces command sequence error Status Register bits SR.4 SR.5. command sequence error occurs during erase suspend, SR.4 SR.5 remains set, even after erase operation resumed. Unless Status Register cleared using Clear Status Register command before resuming erase operation, possible erase errors masked command sequence error. block locked locked-down during erase suspend same block, lock status bits change immediately. However, erase operation completes when resumed. Block lock operations cannot occur during program suspend.
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Flash Security Modes
13.2
Flash One-Time Programmable Protection Registers
flash contains seventeen Protection Registers (PRs) that used implement system security measures and/or flash identification. Each Protection Register individually locked. first 128-bit Protection Register (PR0) comprised 64-bit (8-word) segments. lower 64-bit segment pre-programmed factory with unique 64-bit number. remaining 64-bit segment, well other sixteen 128-bit Protection Registers, blank default. Users program these registers needed. When programmed, users then lock Protection Register(s) prevent additional programming. Figure "Flash One-Time Programmable Protection Register Map" page user-programmable Protection Registers contain one-time programmable (OTP) bits; when programmed, register bits cannot erased. Each Protection Register accessed multiple times program individual bits, long register remains unlocked. Each Protection Register associated Lock Register bit. When Lock Register programmed, associated Protection Register only read; longer programmed. Additionally, because Lock Register bits themselves OTP, when programmed, Lock Register bits cannot erased. Therefore, when Protection Register locked, cannot unlocked
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Flash Security Modes
Figure
Flash One-Time Programmable Protection Register
0x109 128-bit Protection Register (User-Programmable) 0x102
0x91 128-bit Protection Register (User-Programmable) 0x8A Lock Register 0x89
0x88 64-bit Segment (User-Programmable) 0x85 0x84 0x81 Lock Register 0x80
128-Bit Protection Register 64-bit Segment (Factory-Programmed)
13.2.1
Flash Reading Protection Registers
Protection Registers read from within partition's address space. read Protection Register, first issue Read flash Identifier command partitions' address place that partition Read Device Identifier state (see Section 9.3, "Flash Command Definitions" page 66). Next, perform read operation that partition's base address plus address offset corresponding register read. Table "Flash Identifier Information" page shows address offsets Protection Registers Lock Registers. Register data read bits time.
Note:
program erase operation occurs within flash while reading Protection Register, certain restrictions apply. Table "Simultaneous Flash Operation Restrictions" page details.
Intel® PXA27x Processor Family Memory Subsystem
Part Flash Device Operations Flash Security Modes
13.2.2
Flash Programming Protection Registers
program Protection Registers, first issue Program Protection Register command parameter partition's base address plus offset desired Protection Register (see Section 9.3, "Flash Command Definitions" page 66). Next, write desired Protection Register data same Protection Register address (see Figure "Flash One-Time Programmable Protection Register Map" page 86). flash programs 64-bit 128-bit user-programmable Protection Register data bits time (see Figure "Flash One-Time Programmable Protection Register Programming Flowchart" page 120). Issuing Program Protection Register command outside Protection Register's address space causes program error (SR.4 set). Attempting program locked Protection Register causes program error (SR.4 set) lock error (SR.1 set).
Note:
program erase operation occurs when programming Protection Register, certain restrictions apply. Table "Simultaneous Flash Operation Restrictions" p
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