28F320W18, 28F640W18, 28F128W18 High Performance Read-While-Write

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28F320W18, 28F640W18, 28F128W18 High Performance Read-While-Write

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Intel® Wireless Flash Memory (W18)
28F320W18, 28F640W18, 28F128W18
High Performance Read-While-Write/ Erase Burst frequency (zero wait states) Initial access read speed Burst mode read speed Page mode read speed 16-, Continuous-Word Burst mode reads Burst Page mode reads Blocks, across partition boundaries Burst Suspend feature Enhanced Factory Programming µs/word Security 128-bit Protection Register: unique pre-programmed bits user-programmable bits Absolute Write Protection with ground Individual Instantaneous Block Locking/Unlocking with Lock-Down Capability Quality Reliability Temperature Range: 100K Erase Cycles Block ETOXIX Process ETOXVIII Process
Architecture Multiple 4-Mbit partitions Dual Operation: Parameter block size 4-Kword Main block size 32-Kword bottom parameter devices 16-bit wide data Software (typ.) Program Erase Suspend latency time Flash Data Integrator (FDI) Common Flash Interface (CFI) Compatible Programmable WAIT signal polarity Packaging Power 64-Mbit 32-, 64-, 128-Mbit BGA; 128-Mbit QUAD+ package Active Ball Matrix, 0.75 BallPitch 1.70 1.95 VCCQ 1.70 1.95 VCCQ (130 1.70 2.24 1.35 1.80 VCCQ (130 1.35 2.24 Standby current (130 nm): (typ.) Read current: (4-word burst, typ.)
Intel® Wireless Flash Memory (W18) device with flexible multi-partition dual-operation architecture, provides high-performance Asynchronous Synchronous Burst reads. ideal memory low-voltage burst CPUs. Combining high read performance with flash memory intrinsic non-volatility, device eliminates traditional system-performance paradigm shadowing redundant code memory from slow nonvolatile storage faster execution memory. reduces total memory requirement that increases reliability reduces overall system power consumption cost. device's flexible multi-partition architecture allows program erase occur partition while reading from another partition. This allows higher data write throughput compared single-partition architectures designers choose code data partition sizes. dual-operation architecture allows processors interleave code operations while program erase operations take place background.
Order Number: 290701, Revision: January 2005
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January 2005
Intel® Wireless Flash Memory (W18) Order Number: 290701, Revision:
Intel® Wireless Flash Memory (W18)
Contents
Introduction
Nomenclature Conventions.9 Memory Partitioning Lithography Lithography Signal Ballout.18 Signal Descriptions Absolute Maximum Ratings Operating Conditions Current Characteristics Voltage Characteristics.28 Write Characteristics Erase Program Times.47 Reset Specifications Test Conditions Device Capacitance.50 Active Power.51 Automatic Power Savings (APS) Standby Power Power-Up/Down Characteristics.51 8.4.1 System Reset RST# 8.4.2 VCC, VPP, RST# Transitions Power Supply Decoupling.52 Operations 9.1.1 Reads 9.1.2 Writes.54 9.1.3 Output Disable 9.1.4 Burst Suspend 9.1.5 Standby.55 9.1.6 Reset
Functional Overview Package Information
Ballout Signal Descriptions.18
Maximum Ratings Operating Conditions
Electrical Specifications
Characteristics
Power Reset Specifications
Operations Overview
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Intel® Wireless Flash Memory (W18)
10.1 10.2 10.3 10.4 10.5 10.6 10.7 11.1 11.2 11.3
Device Commands Command Sequencing Asynchronous Page Read Mode Synchronous Burst Read Mode. Read Array. Read Identifier Query Read Status Register. Clear Status Register. Word Program Factory Programming Enhanced Factory Program (EFP) 11.3.1 Requirements Considerations 11.3.2 Setup 11.3.3 Program 11.3.4 Verify. 11.3.5 Exit.
10.0 Read Operations
11.0 Program Operations
12.0 Program Erase Operations
12.1 12.2 12.3 13.1 Program/Erase Suspend Resume Block Erase. Read-While-Write Read-While-Erase Block Lock Operations. 13.1.1 Lock 13.1.2 Unlock. 13.1.3 Lock-Down. 13.1.4 Block Lock Status 13.1.5 Lock During Erase Suspend 13.1.6 Status Register Error Checking 13.1.7 Lock-Down Control Protection Register 13.2.1 Reading Protection Register. 13.2.2 Programing Protection Register. 13.2.3 Locking Protection Register. Protection Read Mode (RCR[15]) First Access Latency Count (RCR[13:11]). 14.2.1 Latency Count Settings. WAIT Signal Polarity (RCR[10]). WAIT Signal Function Data Hold (RCR[9]). WAIT Delay (RCR[8]) Burst Sequence (RCR[7])
13.0 Security Modes.
13.2
13.3 14.1 14.2 14.3 14.4 14.5 14.6 14.7
14.0 Read Configuration Register
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Intel® Wireless Flash Memory (W18) Order Number: 290701, Revision:
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14.8 Clock Edge (RCR[6]) 14.9 Burst Wrap (RCR[3]).92 14.10 Burst Length (RCR[2:0])
Appendix Appendix Appendix
Write State Machine States.93 Common Flash Interface (CFI) Ordering Information.
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Intel® Wireless Flash Memory (W18)
Revision History
Date 09/13/00 Revision -001 Initial Release Deleted 16-Mbit density Revised ADV#, Section Revised Protection Registers, Section 4.16 Revised Program Protection Register, Section 4.18 Revised Example First Access Latency Count, Section 5.0.2 Revised Figure Data Output with Setting Code Added WAIT Signal Function, Section 5.0.3 Revised WAIT Signal Polarity, Section 5.0.4 Revised Data Output Configuration, Section 5.0.5 Added Figure Data Output Configuration with WAIT Signal Delay Revised WAIT Delay Configuration, Section 5.0.6 Changed VCCQ Spec from 1.95 2.24 Section 8.2, Extended Temperature Operation 01/29/01 -002 Changed ICCS Spec from Section 8.4, Characteristics Changed ICCR Spec from (CLK MHz, burst length (CLK MHz, burst length respectively Section 8.4, Characteristics Changed ICCWS Spec from Section 8.4, Characteristics Changed ICCES Spec from Section 8.4, Characteristics Changed tCHQX Spec from Section 8.6, Read Characteristics Added Figure WAIT Signal Synchronous Non-Read Array Operation Waveform Added Figure WAIT Signal Asynchronous Page Mode Read Operation Waveform Added Figure WAIT Signal Asynchronous Single Word Read Operation Waveform Revised Appendix Ordering Information Revised entire Section 4.10, Enhanced Factory Program Command (EFP) Figure Enhanced Factory Program Flowchart Revised Section 4.13, Protection Register Revised Section 4.15, Program Protection Register Revised Section 7.3, Capacitance, include 128-Mbit specs 06/12/01 -003 Revised Section 7.4, Characteristics, include 128-Mbit specs Revised Section 7.6, Read Characteristics, include 128-Mbit device specifications Added tVHGL Spec Section 7.6, Read Characteristics Revised Section 7.7, Write Characteristics, include 128-Mbit device specifications Minor text edits Description
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Intel® Wireless Flash Memory (W18) Order Number: 290701, Revision:
Intel® Wireless Flash Memory (W18)
Date
Revision Sections Organization Added 16-Word Burst Feature Added Burst Suspend Section Revised Block Locking State Diagram Revised Active Power Section Revised Automatic Power Savings Section
Description
Revised Power-Up/Down Operation Section 04/05/02 -004 Revised Extended Temperature Operation Added Characteristics Table Added Read Characteristics Revised Table Test Configuration Component Values Worst Case Speed Conditions Added 0.13 Product Read Characteristics Revised Write Characteristics Added Read Write Write Read Transition Waveforms Revised Reset Specifications Various text edits Various text edits 10/10/02 -005 Updated Latency Count Section, including adding Latency Count Tables Added section WAIT Function WAIT Summary Table Updated Package Drawing Dimensions 11/12/02 01/14/03 -006 -007 Various text clarifications Removed Intel Burst Order Revised Table Current Characteristics" Various text edits Revised Table Read Operations, tAPA 03/21/03 -008 Added note table Configuration Register Descriptions Added note section 3.1.1, Read Updated Block-Lock Operations (Section Figure Updated Table (128 ICCR) 12/17/03 -009 Updated Table (WAIT behavior) Added QUAD+ ballout, package mechanicals, order information Various text edits including latest product-naming convention Added product line 02/12/04 -010 Removed µBGA* package Added Page- Burst-Mode descriptions Minor text edits Fixed omitted text Table note regarding voltage pins 05/06/04 06/03/04 -011 -012 Removed Extended Supply Voltage products Minor text edits Updated title layout datasheet VCCQ Max. changed products 06/29/04 -013 Updated "Absolute Maximum Ratings" table Typical ICCS updated Updated subtitle 01/21/05 -014 Typical ICCS updated Minor text edits
Intel® Wireless Flash Memory (W18) Order Number: 290701, Revision:
January 2005
Intel® Wireless Flash Memory (W18)
January 2005
Intel® Wireless Flash Memory (W18) Order Number: 290701, Revision:
Intel® Wireless Flash Memory (W18)
Introduction
This datasheet contains information about Intel® Wireless Flash Memory (W18) device family. This section describes nomenclature used datasheet. Section provides overview flash memory device. Section 6.0, Section 7.0, Section describe electrical specifications extended temperature product offerings. Ordering information found Appendix
Nomenclature
Acronyms that describe product features usage defined here:
SCSP Automatic Power Savings Block Base Address Common Flash Interface Command User Interface Don't Enhanced Factory Programming Flash Data Integrator Connect One-Time Programmable Partition Base Address Read Configuration Register Read-While-Erase Read-While-Write Stacked Chip Scale Package Status Register Data Very-thin, Fine-pitch, Ball Grid Array Write State Machine
Conventions
following list describes abbreviated terms phrases used throughout this document:
"1.8 signal Refers full voltage range 1.95 (except where noted) "VPP refers ±5%. Refers registers means logical cleared means logical Often used interchangeably refer external signal connections package (ball term used BGA).
Intel® Wireless Flash Memory (W18) Order Number: 290701, Revision:
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Intel® Wireless Flash Memory (W18)
Word Signal Voltage
bytes bits. Names CAPS (see Section 4.2, "Signal Descriptions" page 20.) Applied signal subscripted example VPP.
Throughout this document, references made top, bottom, parameter, partition. clarify these references, following conventions have been adopted:
Block Main block Parameter block Block Base Address (BBA) Partition Partition Base Address (PBA) partition Bottom partition Main partition Parameter partition parameter device (TPD) Bottom parameter device (BPD) group bits words) that erase simultaneously with block erase instruction. Contains 32-Kwords. Contains 4-Kwords. first address block. group blocks that share erase program circuitry common Status Register. first address partition. example, 32-Mbit top-parameter device partition number 0x140000. Located highest physical device address. This partition main partition parameter partition. Located lowest physical device address. This partition main partition parameter partition. Contains only main blocks. Contains mixture main blocks parameter blocks. parameter partition memory with parameter blocks that partition. This formerly referred Top-Boot device. parameter partition bottom memory with parameter blocks bottom that partition. This formerly referred Bottom-Boot Block flash device.
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Intel® Wireless Flash Memory (W18)
Functional Overview
This section provides overview device features architecture. device provides Read-While-Write (RWW) Read-White-Erase (RWE) capability with high-performance synchronous asynchronous reads package-compatible densities with 16-bit data bus. Individually-erasable memory blocks optimally sized code data storage. Eight 4-Kword parameter blocks located parameter partition either bottom memory map. rest memory array grouped into 32-Kword main blocks. memory architecture device consists multiple 4-Mbit partitions, exact number depending device density. dividing memory array into partitions, program erase operations take place simultaneously during read operations. Burst reads traverse partition boundaries, user application code responsible ensuring that they don't extend into partition that actively programming erasing. Although each partition burst-read, write, erase capabilities, simultaneous operation limited write erase partition while other partitions read mode. Augmented erase-suspend functionality further enhances capabilities this device. erase suspended perform program read operation within block, except that which erase-suspended. program operation nested within suspended erase subsequently suspended read another memory location. After device power-up reset, device defaults asynchronous page-mode read configuration. Writing device's Read Configuration Register (RCR) enables synchronous burst-mode read operation. synchronous mode, input increments internal burst address generator. also synchronizes flash memory with host outputs data every, every other, valid cycle after initial latency. programmable WAIT output signals when data from flash memory device ready. addition improved architecture interface, device incorporates Enhanced Factory Programming (EFP), feature that enables fast programming low-power designs. feature provides fastest currently-available program performance, which increase factory's manufacturing throughput. device supports read operations erase program operations With option, tied together simple, ultra-low-power design. addition voltage flexibility, dedicated input provides complete data protection when VPPLK. This device (130 allows operation voltages lower than minimum VCCQ This Extended VCCQ range, 1.35 permits even greater system design flexibility. 128-bit protection register enhances user's ability implement security techniques data protection schemes. Unique flash device identification fraud-, cloning-, contentprotection schemes possible through combination factory-programmed user-OTP data cells. Zero-latency locking/unlocking memory block provides instant complete protection critical system code data. additional block lock-down capability provides hardware protection where software commands alone cannot change block's protection status.
Intel® Wireless Flash Memory (W18) Order Number: 290701, Revision:
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Intel® Wireless Flash Memory (W18)
Command User Interface (CUI) system processor's link internal flash memory operation. valid command sequence written initiates device Write State Machine (WSM) operation that automatically executes algorithms, timings, verifications necessary manage flash memory program erase. internal Status Register provides ready/busy indication results operation (success, fail, on). Three power-saving features- Automatic Power Savings (APS), standby, RST# significantly reduce power consumption. device automatically enters mode following read cycle completion. Standby mode begins when system deselects flash memory de-asserting CE#. Driving RST# produces power savings similar standby mode. also resets part read-array mode (important system-level reset), clears internal Status Registers, provides additional level flash write protection.
Memory Partitioning
device divided into 4-Mbit physical partitions, which allows simultaneous operations allows users segment code data areas 4-Mbit boundaries. device's memory array asymmetrically blocked, which enables system code data integration within single flash device. Each block erased independently block erase mode. Simultaneous program erase operations allowed; only partition time actively programming erasing. Table "Bottom Parameter Memory Map" page Table "Top Parameter Memory Map" page 32-Mbit device eight partitions, 64-Mbit device partitions, 128-Mbit device partitions. Each device density contains parameter partition several main partitions. 4-Mbit parameter partition contains eight 4-Kword parameter blocks seven 32Kword main blocks. Each 4-Mbit main partition contains eight 32-Kword blocks each. bulk array divided into main blocks that store code data, parameter blocks that allow storage frequently updated small parameters that normally stored EEPROM. using software techniques, word-rewrite functionality EEPROMs emulated.
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Table
Size (KW) Sixteen Partitions
Bottom Parameter Memory
32-Mbit 64-Mbit 128-Mbit 7F8000-7FFFFF 400000-407FFF 3F8000-3FFFFF 200000-207FFF 1F8000-1FFFFF 100000-107FFF 0F8000-0FFFFF 0C0000-0C7FFF 0B8000-0BFFFF 080000-087FFF 078000-07FFFF 040000-047FFF 038000-03FFFF 008000-00FFFF 007000-007FFF 000000-000FFF
Eight Partitions
3F8000-3FFFFF
200000-207FFF
Four Partitions
1F8000-1FFFFF
1F8000-1FFFFF 100000-107FFF 0F8000-0FFFFF 0C0000-0C7FFF 0B8000-0BFFFF 080000-087FFF 078000-07FFFF 040000-047FFF 038000-03FFFF 008000-00FFFF 007000-007FFF 000000-000FFF
Main Partitions
100000-107FFF
Partition
0F8000-0FFFFF
0C0000-0C7FFF
Partition
0B8000-0BFFFF 080000-087FFF 078000-07FFFF 040000-047FFF 038000-03FFFF 008000-00FFFF 007000-007FFF 000000-000FFF
Partition
Parameter Partition
Partition
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Intel® Wireless Flash Memory (W18)
Table
Size (KW) Parameter Partition
Parameter Memory
32-Mbit 1FF000-1FFFFF 64-Mbit 3FF000-3FFFFF 128-Mbit 7FF000-7FFFFF 7F8000-7F8FFF 7F0000-7F7FFF 7C0000-7C7FFF 7B8000-7BFFFF 780000-787FFF 778000-77FFFF 740000-747FFF 738000-73FFFF 700000-707FFF 6F8000-6FFFFF 600000-607FFF 5F8000-5FFFFF 400000-407FFF 3F8000-3FFFFF 000000-007FFF
Partition
1F8000-1F8FFF 1F0000-1F7FFF
3F8000-3F8FFF 3F0000-3F7FFF
1C0000-1C7FFF
3C0000-3C7FFF
Partition
1B8000-1BFFFF
3B8000-3BFFFF 380000-387FFF 378000-37FFFF 340000-347FFF 338000-33FFFF 300000-307FFF 2F8000-2FFFFF 200000-207FFF 1F8000-1FFFFF 000000-007FFF
18000-187FFF
Partition
178000-17FFFF
140000-147FFF
Partition
138000-13FFFF 100000-107FFF 0F8000-0FFFFF 000000-007FFF
Main Partitions
Four Partitions
Eight Partitions Sixteen Partitions
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Intel® Wireless Flash Memory (W18)
Figure
Ball Corner
Package Information
Lithography
64-Mbit Package Drawing
Ball Corner
View Bump Side Down
Bottom View Ball Side
Seating Plane
Table
64-Mbit Package Dimensions
Millimeters Dimension Symbol 0.665 0.375 7.700 9.000 0.750 1.225 2.250 1.000 0.425 7.800 9.100 0.100 1.325 2.350 0.0059 0.0128 0.2992 0.3504 0.0443 0.0846 0.0262 0.0148 0.3031 0.3543 0.0295 0.0482 0.0886 0.0394 0.0167 0.3071 0.3583 0.0039 0.0522 0.0925 0.150 0.325 7.600 8.900 1.125 2.150 Inches
Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along Corner Ball Distance Along
Intel® Wireless Flash Memory (W18) Order Number: 290701, Revision:
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Intel® Wireless Flash Memory (W18)
Figure
Ball Corner
Lithography
32-, 64-, 128-Mbit Package Drawing
Ball Corn
View Bump Side Down
Bottom View Ball Side
Seating Plane
Table
32-, 64-, 128-Mbit Package Dimensions
Millimeters Dimension Symbol 0.665 0.375 7.700 11.000 9.000 0.750 1.225 2.2875 2.250 1.000 0.425 7.800 11.100 9.100 0.100 1.325 2.975 2.350 0.0059 0.0128 0.2992 0.4291 0.3504 0.0443 0.1093 0.0846 0.0262 0.0148 0.3031 0.4331 0.3543 0.0295 0.0482 0.1132 0.0886 0.0394 0.0167 0.3071 0.4370 0.3583 0.0039 0.0522 0.1171 0.0925 0.150 0.325 7.600 10.900 8.900 1.125 2.775 2.150 Inches
Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width (32/64-Mbit) Package Body Width (128-Mbit) Package Body Length (32/64/128-Mbit) Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along (32/64-Mbit) Corner Ball Distance Along (128-Mbit) Corner Ball Distance Along (32/64/128-Mbit)
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Intel® Wireless Flash Memory (W18) Order Number: 290701, Revision:
Intel® Wireless Flash Memory (W18)
Figure
128-Mbit QUAD+ Package Drawing
Index Mark
View Ball Down
Bottom View Ball
Drawing scale.
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along Corner Ball Distance Along
Symbol
0.200 0.325 9.900 7.900
Millimeters 1.200 0.860 0.375 10.000 8.000 0.800 1.200 0.600
Notes
0.0079
Inches
0.0472
0.425 10.100 8.100
0.0128 0.3898 0.3110
0.0339 0.0148 0.3937 0.3150 0.0315 0.0472 0.0236
0.0167 0.3976 0.3189
1.100 0.500
0.100 1.300 0.700
0.0433 0.0197
0.0039 0.0512 0.0276
Intel® Wireless Flash Memory (W18) Order Number: 290701, Revision:
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Intel® Wireless Flash Memory (W18)
Ballout Signal Descriptions
Signal Ballout
device available 56-ball µBGA Chip Scale Package with 0.75 ball pitch, 88-ball active balls) QUAD+ SCSP package. Figure shows device ballout package. Figure shows device ballout QUAD+ package.
Figure
56-Ball Ballout
VCCQ VSSQ VCCQ VSSQ VSSQ VCCQ VSSQ DQ14 DQ13 DQ11 DQ10 DQ10 DQ11 DQ13 DQ14 DQ15 DQ15 VCCQ WAIT DQ12 DQ12 WAIT ADV# ADV# RST# RST#
View Ball Side Down Complete Mark Shown
Bottom View Ball Side
Notes: lower density devices, upper address balls treated (Example: 32-Mbit density, NC). Section 3.0, "Package Information" page mechanical specifications package.
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Intel® Wireless Flash Memory (W18)
Figure
88-Ball Active Balls) QUAD+ Ballout
F1-VCC F2-VCC
R-LB# S-CS2
F-VPP, F-VPEN R-WE# P1-CS#
F-WP# ADV#
R-UB# F-RST# F-WE#
WAIT F2-CE#
R-OE# F2-OE#
S-CS1# F1-OE# VCCQ
F1-CE# P2-CS# F3-CE# S-VCC P-VCC F2-VCC VCCQ P-Mode, P-CRE
VCCQ F1-VCC
View Ball Side Down Legend: Global SRAM/PSRAM specific Flash specific
Notes: Unused upper address balls treated (for 128-Mbit device, A[25:23] used). Section 3.0, "Package Information" page mechanical specifications package.
Intel® Wireless Flash Memory (W18) Order Number: 290701, Revision:
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Intel® Wireless Flash Memory (W18)
Signal Descriptions
Table describes signals used package. Table describes signals used QUAD+ package.
Table
Symbol A[22:0] D[15:0]
Signal Descriptions Package
Type Input Input/ Output Name Function ADDRESS INPUTS: memory addresses. 32-Mbit: A[20:0]; 64-Mbit: A[21:0]; 128-Mbit: A[22:0] DATA INPUTS/OUTPUTS: Inputs data commands during write cycles; outputs data during memory, Status Register, protection register, configuration code reads. Data pins float when chip outputs deselected. Data internally latched during writes. ADDRESS VALID: ADV# indicates valid address presence address inputs. During synchronous read operations, addresses latched ADV#'s rising edge next valid edge with ADV# low, whichever occurs first. CHIP ENABLE: Asserting activates internal control logic, buffers, decoders, sense amps. De-asserting deselects device, places standby mode, places outputs High-Z. CLOCK: synchronizes device system frequency during synchronous reads increments internal address generator. During synchronous read operations, addresses latched ADV#'s rising edge next valid edge with ADV# low, whichever occurs first. OUTPUT ENABLE: When asserted, enables device's output data buffers during read cycle. When deasserted, data outputs placed high-impedance state. RESET: When low, RST# resets internal automation inhibits write operations. This provides data protection during power transitions. de-asserting RST# enables normal operation places device asynchronous read-array mode. WAIT: WAIT signal indicates valid data during synchronous read modes. configured asserted-high asserted-low based Read Configuration Register. WAIT tristated deasserted. WAIT gated OE#. WRITE ENABLE: controls writes array. Addresses data latched rising edge WE#. WRITE PROTECT: Disables/enables lock-down function. When asserted, lock-down mechanism enabled blocks marked lock-down cannot unlocked through software. Section 13.1, "Block Lock Operations" page details block locking. ERASE PROGRAM POWER: valid voltage this allows erasing programming. Memory contents cannot altered when VPPLK. Block erase program invalid voltages should attempted.
ADV#
Input
Input
Input
Input
RST#
Input
WAIT
Output
Input
Input
Power
in-system program erase operations. accommodate resistor diode drops from system supply, level VPP1 min. must remain above VPP1 perform in-system flash modification. during read operations. VPP2 applied main blocks 1000 cycles maximum parameter blocks 2500 cycles. connected cumulative total exceed hours. Extended this reduce block cycling capability.
VCCQ VSSQ
Power Power Power Power
DEVICE POWER SUPPLY: Writes inhibited VLKO. Device operations invalid voltages should attempted. OUTPUT POWER SUPPLY: Enables outputs driven VCCQ. This input tied directly VCC. GROUND: Pins internal device circuitry must connected system ground. OUTPUT GROUND: Provides ground outputs which driven VCCQ. This signal tied directly VSS. USE: this pin. This should connected power supplies, signals other pins must floated. CONNECT: internal connection; driven floated.
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Intel® Wireless Flash Memory (W18)
Table
Symbol
Signal Descriptions QUAD+ Package (Sheet
Type Description ADDRESS INPUTS: Inputs addresses during read write operations.
A[MAX:MIN]
Input
8-Mbit AMAX lowest-order 16-bit wide address. A[25:24] denote high-order addresses reserved future device densities. D[15:0] Input/ Output DATA INPUTS/OUTPUTS: Inputs data commands during write cycles, outputs data during read cycles. Data signals float when device outputs deselected. Data internally latched during writes flash device. FLASH CHIP ENABLE: Low-true input. F[3:1]-CE# selects associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, sense amplifiers active. When deasserted, associated flash deselected, power reduced standby levels, data WAIT outputs placed high-Z state. F1-CE# selects deselects flash F2-CE# selects deselects flash combinations with only flash die. F3-CE# selects deselects flash stacked combinations with only flash dies. SRAM CHIP SELECT: Low-true High-true input (S-CS1# S-CS2 respectively). S-CS1# S-CS2 Input When either/both SRAM Chip Select signals asserted, SRAM internal control logic, input buffers, decoders, sense amplifiers active. When either/both SRAM Chip Select signals deasserted, SRAM deselected power reduced standby levels. S-CS1# S-CS2 available stacked combinations with SRAM stacked combinations without SRAM die. PSRAM CHIP SELECT: Low-true input. When asserted, PSRAM internal control logic, input buffers, decoders, sense amplifiers active. When deasserted, PSRAM deselected power reduced standby levels. P[2:1]-CS# Input P1-CS# selects PSRAM available only stacked combinations with PSRAM die. This ball stacked combinations without PSRAM. P2-CS# selects PSRAM available only stacked combinations with PSRAM dies. This ball stacked combinations without PSRAM with single PSRAM. FLASH OUTPUT ENABLE: Low-true input. F[2:1]-OE# Input Fx-OE# enables selected flash's output buffers. F[2:1]-OE# high disables selected flash's output buffers, placing them High-Z. F1-OE# controls outputs flash F2-OE# controls outputs flash flash F2-OE# available stacked combinations with three flash stacked combinations with only flash die. OUTPUT ENABLE: Low-true input. R-OE# Input R-OE# enables selected RAM's output buffers. R-OE# high disables output buffers, places selected outputs High-Z. R-OE# available stacked combinations with PSRAM SRAM die, flash-only stacked combinations. FLASH WRITE ENABLE: Low-true input. F-WE# Input F-WE# controls writes selected flash die. Address data latched rising edge FWE#. WRITE ENABLE: Low-true input. R-WE# Input R-WE# controls writes selected die. R-WE# available stacked combinations with PSRAM SRAM flash-only stacked combinations.
256-Mbit AMAX= 128-Mbit AMAX 64-Mbit AMAX 32-Mbit AMAX
F[3:1]-CE#
Input
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Intel® Wireless Flash Memory (W18)
Table
Signal Descriptions QUAD+ Package (Sheet
CLOCK: Synchronizes flash with system clock synchronous read mode increments internal address generator.
Input
During synchronous read operations, addresses latched rising edge ADV#, next valid edge with ADV# low, whichever occurs first. asynchronous mode, addresses latched rising edge ADV#, continuously flowthrough when ADV# kept asserted. WAIT: Output signal. Indicates invalid data during synchronous array non-array flash reads. Read Configuration Register (RCR[10]) determines WAIT-asserted polarity (high low). WAIT High-Z F-CE# deasserted; WAIT gated F-OE#. synchronous array non-array flash read modes, WAIT indicates invalid data when asserted valid data when deasserted. asynchronous flash page read, flash write modes, WAIT asserted. FLASH WRITE PROTECT: Low-true input. F-WP# enables/disables lock-down protection mechanism selected flash die.
WAIT
Output
F-WP#
Input
F-WP# enables lock-down mechanism where locked down blocks cannot unlocked with software commands. F-WP# high disables lock-down mechanism, allowing locked down blocks unlocked with software commands. ADDRESS VALID: Low-true input. During synchronous flash read operations, addresses latched rising edge ADV#, next valid edge with ADV# low, whichever occurs first. asynchronous flash read operations, addresses latched rising edge ADV#, continuously flow-through when ADV# kept asserted. UPPER LOWER BYTE ENABLES: Low-true input. During read write cycles, R-UB# enables high order bytes D[15:8], RLB# enables low-order bytes D[7:0]. R-UB# R-LB# available stacked combinations with PSRAM SRAM flash-only stacked combinations. FLASH RESET: Low-true input.
ADV#
Input
R-UB# R-LB#
Input
F-RST#
Input
F-RST# initializes flash internal circuitry disables flash operations. F-RST# high enables flash operation. Exit from reset places flash asynchronous read array mode. P-Mode (PSRAM Mode): Low-true input. P-Mode used program Configuration Register, enter/exit Power Mode PSRAM die. P-Mode available stacked combinations with asynchronous-only PSRAM die.
P-Mode, P-CRE
Input
P-CRE (PSRAM Configuration Register Enable): High-true input. P-CRE high, write operations load refresh control register control register. P-CRE applicable only combinations with synchronous PSRAM die. P-Mode, P-CRE stacked combinations without PSRAM die. FLASH PROGRAM ERASE POWER: Valid F-VPP voltage this ball enables flash program/ erase operations.
F-VPP, F-VPEN
Power
Flash memory array contents cannot altered when F-VPP(F-VPEN) VPPLK (VPENLK). Erase program operations invalid F-VPP (F-VPEN) voltages should attempted. Refer flash discrete product datasheet additional details. F-VPEN (Erase/Program/Block Lock Enables) available L18/L30 SCSP products. FLASH LOGIC POWER: F1-VCC supplies power core logic flash F2-VCC supplies power core logic flash flash Write operations inhibited when F-VCC VLKO. Device operations invalid F-VCC voltages should attempted. F2-VCC available stacked combinations with three flash dies, stacked combinations with only flash die.
F[2:1]-VCC
Power
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Intel® Wireless Flash Memory (W18)
Table
S-VCC
Signal Descriptions QUAD+ Package (Sheet
SRAM POWER SUPPLY: Supplies power SRAM operations. Power S-VCC available stacked combinations with SRAM die, stacked combinations without SRAM die. PSRAM POWER SUPPLY: Supplies power PSRAM operations. P-VCC available stacked combinations with PSRAM die, stacked combinations without PSRAM die. DEVICE POWER: Supply power device input output buffers. DEVICE GROUND: Connect system ground. float connection. RESERVED FUTURE USE: Reserved future device functionality/ enhancements. Contact Intel regarding balls designated RFU. USE: connect other signal, power supply; must left floating.
P-VCC VCCQ
Power Power Power
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Intel® Wireless Flash Memory (W18)
Warning:
Maximum Ratings Operating Conditions
Absolute Maximum Ratings
Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only.
Notice: This datasheet contains information products design phase development. information here subject change without notice. finalize design with this information.
Table
Absolute Maximum Ratings
Parameter Temperature under Bias Storage Temperature Voltage (except VCC, VCCQ, VPP) Voltage VCCQ Voltage Output Short Circuit Current Maximum Rating +125 -0.5 +2.45 -0.2 +13.1 -0.2 +2.45 1,3,4 Notes
Notes: Specified voltages with respect VSS. During transitions, this level undershoot (130 -2.0 periods overshoot VCCQ +2.0 periods -1.0 periods overshoot VCCQ +1.0 periods Maximum voltage overshoot +14.6 periods program voltage normally VPP1. 1000 cycles main blocks 2500 cycles parameter blocks during program/erase. Output shorted more than second. more than output shorted time.
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Intel® Wireless Flash Memory (W18)
Warning: Table
Symbol
Operating Conditions
Operation beyond "Operating Conditions" recommended, extended exposure beyond "Operating Conditions" affect device reliability. Extended Temperature Operation
Parameter1 Operating Temperature Supply Voltage Supply Voltage Supply Voltage (130 Extended Supply Voltage (130 1.35 0.90 11.4 100,000 1.80 12.0 1.95 1.95 2.24 1.95 12.6 1000 2500 Cycles Hours Unit Note
VPP1
Voltage Supply (Logic Level) Programming
tPPH Block Erase Cycles
Maximum Hours Main Parameter Blocks Main Blocks Parameter Blocks
Notes: Section 6.1, Current Characteristics" page Section 6.2, Voltage Characteristics" page specific voltage-range specifications. normally VPP1. connected 11.4 V-12.6 1000 cycles main blocks extended temperatures 2500 cycles parameter blocks extended temperatures. Contact your Intel field representative VCC/VCCQ operations down 1.65 tables Section 5.0, "Maximum Ratings Operating Conditions" page Section 7.0, Characteristics" page operating characteristics within Extended VCCQ voltage range.
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Intel® Wireless Flash Memory (W18)
Table
Electrical Specifications
Current Characteristics
Current Characteristics (Sheet
VCCQ= 1.35 VCCQ= 32/64-Mbit 128-Mbit VCCMax VCCQ VCCQMax VCCQ VCCMax VCCQ VCCQMax VCCQ VCCMax VCCQ VCCQMax RST# =VSSQ VCCMax VCCQ VCCQMax VSSQ RST# =VCCQ other inputs =VCCQ VSSQ Unit Test Condition Note
Symbol
Parameter
32/64/128Mbit
Input Load
ICCS ICCS ICCAPS
Output Leakage
D[15:0]
Standby
ICCAPS Asynchronous Page Mode f=13
Word Read Burst length Burst length
ICCR
Average Read
Synchronous
Burst length Burst length Continuous Burst length Burst length Burst length Burst length Continuous Burst length Burst length Burst length Burst length Continuous
Synchronous
ICCR
Average Read
Synchronous
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Table
Current Characteristics (Sheet
VCCQ= 1.35 VCCQ= 32/64-Mbit 128-Mbit VCC, Erase Suspended VPP1, Program Progress 4,5,6 VPP2, Program Progress VPP1, Block Erase Progress 4,5,6 VPP2, Block Erase Progress VCC, Program Suspended Unit Test Condition Note
Symbol
Parameter
32/64/128Mbit
ICCW
Program
ICCE
Block Erase
130nm ICCWS 90nm ICCWS 130nm ICCES 90nm ICCWS IPPS (IPPWS, IPPES) IPPR
Program Suspend Erase Suspend Standby Program Suspend Erase Suspend Read
<VCC VPP1, Program Progress
0.05 0.05
0.10 0.10
0.05 0.05
0.10
IPPW
Program 0.10
VPP2, Program Progress VPP1, Erase Progress VPP2, Erase Progress
IPPE
Erase
Notes: currents unless noted. Typical values typical VCC, +25° VCCQ 1.35 1.8V available products only. Automatic Power Savings (APS) reduces ICCR approximately standby levels static operation. ICCRQ specification details. Sampled, 100% tested. read program current read program currents. read erase current read erase currents. ICCES specified with device deselected. device read while erase suspend, current ICCES plus ICCR. VIN>VCC input load current increases max. ICCS average current measured over time interval after de-assertion. Refer section Section 8.2, "Automatic Power Savings (APS)" page ICCAPS measurement details.
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Intel® Wireless Flash Memory (W18)
Table
Voltage Characteristics
Voltage Characteristics
VCCQ= 1.35 VCCQ= 32/64-Mbit VCCQ VCCQ 128-Mbit VCCQ VCCQ VCCMin VCCQ VCCQMin VCCMin VCCQ VCCQMin -100 Unit Test Condition Note
Symbol
Parameter
32/64/128-Mbit VCCQ
Input Input High Output
VCCQ
Output High
VCCQ
VCCQ
VCCQ
VPPLK VLKO VILKOQ
Lock-Out Lock VCCQ Lock
Notes: VCCQ 1.35 1.8V available devices only. undershoot -1.0 durations less overshoot VCCQ+1.0 durations less. VPPLK inhibits erase program operations. Don't VPPL VPPH outside their valid ranges.
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Table
Characteristics
Read Operations Lithography (Sheet
Symbol Parameter (1,2) VCCQ= 1.95
Unit
Notes
Asynchronous Specifications tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tEHEL tELTV tEHTZ Read Cycle Time Address Output Valid Output Valid Output Valid RST# High Output Valid Output Low-Z Output Low-Z High Output High-Z High Output High-Z (OE#) High Output Low-Z Pulse Width High WAIT Valid High WAIT High-Z
Latching Specifications R101 R102 R103 R104 R105 R106 R108 tAVVH tELVH tVLQV tVLVH tVHVL tVHAX tAPA Address Setup ADV# High ADV# High ADV# Output Valid ADV# Pulse Width ADV# Pulse Width High Address Hold from ADV# High Page Address Access Time
Clock Specifications R200 R201 R202 R203 fCLK tCLK tCH/L tCHCL Frequency Period High Time Fall Rise Time
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Intel® Wireless Flash Memory (W18)
Table
Read Operations Lithography (Sheet
Symbol
(1,2)
Parameter
VCCQ= 1.95
Unit
Notes
Synchronous Specifications R301 R302 R303 R304 R305 R306 R307 tAVCH tVLCH tELCH tCHQV tCHQX tCHAX tCHTV Address Valid Setup ADV# Setup Setup Output Valid Output Hold from Address Hold from WAIT Valid
Figure Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate. specifications assume data voltage less than equal VCCQ when read operation initiated. Address hold synchronous-burst mode defined tCHAX tVHAX, whichever timing specification satisfied first. delayed tELQV- tGLQV after falling edge without impact tELQV. Sampled, 100% tested. Applies only subsequent synchronous reads. During initial access synchronous burst read, data from first word begin driven onto data early first clock edge after tAVQV. preceding specifications apply densities.
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Intel® Wireless Flash Memory (W18)
Table
Symbol
Read Operations Lithography (Sheet
VCCQ= 1.35 Parameter (1,2) VCCQ= 2.24 Unit Notes
Asynchronous Specifications tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tEHEL tELTV tEHTZ Read Cycle Time Address Output Valid Output Valid Output Valid RST# High Output Valid Output Low-Z Output Low-Z High Output High-Z High Output High-Z (OE#) High Output Low-Z Pulse Width High WAIT Valid High WAIT High-Z
Latching Specifications R101 R102 R103 R104 R105 R106 R108 tAVVH tELVH tVLQV tVLVH tVHVL tVHAX tAPA Address Setup ADV# High ADV# High ADV# Output Valid ADV# Pulse Width ADV# Pulse Width High Address Hold from ADV# High Page Address Access Time
Clock Specifications R200 R201 R202 R203 fCLK tCLK tCH/L tCHCL Frequency Period High Time Fall Rise Time 18.5 18.5
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Intel® Wireless Flash Memory (W18)
Table
Symbol
Read Operations Lithography (Sheet
VCCQ= 1.35 Parameter (1,2) VCCQ= 2.24 Unit Notes
Synchronous Specifications R301 R302 R303 R304 R305 R306 R307 tAVCH tVLCH tELCH tCHQV tCHQX tCHAX tCHTV Address Valid Setup ADV# Setup Setup Output Valid Output Hold from Address Hold from WAIT Valid Note:
numbered note references this table, refer notes Table "Read Operations Lithography" page
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Intel® Wireless Flash Memory (W18)
Figure
Asynchronous Read Operation Waveform
Address
Valid Address
High High
WAIT
Note
Data [D/Q]
High
Valid Output
RST#
Notes: WAIT shown asserted (RCR[10]=0) ADV# assumed driven this waveform
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Intel® Wireless Flash Memory (W18)
Figure
Latched Asynchronous Read Operation Waveform
A[MAX:2]
Valid Address
Valid Address
A[1:0]
R101 R105 R106
Valid Address
Valid Address
ADV#
R104 R103
R102
Data
High
Valid Output
RST#
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Intel® Wireless Flash Memory (W18)
Figure
Page-Mode Read Operation Waveform
A[MAX:2]
Valid Address
A[1:0]
R101 R105 R106
Valid Address
Valid Address
Valid Address
Valid Address
ADV#
R104 R103
R102
WAIT
High Valid Output Valid Output Valid Output Valid Output High
Note
R108
High
Data [D/Q]
RST#
Note:
WAIT shown asserted (RCR[10]
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Intel® Wireless Flash Memory (W18)
Figure
Single Synchronous Read-Array Operation Waveform
Notes: Section 14.2, "First Access Latency Count (RCR[13:11])" page describes insert clock cycles during initial access. WAIT (shown asserted; RCR[10]=0) configured assert either during, data cycle before, valid data. This waveform illustrates case which x-word burst initiated main array terminated deassertion after first word burst. this access been done Status, Query reads, asserted (low) WAIT signal would have remained asserted (low) long asserted (low).
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Figure
Synchronous 4-Word Burst Read Operation Waveform
Notes: Section 14.2, "First Access Latency Count (RCR[13:11])" page describes insert clock cycles during initial access. WAIT (shown asserted; RCR[10] configured assert either during, data cycle before, valid data.
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Intel® Wireless Flash Memory (W18)
Figure
WAIT Functionality EOWL (End-of-Word Line) Condition Waveform
Notes: Section 14.2, "First Access Latency Count (RCR[13:11])" page describes insert clock cycles during initial access. WAIT (shown asserted; RCR[10]=0) configured assert either during, data cycle before, valid data (assumed wait delay clocks, example).
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Figure
WAIT Signal Synchronous Non-Read Array Operation Waveform
Notes: Section 14.2, "First Access Latency Count (RCR[13:11])" page describes insert clock cycles during initial access. WAIT shown asserted (RCR[10]=0).
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Intel® Wireless Flash Memory (W18)
Figure
Burst Suspend
R304 R305 R305 R305
Address R101 R105 ADV# WAIT DATA [D/Q] R304 R304
R106
Note:
During Burst Suspend, Clock signal held high low.
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Intel® Wireless Flash Memory (W18)
Table
Write Characteristics
Write Characteristics Lithography
(1,2)
Parameter
VCCQ 1.95
Unit
Notes
Notes:
tPHWL (tPHEL) tELWL (tWLEL) tWLWH (tELEH) tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWHWL (tEHEL) tVPWH (tVPEH) tQVVL tQVBL tBHWH (tBHEH) tWHGL (tEHGL) tWHQV tWHAV tWHCV tWHVH tVHWL tCHWL tWHEL tWHVL
RST# High Recovery (CE#) (WE#) Setup (CE#) (CE#) Write Pulse Width Data Setup (CE#) High Address Setup (CE#) High (WE#) Hold from (CE#) High Data Hold from (CE#) High Address Hold from (CE#) High (CE#) Pulse Width High Setup (CE#) High Hold from Valid Hold from Valid Setup (CE#) High Write Recovery before Read High Valid Data High Address Valid High Valid High ADV# High ADV# High High High ADV#
tAVQV
5,6,7
3,6,10 3,9,10 3,10 3,10
Write timing characteristics during erase suspend same during write-only operations. write operation terminated with either WE#. Sampled, 100% tested. Write pulse width (tWLWH tELEH) defined from (whichever occurs last) high (whichever occurs first). Hence, tWLWH tELEH tWLEH tELWH. Write pulse width high (tWHWL tEHEL) defined from high (whichever first) (whichever last). Hence, tWLWH tEHEL tWHEL tEHWL. System designers should take this into account insert software No-Op instruction delay first read after issuing command. commands other than resume commands. should held VPP1 VPP2 until block erase program success determined. Applicable during asynchronous reads following write. tWHCH/L tWHVH must when transitioning from write cycle synchronous burst read. tWHCH/L tWHVH both refer address latching event (either rising/falling clock edge rising ADV# edge, whichever occurs first). specifications tVHWL tCHWL ignored there clock toggling during write cycle.
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Intel® Wireless Flash Memory (W18)
Table
Write Characteristics Lithography
VCCQ 1.35 VCCQ 2.24 tAVQV tAVQV 3,6,10 3,9,10 3,10 3,10 5,6,7 Unit Notes
Parameter (1,2)
tAVQV
tPHWL (tPHEL) tELWL (tWLEL) tWLWH (tELEH) tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWHWL (tEHEL) tVPWH (tVPEH) tQVVL tQVBL tBHWH (tBHEH) tWHGL (tEHGL) tWHQV tWHAV tWHCV tWHVH
RST# High Recovery (CE#) (WE#) Setup (CE#) (CE#) Write Pulse Width Data Setup (CE#) High Address Setup (CE#) High (WE#) Hold from (CE#) High Data Hold from (CE#) High Address Hold from (CE#) High (CE#) Pulse Width High Setup (CE#) High Hold from Valid Hold from Valid Setup (CE#) High Write Recovery before Read High Valid Data High Address Valid High Valid High ADV# High
tAVQV
Notes: numbered note references this table, refer notes Table Write Characteristics Lithography" page
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Intel® Wireless Flash Memory (W18)
Figure
Write Operations Waveform
Note
Note
Valid Address
Note
Valid Address
Note
Note
Valid Address
Address
R101 R105 R106
ADV#
R104
(WE#) [E(W)]
Note
(CE#) [W(E)]
Note
Data
Data Data
Valid
RST#
VPPH
VPPLK
Notes:
power-up standby. Write Program Erase Setup command. Write valid address data (for program) Erase Confirm command. Automated program/erase delay. Read Status Register data (SRD) determine program/erase operation completion. must asserted must deasserted read operations. ignored. (but kept active/toggling)
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Intel® Wireless Flash Memory (W18)
Figure
Asynchronous Read Write Operation Waveform
Address Data [D/Q] RST#
Figure
Asynchronous Write Read Operation
Address
Data [D/Q]
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Intel® Wireless Flash Memory (W18)
Figure
Synchronous Read Write Operation
Latency Count R301 R302 R306
R101 Address R105 R106 R102 ADV# R303 WAIT R304 Data [D/Q] R305 R307 R104
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Intel® Wireless Flash Memory (W18)
Figure
Synchronous Write Read Operation
Latency Count R302 R301
Address ADV# R303 R106 R104 R306
WAIT Data [D/Q RST# R304 R304 R305 R307
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Intel® Wireless Flash Memory (W18)
Table
Operation
Erase Program Times
Erase Program Times
Symbol Parameter Description VPP1 Notes VPP2 Unit
Erasing Suspending W500 Erase Time W501 Suspend Latency Programming W200 Program Time W201 W202 tPROG/W tPROG/PB tPROG/MB Single Word 4-Kword Parameter Block 32-Kword Main Block 0.05 0.03 0.24 0.07 W600 W601 tERS/MB tSUSP/P tSUSP/E 32-Kword Main Block Program Suspend Erase Suspend tERS/PB 4-Kword Parameter Block 0.25
Enhanced Factory Programming W400 Program W401 W402 W403 Operation Latency W404 W405 tEFP/W tEFP/PB tEFP/MB tEFP/SETUP tEFP/TRAN tEFP/VERIFY Single Word 4-Kword Parameter Block 32-Kword Main Block Setup Program Verify Transition Verify
Notes: Unless noted otherwise, parameters measured nominal voltages, they sampled, 100% tested. Excludes external system-level overhead. Exact results vary based system overhead. W400-Typ calculated delay single programming pulse. W400-Max includes delay when programming within word-line. Some performance degradation occur block cycling exceeds
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Intel® Wireless Flash Memory (W18)
Table
Notes:
Reset Specifications
Reset Specifications
Symbol tPLPH tPLRH tVCCPH Parameter RST# Reset during Read RST# RST# Reset during Power Valid Reset Notes 1,3,4,5,6 Unit
These specifications valid product versions (packages speeds). device reset tPLPH< tPLPHMin, this guaranteed. applicable RST# tied VCC. Sampled, 100% tested. RST# tied VCC, device ready until tVCCPH occurs after when VCCMin. RST# tied supply/signal with VCCQ voltage levels, RST# input voltage must exceed until VCCMin.
Figure
Reset Operations Waveforms
Reset during read mode
RST#
Reset during program block erase
Abort Complete
RST#
Reset during program block erase
Abort Complete
RST#
Power-up RST# high
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Intel® Wireless Flash Memory (W18)
Figure
Test Conditions
Input/Output Reference Waveform
VCCQ Input
Note: Input timing begins, output timing ends, VCCQ/2. Input rise fall times (10% 90%) Worst case speed conditions when VCCMin.
VCCQ/2
Test Points
VCCQ/2
Output
Figure
Transient Equivalent Testing Load Circuit
VCCQ
Device Under Test
Note:
Table page component values.
Table
Test Configuration Component Values Worst Case Speed Conditions
Test Configuration -Note: includes capacitance. (pF) 13.5 16.7 13.5 16.7
Figure
Clock Input Waveform
R201
R202 R203
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Intel® Wireless Flash Memory (W18)
Device Capacitance
Symbol COUT
Input Capacitance Output Capacitance Input Capacitance
Unit
Condition VOUT
Sampled, 100% tested.
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Intel® Wireless Flash Memory (W18)
Power Reset Specifications
Intel® Wireless Flash Memory (W18) devices have layered approach power savings that significantly reduce overall system power consumption. feature reduces power consumption when device selected idle. deasserted, memory enters standby mode, where current consumption even lower. Asserting RST# provides current savings similar standby mode. combination these features minimize memory power consumption, therefore, overall system power consumption.
Active Power
With RST# VIH, device active mode. Refer Section 6.1, Current Characteristics" page values. When device "active" state, consumes most power from system. Minimizing device active current therefore reduces system power consumption, especially battery-powered applications.
Automatic Power Savings (APS)
Automatic Power Saving (APS) provides low-power operation during read's active state. During mode, ICCAPS average current measured over time interval after following events happen:
There internal sense activity; asserted; address lines quiescent, VSSQ VCCQ.
asserted during APS.
Standby Power
With device read mode, flash memory standby mode, which disables most device circuitry substantially reduces power consumption. Outputs placed highimpedance state independent signal state. transitions during erase program operations, device continues operation consumes corresponding active power until operation complete. ICCS average current measured over time interval after de-assertion.
Power-Up/Down Characteristics
device protected against accidental block erasure programming during power transitions. Power supply sequencing required VCC, VCCQ, connected together; doesn't matter whether powers-up first. VCCQ and/or connected system supply, then should attain VCCMIN before applying VCCQ VPP. Device inputs should driven before supply voltage VCCMIN. Power supply transitions should only occur when RST# low.
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Intel® Wireless Flash Memory (W18)
8.4.1
System Reset RST#
RST# during system reset important with automated program/erase devices because system expects read from flash memory when comes reset. reset occurs without flash memory reset, proper initialization will occur because flash memory providing status information instead array data. allow proper CPU/flash initialization system reset, connect RST# system RESET# signal. System designers must guard against spurious writes when voltages above VLKO. Because both must command write, driving either signal inhibits writes device. architecture provides additional protection because alteration memory contents only occur after successful completion two-step command sequences. device also disabled until RST# brought VIH, regardless control input states. holding device reset (RST# connected system PowerGood) during power-up/down, invalid conditions during power-up masked, providing another level memory protection.
8.4.2
VCC, VPP, RST# Transitions
latches commands issued system software altered transitions actions. Read-array mode power-up default state after exit from reset mode after transitions above VLKO (Lockout voltage). After completing program block erase operations (even after transitions below VPPLK), Read Array command must reset read-array mode flash memory array access desired.
Power Supply Decoupling
When device accessed, many internal conditions change. Circuits enabled charge pumps switch voltages. This internal activity produces transient noise. minimize effect this transient noise, device decoupling capacitors required. Transient current magnitudes depend device outputs' capacitive inductive loading. Two-line control proper decoupling capacitor selection suppresses these transient voltage peaks. Each flash device should have ceramic capacitor connected between each power (VCC, VCCQ, VPP), ground (VSS, VSSQ) signal. High-frequency, inherently low-inductance capacitors should close possible package signals.
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Intel® Wireless Flash Memory (W18)
Operations Overview
This section provides overview device operations. Intel® Wireless Flash Memory (W18) family includes on-chip manage block erase program algorithms. Command User Interface (CUI) allows minimal processor overhead with RAM-like interface timings. Device commands written using standard microprocessor timings.
Operations
cycles to/from device conform standard microprocessor operations. Table summarizes operations logic levels that must applied device's control signal inputs.
Table
Operations Summary
RST# Running Halted ADV# WAIT Asserted Driven Active Asserted Asserted High-Z High-Z DQ[15:0] Output Output Output Input High-Z High-Z High-Z Notes
Operation Asynchronous Read Synchronous Burst Suspend Write Output Disable Standby Reset Notes:
WAIT only valid during synchronous array-read operations. Refer Table "Bus Cycle Definitions" page valid DQ[15:0] during write operation. Don't Care RST# must meet maximum specified power-down current.
9.1.1
Reads
Device read operations performed placing desired address A[22:0] asserting OE#. ADV# must low, RST# must high. read operations independent voltage level VPP. CE#-low selects device enables internal circuits. OE#-low WE#-low determine whether DQ[15:0] outputs inputs, respectively. must same time indeterminate device operation will result. asynchronous-page mode, rising edge ADV# used latch address. only asynchronous read mode used, ADV# tied ground. used asynchronouspage mode should tied high. synchronous-burst mode, ADV# used latch initial address either rising edge ADV# rising falling) edge with ADV# low, whichever occurs first. used synchronous-burst mode increment internal address counter, output read data DQ[15:0]. Each device partition placed several read states:
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Intel® Wireless Flash Memory (W18)
Read Array: Returns flash array data from addressed location. Read Identifier (ID): Returns manufacturer device codes, block lock status,
protection register data. Read Identifier information accessed from 4-Mbit partition base address.
Query: Returns Common Flash Interface (CFI) information. information
accessed starting 4-Mbit partition base addresses.
Read Status Register: Returns Status Register (SR) data from addressed partition.
appropriate command must written partition order place desired read state (see Table "Command Codes Descriptions" page 56). Non-array read operations (Read Query, Read Status Register) execute single synchronous asynchronous read cycles. WAIT asserted throughout non-array read operations.
9.1.2
Writes
Device write operations performed placing desired address A[22:0] asserting WE#. RST# must high. Data written desired address placed DQ[15:0]. ADV# must held throughout write cycle toggled latch address. ADV# held low, address data latched rising edge WE#. used during write operations, ignored; either free-running halted VIH. write operations asynchronous. Table "Command Codes Descriptions" page shows available device commands. Appendix "Write State Machine States" page provides information moving between different device operations using commands.
9.1.3
Output Disable
When deasserted, device outputs DQ[15:0] disabled placed high-impedance (High-Z) state.
9.1.4
Burst Suspend
Burst Suspend feature allows system temporarily suspend synchronous-burst read operation. This useful system needs access another device same address data flash during burst-read operation. Synchronous-burst accesses suspended during initial latency (before data received) after device output data. When burst access suspended, internal array sensing continues previously latched internal data retained. Burst Suspend occurs when asserted, current address been latched (either ADV# rising edge valid edge), halted, deasserted. halted when VIL. resume burst access, reasserted restarted. Subsequent edges resume burst sequence where left off. Within device, gates WAIT. Therefore, during Burst Suspend WAIT still driven. This cause contention with another device attempting control system's READY signal during Burst Suspend. Systems using Burst Suspend feature should connect device's WAIT signal directly system's READY signal. Refer Figure "Burst Suspend" page
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9.1.5
Standby
De-asserting deselects device places standby mode, substantially reducing device power consumption. standby mode, outputs placed high-impedance state independent OE#. deselected during program erase algorithm, device shall consume active power until program erase operation completes.
9.1.6
Reset
device enters reset mode when RST# asserted. reset mode, internal circuitry turned outputs placed high-impedance state. After returning from reset, time tPHQV required until outputs valid, delay (tPHWV) required before write sequence initiated. After this wake-up interval, normal operation restored. device defaults read-array mode, Status Register 80h, Configuration Register defaults asynchronous page-mode reads. RST# asserted during erase program operation, operation aborts memory contents aborted block address invalid. Figure "Reset Operations Waveforms" page detailed information regarding reset timings. Like automated device, important assert RST# during system reset. When system comes reset, processor expects read from flash memory array. Automated flash memories provide status information when read during program erase operations. reset occurs with flash memory reset, proper initialization occur because flash memory providing status information instead array data. Intel flash memories allow proper initialization following system reset through RST# input. this application, RST# controlled same reset signal.
Device Commands
device's on-chip manages erase program algorithms. This local (WSM) controls device's in-system read, program, erase operations. cycles from flash memory conform standard microprocessor cycles. RST#, CE#, OE#, WE#, ADV# control signals dictate data flow into device. WAIT informs valid data during burst reads. Table "Bus Operations Summary" page summarizes operations. Device operations selected writing specific commands into device's CUI. Table "Command Codes Descriptions" page lists possible command codes descriptions. Table "Bus Cycle Definitions" page lists command definitions. Because commands partition-specific, important issue write commands within target address range.
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Table
Operation
Command Codes Descriptions (Sheet
Code Device Command Read Array Read Status Register Description Places selected partition Read Array mode. Places selected partition Status Register read mode. After issuing this command, reading from partition outputs data DQ[15:0]. partition automatically enters this mode after issuing Program Erase command. Places selected partition Read mode. Device reads from partition addresses output manufacturer/device codes, Configuration Register data, block lock status, protection register data DQ[15:0]. Puts addressed partition Query mode. Device reads from partition addresses output information DQ[7:0]. Status Register's block lock (SR[1]), (SR[3]), program (SR[4]), erase (SR[5]) status bits, cannot clear them. SR[5:3,1] only cleared device reset through Clear Status Register command. This preferred program command's first cycle prepares program operation. second cycle latches address data, executes program algorithm this location. Status register updates occur when toggled. Read Array command required read array data after programming. Equivalent Program Setup command (40h). This program command activates mode. first write cycle sets command. second cycle Confirm command (D0h), subsequent writes provide program data. other commands ignored after mode begins. first command Setup (30h), latches address data, prepares device mode. This command prepares Block Erase. device erases block addressed Erase Confirm command. next command Erase Confirm, sets Status Register bits SR[5:4] indicate command sequence error places partition read Status Register mode. first command Erase Setup (20h), latches address data, erases block indicated erase confirm cycle address. During program erase, partition responds only Read Status Register, Program Suspend, Erase Suspend commands. toggle updates Status Register data. This command, issued device address, suspends currently executing program erase operation. Status register data indicates operation successfully suspended SR[2] (program suspend) SR[6] (erase suspend) SR[7] set. remains suspended state regardless control signal states (except RST#). This command, issued device address, resumes suspended program erase operation.
Read
Read Identifier
Query Clear Status Register
Word Program Setup
Program
Alternate Setup
Setup
Confirm
Erase
Erase Setup
Erase Confirm
Suspend
Program Suspend Erase Suspend Suspend Resume
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Table
Operation
Command Codes Descriptions (Sheet
Code Device Command Lock Setup Description This command prepares lock configuration. next command Lock Block, Unlock Block, Lock-Down, sets SR[5:4] indicate command sequence error. previous command Lock Setup (60h), locks addressed block. previous command Lock Setup (60h), latches address unlocks addressed block. previously locked-down, operation effect. previous command Lock Setup (60h), latches address locks-down addressed block. This command prepares protection register program operation. second cycle latches address data, starts WSM's protection register program lock algorithm. Toggling updates flash Status Register data. read array data after programming, issue Read Array command. This command prepares device configuration. Configuration Register next command, sets SR[5:4] indicate command sequence error. previous command Configuration Setup (60h), latches address writes data from A[15:0] into configuration register. Subsequent read operations access array data.
Block Locking
Lock Block
Unlock Block
Lock-Down
Protection
Protection Program Setup
Configuration Note:
Configuration Setup Configuration Register
unassigned commands. Intel reserves right redefine these codes future functions.
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Table
Operation
Cycle Definitions
Command Cycles First Cycle Oper Write Write Write Write Write Write Write Write Write Write Write Write Write Write Addr1 Data2,3 40h/10h Write Write Write Write Write Write Write Second Cycle Oper Read Read Read Read Addr1 Read Address PBA+IA PBA+QA Data2,3 Array Data
Read Array/Reset Read Identifier Read Query Read Status Register Clear Status Register Block Erase Program Erase Word Program Program/Erase Suspend Program/Erase Resume Lock Block Lock Unlock Block Lock-Down Block Protection Program Protection Lock Protection Program
Write
Write
FFFDh
Configuration
Configuration Register
Write
Write
Notes: First-cycle command addresses should same operation's target address. Examples: first-cycle address Read Identifier command should same Identification code address (IA); first-cycle address Word Program command should same word address (WA) programmed; first-cycle address Erase/Program Suspend command should same address within block suspended; etc. valid address within device. Identification code address. Block Address. address within specific block. Lock Protection Address obtained from (through Query command). Intel Wireless Flash Memory family's 0080h. User programmable 4-word protection address. address within specific partition. Partition Base Address. very first address particular partition. code address. Word address memory location written. Status register data. Data written location Identifier code data. User programmable 4-word protection data. Query code data DQ[7:0]. Configuration register code data presented device addresses A[15:0]. A[MAX:16] address bits select partition. Table "Read Configuration Register Descriptions" page Configuration Register bits descriptions. Commands other than those shown above reserved Intel future device implementations should used.
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Command Sequencing
When issuing 2-cycle write sequence flash device, read operation allowed occur between write cycles. setup phase 2-cycle write sequence places addressed partition into read-status mode, same partition read before second "confirm" write cycle issued, Status Register data will returned. Reads from other partitions, however, return actual array data assuming addressed partition already read-array mode. Figure Figure illustrate these conditions.
Figure
Normal Write Read Cycles
Address Data
Partition
Partition
Partition
Block Erase Setup
Block Erase Conf
Read Array
Figure
Interleaving 2-Cycle Write Sequence with Array Read
Address Data
Partition
Partition
Partition
Partition
Read Array
Erase Setup
Array Data
Read
Erase Conf
contrast, write cycle interrupt 2-cycle write sequence. Doing causes command sequence error appear Status Register. Figure illustrates command sequence error. Figure Improper Command Sequencing
Address Data [D/Q]
Partition
Partitio
Partition
Partition
Data
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10.0
Read Operations
device supports read modes asynchronous page synchronous burst mode. Asynchronous page mode default read mode after device power-up reset. Read Configuration Register (RCR) must configured enable synchronous burst reads flash memory array (see Section 14.0, "Set Read Configuration Register" page 84). Each partition device four read states: Read Array, Read Identifier, Read Status Query. Upon power-up, after reset, partitions device default Read Array state. change partition's read state, appropriate read command must written device (see Section 9.2, "Device Commands" page 55). following sections describe device read modes read states detail.
10.1
Asynchronous Page Read Mode
Following device power-up reset, asynchronous page mode default read mode partitions Read Array. However, perform array reads after other device operation (e.g. write operation), Read Array command must issued order read from flash memory array.
Note:
Asynchronous page-mode reads only performed when Read Configuration Register RCR[15] (see Section 14.0, "Set Read Configuration Register" page 84). perform asynchronous page mode read, address driven onto A[MAX:0], CE#, ADV# asserted. RST# must deasserted. WAIT asserted during asynchronous page mode. ADV# driven high latch address, must held throughout read cycle. used asynchronous page-mode reads, ignored. only asynchronous reads performed, should tied valid level, WAIT signal floated ADV# must tied ground. Array data driven onto DQ[15:0] after initial access time tAVQV delay. (see Section 7.0, Characteristics" page 29). asynchronous page mode, four data words "sensed" simultaneously from flash memory array loaded into internal page buffer. buffer word corresponding initial address A[MAX:0] driven onto DQ[15:0] after initial access delay. Address bits A[MAX:2] select 4-word page. Address bits A[1:0] determine which word 4-word page output from data buffer given time.
10.2
Synchronous Burst Read Mode
perform synchronous burst- read, initial address driven onto A[MAX:0], asserted. RST# must deasserted. ADV# asserted, then deasserted latch address. Alternately, ADV# remain asserted throughout burst access, which case address latched next valid edge after ADV# asserted. Section 14.0, "Set Read Configuration Register" page During synchronous array non-array read modes, first word output from data buffer next valid edge after initial access latency delay (see Section 14.2, "First Access Latency Count (RCR[13:11])" page 86). Subsequent data output valid edges
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following minimum delay. However, synchronous non-array read, same word data will output successive clock edges until burst length requirements satisfied. Section 7.0, Characteristics" page
10.3
Read Array
Read Array command places resets) partition read-array mode used read data from flash memory array. Upon initial device power-up, after reset (RST# transitions from VIH), partitions default asynchronous read-array mode. read array data from flash device, first write Read Array command (FFh) specify desired word address. Then read from that address. partition already read-array mode, issuing Read Array command required read from that partition. Read Array command written partition that erasing programming, device presents invalid data until program erase operation completes. After program erase finishes that partition, valid array data then read. Erase Suspend Program Suspend command suspends WSM, subsequent Read Array command places addressed partition read-array mode. Read Array command functions independently VPP.
10.4
Read Identifier
Read Identifier mode outputs manufacturer/device identifier, block lock status, protection register codes, Configuration Register data. identifier information contained within separate memory space device accessed along 4-Mbit partition address range supplied Read Identifier command (90h) address. Reads from addresses Table retrieve information. Issuing Read Identifier command partition that programming erasing places that partition's outputs read mode while partition continues program erase background.
Table
Device Identification Codes (Sheet
Address1 Item Base Manufacturer Partition Offset 0089h 8862h 8863h 8864h Device Partition 8865h 8866h 8867h Block Lock Status(2) Block Block Lock-Down Status(2) Configuration Register Block Partition Register Data Block locked down Block locked Block locked-down 64-Mbit 128-Mbit 128-Mbit Block unlocked Intel 32-Mbit 32-Mbit 64-Mbit Data Description
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Table
Device Identification Codes (Sheet
Address1 Item Base Protection Register Lock Status Protection Register Partition Partition Offset Lock Data Register Data Multiple reads required read entire 128-bit Protection Register. Data Description
Notes: address constructed from base address plus offset. example, read Block Lock Status block number BPD, address (0F8000h) plus offset (02h), i.e. 0F8002h. Then examine data determine block locked. Section 13.1.4, "Block Lock Status" page valid lock status.
10.5
Query
This device contains separate query database that acts "on-chip datasheet." information within this device accessed issuing Read Query command supplying specific address. address constructed from base address partition plus particular offset corresponding desired field. Appendix "Common Flash Interface (CFI)" page shows accessible fields their address offsets. Issuing Read Query command partition that programming erasing puts that partition read query mode while partition continues program erase background.
10.6
Read Status Register
device's Status Register displays program erase operation status. partition's status read after writing Read Status Register command location within partition's address range. Read-status mode default read mode following Program, Erase, Lock Block command sequence. Subsequent single reads from that partition will return status until another valid command written. read-status mode supports single synchronous single asynchronous reads only; doesn't support burst reads. first falling edge latches updates Status Register data. operation doesn't affect other partitions' modes. Because Status Register bits wide, only [7:0] contains valid Status Register data; [15:8] contains zeros. Table "Status Register Definitions" page Table "Status Register Descriptions" page Each 4-Mbit partition contains Status Register. Bits SR[6:0] unique each partition, SR[7], Device Status (DWS) bit, pertains entire device. SR[7] provides program erase status entire device. contrast, Partition Status (PWS) bit, SR[0], provides program erase status addressed partition only. Status register bits SR[6:1] present information about partition-specific program, erase, suspend, VPP, block-lock states. Table "Status Register Device Partition Write Status Description" page presents descriptions (SR[7]) (SR[0]) combinations.
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Table
Status Register Definitions
VPPS
Table
Status Register Descriptions
Name State Device Busy Device Ready Erase progress/completed Erase suspended Erase successful Erase error Program successful Program error detect, operation aborted Program progress/completed Program suspended Unlocked Aborted erase/program attempt locked block This partition busy, only SR[7]=0 Another partition busy, only SR[7]=0 Description SR[7] indicates erase program completion device. SR[6:1] invalid while SR[7] Table valid SR[7] SR[0] combinations. After issuing Erase Suspend command, halts sets SR[7] SR[6]. SR[6] remains until device receives Erase Resume command. SR[5] attempted erase failed. Command Sequence Error indicated when SR[7,5:4] set. SR[4] failed program word. indicates level after program erase completes. SR[3] does provide continuous feedback isn't guaranteed when VPP1/2. After receiving Program Suspend command, halts execution sets SR[7] SR[2]. They remain until Resume command received. erase program operation attempted locked block VIL), sets SR[1] aborts operation. Addressed partition erasing programming. mode, SR[0] indicates that data-stream word finished programming verifying depending particular phase. Table valid SR[7] SR[0] combinations.
Device Status Erase Suspend Status Erase Status Program Status VPPS Status
Program Suspend Status Device Protect Status
Partition Write Status
Table
(SR[7])
Status Register Device Partition Write Status Description
(SR[0]) Description addressed partition performing program/erase operation. EFP: device finished programming verifying data, ready data. partition other than currently addressed performing program/erase operation. EFP: device either programming verifying data. program/erase operation progress partition. Erase Program suspend bits (SR[6,2]) indicate whether other partitions suspended. EFP: device exited mode. Won't occur standard program erase modes. EFP: this combination does occur.
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10.7
Clear Status Register
Clear Status Register command clears Status Register leaves partition output states unchanged. Status Register bits clear bits SR[7:6,2,0]. Because bits SR[5,4,3,1] indicate various error conditions, they only cleared Clear Status Register command. allowing system software reset these bits, several operations (such cumulatively programming several addresses erasing multiple blocks sequence) performed before reading Status Register determine error occurrence. error detected, Status Register must cleared before beginning another command sequence. Device reset (RST# VIL) also clears Status Register. This command functions independently VPP.
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11.0
11.1
Program Operations
Word Program
When Word Program command issued, executes sequence internally timed events program word desired address verify that bits sufficiently programmed. Programming flash array changes specifically addressed bits bits change memory cell contents. Programming occur only partition time. other partitions must either read mode erase suspend mode. Only partition erase suspend mode time. Status Register examined program progress reading address within partition that busy programming. However, while most Status Register bits partition-specific, Device Status bit, SR[7], device-specific; that Status Register read from other partition, SR[7] indicates program status entire device. This permits system monitor program progress while reading status other partitions. toggle (during polling) updates Status Register. Several commands issued partition that programming: Read Status Register, Program Suspend, Read Identifier, Read Query. Read Array command also issued, read data indeterminate. After programming completes, three Status Register bits signify various possible error conditions. SR[4] indicates program failure set. SR[3] set, couldn't execute Word Program command because outside acceptable limits. SR[1] set, program aborted because attempted program locked block. After Status Register data examined, clear with Clear Status Register command before command issued. partition remains Status Register mode until another command written that partition. command issued after Status Register indicates program completion. deasserted while device programming, devices will enter standby mode until program operation completes.
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Figure
Word Program Flowchart
WORD PROGRAM PROCEDURE
Start Command Operation Write Program Setup Data Comments Data Addr Location program (WA) Data Data program (WD) Addr Location program (WA) Read Toggle update Check SR[7] ready busy
Write 40h, Word Address Write Data Word Address
Write
Read Read Status Register
Suspend Program Loop Suspend Program
Standby
SR[7]
Repeat subsequent programming operations. Full status register check done after each program after sequence program operations.
Full Program Status Check desired) Program Complete
FULL PROGRAM STATUS CHECK PROCEDURE
Read Status Register Command Operation Standby SR[3]
Comments Check SR[3] error Check SR[4] Data program error Check SR[1] Attempted program locked block Program aborted
Range Error Standby Program Error
SR[4]
Standby
SR[1]
Device Protect Error
SR[3] MUST cleared before will allow further program attempts Only Clear Staus Register command clears SR[4:3,1]. error detected, clear status register before attempting program retry other error recovery.
Program Successful
11.2
Factory Programming
standard factory programming mode uses same commands algorithm Word Program mode (40h/10h). When VPP1, program erase currents drawn through VCC. driven logic signal, VPP1 must remain above VPP1Min value perform insystem flash modifications. When connected power supply, device draws program erase current directly from VPP. This eliminates need external switching transistor control voltage. Figure "Examples Power Supply Configurations" page shows examples flash power supply usage various configurations.
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12-V mode enhances programming performance during short time period typically found manufacturing processes; however, intended extended use.12 applied during program erase operations specified Section 5.0, "Maximum Ratings Operating Conditions" page connected total tPPH hours maximum. Stressing device beyond these limits cause permanent damage.
11.3
Enhanced Factory Program (EFP)
substantially improves device programming performance through number enhancements conventional Volt word program algorithm. EFP's more efficient algorithm eliminates traditional overhead delays conventional word program mode both host programming system flash device. Changes conventional word programming flowchart internal routine were developed because today's beat-rate-sensitive manufacturing environments; balance between programming speed cycling performance attained. host programmer writes data device checks Status Register determine when data completed programming. This modification essentially cuts write cycles half. Following each internal program pulse, increments device's address next physical location. Now, programming equipment sequentially stream program data throughout entire block without having setup present each address. combination, these enhancements reduce much host programmer overhead, enabling more data streaming approach device programming. further speeds programming performing internal code verification. With this, PROM programmers rely device verify that been programmed properly. From device side, streamlines internal overhead eliminating delays previously associated switch voltages between programming verify levels each memory-word location. consists four phases: setup, program, verify exit. Refer Figure "Enhanced Factory Program Flowchart" page detailed graphical representation implement EFP.
11.3.1
Requirements Considerations
Ambient temperature: Requirements within specified operating range within specified VPP2 range Target block unlocked Block cycling below erase cycles supported2 Considerations programs block time cannot suspended Notes: Recommended optimum performance. Some degradation performance occur this limit exceeded, internal algorithm will continue work properly. Code data cannot read from another partition during EFP.
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11.3.2
Setup
After receiving Setup (30h) Confirm (D0h) command sequence, SR[7] transitions from indicating that busy with algorithm startup. delay before checking SR[7] required allow time perform setups checks (VPP level block lock status). error detected, Status Register bits SR[4], SR[3], and/or SR[1] operation terminates.
Note:
After Setup Confirm command sequence, reads from device automatically output Status Register data. issue Read Status Register command; will interpreted data program WA0.
11.3.3
Program
After setup completion, host programming system must check SR[0] determine "data-stream ready" status (SR[0]=0). Each subsequent write after this program-data write flash array. Each cell within memory word programmed receives pulse; additional pulses, required, occur verify phase. SR[0]=1 indicates that busy applying program pulse. host programmer must poll device's Status Register "program done" state after each data-stream write. SR[0]=0 indicates that appropriate cell(s) within accessed memory location have received their single program pulse, that device ready next word. Although host check full status errors time, only necessary block basis, after exit. Addresses must remain within target block. Supplying address outside target block immediately terminates program phase; then enters verify phase. address either hold constant increment. device compares incoming address that stored from setup phase (WA0); they match, programs data word next sequential memory location. they differ, jumps address location. program phase concludes when host programming system writes different block address, data supplied must FFFFh. Upon program phase completion, device enters verify phase.
11.3.4
Verify
high percentage flash bits program first pulse. However, those cells that completely program their first attempt, internal verification identifies them applies additional pulses required. verify phase identical flow program phase, except that instead programming incoming data, compares verify-stream data that which previously programmed into block. data compares correctly, host programmer proceeds next word. not, host waits while applies additional pulse(s). host programmer must reset initial verify-word address same starting location supplied during program phase. then reissues each data word same order during program phase. Like programming, host write each subsequent data word increment through block addresses.
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verification phase concludes when interfacing programmer writes different block address; data supplied must FFFFh. Upon completion verify phase, device enters exit phase.
11.3.5
Exit
SR[7]=1 indicates that device returned normal operating conditions. full status check should performed this time ensure entire block programmed successfully. After exit, valid command issued.
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Figure
Enhanced Factory Program Flowchart
ENHANCED FACTORY PROGRAMMING PROCEDURE Setup
Start
Program
Read Status Register
Verify
Read Status Register
Exit
Read Status Register
Unlock Block
SR[0]=1=N
Data Stream Ready? SR[0] =0=Y Write Data Address
SR[0]=1=N Verify Stream Ready? SR[0] =0=Y Write Data Address
SR[7]=0=N
Exited? SR[7]=1=Y
Write Address
Full Status Check Procedure
Write Address
setup time
Read Status Register
Program Done? SR[0]=0=Y
Read Status Register
Read Status Register
Operation Complete
Verify Done? SR[0]=0=Y
Setup Done? SR[7]=1=N Check Lock errors (SR[3,1])
Last Data? Write FFFFh Address
Last Data? Write FFFFh Address
Exit
Setup
State Write Write Write Standby Read Unlock Block Setup Comments Unlock block Data Address State Read
Program
Comments Status Register State Read
Verify
Comments Status Register
Data Check SR[0] Standby Stream Ready data Ready? ready data Write (note Read Data Data program Address Status Register
Verify Check SR[0] Standby Stream Ready verify Ready? ready verify Write (note Read Standby (note Standby Verify Done? Last Data? Exit Verify Phase Data Word verify Address Status Register Check SR[0] Verify done Verify done Device automatically increments address. Data FFFFh Address within same
Data Confirm Address setup time
Status Register Check SR[7] Standby Setup ready Done? ready SR[7] Error Check SR[3,1] Standby Condition SR[3] error Check SR[1] locked block
Check SR[0] Program Program done Standby Done? Program done Standby Last Data? Device automatically increments address.
Write
Exit Data FFFFh Program Address within same Phase
Write
Exit
first Word Address programmed within target block. (Block Base Read Status Register Address) must remain constant throughout program phase data stream; held Check SR[7] constant first address location, written sequence through addresses Exit finished Standby within block. Writing equal that block currently being written Exited? Exit completed terminates program phase, instructs device enter verify phase. proper verification occur verify data stream must presented device Repeat subsequent operations. same sequence that program phase data stream. Writing equal After exit, Full Status Check terminates verify phase, instructs device exit determine program error occurred. Bits that fully program with single pulse program phase receive additional program-pulse attempts during verify phase. device will report program failure setting SR[4]=1; this check performed during full status check afterSee Full Status Check procedure Word Program flowchart. been exited that block, will indicate error within entire data stream.
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12.0
12.1
Program Erase Operations
Program/Erase Suspend Resume
Program Suspend Erase Suspend commands halt in-progress program erase operation. command issued device address. partition corresponding command's address remains previous state. suspend command allows data accessed from memory locations other than being programmed block being erased. program operation suspended only perform read operation. erase operation suspended perform either program read operation within block, except block that erase suspended. program command nested within suspended erase subsequently suspended read another location. Once program erase process starts, Suspend command requests that suspend program erase sequence predetermined points algorithm. partition that actually suspended continues output Status Register data after Suspend command written. operation suspended when status bits SR[7] SR[6] and/or SR[2] set. read data from blocks within partition (other than erase-suspended block), write Read Array command. Block erase cannot resume until program operations initiated during erase suspend complete. Read Array, Read Status Register, Read Identifier (ID), Read Query, Program Resume valid commands during Program Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Erase Resume, Lock Block, Unlock Block, LockDown Block valid commands during erase suspend. read data from block partition that programming erasing, operation does need suspended. other partition already Read Array, Query mode, issuing valid address returns corresponding data. other partition read mode, read commands must issued partition before data read. During suspend, places device standby state, which reduces active current. must remain program level must remain unchanged while suspend mode. resume command instructs continue programming erasing clears Status Register bits SR[2] SR[6]) SR[7]. Resume command written partition. When read partition that programming erasing, device outputs data corresponding partition's last mode. Status Register error bits set, Status Register cleared before issuing next instruction. RST# must remain VIH. Figure "Program Suspend Resume Flowchart" page Figure "Erase Suspend Resume Flowchart" page suspended partition placed Read Array, Read Status Register, Query mode during suspend, device remains that mode outputs data corresponding that mode after program erase operation resumed. After resuming suspended operation, issue read command appropriate read operation. read status after resuming suspended operation, issue Read Status Register command (70h) return suspended partition status mode.
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Figure
Program Suspend Resume Flowchart
PROGRAM SUSPEND RESUME PROCEDURE
Start
Program Suspend
Command Operation Write
Comments
Write Address
Read Status
Program Data Suspend Addr Block suspend (BA) Read Status Data Addr Same partition Status register data Toggle update Status register Addr Suspended block (BA) Check SR.7 ready busy Check SR.2 Program suspended Program completed Read Array Data Addr address within suspended partition Read array data from block other than being programmed Program Data Resume Addr Suspended block (BA)
Write
Write Same Partition Read Status Register Read
SR.7
Standby
SR.2
Read Array
Program Completed
Standby
Write
Write Susp Partition Read Read Array Data
Write
Done Reading
Program Resume
suspended partition placed Read Array mode: Write
Read Array
Read Status
Return partition Status mode: Data Addr Same partition
Write Address Program Resumed
Read Status
Write Pgm'd Partition Read Array Data
Write Same Partition
PGM_SUS.WMF
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Figure
Erase Suspend Resume Flowchart
ERASE SUSPEND RESUME PROCEDURE
Start
Erase Suspend
Command Operation Write Erase Suspend Read Status
Comments Data Addr address Data Addr Same partition Status register data. Toggle update Status register Addr Same partition Check SR.7 ready busy Check SR.6 Erase suspended Erase completed
Write Address
Read Status
Write
Write Same Partition Read Read Status Register Standby SR.7
Standby Erase Completed Write Read Write Write Program Resume
SR.6
Read Array Data Program Addr Block program read Read array program data from/to block other than being erased Data Addr address
Read
Read Program?
Program
Read Array Data
Program Loop
Done?
Erase Resume Read Array
suspended partition placed Read Array mode Program Loop: Write Read Status Return partition Status mode: Data Addr Same partition
Write Address
Write Erased Partition Read Array Data
Erase Resumed
Read Status
Write Same Partition
ERAS_SUS.WMF
12.2
Block Erase
2-cycle block erase command sequence, consisting Erase Setup (20h) Erase Confirm (D0h), initiates block erase addressed block. Only partition erase mode time; other partitions must read mode. Erase Confirm command internally latches address block erased. Erase forces bits within block SR[7] cleared while erase executes.
Intel® Wireless Flash Memory (W18) Order Number: 290701, Revision:
January 2005
Intel® Wireless Flash Memory (W18)
After writing Erase Confirm command, selected partition placed read Status Register mode reads performed that partition return current status data. address given during Erase Confirm command does need same address used Erase Setup command. Erase Confirm command given partition then selected block partition will erased even Erase Setup command partition 2-cycle erase sequence cannot interrupted with write operation. example, Erase Setup command must immediately followed Erase Confirm command order execute properly. different command issued between setup confirm commands, partition placed read-status mode, Status Register signals command sequence error, subsequent erase commands that partition ignored until Status Register cleared. detect block erase completion analyzing SR[7] that partition. error (SR[5,3,1]) flagged, Status Register cleared issuing Clear Status Register command before attempting next operation. partition remains read-status mode until another command written CUI. instruction follow after erasing completes. read-array mode prevent inadvertent Status Register reads.
January 2005
Intel® Wireless Flash Memory (W18) Order Number: 290701, Revision:
Intel® Wireless Flash Memory (W18)
Figure
Block Erase Flowchart
BLOCK ERASE PROCEDURE
Start Command Comments Operation Block Data Write Erase Addr Block erased (BA) Setup Write Write Block Address Read Read Status Register
Write Block Address
Erase Confirm
Data Addr Block erased (BA) Read Toggle update Check SR[7] ready busy
Suspend Erase Loop Suspend Erase
Standby
SR[7]
Repeat subsequent block erasures. Full status register check done after each block erase after sequence block erasures.
Full Erase Status Check desired) Block Erase Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status Register Range Error Standby
Command Operation Standby Check SR[3] error
Comments
SR[3]
Check SR[5:4] Both Command sequence error Check SR[5] Block erase error Check SR[1] Attempted erase locked block Erase aborted
SR[5:4]
Command Sequence Error Block Erase Error Erase Locked Block Aborted
Standby
SR[5]
Standby
SR[1]
SR[3,1] must cleared before will allow further erase attempts. Only Clear Status Register command clears SR[5:3,1]. error detected, clear Status register before attempting erase retry other error recovery.
Block Erase Successful
12.3
Read-While-Write Read-While-Erase
Intel® Wireless Flash Memory (W18) supports flexible multi-partition dual-operation architecture. dividing flash memory into many separate partitions, device read from partition while programing erasing another partition; hence terms, RWE. Both these features greatly enhance data storage performance.
Intel® Wireless Flash Memory (W18) Order Number: 290701, Revision:
January 2005
Intel® Wireless Flash Memory (W18)
product does support simultaneous program erase operations. Attempting perform operations such these results command sequence error. Only partition programming erasing while another partition reading. However, partition erase suspend mode while second partition performing program operation, another partition executing read command. Table "Command Codes Descriptions" page describes command codes available functions.
January 2005
Intel® Wireless Flash Memory (W18) Order Number: 290701, Revision:
Intel® Wireless Flash Memory (W18)
13.0
Security Modes
Intel Wireless Flash Memory offers both hardware software security features protect flash data. software security feature used executing Lock Block command. hardware security feature used executing Lock-Down Block command asserting signal. Refer Figure "Block Locking State Diagram" page state diagram flash security features. Also Figure "Locking Operations Flowchart" page
13.1
Block Lock Operations
Individual instant block locking protects code data allowing block locked unlocked with latency. This locking scheme offers levels protection. first allows software-only control block locking (useful frequently changed data blocks), while second requires hardware interaction before locking changed (protects infrequently changed code blocks). following sections discuss locking system operation. term "state [abc]" specifies locking states; example, "state [001]," where value, block lock-down status Block Lock Status Register Figure "Block Locking State Diagram" page defines possible locking states. following summarizes locking functionality.
blocks power-up locked state. Unlock commands unlock these blocks, lock commands lock them again. Lock-Down command locks block prevents from being unlocked when
asserted. Locked-down blocks unlocked locked with commands long deasserted. lock-down status cleared only when device reset powered-down.
Block lock registers affected level. They modified read even VPPLK. Each block's locking status locked, unlocked, lock-down, described following sections. Figure "Locking Operations Flowchart" page
Intel® Wireless Flash Memory (W18) Order Number: 290701, Revision:
January 2005
Intel® Wireless Flash Memory (W18)
Figure
Block Locking State Diagram
Power-Up/Reset
Locked [X01]
LockedDown4,5 [011]
Hardware Locked5 [011]
Hardware Control
Unlocked [X00]
Software Locked [111]
Unlocked [110]
Software Block Lock (0x60/0x01) Software Block Unlock (0x60/0xD0) Software Block Lock-Down (0x60/0x2F) hardware control
Notes:
[a,b,c] represents [WP#, D0]. Don't Care. indicates block Lock-down status. `0', Lock-down been issued this block. `1', Lock-down been issued this block. indicates block lock status. `0', block unlocked. `1', block locked. Locked-down Hardware Software locked. [011] states should tracked system software determine difference between Hardware Locked Locked-Down states.
13.1.1
Lock
blocks default locked (state [x01]) after initial power-up reset. Locked blocks fully protected from alteration. Attempted program erase operations locked block will return error SR[1]. Unlocked blocks locked using Lock Block command sequence. Similarly, locked block's status changed unlocked lock-down using appropriate software commands.
13.1.2
Unlock
Unlocked blocks (states [x00] [110]) programmed erased. unlocked blocks return locked state when device reset powered-down. unlocked block's status changed locked locked-down state using appropriate software commands. locked block unlocked writing Unlock Block command sequence block lockeddown.
13.1.3
Lock-Down
Locked-down blocks (state [011]) offer user additional level write protection beyond that regular locked block. block that locked-down cannot have it's state changed software asserted. locked unlocked block locked-down writing Lock-Down Block command sequence. block locked-down, then later changed unlocked, Lock-
January 2005
Intel® Wireless Flash Memory (W18) Order Number: 290701, Revision:
Intel® Wireless Flash Memory (W18)
Down command should issued prior asserting will that block back locked-down state. When deasserted, locked-down blocks changed locked state then unlocked Unlock Block command.
13.1.4
Block Lock Status
Every block's lock status read read identifier mode. enter this mode, issue Read Identifier command device. Subsequent reads will output that block's lock status. example, read block lock status block address sent device should 50002h (for top-parameter device). lowest data bits read data, DQ0, represent lock status. indicates block lock status. Lock Block command cleared Block Unlock command. also when entering lock-down state. indicates lock-down status Lock-Down command. lock-down status cannot cleared software-only device reset power-down. Table
Table
Write Protection Truth Table
RST# Write Protection Device inaccessible Word program block erase prohibited lock-down blocks locked lock-down blocks

28F320W18, 28F640W18, 28F128W18 High Performance Read-While-Write

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