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OMAP5912 Applications Processor

Literature Number: SPRS231B December 2003 - Revised March 2004

OMAP5912 Applications Processor
Data Manual
Literature Number: SPRS231B December 2003 - Revised March 2004
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Revision History
REVISION HISTORY
This data sheet revision history highlights the technical changes made to SPRS231A to generate SPRS231B. Scope: SPRS231B is the only revision of this document that has been released.
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Revision History
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Contents
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Contents
Page 153 154 154 155 155 156 157 157 157 158 158 160 160 161 162 162 163 164 165 166 167 167 167 168 168 168 168 168 169 169 170
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Contents
Page 181 181 182 183 183 190 194 198 204 208 212 212 217 221 223 224 224 225 226 227 228 230 232 234 235 236 237 239
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Figures
List of Figures
Figure 2-1 2-2 OMAP5912 289-Ball ZDY Plastic Ball Grid Array (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5912 289-Ball ZZG Plastic Ball Grid Array (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18 19
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Figures
Page 207 207 210 210 211 215 216 217 218 219 220 222 222 223 225 226 227 229 229 230 231 232 232 233 233 234 235 236 237 237 238 238 238 238 239 240
OMAP5912 289-Ball Plastic Ball Grid Array Package (ZDY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5912 289-Ball MicroStar BGA Plastic Ball Grid Array Package (ZZG) . . . . . . . . . . . . . . . . . .
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Tables
List of Tables
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Tables
Table 3-35 3-36 3-37 3-38 3-39 3-40 3-41 3-42 3-43 3-44 3-45 3-46 3-47 3-48 3-49 3-50 3-51 3-52 3-53 3-54 3-55 3-56 3-57 3-58 3-59 3-60 3-61 3-62 3-63 3-64 3-65 3-66 3-67 3-68 3-69 3-70 3-71 3-72 3-73 3-74 I2C1 Registers ...................................
Page 118 119 119 120 120 121 122 122 123 123 124 124 125 126 127 128 130 130 131 132 132 132 133 133 133 134 134 135 135 136 136 136 137 137 138 139 141 141 142 142
General-Purpose Timer6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Timer7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC / SDIO2 Registers UART3 Registers ............................... ..................................
MCSI1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCSI2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP3 Registers ................................. ........................ ...................... MPU UART TIPB Bus Switch Registers OMAP5912 Configuration Registers
Ultra Low-Power Device Peripheral Registers
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Tables
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Tables
Page 223 223 224 224 225 225 226 227 228 230 230 232 232 234 235 236 236 237 237 239
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Tables
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Features
OMAP5912 Features
D Low-Power, High-Performance CMOS
D MPU Peripherals
All trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture.
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PRODUCT PREVIEW
Introduction
This section describes the main features of the OMAP5912 device, lists the terminal assignments, and describes the function of each terminal. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging.
Description
OMAP5912 is a highly integrated hardware and software platform, designed to meet the application processing needs of next-generation embedded devices. The OMAP platform enables OEMs and ODMs to quickly bring to market devices featuring rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture provides benefits of both DSP and reduced instruction set computer (RISC) technologies, incorporating a TMS320C55x DSP core and a high-performance ARM926EJ-S ARM core. The OMAP5912 device is designed to run leading open and embedded RISC-based operating systems, as well as the Texas Instruments (TI) DSP / BIOS software kernel foundation, and is available in two 289-ball lead-free ball grid array (BGA) packages (ZDY and ZZG). The OMAP5912 device is targeted at the following applications: · · Applications Processing Devices Mobile Communications - - - - · · · · · · WAN 802.11X Bluetooth GSM, GPRS, EDGE CDMA
PRODUCT PREVIEW
Video and Image Processing (MPEG4, JPEG, Windows Media Video, etc.) Advanced Speech Applications (text-to-speech, speech recognition) Audio Processing (MPEG-1 Audio Layer3 MP3, AMR, WMA, AAC, and Other GSM Speech Codecs) Graphics and Video Acceleration Generalized Web Access Data Processing
TMS320C55x, C55x, VLYNQ, OMAP, and DSP / BIOS are trademarks of Texas Instruments. ARM926EJ-S and ETM9 are trademarks of ARM Limited in the EU and other countries. Thumb and ARM are registered trademarks of ARM Limited in the EU and other countries. 1-Wire is a registered trademark of Dallas Semiconductor Corporation. CompactFlash is a trademark of CompactFlash Association. Bluetooth is a trademark owned by Bluetooth SIG, Inc. Windows is a registered trademark of Microsoft Corporation in the United States and / or other countries.
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Introduction
2.1.1 TMS320C55x DSP Core
The DSP core of the OMAP5912 device is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity. The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic / logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the address unit (AU) and data unit (DU) of the C55x CPU. The C55x DSPs support a variable byte width instruction set for improved code density. The instruction unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the program unit (PU). The program unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The OMAP5912 DSP core also includes a 24K-byte instruction cache to minimize external memory accesses, improving data throughput and conserving system power.
DSP Tools Support
DSP Software Support
Texas Instruments has also developed foundation software available for the 55x DSP core. The C55x DSP Library (DSPLIB) features over 50 C-callable software routines (FIR / IIR filters, Fast Fourier Transforms (FFTs), and various computational functions). The DSP Image / Video Processing Library (IMGLIB) contains over 20 software routines highly optimized for C55x DSPs and is compiled with the latest revision of the C55x DSP code generation tools. These imaging functions support a wide range of applications that include compression, video processing, machine vision, and medical imaging.
eXpressDSP, Code Composer Studio, TMS320, RTDX, and XDS510 are trademarks of Texas Instruments. 17
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PRODUCT PREVIEW
Introduction
2.1.2 ARM926EJ-S RISC Processor
The MPU core is a ARM926EJ-S reduced instruction set computer (RISC) processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The MPU core incorporates: · · · A coprocessor 15 (CP15) and protection module Data and program Memory Management Units (MMUs) with table look-aside buffers. Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).
The OMAP5912 device uses the ARM926EJ-S core in little-endian mode only. To minimize external memory access time, the ARM926EJ-S includes an instruction cache, data cache, and a write buffer. In general, these are transparent to program execution.
Terminal Assignments
Figure 2-1 illustrates the ball locations for the 289-ball ZDY package and Figure 2-2 illustrates the ball locations for the 289-ball ZZG package. Figure 2-1 and Figure 2-2 are used in conjunction with Table 2-1 and Table 2-2, respectively, to locate signal names and ball grid numbers. BGA ball numbers in Table 2-1 and Table 2-2 are read from left-to-right, top-to-bottom.
PRODUCT PREVIEW
Bottom View
Figure 2-1. OMAP5912 289-Ball ZDY Plastic Ball Grid Array (Bottom View)
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Introduction
Figure 2-2. OMAP5912 289-Ball ZZG Plastic Ball Grid Array (Bottom View) In Table 2-1 and Table 2-2, signals with multiplexed functions are highlighted in gray. Signals within a multiplexed pin name are separated with forward slashes as follows: · signal1 / signal2 / signal3 (e.g., MPUIO1 / RTCK / SPIF.SCK)
Signals which are associated with specific peripherals are denoted by using the peripheral name, followed by a period, and then the signal name as follows: · peripheral1.signal1 (i.e., MCSI1.DOUT)
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PRODUCT PREVIEW
Introduction
Table 2-1. ZDY Package Terminal Assignments
A17 B4 B8
DVDD5 SDRAM.D1 SDRAM.D12
B2 B6 B10
B3 B7 B11
PRODUCT PREVIEW
SDRAM.D9
SDRAM.CKE
B16 C3 C7
B17 C4 C8
C2 C6 C10
FLASH.A2(0) SDRAM.A8 SDRAM.D14
DVDD1
C15 D2 D6
C16 D3 D7
C17 D4 D8
SDRAM.A13
DVDD4
D14 E1 E5
D15 E2 E6
D16 E3 E7
D17 E4 E8
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Introduction
Table 2-1. ZDY Package Terminal Assignments (Continued)
SDRAM.A11
SDRAM.A6
VSS KB.R1(0) / MPUIO9(1) / VLYNQ.RX0(2) FLASH.A20
E17 F4
FLASH.A11(0) FLASH.A12(0)
SDRAM.A10
SDRAM.A9
VSS MCBSP1.CLKX(0) / GPIO54(7) FLASH.A13(0) VSS
KB.R4(0) / MPUIO15(1) / VLYNQ.TX1(2) KB.C5(0) / GPIO28(7) FLASH.A14(0) CVDD2
F16 G3 G7
F17 G4 G8
G2 G6 G10
DVDD1
MCBSP1.FSX(0) / MCBSP1.DX(1) / MCBSP1.DXZ(2) GPIO53(7) FLASH.A22 FLASH.ADV
CAM.LCLK(0) / ETM.CLK(1) / UWIRE.SCLK(2) / GPIO39(7) FLASH.A18 CVDD2
LDO.FILTER
FLASH.A21 VSS CAM.D3(0) / ETM.D3(1) / UART3.RX(2) / GPIO31(7)
CVDD3
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PRODUCT PREVIEW
Introduction
Table 2-1. ZDY Package Terminal Assignments (Continued)
ZDY BALL NO. SIGNAL ZDY BALL NO. SIGNAL CAM.D6(0) / ETM.D6(1) / UWIRE.CS3(2) / MMC2.CMD / SPI.DO(3) / GPIO34(7) FLASH.A23 ZDY BALL NO. SIGNAL ZDY BALL NO. SIGNAL
CAM.D7(0) / ETM.D7(1) / UWIRE.CS0(2) / MMC2.DAT2(3) / GPIO35(7) FLASH.CS1(0) / FLASH.CS1L(1)
CAM.D5(0) / ETM.D5(1) / UWIRE.SDI(2) / GPIO33(7)
FLASH.BE0(0) / FLASH.CS2UOE(1) / GPIO59(7) GPIO62(0) / FLASH.CS0(1)
FLASH.A24 FLASH.CS2(0) / FLASH.BAA(1) / FLASH.CS2L(2) CAM.HS(0) / ETM.PSTAT1(1) / UART2.CTS(2) / MMC2.DAT0 / SPI.DI(3) / GPIO38(7) CAM.D1(0) / ETM.D1(1) / UART3.RTS(2) / GPIO29(7)
FLASH.CS3(0) / GPIO3(7)
FLASH.D3
PRODUCT PREVIEW
CVDD3
CAM.D4(0) / ETM.D4(1) / UART3.TX(2) / GPIO32(7)
CAM.D2(0) / ETM.D2(1) / UART3.CTS(2) / GPIO30(7)
DVDD8
FLASH.CLK(0) / FLASH.CS2UOE(1)
FLASH.CS2U(0) / GPIO5(1)
K6 K10
K7 K11
FLASH.D12 CVDD3 UART3.RX(0) / PWL(1) / UART2.RX(3) / TIMER.PWM1(4) / GPIO49(7)
FLASH.D0
FLASH.D2
DVDD5
FLASH.D8
FLASH.RDY(0) / GPIO10(1)
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Introduction
Table 2-1. ZDY Package Terminal Assignments (Continued)
CVDDRTC
FLASH.D4 VSS
FLASH.D11 CVDD I2C.SDA(0) / GPIO48(7)
FLASH.OE UART1.CTS(0) / UART1.IRSEL(2) / GPIO38(7) DVDD9 GPIO4(0) / SPI.CS2(1) / MCBSP3.FSX(2) / TIMER.EVENT4(3) / SPIF.DIN(4) FLASH.D15
GPIO1(0) / UART3.RTS(1)
GPIO2(0) / SPI.CLK(1) / ETM.PSTAT4(5) / RTDX.D0 (7) FLASH.RP(0) / FLASH.CS2UWE(1) MMC.CMD / SPI.DO(0) / CFLASH.CD2(3) / SSI.CADATA(6) / GPIO55(7)
FLASH.D9 MCBSP2.FSX(0) / VLYNQ.RX1(3) / GPIO21(7) MCSI1.SYNC(0) / MCBSP3.DR(1) / USB1.VP(2) / MCBSP3.FSX(4)
MPUIO1(0) / RTCK(1) / SPIF.SCK(6)
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PRODUCT PREVIEW
GPIO7(0) / MMC.DAT2(1) / TCK(3) / MCSI1.CLK(4) / ETM.SYNC1(5) / RTDX.D2(7)
GPIO12(0) / MCBSP3.FSX(1) / TIMER.EXTCLK(3) / VLYNQ.RX04
FLASH.D1
Introduction
Table 2-1. ZDY Package Terminal Assignments (Continued)
FLASH.D13
FLASH.WE
UART2.CTS(0) / USB2.RCV(1) / GPIO7(2) / USB0.RCV(5)
PRODUCT PREVIEW
MMC.DAT3(0) / MPUIO9(1) / MPUIO6(2) / CFLASH.CD1(3) / SSI.ACFLAG(6)
UWIRE.SDI(0) / UART3.DSR(1) / UART1.DSR(2) / MCBSP3.DR(3) / SPIF.DIN(6) / GPIO47(7) FLASH.D14
FLASH.WP
MCBSP2.FSR(0) / GPIO12(1) / VLYNQ.RX0(3)
MPUIO3(0) / MMC2.DAT1(6)
DVDDRTC
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Introduction
Table 2-1. ZDY Package Terminal Assignments (Continued)
ZDY BALL NO. SIGNAL UWIRE.SDO(0) / UART3.DTR(1) / UART1.DTR(2) / MCBSP3.DX(3) / UART3.RTS(4) / MCBSP3.DXZ(5) / SPIF.DOUT(6) / GPIO46(7) ZDY BALL NO. SIGNAL ZDY BALL NO. SIGNAL ZDY BALL NO. SIGNAL
FLASH.CS1U(0) / GPIO16(7)
USB.DP(0) / I2C.SDA(4) UART1.RX(5) / USB.PUEN(7)
CVDD1
MCBSP2.DX(0) / MCBSP2.DR(1) / MCBSP2.DXZ(2) / GPIO19(7)
DVDD3
DVDD6
DVDD7
TDO / VLYNQ.TX0
DVDD2
MCLK(0) / MMC2.DATDIR0(6) / GPIO24(7)
MCBSP2.CLKX(0) / VLYNQ.TX1(3) / GPIO20(7)
MCBSP2.CLKR(0) / GPIO11(1) / VLYNQ.CLK(3)
GPIO9(0) / EMU0(3) / MCSI1.SYNC(4) / MMC2.DAT0 / SPI.DI(6)
MMC.DAT1(0) / MPUIO10(1) / MPUIO7(2) / CFLASH.IREQ(3) / SSI.ACDATA(6)
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PRODUCT PREVIEW
Introduction
Table 2-1. ZDY Package Terminal Assignments (Continued)
UART1.RX(0) / UART1.IRRX(2) / GPIO37(7)
PRODUCT PREVIEW
26 SPRS231B
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Introduction
Table 2-2. ZZG Package Terminal Assignments
DVDD1
A21 B4 B8
VSS SDRAM.CAS SDRAM.A10
B2 B6 B10
B3 B7 B12
CVDD3
DVDD4
CVDD3
B21 C4 C8 C12
C1 C5 C9 C13
C2 C6 C10 C14
DVDD5 SDRAM.D1 SDRAM.D8 SDRAM.DQSH
C3 C7 C11 C15
C20 D4 D8
C21 D5 D9
D2 D6 D10
FLASH.A5(0) SDRAM.D0 SDRAM.DQMU
D3 D7 D11
SDRAM.D14
SDRAM.D13
SDRAM.D9
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SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-2. ZZG Package Terminal Assignments (Continued)
KB.C2(0) / GPIO61(7)
FLASH.A7(0) KB.R4(0) / MPUIO15(1) / VLYNQ.TX1(2) FLASH.A9(0)
DVDD1
FLASH.A6(0) VSS SDRAM.CS
F18 G2 G9
F19 G3 G10
F20 G4 G11
VSS FLASH.A10(0) SDRAM.A7 KB.R0(0) / MPUIO8(1) / VLYNQ.RX1(2)
PRODUCT PREVIEW
SDRAM.A6
G19 H3 H9
G20 H4 H10
G21 H7 H11
H2 H8 H12
DVDD5 SDRAM.WE SDRAM.CKE MCBSP1.DX(0) / MCBSP1.FSX(1) / MCBSP1.DXZ(2) / GPIO52(7)
MCBSP1.DR(0) / GPIO51(7)
LDO.FILTER
FLASH.A17
FLASH.A18 CAM.LCLK(0) / ETM.CLK(1) / UWIRE.SCLK(2) / GPIO39(7)
FLASH.A8(0) CAM.D7(0) / ETM.D7(1) / UWIRE.CS0(2) / MMC2.DAT2(3) / GPIO35(7)
FLASH.A1(0) CAM.D6(0) / ETM.D6(1) / UWIRE.CS3(2) / MMC2.CMD SPI.DO(3) / GPIO34(7)
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Introduction
Table 2-2. ZZG Package Terminal Assignments (Continued)
CVDD3
FLASH.A23 CAM.D1(0) / ETM.D1(1) / UART3.RTS(2) / GPIO29(7)
FLASH.A22
FLASH.A16(0)
FLASH.A13(0)
CAM.D2(0) / ETM.D2(1) / UART3.CTS(2) / GPIO30(7) NC
CAM.D4(0) / ETM.D4(1) / UART3.TX(2) / GPIO32(7) FLASH.BE0(0) / FLASH.CS2UOE(1) / GPIO59(7) UART3.RX(0) / PWL(1) / UART2.RX(3) / TIMER.PWM1(4) / GPIO49(7)
CAM.D3(0) / ETM.D3(1) / UART3.RX(2) / GPIO31(7) FLASH.ADV CAM.HS(0) / ETM.PSTAT1(1) / UART2.CTS(2) / MMC2.DAT0 / SPI.DI(3) / GPIO38(7)
FLASH.A24
FLASH.A21
CAM.D0(0) / ETM.D0(1) / MPUIO12(2) / MMC2.DAT3(3) FLASH.CS2(0) / FLASH.BAA(1) / FLASH.CS2L(2) GPIO7(0) / MMC.DAT2(1) / TCK(3) / MCSI1.CLK(4) / ETM.SYNC1(5) / RTDX.D2(7) VSS
DVDD8
FLASH.CS1(0) / FLASH.CS1L(1) GPIO2(0) / SPI.CLK(1) / ETM.PSTAT4(5) / RTDX.D0 (7) GPIO15(0) / KB.R7(1) / TIMER.PWM2(2) / VLYNQ.TX1(4)
FLASH.D0
FLASH.D2
FLASH.CS3(0) / GPIO3(7)
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PRODUCT PREVIEW
CAM.VS(0) / ETM.PSTAT2(1) / MPUIO14(2) / MMC2.DAT1(3)
Introduction
Table 2-2. ZZG Package Terminal Assignments (Continued)
GPIO12(0) / MCBSP3.FSX(1) / TIMER.EXTCLK(3) / VLYNQ.RX04 FLASH.D3
FLASH.D11
PRODUCT PREVIEW
GPIO3(0) / SPI.CS3(1) / MCBSP3.FSX(2) / LED1(3) / ETM.PSTAT3(5) / RTDX.D1(7)
GPIO6(0) / SPI.CS1(1) / MCBSP3.FSX(2) / TIMER.EVENT3(3) / MCSI1.DIN(4) / TMS(5)
DVDD5
FLASH.D6
FLASH.D7
FLASH.D8
GPIO1(0) / UART3.RTS(1)
FLASH.D10
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Introduction
Table 2-2. ZZG Package Terminal Assignments (Continued)
FLASH.D14
I2C.SCL
MPUIO1(0) / RTCK(1) / SPIF.SCK(6)
DVDD9
MCBSP2.CLKR(0) / GPIO11(1) / VLYNQ.CLK(3)
MPUIO3(0) / MMC2.DAT1(6)
MCSI2.SYNC(0) / GIOP7(1) / USB2.SPEED(2) / USB0.SPEED(5) / MMC2.CMDDIR(6)
MMC.CLK(0) / SSI.CARDY(6) / GPIO57(7) MCSI1.DIN(0) / USB1.RCV(1) / EMU1(3) / MCBSP3.DR(4) / SSI.ACWAKE(6) / GPIO56(7) UWIRE.SCLK(0) / KB.C7(1) / MPUIO1(2) / UART3.CTS(4)
DVDDRTC
UART1.RX(0) / UART1.IRRX(2) / GPIO37(7)
I2C.SDA(0) / GPIO48(7)
FLASH.WE
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PRODUCT PREVIEW
FLASH.D15
FLASH.WP
MCLK(0) / MMC2.DATDIR0(6) / GPIO24(7)
Introduction
Table 2-2. ZZG Package Terminal Assignments (Continued)
MCBSP2.FSX(0) / VLYNQ.RX1(3) / GPIO21(7) MMC.DAT3(0) / MPUIO9(1) / MPUIO6(2) / CFLASH.CD1(3) / SSI.ACFLAG(6)
GPIO9(0) / EMU0(3) / MCSI1.SYNC(4) / MMC2.DAT0 / SPI.DI(6)
CVDDRTC
PRODUCT PREVIEW
BCLKREQ(0) / UART3.CTS(1) / MMC2.DAT2(6) / GPIO40(7)
FLASH.CS1U(0) / GPIO16(7) UART2.CTS(0) / USB2.RCV(1) / GPIO7(2) / USB0.RCV(5)
DVDD3
DVDD7
CVDDA
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Introduction
Table 2-2. ZZG Package Terminal Assignments (Continued)
ZZG BALL NO. SIGNAL ZZG BALL NO. SIGNAL ZZG BALL NO. SIGNAL ZZG BALL NO. SIGNAL MCBSP2.DX(0) / MCBSP2.DR(1) / MCBSP2.DXZ(2) / GPIO19(7)
DVDD2
CVDD1
MCSI2.DIN(0) / USB2.VP(1) / USB0.VP(5) / GPIO26(7) MCSI1.SYNC(0) / MCBSP3.DR(1) / USB1.VP(2) / MCBSP3.FSX(4)
DVDD6
TDO / VLYNQ.TX0
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PRODUCT PREVIEW
Introduction
Terminal Characteristics and Multiplexing
PRODUCT PREVIEW
ZDY BALL NO. E7 A12 A2 D5 D4 C7 A8
SIGNAL NAME SDRAM.CS SDRAM.DQSH SDRAM.DQSL SDRAM.CAS SDRAM.RAS SDRAM.DQML SDRAM.DQMU
MUX CTRL SETTING NA NA NA NA NA NA NA
PULLUP / PULLDN
SUPPLY DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4
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Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
SIGNAL NAME SDRAM.WE SDRAM.A13:0
MUX CTRL SETTING NA NA
PULLUP / PULLDN
RESET STATE# 1 0
SUPPLY DVDD4 DVDD4
SDRAM.BA1:0 SDRAM.D15:0
3 mA (Lv) 8 mA (Hv) 3 mA (Lv) 6 mA (Hv)
DVDD4 DVDD4
3 mA (Lv) 6 mA (Hv) 3 mA (Lv) 6 mA (Hv) 3 mA (Lv) 8 mA (Hv) 2 mA (Lv) 6 mA (Hv)
DVDD4 DVDD4 DVDD4 DVDD1
2 mA (Lv) 6 mA (Hv)
DVDD1
December 2003 - Revised March 2004
SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
PULLUP / PULLDN PU20, PD20
RESET STATE# 0
SUPPLY DVDD1
PU20, PD20
2 mA (Lv) 6 mA (Hv)
DVDD1
PU20, PD20
2 mA (Lv) 6 mA (Hv)
DVDD1
PRODUCT PREVIEW
PU20, PD20
2 mA (Lv) 6 mA (Hv)
DVDD1
PU20, PD20
2 mA (Lv) 6 mA (Hv)
DVDD1
PU20, PD20
2 mA (Lv) 6 mA (Hv)
DVDD1
PU20, PD20
2 mA (Lv) 6 mA (Hv)
DVDD1
2 mA (Lv) 6 mA (Hv)
DVDD1
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
PULLUP / PULLDN PU20, PD20
RESET STATE# 0
SUPPLY DVDD1
PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20
2 mA (Lv) 6 mA (Hv)
DVDD1
2 mA (Lv) 6 mA (Hv)
DVDD1
2 mA (Lv) 6 mA (Hv)
DVDD1
2 mA (Lv) 6 mA (Hv)
DVDD1
2 mA (Lv) 6 mA (Hv)
DVDD1
2 mA (Lv) 6 mA (Hv)
DVDD1
2 mA (Lv) 6 mA (Hv)
DVDD1
2 mA (Lv) 6 mA (Hv)
DVDD1
4 mA (Lv) 8 mA (Hv)
DVDD1
December 2003 - Revised March 2004
SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. D16 SIGNAL NAME KB.C4 GPIO27 E15 KB.C3 GPIO63 B17 KB.C2 GPIO61 C17 KB.C1 MPUIO6 F14 KB.C0 MPUIO0 F13 KB.R4 MPUIO15 VLYNQ.TX1 D17 KB.R3 MPUIO13 VLYNQ.TX0 E16 KB.R2 MPUIO10 VLYNQ.CLK E17 KB.R1 MPUIO9 VLYNQ.RX0 F15 KB.R0 MPUIO8 VLYNQ.RX1 F17 KB.C5 GPIO28 G13 MCBSP1.CLKS SOSSI.TE GPIO62 F16
PULLUP / PULLDN PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU100, PD20
RESET STATE# 0
SUPPLY DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
PRODUCT PREVIEW
PU100, PD20
4 mA (Lv) 11 mA (Hv)
DVDD1
PU100, PD20
4 mA (Lv) 11 mA (Hv)
DVDD1
PU100, PD20
4 mA (Lv) 11 mA (Hv)
DVDD1
PU100, PD20
4 mA (Lv) 11 mA (Hv)
DVDD1
PU20, PD20 PU20, PD20
2 mA (Lv) 6 mA (Hv) 4 mA (Lv) 8 mA (Hv)
DVDD1 DVDD1
MCBSP1.CLKX GPIO54
PU20, PD20
4 mA (Lv) 8 mA (Hv)
DVDD1
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
PULLUP / PULLDN PU20, PD20
RESET STATE# Z
SUPPLY DVDD1
PU20, PD20
2 mA (Lv) 6 mA (Hv)
DVDD1
PU20, PD20 PU20, PD20
2 mA (Lv) 6 mA (Hv) 4 mA (Lv) 11 mA (Hv)
DVDD1 DVDD8
PU20, PD20
4 mA (Lv) 11 mA (Hv)
DVDD8
2 mA (Lv) 6 mA (Hv) PU20, PD20 4 mA (Lv) 11 mA (Hv)
- Z DVDD8
PU20, PD20
4 mA (Lv) 11 mA (Hv)
DVDD8
December 2003 - Revised March 2004
SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. H17 SIGNAL NAME CAM.D5 ETM.D5 UWIRE.SDI GPIO33 J11 CAM.D4 ETM.D4 UART3.TX GPIO32 H13 CAM.D3 ETM.D3 UART3.RX GPIO31 J14 CAM.D2 ETM.D2 UART3.CTS GPIO30 J16 CAM.D1 ETM.D1 UART3.RTS GPIO29 J17 CAM.D0 ETM.D0 MPUIO12 MMC2.DAT3 J13 CAM.VS ETM.PSTAT2 MPUIO14 MMC2.DAT1
PULLUP / PULLDN PU20, PD20
RESET STATE# Z
SUPPLY DVDD8
PU20, PD20
4 mA (Lv) 11 mA (Hv)
DVDD8
PU20, PD20
4 mA (Lv) 11 mA (Hv)
DVDD8
PRODUCT PREVIEW
PU20, PD20
4 mA (Lv) 11 mA (Hv)
DVDD8
PU20, PD20
4 mA (Lv) 11 mA (Hv)
DVDD8
PU20, PD20
4 mA (Lv) 11 mA (Hv)
DVDD8
PU20, PD20
4 mA (Lv) 11 mA (Hv)
DVDD8
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
PULLUP / PULLDN PU20, PD20
RESET STATE# Z
SUPPLY DVDD8
PU20, PD20
4 mA (Lv) 11 mA (Hv)
DVDD8
PU20, PD20
4 mA (Lv) 8 mA (Hv)
DVDD9
PU20, PD20
4 mA (Lv) 8 mA (Hv)
DVDD9
PU100, PD20
4 mA (Lv) 11 mA (Hv)
DVDD9
PU100, PD20
4 mA (Lv) 11 mA (Hv)
DVDD9