Performance 110/115/120/150 Initial Access Speed Initial Access Speed
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28F256J3, 28F128J3, 28F640J3, 28F320J3 (x8/x16)
Performance 110/115/120/150 Initial Access Speed Initial Access Speed (256 Mbit density only) Asynchronous Page mode Reads Asynchronous Page mode Reads (256Mbit density only) 32-Byte Write Buffer -6.8 byte effective programming time Software Program Erase suspend support Flash Data Integrator (FDI), Common Flash Interface (CFI) Compatible Security 128-bit Protection Register -64-bit Unique Device Identifier -64-bit User Programmable Cells Absolute Protection with VPEN Individual Block Locking Block Erase/Program Lockout during Power Transitions
Architecture Multi-Level Cell Technology: High Density Cost High-Density Symmetrical 128-Kbyte Blocks -256 Mbit (256 Blocks) (0.18µm only) -128 Mbit (128 Blocks) Mbit Blocks) Mbit Blocks) Quality Reliability Operating Temperature: 100K Minimum Erase Cycles Block 0.18 ETOXVII Process (J3C) 0.25 ETOXVI Process (J3A) Packaging Voltage 56-Lead TSOP Package 64-Ball Intel® Easy Package Lead-free packages available 48-Ball Intel® Package Mbit) (x16 only) VCCQ
Capitalizing Intel's 0.25 0.18 micron, two-bit-per-cell technology, Intel StrataFlash® Memory (J3) device provides bits space, with features mainstream performance. Offered 256Mbit (32-Mbyte), 128-Mbit (16-Mbyte), 64-Mbit, 32-Mbit densities, device brings reliable, two-bitper-cell storage technology flash market segment. Benefits include more density less space, high-speed interface, lowest cost-per-bit device, support code data storage, easy migration future devices. Using same NOR-based ETOXtechnology Intel's one-bit-per-cell products, device takes advantage over billion units flash manufacturing experience since 1987. result, components ideal code data applications where high density cost required. Examples include networking, telecommunications, digital boxes, audio recording, digital imaging. applying FlashFilememory family pinouts, memory components allow easy design migrations from existing Word-Wide FlashFile memory (28F160S3 28F320S3), first generation Intel StrataFlash® memory (28F640J5 28F320J5) devices. memory components deliver generation forward-compatible software support. using Common Flash Interface (CFI) Scalable Command (SCS), customers take advantage density upgrades optimized write capabilities future Intel StrataFlash® memory devices. Manufactured Intel® 0.18 micron ETOXVII (J3C) 0.25 micron ETOXVI (J3A) process technology, memory device provides highest levels quality reliability. Notice: This document contains information products production. specifications subject change without notice. Verify with your local Intel sales office that have latest datasheet before finalizing design.
Order Number: 290667-020 November 2004
INFORMATION THIS DOCUMENT PROVIDED CONNECTION WITH INTEL® PRODUCTS. LICENSE, EXPRESS IMPLIED, ESTOPPEL OTHERWISE, INTELLECTUAL PROPERTY RIGHTS GRANTED THIS DOCUMENT. EXCEPT PROVIDED INTEL'S TERMS CONDITIONS SALE SUCH PRODUCTS, INTEL ASSUMES LIABILITY WHATSOEVER, INTEL DISCLAIMS EXPRESS IMPLIED WARRANTY, RELATING SALE AND/OR INTEL PRODUCTS INCLUDING LIABILITY WARRANTIES RELATING FITNESS PARTICULAR PURPOSE, MERCHANTABILITY, INFRINGEMENT PATENT, COPYRIGHT OTHER INTELLECTUAL PROPERTY RIGHT. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Volt Intel StrataFlash® Memory contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright 2004, Intel Corporation. rights reserved. Intel ETOX trademarks registered trademarks Intel Corporation subsidiaries United States other countries. *Other names brands claimed property others.
Contents
Contents
Introduction.7 Nomenclature Conventions.7 Block Diagram Memory 56-Lead TSOP Package Easy (J3) Package VF-BGA (J3) Package Easy Ballout (32/64/128/256 Mbit) 56-Lead TSOP (32/64/128/256 Mbit).15 Ballout Mbit) Signal Descriptions Absolute Maximum Ratings Operating Conditions Current Characteristics Voltage Characteristics.20 Read Operations.22 Write Operations Block Erase, Program, Lock-Bit Configuration Performance Reset Operation.29 Test Conditions.29 Capacitance Power-Up/Down Characteristics.31 Power Supply Decoupling.31 Reset Characteristics.31 Operations Overview 9.1.1 Read Operation 9.1.2 Write Operation 9.1.3 Output Disable 9.1.4 Standby.34 9.1.5 Reset/Power-Down
Functional Overview
Package Information
Ballout Signal Descriptions
Maximum Ratings Operating Conditions.18
Electrical Specifications
Characteristics
Power Reset Specifications
Operations
Contents
Device Commands
10.0 Read Operations. 10.1 Read Array. 10.1.1 Asynchronous Page Mode Read 10.1.2 Enhanced Configuration Register (ECR). Read Identifier Codes 10.2.1 Read Status Register. Read Query/CFI. Byte/Word Program Write Buffer. Program Suspend. Program Resume. Block Erase. Block Erase Suspend Erase Resume Block Lock-Bit. Clear Block Lock-Bits. Protection Register Program 13.3.1 Reading Protection Register. 13.3.2 Programming Protection Register. 13.3.3 Locking Protection Register. Array Protection Read Configuration Register Command Status (STS)
10.2 10.3 11.1 11.2 11.3 11.4 12.1 12.2 12.3 13.1 13.2 13.3
11.0 Programming Operations
12.0 Erase Operations.
13.0 Security Modes
13.4 14.1 14.2
14.0 Special Modes.
Appendix Common Flash Interface.52 Appendix Flow Charts Appendix Design Considerations Appendix Additional Information Appendix Ordering Information.71
Contents
Revision History
Date Revision 07/07/99 08/03/99 09/07/99 Version -001 -002 -003 Original Version A0-A2 indicated block diagram Changed Minimum Block Erase time,IOL, IOH, Page Mode Byte Mode currents. Modified Waveform Write Operations Changed Block Erase time tAVWH Removed references operation Corrected Ordering Information, Valid Combinations entries 12/16/99 -004 Changed program time Added Lead Descriptions table Changed Chip Scale Package Ball Grid Array Package Changed default read mode page mode Removed erase queuing from Figure Block Erase Flowchart Added Program time Added Erase time Added page mode read current Moved tables correspond with sections Fixed typographical errors ordering information parameter table Removed VCCQ1 setting changed VCCQ2/3 VCCQ1/2 03/16/00 -005 Added recommended resister value Change operation temperature range Removed note that could Removed 0.45 Removed Updated ICCR values Added lock-bit program lock times Added note measurements Updated cover sheet statement million units billion 06/26/00 -006 Corrected Table show correct maximum program times Corrected error block program time section Corrected typical erase time section Updated cover page reflect 100K minimum erase cycles Updated cover page reflect read speed Removed Read Configuration command from Table Updated Table reflect reserved bits 1-7; Updated Table definition from 2/15/01 -007 Changed VPENLK voltage from Section 6.4, Characteristics Updated 32Mbit Read Parameters reflect 110ns, Section 6.5, Characteristics-Read-Only Operations (1,2) Updated write parameter (tWHRL) from Section 6.6, Characteristics-Write Operations Updated Max. Program Suspend Latency (tWHRH1) from Section 6.7, Block Erase, Program, Lock-Bit Configuration Performance Description
(1,2,3)
04/13/01
-008
Revised Section 7.0, Ordering Information
Contents
Date Revision
Version
Description Added Figure Volt Intel StrataFlash® Memory Package Mbit) Added Figure Volt Intel StrataFlash® Memory Mechanical Specifications Updated Operating Temperature Range Extended (Section Table
07/27/01
-009
Reduced tEHQZ Reduced tWHEH Added parameter values operation Lock-Bit Suspend Latency Updated VLKO VPENLK Removed Note Section Section Minor text edits Added notes under lead descriptions Package Removed Vcc, Vccq columns under Characteristics
10/31/01
-010
Removed byte mode read current characteristics Added ordering information Package Minor text edits Changed datasheet reflect best known methods Updated value Clear Block Lock-Bits time Minor text edits Added nomenclature (0.18 devices. Added access speed device. Added access speed device. Added "TE" package designator TSOP package. Revised Asynchronous Page Read description. Revised Write-to-Buffer flow chart. Updated timing waveforms. Added 256-Mbit pinout. Added 256Mbit device timings, device information. Also corrected VLKO specification. Corrected memory block count from 255. Memory block count fix. Restructured datasheet layout. Added lead-free part numbers 8-word page information. Added Note Voltage Characteristics table; "Speed Bin" Read Operations table; Corrected format Waveform Reset Operation figure; Corrected "8W" headings Enhanced Configuration Register table because they were transposed; Added ordering information corrected 56Lead TSOP combination number.
03/21/02
-011
12/12/02 01/24/03 12/09/03 1/3/04 1/23/04 1/23/04 5/19/04 7/7/04
-012 -013 -014 -015 -016 -016 -018 -019
11/23/04
-020
28F256J3, 28F128J3, 28F640J3, 28F320J3
Introduction
This document describes Intel StrataFlash® Memory (J3) device. includes description device features, operations, specifications.
Nomenclature
AMIN: AMAX: AMIN AMIN Mbit AMAX Mbit AMAX Mbit AMAX Mbit AMAX group flash cells that share common erase circuitry erase simultaneously Indicates logic zero Command User Interface Multi-Level Cell Time Programmable Protection Lock Register Protection Register Protection Register Data write data flash array Reserved Future Indicates logic Status Register Status Register Data Refers signal package connection name Refers timing voltage levels Write State Machine Extended Configuration Register eXtended Status Register
Block: Clear: CUI: MLC: OTP: PLR: Program: RFU: Set: SRD: VPEN: VPEN: WSM: ECR: XSR:
Conventions
(noun): (noun): Nibble Byte: Word: Kword: Brackets: Hexadecimal prefix Binary prefix 1,000 1,000,000 bits bits bits 1,024 words 1,024 bits 1,024 bytes 1,048,576 bits 1,048,576 bytes Square brackets ([]) will used designate group membership define group signals with similar function (i.e., A[21:1], SR[4,1] D[15:0]).
28F256J3, 28F128J3, 28F640J3, 28F320J3
Functional Overview
Intel StrataFlash® memory family contains high-density memories organized Mbytes 16Mwords (256-Mbit, available 0.18µm lithography process only), Mbytes Mwords (128-Mbit), Mbytes Mwords (64-Mbit), Mbytes Mwords (32-Mbit). These devices accessed 16-bit words. 128-Mbit device organized one-hundredtwenty-eight 128-Kbyte (131,072 bytes) erase blocks. 64-Mbit device organized sixtyfour 128-Kbyte erase blocks while 32-Mbit device contains thirty-two 128-Kbyte erase blocks. 128-bit Protection Register multiple uses, including unique flash device identification. device's optimized architecture interface dramatically increases read performance supporting page-mode reads. This read mode ideal non-clock memory systems. Common Flash Interface (CFI) permits software algorithms used entire families devices. This allows device-independent, JEDEC ID-independent, forward- backwardcompatible software support specified flash device families. Flash vendors standardize their existing interfaces long-term compatibility. Scalable Command (SCS) allows single, simple software driver host systems work with SCS-compliant flash memory devices, independent system-level packaging (e.g., memory card, SIMM, direct-to-board placement). Additionally, provides highest system/device data transfer rates minimizes device system-level implementation costs. Command User Interface (CUI) serves interface between system processor internal operation device. valid command sequence written initiates device automation. internal Write State Machine (WSM) automatically executes algorithms timings necessary block erase, program, lock-bit configuration operations. block erase operation erases device's 128-Kbyte blocks typically within second- independent other blocks. Each block independently erased 100,000 times. Block erase suspend mode allows system software suspend block erase read program data from other block. Similarly, program suspend allows system software suspend programming (byte/ word program write-to-buffer operations) read data execute code from other block that being suspended. Each device incorporates Write Buffer bytes words) allow optimum programming performance. using Write Buffer, data programmed buffer increments. This feature improve system program performance more than times over non-Write Buffer writes. Blocks selectively individually lockable in-system.Individual block locking uses block lock-bits lock unlock blocks. Block lock-bits gate block erase program operations. Lock-bit configuration operations clear lock-bits (Set Block Lock-Bit Clear Block Lock-Bits commands). Status Register indicates when WSM's block erase, program, lock-bit configuration operation finished. (STATUS) output gives additional indicator activity providing both hardware signal status (versus software polling) status masking (interrupt masking background block erase, example). Status indication using minimizes both overhead system power consumption. When configured level mode (default mode), acts signal. When low, indicates that performing block erase, program, lockbit configuration. STS-high indicates that ready command, block erase
28F256J3, 28F128J3, 28F640J3, 28F320J3
suspended (and programming inactive), program suspended, device reset/powerdown mode. Additionally, configuration command allows signal configured pulse completion programming and/or block erases. Three signals used enable disable device. unique logic design (see Table "Chip Enable Truth Table" page reduces decoder logic typically required multi-chip designs. External logic required when designing single chip, dual chip, 4chip miniature card SIMM module. BYTE# signal allows either read/writes device. BYTE#-low selects 8-bit mode; address selects between byte high byte. BYTE#-high enables 16-bit operation; address becomes lowest order address address used (don't care). device block diagram shown Figure page When device disabled (see Table page 33), with VIH, standby mode enabled. When VIL, further power-down mode enabled which minimizes power consumption provides write protection during reset. reset time (tPHQV) required from going high until data outputs valid. Likewise, device wake time (tPHWL) from RP#-high until writes recognized. With VIL, reset Status Register cleared.
Block Diagram
Figure Volt Intel StrataFlash® Memory Block Diagram
D[15:0]
VCCQ
Output Buffer
Input Buffer
Query Output Latch/Multiplexer Write Buffer Identifier Register Status Register
Logic Data Register Logic
BYTE#
Command User Interface
A[2:0]
Multiplexer Data Comparator
Y-Decoder A[MAX:MIN] Input Buffer
Y-Gating 32-Mbit: Thirty-two 64-Mbit: Sixty-four 128-Mbit: One-hundred twenty-eight 128-Kbyte Blocks Write State Machine Program/Erase Voltage Switch
VPEN
Address Latch Address Counter
X-Decoder
28F256J3, 28F128J3, 28F640J3, 28F320J3
Memory
Figure Intel StrataFlash® Memory (J3) Memory
A[24-0]: Mbit [23-0]:128 Mbit [22-0]: Mbit [21-0]: Mbit
1FFFFFF
A[24-1]: Mbit [23-1]: Mbit [22-1]: Mbit [21-1]: Mbit
FFFFFF
128-Kbyte Block
1FE0000
64-Kword Block
FF0000
0FFFFFF 0FE0000
128-Kbyte Block
7FFFFF 7F0000
64-Kword Block
07FFFFF
3FFFFF
128-Kbyte Block
07E0000
3F0000
64-Kword Block
128-Kbyte Block
1F0000
64-Kword Block
03E0000
003FFFF
01FFFF
128-Kbyte Block
0020000 001FFFF 0000000
010000 00FFFF 000000
64-Kword Block 64-Kword Block
128-Kbyte Block
Byte-Wide (x8) Mode
Word Wide (x16) Mode
32-Mbit
64-Mbit
03FFFFF
1FFFFF
28-Mbit
256-Mbit
28F256J3, 28F128J3, 28F640J3, 28F320J3
Package Information
56-Lead TSOP Package
Figure 56-Lead TSOP Package Drawing Specifications
Notes
Note
Detail
Seating Plane
Detail
Detail Detail
Table
56-Lead TSOP Dimension Table
Millimeters 1.200 0.050 0.965 0.100 0.100 18.200 13.800 0.995 0.150 0.150 18.400 14.000 0.500 19.800 0.500 20.00 0.600 0.100 0.150 0.250 0.350 0.006 0.010 20.200 0.700 0.780 0.020 1.025 0.200 0.200 18.600 14.200 0.002 0.038 0.004 0.004 0.717 0.543 0.039 0.006 0.006 0.724 0.551 0.0197 0.787 0.024 0.004 0.014 0.795 0.028 0.040 0.008 0.008 0.732 0.559 Notes Inches 0.047 Notes
Package Height Standoff Package Body Thickness Lead Width Lead Thickness Package Body Length Package Body Width Lead Pitch Terminal Dimension Lead Length Lead Count Lead Angle Seating Plane Coplanarity Lead Package Offset
28F256J3, 28F128J3, 28F640J3, 28F320J3
Easy (J3) Package
Figure Intel StrataFlash® Memory (J3) Easy Mechanical Specifications
Ball Corner Ball Corner
View Ball side down
Bottom View Ball Side
Seating Plane
Note: Drawing scale
Table
Easy Package Dimensions
Millimeters
Symbol 1.200 0.250 0.780 0.330 9.900 12.900 14.900 0.430 10.000 13.000 15.000 1.000 0.100 1.400 2.900 3.900 1.500 3.000 4.000 1.600 3.100 4.100 0.0551 0.1142 0.1535 0.0591 0.1181 0.1575 0.530 10.100 13.100 15.100 0.0130 0.3898 0.5079 0.5866 0.0098 0.0307 0.0169 0.3937 0.5118 0.5906 0.0394 0.0039 0.0630 0.1220 0.1614 0.0209 0.3976 0.5157 0.5945 Notes
Inches
0.0472
Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Package Body Length (256 Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along (32/64/128/256 Corner Ball Distance Along (32/64/128 Corner Ball Distance Along (256
NOTES: Daisy Chain Evaluation Unit information refer Intel Flash Memory Packaging Technology page Packaging Shipping Media information
28F256J3, 28F128J3, 28F640J3, 28F320J3
VF-BGA (J3) Package
Figure Intel StrataFlash® Memory (J3) Mechanical Specifications
illim 1.000 0.425 7.386 10.850 Pitc 0.100 1.118 3.650
NOTES: Daisy Chain Evaluation Unit information refer Intel Flash Memory Packaging Technology page Packaging Shipping Media information refer Intel Flash Memory Packaging Technology page
28F256J3, 28F128J3, 28F640J3, 28F320J3
Ballout Signal Descriptions
Intel StrataFlash® memory available three package types. Each density supported both 64-ball Easy 56-lead Thin Small Outline Package (TSOP) packages. 48-ball package available Mbit devices. Figure Figure Figure show pinouts.
Easy Ballout (32/64/128/256 Mbit)
Figure Intel StrataFlash® Memory Easy Ballout (32/64/128/256 Mbit)
BYTE# 128M CE2# Easy View- Ball side down 256M 256M CE2# Easy Bottom View- Ball side VCCQ VCCQ 128M BYTE# CEO# CE1# CE1# CEO# VPEN VPEN
NOTES: Address only valid 64-Mbit densities above, otherwise, connect (NC). Address only valid 128-Mbit densities above, otherwise, connect (NC). Address only valid 256-Mbit densities above, otherwise, connect (NC).
28F256J3, 28F128J3, 28F640J3, 28F320J3
56-Lead TSOP (32/64/128/256 Mbit)
Figure Intel StrataFlash® Memory 56-Lead TSOP (32/64/128/256 Mbit)
Volt Intel StrataFlash Memory 28F160S3 28F320J5 VCC(4) VPEN 32/64/128M A22(1) VPEN Volt Intel StrataFlash Memory 32/64/128M A24(3) DQ15 DQ14 DQ13 DQ12 VCCQ DQ11 DQ10 BYTE# A23(2) 28F320J5 DQ15 DQ14 DQ13 DQ12 VCCQ DQ11 DQ10 VCC(4) BYTE# 28F160S3 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 BYTE#
Volt Intel StrataFlash® Memory 56-Lead TSOP Standard Pinout View
Highlights pinout changes
NOTES: exists 64-, 128- 256-Mbit densities. 32-Mbit densities this signal no-connect (NC). exists 128-Mbit densities. 64-Mbit densities this signal no-connect (NC). exists 256-Mbit densities. 32-, 128-Mbit densities this signal no-connect (NC). 28F640J5/28F320J5.
Ballout Mbit)
Figure Intel StrataFlash® Memory Ballout Mbit)
NOTES: equivalent CE0, internally grounded. exists density only. 32-Mbit density, this signal no-connect (NC). supported this package. supported this package.
28F256J3, 28F128J3, 28F640J3, 28F320J3
Signal Descriptions
Table describes active signals used.
Table
Symbol
Signal Descriptions (Sheet
Type Input Name Function BYTE-SELECT ADDRESS: Selects between high byte when device mode. This address latched during program cycle. used mode (i.e., input buffer turned when BYTE# high). ADDRESS INPUTS: Inputs addresses during read program operations. Addresses internally latched during program cycle. 32-Mbit: A[21:0] 64-Mbit: A[22:0] 128-Mbit: A[23:0] 256-Mbit: A[24:0] LOW-BYTE DATA BUS: Inputs data during buffer writes programming, inputs commands during writes. Outputs array, CFI, identifier, status data appropriate read mode. Data internally latched during write operations. HIGH-BYTE DATA BUS: Inputs data during buffer writes programming operations. Outputs array, CFI, identifier data appropriate read mode; used Status Register reads. Data internally latched during write operations mode. D[15-8] float mode CHIP ENABLES: Activates device's control logic, input buffers, decoders, sense amplifiers. When device de-selected (see Table page 33), power reduces standby levels. timing specifications same these three signals. Device selection occurs with first edge CE0, CE1, that enables device. Device deselection occurs with first edge CE0, CE1, that disables device (see Table page 33). RESET/ POWER-DOWN: RP#-low resets internal automation puts device powerdown mode. RP#-high enables normal operation. Exit from reset sets device read array mode. When driven low, inhibits write operations which provides data protection during power transitions. OUTPUT ENABLE: Activates device's outputs through data buffers during read cycle. active low. WRITE ENABLE: Controls writes CUI, Write Buffer, array blocks. active low. Addresses data latched rising edge WE#. STATUS: Indicates status internal state machine. When configured level mode (default), acts RY/BY# signal. When configured pulse modes, pulse indicate program and/or erase completion. alternate configurations STATUS signal, Configurations command. tied VCCQ with pull-up resistor. BYTE ENABLE: BYTE#-low places device mode; data input output D[7:0], while D[15:8] placed High-Z. Address selects between high byte. BYTE#high places device mode, turns input buffer. Address becomes lowest-order address bit. ERASE PROGRAM BLOCK LOCK ENABLE: erasing array blocks, programming data, configuring lock-bits. With VPEN VPENLK, memory contents cannot altered. CORE POWER SUPPLY: Core (logic) source voltage. Writes flash array inhibited when VLKO. Device operation invalid voltages should attempted. POWER SUPPLY: Output-driver source voltage. This ball tied VCC.
A[MAX:1]
Input
D[7:0]
Input/Output
D[15:8]
Input/Output
CE0, CE1,
Input
Input
Input Input
Open Drain Output
BYTE#
Input
VPEN
Input
VCCQ
Power Power
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table
Symbol
Signal Descriptions (Sheet
Type Supply Name Function GROUND: float ground signals. CONNECT: Lead internally connected; driven floated. RESERVED FUTURE USE: Balls designated reserved Intel future device functionality enhancement.
28F256J3, 28F128J3, 28F640J3, 28F320J3
Maximum Ratings Operating Conditions
Absolute Maximum Ratings
This datasheet contains information products production. specifications subject change without notice. Verify with your local Intel Sales office that have latest datasheet before finalizing design. Absolute maximum ratings shown Table
Warning:
Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect device reliability. Absolute Maximum Ratings
Parameter Temperature under Bias Extended Storage Temperature Voltage signal Output Short Circuit Current Maximum Rating +125 -2.0 +5.0 V(1) mA(2)
Table
NOTES: specified voltages with respect GND. Minimum voltage -0.5 input/output signals -0.2 VPEN signals. During transitions, this level undershoot -2.0 periods Maximum voltage input/output signals, VCC, VPEN +0.5 which, during transitions, overshoot +2.0 periods Output shorted more than second. more than output shorted time.
Table
Operating Conditions
Temperature Operating Conditions
Symbol VCCQ Parameter Operating Temperature VCC1 Supply Voltage (2.7 V-3.6 VCCQ Supply Voltage (2.7 V-3.6 2.70 2.70 3.60 3.60 Unit Test Condition Ambient Temperature
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table
Electrical Specifications
Current Characteristics
Current Characteristics (Sheet
VCCQ 3.6V 3.6V Unit Max; VCCQ VCCQ VCCQ VCC= Max; VCCQ VCCQ VCCQ CMOS Inputs, Max, Device disabled (see Table "Chip Enable Truth Table" page 33), VCCQ Inputs, Max, Device disabled (see Table 13), IOUT (STS) CMOS Inputs, Max, VCCQ VCCQ using standard word page mode reads. Device enabled (see Table MHz, IOUT CMOS Inputs,VCC Max, VCCQ VCCQ using standard word page mode reads. Device enabled (see Table MHz, IOUT CMOS Inputs, Max, VCCQ VCCQ using standard word page mode reads. Device enabled (see Table MHz, IOUT CMOS Inputs,VCC Max, VCCQ VCCQ using standard word page mode reads. Device enabled (see Table MHz, IOUT Density: 128-, 64-, Mbit CMOS Inputs,VCC Max, VCCQ VCCQ using standard word page mode reads. Device enabled (see Table MHz, IOUT Density: 256Mbit CMOS Inputs, VPEN Inputs, VPEN Test Conditions Notes
Symbol
Parameter Input VPEN Load Current Output Leakage Current
ICCS Standby Current 0.71 ICCD Power-Down Current
1,2,3
4word Page
ICCR Page Mode Read Current
8word Page
ICCW
Program LockBit Current
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table
Current Characteristics (Sheet
VCCQ 3.6V 3.6V Unit CMOS Inputs, VPEN Inputs, VPEN Device enabled (see Table Test Conditions Notes
Symbol ICCE ICCWS ICCES
Parameter Block Erase Clear Block Lock-Bits Current Program Suspend Block Erase Suspend Current
NOTES: currents unless otherwise noted. These currents valid product versions (packages speeds). Contact Intel's Application Support Hotline your local sales office information about typical specifications. Includes STS. CMOS inputs either inputs either VIH. Sampled, 100% tested. ICCWS ICCES specified with device selected. device read written while erase suspend mode, device's current draw ICCR ICCWS
Table
Voltage Characteristics
Voltage Characteristics
Symbol Parameter Input Voltage Input High Voltage -0.5 VCCQ Output Voltage 0.85 VCCQ VCCQ VPEN Lockout during Program, Erase Lock-Bit Operations Unit VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ -2.5 VCCQ VCCQ -100 2,3,4,7 Test Conditions Notes
Output High Voltage
VPENLK
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table
Voltage Characteristics
Symbol VPENH VLKO Parameter VPEN during Block Erase, Program, Lock-Bit Operations Lockout Voltage Unit Test Conditions Notes
NOTES: Includes STS. Sampled, 100% tested. Block erases, programming, lock-bit configurations inhibited when VPEN VPENLK, guaranteed range between VPENLK (max) VPENH (min), above VPENH (max). Typically, VPEN connected (2.7 V-3.6 Block erases, programming, lock-bit configurations inhibited when VLKO, guaranteed range between VLKO (min) (min), above (max). Includes operational modes device including standby power-up sequences. operating condition standby meet typical operationg coditons.
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table
Characteristics
Read Operations
Read Operations (Sheet
V-3.6 VCCQ V-3.6 Notes Speed -110 Mbit 1,2,5 1,2,5 1,2,5 1,2,5 -115 -120 -125 -150 1,2,4
Asynchronous Specifications (All units unless otherwise noted)
Parameter
Density Mbit
tAVAV
Read/Write Cycle Time
Mbit Mbit Mbit Mbit
tAVQV
Address Output Delay
Mbit Mbit Mbit Mbit
tELQV
Output Delay
Mbit Mbit Mbit
tGLQV
NonArray Output Delay
tPHQV
High Output Delay
Mbit Mbit Mbit
tELQX tGLQX tEHQZ tGHQZ tELFL/ tELFH
Output Output High Output High High Output High Output Hold from Address, CEX, Change, Whichever Occurs First BYTE# High
1,2,5
1,2,5
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table
Read Operations (Sheet
V-3.6 VCCQ V-3.6 Notes Speed -110 1000 1000 -115 1000 1000 -120 1000 1000 -125 1000 1000 -150 1000 1000 1,2,5 1,2,5
Asynchronous Specifications (All units unless otherwise noted)
tFLQV/ tFHQV tFLQZ tEHEL tAPA tGLQV
Parameter
Density
BYTE# Output Delay BYTE# Output High High Page Address Access Time Array Output Delay
NOTES:
defined first edge CE0, CE1, that enables device. high defined first edge CE0, CE1, that disables device (see Table 13).
Input/Output Reference Waveforms maximum allowable input slew rate. delayed tELQV-tGLQV after first edge CE0, CE1, that enables device (see Table without impact tELQV. Figure "Transient Input/Output Reference Waveform VCCQ V-3.6 page Figure "Transient Equivalent Testing Load Circuit" page testing characteristics. When reading flash array faster tGLQV (R16) applies. Non-array reads refer Status Register reads, query reads, device identifier reads. Sampled, 100% tested. devices configured standard word/byte read mode, (tAPA) will equal (tAVQV).
Figure Single Word Asynchronous Read Waveform
Address Data [D/Q] BYTE#[F]
28F256J3, 28F128J3, 28F640J3, 28F320J3
0606_16
NOTES: defined last edge CE0, CE1, that enables device. high defined first edge CE0, CE1, that disables device (see Table 13). When reading flash array faster tGLQV (R16) applies. non-array reads, applies (i.e.: Status Register reads, query reads, device identifier reads).
Figure 4-Word Page Mode Read Waveform
A[MAX:3] A[2:1]
D[15:0]
NOTE: defined last edge CE0, CE1, that enables device. high defined first edge CE0, CE1, that disables device (see Table 13).
28F256J3, 28F128J3, 28F640J3, 28F320J3
Figure 8-word Asynchronous Page Mode Read
A[MAX:4] A[3:1]
D[15:0] BYTE#
NOTES: defined last edge CE0, CE1, that enables device. high defined first edge CE0, CE1, that disables device (see Table 13). this diagram, BYTE# asserted high.
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table
Write Operations
Write Operations
Versions Valid Speeds Parameter High Recovery (CEX) Going (WE#) (CEX) Going Write Pulse Width Data Setup (CEX) Going High Address Setup (CEX) Going High (WE#) Hold from (CEX) High Data Hold from (CEX) High Address Hold from (CEX) High Write Pulse Width High VPEN Setup (CEX) Going High Write Recovery before Read (CEX) High Going VPEN Hold from Valid SRD, Going High 1,2,3 1,2,4 1,2,4 1,2,5 1,2,5 1,2, 1,2, 1,2, 1,2,6 1,2,3 1,2,7 1,2,8 1,2,3,8,9
Unit
Notes
Symbol tPHWL (tPHEL) tELWL (tWLEL) tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWPH tVPWH (tVPEH) tWHGL (tEHGL) tWHRL (tEHRL) tQVVL
NOTES:
defined first edge CE0, CE1, that enables device. high defined first edge CE0, CE1, that disables device (see Table 13).
Read timing characteristics during block erase, program, lock-bit configuration operations same during read-only operations. Refer Characteristics-Read-Only Operations. write operation initiated terminated with either WE#. Sampled, 100% tested. Write pulse width (tWP) defined from going (whichever goes last) going high (whichever goes high first). Hence, tWLWH tELEH tWLEH tELWH. Refer Table valid block erase, program, lock-bit configuration. Write pulse width high (tWPH) defined from going high (whichever goes high first) going (whichever goes first). Hence, tWPH tWHWL tEHEL tWHEL tEHWL. array access, tAVQV required addition tWHGL accesses after write. timings based configured RY/BY# default mode. VPEN should held VPENH until determination block erase, program, lock-bit configuration success (SR[1,3,4:5]
28F256J3, 28F128J3, 28F640J3, 28F320J3
Block Erase, Program, Lock-Bit Configuration Performance
Table Configuration Performance
tWHQV3 tEHQV3 Parameter Write Buffer Byte Program Time (Time Program bytes/16 words) Byte Program Time (Using Word/Byte Program Command) Block Program Time (Using Write Buffer Command) tWHQV4 tEHQV4 tWHQV5 tEHQV5 tWHQV6 tEHQV6 tWHRH1 tEHRH1 tWHRH tEHRH Block Erase Time Lock-Bit Time Clear Block Lock-Bits Time Program Suspend Latency Time Read Erase Suspend Latency Time Read Max(8) 75/85 0.70/1.4 75/90 35/40 Unit Notes 1,2,3,4,5,6,7 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4,9 1,2,3,4,10 1,2,3,9 1,2,3,9
NOTES: Typical values measured nominal voltages. Assumes corresponding lock-bits set. Subject change based device characterization. These performance numbers valid speed versions. Sampled 100% tested. Excludes system-level overhead. These values valid when buffer full, start address aligned 32-byte boundary. Effective per-byte program time (tWHQV1, tEHQV1) µs/byte (typical). Effective per-word program time (tWHQV2, tEHQV2) 13.6 µs/word (typical). values measured worst case temperature corner after 100k cycles (except noted). values expressed °C/-40 10.Max values expressed °C/-40
28F256J3, 28F128J3, 28F640J3, 28F320J3
Figure Asynchronous Write Waveform
ADDRESS (WE#) (W)] (CEx) (E)] DATA [D/Q] STS[R] VPEN
Figure Asynchronous Write Read Waveform
Address Data [D/Q] RST#/ VPEN
28F256J3, 28F128J3, 28F640J3, 28F320J3
Reset Operation
Figure Waveform Reset Operation
NOTE: shown default mode (RY/BY#).
Table Reset Specifications
tPLPH tPHRH Parameter Pulse Time tied VCC, this specification applicable) High Reset during Block Erase, Program, Lock-Bit Configuration Unit Notes
NOTES: These specifications valid product versions (packages speeds). asserted while block erase, program, lock-bit configuration operation executing then minimum required Pulse Time reset time, tPHQV, required from latter RY/BY# mode) going high until outputs valid.
Test Conditions
Figure Transient Input/Output Reference Waveform VCCQ V-3.6
VCCQ Input VCCQ/2
NOTE: test inputs driven VCCQ Logic Logic "0." Input timing begins, output timing ends, VCCQ/2 (50% VCCQ). Input rise fall times (10% 90%)
Test Points
VCCQ/2
Output
28F256J3, 28F128J3, 28F640J3, 28F320J3
Figure Transient Equivalent Testing Load Circuit
1.3V 1N914 Device Under Test
NOTE: Includes Capacitance. Test Configuration VCCQ V-3.6 (pF)
Capacitance
Symbol COUT Parameter(1) Input Capacitance Output Capacitance Type Unit Condition VOUT
NOTES: Sampled, 100% tested.
28F256J3, 28F128J3, 28F640J3, 28F320J3
Power Reset Specifications
This section provides overview system level considerations Intel StrataFlash® memory family device. This section provides brief description power-up, power-down, decoupling reset design considerations.
Power-Up/Down Characteristics
order prevent condition that result spurious write erase operation, recommended power-up power-down VCCQ together. also recommended power-up VPEN with slightly after VCC. Conversely, VPEN must power down with slightly before VCC.
Power Supply Decoupling
When device enabled, many internal conditions change. Circuits energized, charge pumps switched internal voltage nodes ramped. this internal activities produce transient signals. magnitude transient signals depends device system loading. minimize effect these transient signals, ceramic capacitor required across each VCC/VSS VCCQ signal. Capacitors should placed close possible device connections. Additionally, every eight flash devices, electrolytic capacitor should placed between power supply connection. This capacitor should help overcome voltage slumps caused (printed circuit board) trace inductance.
Reset Characteristics
holding flash device reset during power-up power-down transitions, invalid conditions masked. flash device enters reset mode when driven low. reset, internal flash circuitry disabled outputs placed high-impedance state. After return from reset, certain amount time required before flash device able perform normal operations. After return from reset, flash device defaults asynchronous page mode. driven during program erase operation, program erase operation will aborted memory contents aborted block address longer valid. Figure Waveform Reset Operation" page detailed information regarding reset timings.
28F256J3, 28F128J3, 28F640J3, 28F320J3
Operations
This section provides overview device operations. on-chip Write State Machine (WSM) manages erase program algorithms. system provides control insystem read, write, erase operations device system bus. Device commands written control flash memory device's operations. does occupy addressable memory location; it's mechanism through which flash device controlled.
Operations Overview
local reads writes flash memory in-system. cycles from flash memory conform standard microprocessor cycles.
Table Operations
Mode Read Array Output Disable Standby Reset/Power-Down Mode Read Identifier Codes CE[2:0](1) Enabled Enabled Disabled Enabled OE#(2) WE#(2) Address Table Table 10.3 VPEN Data(3) DOUT High High High Note (default mode) High Z(7) High Z(7) High Z(7) High Z(7) Notes 4,5,6
Read Query Read Status (WSM off) Read Status (WSM Write
Enabled Enabled Enabled Enabled
VPENH
Note DOUT DOUT D[15:8] High D[6:0] High
6,10,11
NOTES: Table page valid configurations. should never enabled simultaneously. refers D[7:0] BYTE# D[15:0] BYTE# high. Refer Characteristics. When VPEN VPENLK, memory contents read, altered. control address signals, VPENLK VPENH VPEN. Characteristics VPENLK VPENH voltages. default mode, when executing internal block erase, program, lock-bit configuration algorithms. when busy, block erase suspend mode (with programming inactive), program suspend mode, reset/power-down mode. High will with external pull-up resistor. Section 10.2, "Read Identifier Codes" page read identifier code data. Section 10.3, "Read Query/CFI" page read query data. 10.Command writes involving block erase, program, lock-bit configuration reliably executed when VPEN VPENH within specification.
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table Chip Enable Truth Table
DEVICE Enabled Disabled Disabled Disabled Enabled Enabled Enabled Disabled
NOTE: single-chip applications, connected VIL.
9.1.1
Read Operation
perform read operation, (refer Table page must asserted. device-select control; when active, enables flash memory device. dataoutput control; when active, addressed flash memory data driven onto bus. read states, must de-asserted. Section 7.1, "Read Operations" page Refer Section 10.0, "Read Operations" page details reading from flash array, refer Section 14.0, "Special Modes" page details regarding other available read states.
9.1.2
Write Operation
Writing commands Command User Interface enables various modes operation, including reading array data, data, identifier codes, inspection clearing Status Register, and, when VPEN VPENH, block erasure, program, lock-bit configuration. Block Erase command requires appropriate command data address within block erased. Byte/Word Program command requires command address location written. Block Lock-Bit commands require command block within device locked. Clear Block Lock-Bits command requires command address within device. does occupy addressable memory location. written when device enabled active. address data needed execute command latched rising edge first edge CE0, CE1, that disables device (see Table page 33). Standard microprocessor write timings used.
9.1.3
Output Disable
With asserted, logic-high level (VIH), device outputs disabled. Output signals D[15:0] placed high-impedance state.
28F256J3, 28F128J3, 28F640J3, 28F320J3
9.1.4
Standby
CE0, CE1, disable device (see Table page place standby mode. This manipulation substantially reduces device power consumption. D[15:0] outputs placed high-impedance state independent OE#. deselected during block erase, program, lock-bit configuration, continues functioning, consuming active power until operation completes.
9.1.5
Reset/Power-Down
initiates reset/power-down mode. read modes, RP#-low deselects memory, places output drivers high-impedance state, turns numerous internal circuits. must held minimum tPLPH. Time tPHQV required after return from reset mode until initial memory access outputs valid. After this wakeup interval, normal operation restored. reset read array mode Status Register 0x80. During block erase, program, lock-bit configuration modes, RP#-low will abort operation. default mode, transitions remains maximum time tPLPH tPHRH until reset operation complete. Memory contents being altered longer valid; data partially corrupted after program partially altered after erase lock-bit configuration. Time tPHWL required after goes logic-high (VIH) before another command written. with automated device, important assert during system reset. When system comes reset, expects read from flash memory. Automated flash memories provide status information when accessed during block erase, program, lock-bit configuration modes. reset occurs with flash memory reset, proper initialization occur because flash memory providing status information instead array data. Intel StrataFlash® memory family devices allow proper initialization following system reset through input. this application, controlled same RESET# signal that resets system CPU.
28F256J3, 28F128J3, 28F640J3, 28F320J3
Device Commands
When VPEN voltage VPENLK, only read operations from Status Register, CFI, identifier codes, blocks enabled. Placing VPENH VPEN additionally enables block erase, program, lock-bit configuration operations. Device operations selected writing specific commands into CUI. Table "Command Bus-Cycle Definitions" page defines these commands.
Table Command Bus-Cycle Definitions (Sheet
Command Scalable Basic Command Set(2) SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS/BCS Cycles Req'd. First Cycle Oper(3) Write Write Write Write Write Write Write Write Write Write Write Write Addr(4) Data(5,6) 0xFF 0X90 0x98 0x70 0x50 0xE8 0x40 0x10 0x20 0xB0 0xD0 0xB8 0x60 Write Write 0x01 Write Write Write 0xD0 Read Read Read Second Cycle Notes Oper(3) Addr(4) Data(5,6) 1,9, 1,12,13 1,11,12 1,12,14 1,12
Read Array Read Identifier Codes Read Query Read Status Register Clear Status Register Write Buffer Word/Byte Program Block Erase Block Erase, Program Suspend Block Erase, Program Resume Configuration Block Lock-Bit
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table Command Bus-Cycle Definitions (Sheet
Command Scalable Basic Command Set(2) Cycles Req'd. First Cycle Oper(3) Write Write Addr(4) Data(5,6) 0x60 0xC0 Second Cycle Notes Oper(3) Write Write Addr(4) Data(5,6) 0xD0 1,15
Clear Block Lock-Bits Protection Program
NOTES: Commands other than those shown above reserved Intel future device implementations should used. Basic Command (BCS) same 28F008SA Command Intel Standard Command Set. Scalable Command (SCS) also referred Intel Extended Command Set. operations defined Table valid address within device. Address within block. Identifier Code Address: Table Query database Address. Address memory location programmed. Data written read configuration register. This data presented device A[16:1]; other address inputs ignored. Data read from Identifier Codes. Data read from Query database. Data read from Status Register. Table description Status Register bits. Data programmed location Data latched rising edge WE#. Configuration Code. upper byte data (D[15:8]) during command writes "Don't Care" operation. Following Read Identifier Codes command, read operations access manufacturer, device block lock codes. Section 10.2 read identifier code data. running, only valid; D[15:8] D[6:0] float, which places them high-impedance state. After Write Buffer command issued check make sure buffer available writing. 10.The number bytes/words written Write Buffer where byte/word count argument. Count ranges this device byte mode word mode 0x00 0x0F. third consecutive cycles, determined writing data into Write Buffer. Confirm command (0xD0) expected after exactly write cycles; other command that point sequence aborts write buffer operation. Figure "Write Buffer Flowchart" page additional information 11.The write buffer erase operation does begin until Confirm command (0xD0) issued. 12.Attempts issue block erase program locked block. 13.Either 0x40 0x10 recognized byte/word program setup. 14.Program suspends issued after either Write-to-Buffer Word/Byte-Program operation initiated. 15.The clear block lock-bits operation simultaneously clears block lock-bits.
28F256J3, 28F128J3, 28F640J3, 28F320J3
10.0
Read Operations
device supports four types read modes: Read Array, Read Identifier, Read Status, query. Upon power-up return from reset, device defaults read array mode. change device's read mode, appropriate read-mode command must written device. (See Section 9.2, "Device Commands" page 35.) Section 14.0, "Special Modes" page details regarding read status, read query modes. Upon initial device power-up after exit from reset/power-down mode, device automatically resets read array mode. Otherwise, write appropriate read mode command (Read Array, Read Query, Read Identifier Codes, Read Status Register) CUI. control signals dictate data flow component: CE0, CE1, CE2, OE#, WE#, RP#. device must enabled (see Table "Chip Enable Truth Table" page 33), must driven active obtain data outputs. CE0, CE1, device selection controls and, when enabled (see Table 13), select memory device. data output (D[15:0]) control and, when active, drives selected memory data onto bus. must VIH.
10.1
Read Array
Upon initial device power-up after exit from reset/power-down mode, device defaults read array mode. device defaults four-word asynchronous read page mode. Read Array command also causes device enter read array mode. device remains enabled reads until another command written. internal started block erase, program, lockbit configuration, device will recognize Read Array command until completes operation unless suspended Erase Program Suspend command. Read Array command functions independently VPEN voltage.
10.1.1
Asynchronous Page Mode Read
There Asynchronous Page mode configurations that available depending user's system design requirements:
Four-Word Page mode: This default mode power-up reset. Array data
sensed four words Bytes) time.
Eight-Word Page mode: Array data sensed eight words Bytes) time. This
mode must enabled power-up reset using command sequence found Table "Command Bus-Cycle Definitions" page Address bits A[3:1] determine which word output during read operation, A[3:0] determine which byte output width. After initial access delay, first word page buffer corresponds initial address. Four-Word Page mode, address bits A[2:1] determine which word output from page buffer width, A[2:0] determine which byte output from page buffer width. Subsequent reads from device come from page buffer. These reads output D[15:0] width D[7:0] width after minimum delay long A[2:0] (Four-Word Page mode) A[3:0] (Eight-Word Page mode) only address bits that change. Data read from page buffer multiple times, order. Four-Word Page Mode, address bits A[MAX:3] (A[MAX:4] Eight-Word Page Mode) change time, toggled, device will sense load data into page buffer. Asynchronous Page Mode default read mode power-up reset.
28F256J3, 28F128J3, 28F640J3, 28F320J3
perform page mode read after other operation, Read Array command must issued read from flash array. Asynchronous page mode reads permitted blocks used access register information. During register access, only word loaded into page buffer.
10.1.2
Enhanced Configuration Register (ECR)
Enhanced Configuration Register (ECR) volatile storage register that when addressed Enhanced Configuration Register command, select between Four-Word Page mode Eight-Word Page mode. volatile; bits will reset default values when deasserted power removed from device. modify settings, Enhanced Configuration Register command. Enhanced Configuration Register command written along with configuration register value, which placed lower bits address A[15:0]. This followed second write that confirms operation again presents enhanced configuration register data address bus. After executing this command, device returns Read Array mode. shown Table "Enhanced Configuration Register" page
Note:
forward compatibility reasons, 8-word Asynchronous Page mode used J3C, Clear Status Register command must issued after issuing Enhanced Configuration Register command. Table "J3C Asynchronous 8-Word Page Mode Command Bus-Cycle Definition" page further details.
Table Enhanced Configuration Register
Res. Reserved
BITS ECR[15:14] ECR[13] ECR[12:0] Reserved
DESCRIPTION
NOTES Reserved Future Use. until further notice.
8Word Page mode 4Word Page mode Reserved NOTE: reserved bits should Reserved Future Use. until further notice.
Table Asynchronous 8-Word Page Mode Command Bus-Cycle Definition
Command Enhanced Configuration Register (Set ECR) Cycles Req'd. First Cycle Oper Write Addr(1) Data 0x60 Second Cycle Oper Write Addr(1) Data 0x04 Third Cycle Oper Write Addr(1) Data 0x50
NOTE: valid address within device. Enhanced Configuration Register Data.
28F256J3, 28F128J3, 28F640J3, 28F320J3
10.2
Read Identifier Codes
Read identifier codes operation outputs manufacturer code, device-code, block lock configuration codes each block (See Section 9.2, "Device Commands" page details issuing Read Device Identifier command). Page-mode reads supported this read mode. terminate operation, write another valid command. Like Read Array command, Read Identifier Codes command functions independently VPEN voltage. This command valid only when device suspended. Following Read Identifier Codes command, following information read.
Table Read Identifier Codes
Code Manufacture Code Device Code 32-Mbit 64-Mbit 128-Mbit 256-Mbit Block Lock Configuration Block Unlocked Block Locked Reserved Future Address(1) 00000 00001 00001 00001 00001
X0002(2)
Data (00) (00) (00) (00) (00)
D[7:1]
NOTES: used either modes when obtaining identifier codes. lowest order address line Data always presented byte mode (upper byte contains 00h). selects specific block's lock configuration code. D[7:1] invalid should ignored.
10.2.1
Read Status Register
Status Register read determine when block erase, program, lock-bit configuration complete whether operation completed successfully. read only after specified time (see Table "Write Operations" page 26). After writing this command, subsequent read operations output data from Status Register until another valid command written. Page-mode reads supported this read mode. Status Register contents latched falling edge first edge CE0, CE1, that enables device (see Table "Chip Enable Truth Table" page 33). must toggle device must disabled before further reads update Status Register latch. Read Status Register command functions independently VPEN voltage. During program, block erase, lock-bit, clear lock-bit command sequence, only SR.7 valid until Write State Machine completes suspends operation. Device signals D[6:0] D[15:8] placed high-impedance state. When operation completes suspends (check SR.7), contents Status Register valid when read.
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table Status Register Definitions
WSMS High When Busy? ECLBS PSLBS VPENS bit2
Status Register Bits SR.7 WRITE STATE MACHINE STATUS Ready Busy SR.6 ERASE SUSPEND STATUS Block Erase Suspended Block Erase Progress/Completed SR.5 ERASE CLEAR LOCK-BITSSTATUS Error Block Erasure Clear Lock-Bits Successful Block Erase Clear Lock-Bits SR.4 PROGRAM LOCK-BIT STATUS Program Error Error Setting Lock-Bit Successful Program/Set Block Lock SR.3 PROGRAMMING VOLTAGE STATUS Programming Voltage Detected, Operation Aborted Programming Voltage SR.2 PROGRAM SUSPEND STATUS Program suspended Program progress/completed SR.1 DEVICE PROTECT STATUS Block Lock-Bit Detected, Operation Abort Unlock
Notes Check SR.7 determine block erase, program, lock-bit configuration completion. SR[6:0] driven while SR.7 "0."
both SR.5 SR.4 "1"s after block erase lock-bit configuration attempt, improper command sequence entered.
SR.3 does provide continuous programming voltage level indication. interrogates indicates programming voltage level only after Block Erase, Program, Block Lock-Bit, Clear Block Lock-Bits command sequences.
SR.1 does provide continuous indication block lock-bit values. interrogates block lock-bits only after Block Erase, Program, Lock-Bit configuration command sequences. informs system, depending attempted operation, block lock-bit set. Read block lock configuration codes using Read Identifier Codes command determine block lock-bit status. reserved future should masked when polling Status Register.
RESERVED FUTURE ENHANCEMENTS
Table Extended Status Register Definitions
High When Busy? Reserved Bits
Status Register Bits
Notes After Buffer-Write command, XSR.7 indicates that Write Buffer available. SR[6:0] reserved future should masked when polling Status Register.
XSR.7 WRITE BUFFER STATUS Write buffer available Write buffer available XSR.6-XSR0 RESERVED FUTURE ENHANCEMENTS
28F256J3, 28F128J3, 28F640J3, 28F320J3
10.3
Read Query/CFI
query register contains assortment flash product information such block size, density, allowable command sets, electrical specifications other product information. data contained this register conforms Common Flash Interface (CFI) protocol. obtain information from query register, execute Read Query Register command. Section 9.2, "Device Commands" page details issuing Query command. Refer Appendix "Query Structure Overview" page detailed explanation register. Information contained this register only accessed executing single-word read.
28F256J3, 28F128J3, 28F640J3, 28F320J3
11.0
Programming Operations
device supports different programming methods: word programming, write-buffer programming. Successful programming requires addressed block unlocked. attempt program locked block will result operation aborting, SR.1 SR.4 being set, indicating programming error. following sections describe device programming detail.
11.1
Byte/Word Program
Byte/Word program executed two-cycle command sequence. Byte/Word program setup (standard 0x40 alternate 0x10) written followed second write that specifies address data (latched rising edge WE#). then takes over, controlling program program verify algorithms internally. After program sequence written, device automatically outputs when read (see Figure "Byte/Word Program Flowchart" page 61). detect completion program event analyzing signal SR.7. When program complete, SR.4 should checked. program error detected, Status Register should cleared. internal verify only detects errors "1"s that successfully program "0"s. remains Read Status Register mode until receives another command. Reliable byte/word programming only occur when VPEN valid. byte/word program attempted while VPEN VPENLK, SR.4 SR.3 will set. Successful byte/word programs require that corresponding block lock-bit cleared. byte/word program attempted when corresponding block lock-bit set, SR.1 SR.4 will set.
11.2
Write Buffer
program flash device, Write Buffer command sequence initiated. variable number bytes, buffer size, loaded into buffer written flash device. First, Write Buffer Setup command issued along with Block Address (see Figure "Write Buffer Flowchart" page 59). this point, eXtended Status Register (XSR, Table information loaded XSR.7 reverts "buffer available" status. XSR.7 write buffer available. retry, continue monitoring XSR.7 issuing Write Buffer setup command with Block Address until XSR.7 When XSR.7 transitions "1," buffer ready loading. Next, word/byte count given part with Block Address. next write, device start address given along with write buffer data. Subsequent writes provide additional device addresses data, depending count. subsequent addresses must within start address plus count. Internally, this device programs many flash cells parallel. Because this parallel programming, maximum programming performance lower power obtained aligning start address beginning write buffer boundary (i.e., A[4:0] start address
28F256J3, 28F128J3, 28F640J3, 28F320J3
After final buffer data given, Write Confirm command issued. This initiates (Write State Machine) begin copying buffer data flash array. command other than Write Confirm written device, "Invalid Command/Sequence" error will generated SR.5 SR.4 will set. additional buffer writes, issue another Write Buffer Setup command check XSR.7. error occurs while writing, device will stop writing, SR.4 will indicate program failure. internal verify only detects errors "1"s that successfully program "0"s. program error detected, Status Register should cleared. time SR.4 and/or SR.5 (e.g., media failure occurs during program erase), device will accept more Write Buffer commands. Additionally, user attempts program past erase block boundary with Write Buffer command, device will abort write buffer operation. This will generate "Invalid Command/Sequence" error SR.5 SR.4 will set. Reliable buffered writes only occur when VPEN VPENH. buffered write attempted while VPEN VPENLK, SR.4 SR.3 will set. Buffered write attempts with invalid VPEN voltages produce spurious results should attempted. Finally, successful programming requires that corresponding block lock-bit reset. buffered write attempted when corresponding block lock-bit set, SR.1 SR.4 will set.
11.3
Program Suspend
Program Suspend command allows program interruption read data other flash memory locations. Once programming process starts (either initiating write buffer byte/word program operation), writing Program Suspend command requests that suspend program sequence predetermined point algorithm. device continues output when read after Program Suspend command written. Polling SR.7 determine when programming operation been suspended. When SR.7 SR.2 should also set, indicating that device program suspend mode. level RY/BY# mode will also transition VOH. Specification tWHRH1 defines program suspend latency. this point, Read Array command written read data from locations other than that which suspended. only other valid commands while programming suspended Read Query, Read Status Register, Clear Status Register, Configure, Program Resume. After Program Resume command written, will continue programming process. SR.2 SR.7 will automatically clear RY/BY# mode will return VOL. After Program Resume command written, device automatically outputs when read. VPEN must remain VPENH must remain valid levels (the same VPEN levels used programming) while program suspend mode. Refer Figure "Program Suspend/Resume Flowchart" page
11.4
Program Resume
resume (i.e., continue) program suspend operation, execute Program Resume command. Resume command written device address. When program operation nested within erase suspend operation Program Suspend command issued, device will suspend program operation. When Resume command issued, device will resume complete program operation. Once nested program operation completed, additional Resume command required complete block erase operation. device supports maximum suspend/resume nested routines. Figure "Program Suspend/Resume Flowchart" page 62).
28F256J3, 28F128J3, 28F640J3, 28F320J3
12.0
Erase Operations
Flash erasing performed block basis; therefore, only block erased time. Once block erased, bits within that block will read logic level one. determine status block erase, poll Status Register analyze bits. This following section describes block erase operations detail.
12.1
Block Erase
Erase executed block time initiated two-cycle command. block erase setup first written, followed block erase confirm. This command sequence requires appropriate address within block erased (erase changes block data FFH). Block preconditioning, erase, verify handled internally (invisible system). After two-cycle block erase sequence written, device automatically outputs when read (see Figure "Block Erase Flowchart" page 63). detect block erase completion analyzing output signal SR.7. Toggle OE#, CE0, CE1, update Status Register. When block erase complete, SR.5 should checked. block erase error detected, Status Register should cleared before system software attempts corrective actions. remains Read Status Register mode until command issued. This two-step command sequence setup followed execution ensures that block contents accidentally erased. invalid Block Erase command sequence will result both SR.4 SR.5 being set. Also, reliable block erasure only occur when valid VPEN VPENH. block erase attempted while VPEN VPENLK, SR.3 SR.5 will set. Successful block erase requires that corresponding block lock-bit cleared. block erase attempted when corresponding block lock-bit set, SR.1 SR.5 will set.
12.2
Block Erase Suspend
Block Erase Suspend command allows block-erase interruption read program data another block memory. Once block erase process starts, writing Block Erase Suspend command requests that suspend block erase sequence predetermined point algorithm. device outputs when read after Block Erase Suspend command written. Polling SR.7 then SR.6 determine when block erase operation been suspended (both will set). default mode, will also transition VOH. Specification tWHRH defines block erase suspend latency. this point, Read Array command written read data from blocks other than that which suspended. program command sequence also issued during erase suspend program data other blocks. During program operation with block erase suspended, SR.7 will return output default mode) will transition VOL. However, SR.6 will remain indicate block erase suspend status. Using Program Suspend command, program operation also suspended. Resuming suspended programming operation issuing Program Resume command allows continuing suspended programming operation. resume suspended erase, user must wait programming operation complete before issuing Block Erase Resume command.
28F256J3, 28F128J3, 28F640J3, 28F320J3
only other valid commands while block erase suspended Read Query, Read Status Register, Clear Status Register, Configure, Block Erase Resume. After Block Erase Resume command written flash memory, will continue block erase process. SR.6 SR.7 will automatically clear default mode) will return VOL. After Erase Resume command written, device automatically outputs when read (see Figure "Block Erase Suspend/Resume Flowchart" page 64). VPEN must remain VPENH (the same VPEN level used block erase) while block erase suspended. Block erase cannot resume until program operations initiated during block erase suspend have completed.
12.3
Erase Resume
resume (i.e., continue) erase suspend operation, execute Erase Resume command. Resume command written device address. When program operation nested within erase suspend operation Program Suspend command issued, device will suspend program operation. When Resume command issued, device will resume program operations first. Once nested program operation completed, additional Resume command required complete block erase operation. device supports maximum suspend/resume nested routines. Figure "Block Erase Flowchart" page
28F256J3, 28F128J3, 28F640J3, 28F320J3
13.0
Security Modes
This device offers both hardware software security features. Block lock operations, PRs, VPEN allow user implement various levels data protection. following section describes security features detail. Other security features available that described this datasheet. Please contact your local Intel Field Representative more information.
13.1
Block Lock-Bit
flexible block locking scheme enabled block lock-bits. block lock-bits gate program erase operations. Individual block lock-bits using Block Lock-Bit command. This command invalid while running device suspended. block lock-bit commands executed two-cycle sequence. block setup along with appropriate block address followed either block lock-bit confirm (and address within block locked). then controls lock-bit algorithm. After sequence written, device automatically outputs Status Register data when read (see Figure page 65). detect completion lock-bit event analyzing signal output SR.7. When lock-bit operation complete, SR.4 should checked. error detected, Status Register should cleared. will remain Read Status Register mode until command issued. This two-step sequence setup followed execution ensures that lock-bits accidentally set. invalid Block Lock-Bit command will result SR.4 SR.5 being set. Also, reliable operations occur only when VPEN valid. With VPEN VPENLK, lock-bit contents protected against alteration.
13.2
Clear Block Lock-Bits
block lock-bits cleared parallel Clear Block Lock-Bits command. Block lockbits cleared using only Clear Block Lock-Bits command. This command invalid while running device suspended. Clear block lock-bits command executed two-cycle sequence. clear block lock-bits setup first written. device automatically outputs Status Register data when read (see Figure page 66). detect completion clear block lock-bits event analyzing signal output SR.7. When operation complete, SR.5 should checked. clear block lock-bit error detected, Status Register should cleared. will remain Read Status Register mode until another command issued.
28F256J3, 28F128J3, 28F640J3, 28F320J3
This two-step sequence setup followed execution ensures that block lock-bits accidentally cleared. invalid Clear Block Lock-Bits command sequence will result SR.4 SR.5 being set. Also, reliable clear block lock-bits operation only occur when VPEN valid. clear block lock-bits operation attempted while VPEN VPENLK, SR.3 SR.5 will set. clear block lock-bits operation aborted VPEN transitioning valid range, block lock-bit values left undetermined state. repeat clear block lock-bits required initialize block lock-bit contents known values.
13.3
Protection Register Program
Intel StrataFlash® memory (J3) includes 128-bit Protection Register (PR) that used increase security system design. example, number contained used "mate" flash component with other system components such ASIC, preventing device substitution. 128-bits divided into 64-bit segments. segments programmed Intel factory with unique 64-bit number, which unalterable. other segment left blank customer designers program desired. Once customer segment programmed, locked prevent further programming.
13.3.1
Reading Protection Register
Protection Register read identification read mode. device switched this mode issuing Read Identifier command (0x90). Once this mode, read cycles from addresses shown Table Table retrieve specified information. return read array mode, write Read Array command (0xFF).
13.3.2
Programming Protection Register
Protection Register bits programmed using two-cycle Protection Program command. 64-bit number programmed bits time word-wide configuration eight bits time byte-wide configuration. First write Protection Program Setup command, 0xC0. next write device will latch address data program specified location. allowable addresses shown Table Table Figure "Protection Register Programming Flowchart" page attempt address Protection Program commands outside defined address space will result Status Register error (SR.4 will set). Attempting program locked segment will result Status Register error (SR.4 SR.1 will set).
13.3.3
Locking Protection Register
user-programmable segment Protection Register lockable programming this location programmed Intel factory protect unique device number. using Protection Program command program "0xFFFD" PLR. After these bits have been programmed, further changes made values stored Protection Register. Protection Program commands locked section will result Status Register error (SR.4 SR.1 will set). lockout state reversible.
28F256J3, 28F128J3, 28F640J3, 28F320J3
Figure Protection Register Memory
Word Address
0x88
A[24:1]: Mbit A[23:1]: Mbit
A[22:1]: Mbit A[21:1]: Mbit
64-bit Segment (User-Programmable) 0x85 0x84 0x81 Lock Register 0x80
128-Bit Protection Register 64-bit Segment (Factory-Programmed)
NOTE: used mode when accessing Protection Register (See Table addressing). mode used (See Table addressing).
Table Word-Wide Protection Register Addressing
Word LOCK Both Factory Factory Factory Factory User User User User
Table Byte-Wide Protection Register Addressing (Sheet
Byte LOCK LOCK Both Both Factory Factory Factory Factory Factory Factory
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table Byte-Wide Protection Register Addressing (Sheet
Factory Factory User User User User User User User User
NOTE: address lines specified above table must when accessing Protection Register, i.e.g., A[MAX:9]
13.4
Array Protection
VPEN signal hardware mechanism prohibit array alteration. When VPEN voltage below VPENLK voltage, array contents cannot altered. ensure proper erase program operation, VPEN must valid voltage level. determine status erase program operation, poll Status Register analyze bits.
28F256J3, 28F128J3, 28F640J3, 28F320J3
14.0
Special Modes
This section describes read status, registers. This section also details configure signal.
14.1
Read Configuration Register Command
This command longer supported J3C. device will ignore this command, while device will result invalid command sequence (SR.4 SR.5 =1).
14.2
Status (STS)
Status (STS) signal configured different states using Configuration command. Once signal been configured, remains that configuration until another configuration command issued asserted low. Initially, signal defaults operation where RY/BY# indicates that busy. RY/BY# high indicates that state machine ready operation suspended. Table "STS Configuration Coding Definitions" page displays possible configurations. reconfigure Status (STS) signal other modes, Configuration command given followed desired configuration code. three alternate configurations pulse mode system interrupt described below. these configurations, controls Erase Complete interrupt pulse, controls Program Complete interrupt pulse. Supplying 0x00 configuration code with Configuration command resets signal default RY/BY# level mode. possible configurations their usage described Table "STS Configuration Coding Definitions" page Configuration command only given when device busy suspended. Check SR.7 device status. invalid configuration code will result both SR.4 SR.5 being set. When configured pulse modes, signal pulses with typical pulse width
Table Configuration Coding Definitions
Pulse Program Complete Notes
Used control HOLD memory controller prevent accessing flash memory subsystem while flash device's busy. Used generate system interrupt pulse when flash device array completed block erase. Helpful reformatting blocks after file system free space reclamation "cleanup."
Pulse Erase Complete
Reserved
D[1:0] Configuration Codes
default, level mode; device ready indication pulse Erase Complete
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table Configuration Coding Definitions
Pulse Program Complete Notes
Used generate system interrupt pulse when flash device array completed program operation. Provides highest performance servicing continuous buffer write operations. Used generate system interrupts trigger servicing flash arrays when either erase program operations completed, when common interrupt service routine desired.
Pulse Erase Complete
Reserved
D[1:0] Configuration Codes
pulse Program Complete pulse Erase Program Complete
NOTES: When configured pulse modes, pulses with typical pulse width invalid configuration code will result both SR.4 SR.5 being set.
28F256J3, 28F128J3, 28F640J3, 28F320J3
Appendix Common Flash Interface
Common Flash Interface (CFI) specification outlines device host system software interrogation handshake which allows specific vendor-specified software algorithms used entire families devices. This allows device independent, JEDEC ID-independent, forwardand backward-compatible software support specified flash device families. allows flash vendors standardize their existing interfaces long-term compatibility. This appendix defines data structure "database" returned Common Flash Interface (CFI) Query command. System software should parse this structure gain critical information such block size, density, x8/x16, electrical specifications. Once this information been obtained, software will know which command sets enable flash writes, block erases, otherwise control flash component. Query command part overall specification multiple command control interface descriptions called Common Flash Interface, CFI.
Query Structure Output
Query "database" allows system software gain information controlling flash component. This section describes device's CFI-compliant interface that allows host system access Query data. Query data always presented lowest-order data outputs (D[7:0]) only. numerical offset value address relative maximum width supported device. this family devices, Query table device starting address 10h, which word address devices. word-wide (x16) device, first bytes Query structure, ASCII, appear byte word addresses 11h. This CFI-compliant device outputs data upper bytes. Thus, device outputs ASCII byte (D[7:0]) 0x00 (00h) high byte (D[15:8]). Query addresses containing more bytes information, least significant data byte presented lower address, most significant data byte presented higher address. following tables, addresses data represented hexadecimal notation, suffix been dropped. addition, since upper byte word-wide devices always "00h," leading "00" been dropped from table notation only lower byte value shown. device outputs assumed have upper byte this mode.
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table Summary Query Structure Output Function Device Mode
Device Type/ Mode Query start location maximum device width addresses Query data with maximum device width addressing Offset device mode device mode Code 0051 0052 0059 N/A(1) ASCII Value Query data with byte addressing Offset Code ASCII Value "Null"
N/A(1)
NOTE: system must drive lowest order addresses access device's array data when device configured mode. Therefore, word addressing, where these lower addresses toggled system, "Not Applicable" x8-configured devices.
Table Example Query Structure Output x16- x8-Capable Device
Word Addressing Offset A15-A0 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0051 0052 0059 P_IDLO P_IDHI A_IDLO A_IDHI Code D15-D0 PrVendor PrVendor TblAdr AltVendor Value Offset A7-A0 P_IDLO P_IDLO P_IDHI Byte Addressing Code D7-D0 PrVendor Value
Query Structure Overview
Query command causes flash component display Common Flash Interface (CFI) Query structure "database." structure sub-sections address locations summarized below. AP-646 Common Flash Interface (CFI) Command Sets (order number 292204) full description commands. following sections describe Query structure sub-sections detail.
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table Query Structure
Offset (BA+2)h(2) 04-0Fh P(3) Block Status Register Reserved Query Identification String System Interface Information Device Geometry Definition Primary Intel-Specific Extended Query Table Sub-Section Name Device Code Block-Specific Information Reserved Vendor-Specific Information Reserved Vendor-Specific Information Command Vendor Data Offset Flash Device Layout Vendor-Defined Additional Information Specific Primary Vendor Algorithm Description Manufacturer Code Notes
NOTES: Refer Query Structure Output section offset detailed definition offset address function device width mode. Block Address beginning location (i.e., 02000h block beginning location when block size Kbyte). Offset defines which points Primary Intel-Specific Extended Query Table.
Block Status Register
block status register indicates whether erase operation completed successfully whether given block locked accessed flash program/erase operations.
Table Block Status Register
Offset (BA+2)h
Length
Description Block Lock Status Register BSR.0 Block Lock Status Unlocked Locked 1-7: Reserved Future
Address BA+2: BA+2:
Value (bit
BA+2: (bit 1-7): NOTE: beginning location Block Address (i.e., 008000h block (64-KB block) beginning location word mode).
Query Identification String
Query Identification String provides verification that component supports Common Flash Interface specification. also indicates specification version supported vendor-specified command set(s).
Table Identification (Sheet
Offset Length Description Add. Code Value
Query-unique ASCII string "QRY" Primary vendor command control interface code. 16-bit code vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command control interface code.
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table Identification (Sheet
Offset Length Description 0000h means second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists Add. Code Value
System Interface Information
following device information optimize system interface software.
Table System Interface Information
Offset Length Description logic supply minimum program/erase voltage bits bits volts logic supply maximum program/erase voltage bits bits volts [programming] supply minimum program/erase voltage bits bits volts [programming] supply maximum program/erase voltage bits bits volts such that typical single word program time-out such that typical max. buffer write time-out such that typical block erase time-out such that typical full chip erase time-out such that maximum word program time-out times typical such that maximum buffer write time-out times typical such that maximum block erase time-out times typical such that maximum chip erase time-out times typical Add. Code Value
Device Geometry Definition
This field provides critical details flash device geometry.
Table Device Geometry Definition (Sheet
Offset Length Description such that device size number bytes Flash device interface: async async x8/x16 async 28:00,29:00 28:01,29:00 28:02,29:00 such that maximum number bytes write buffer Code Table Below
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table Device Geometry Definition (Sheet
Offset Length Description Number erase block regions within device: means erase blocking; device erases "bulk" specifies number device partition regions with more contiguous same-size erase blocks Symmetrically blocked partitions have blocking region Partition size (total blocks) (individual block size) Erase Block Region Information bits 0-15 number identical-size erase blocks bits 16-31 region erase block(s) size bytes Code Table Below
Device Geometry Definition
Address Mbit Mbit Mbit 256Mbit
Primary-Vendor Specific Extended Query Table
Certain flash features commands optional. Primary Vendor-Specific Extended Query table specifies this other similar information.
Table Primary Vendor-Specific Extended Query (Sheet
Offset(1) (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h Length Description (Optional Flash Features Commands) Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Add. Code Value
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table Primary Vendor-Specific Extended Query (Sheet
Offset(1) Length Description (Optional Flash Features Commands) Optional feature command support (1=yes, 0=no) bits 9-31 reserved; undefined bits "0." then another field optional features follows bit-30 field. Chip erase supported Suspend erase supported Suspend program supported Legacy lock/unlock supported Queued erase supported Instant Individual block locking supported Protection bits supported Page-mode read supported Synchronous read supported Supported functions after suspend: read Array, Status, Query Other supported operations are: bits reserved; undefined bits Program supported after erase suspend Block status register mask bits 2-15 Reserved; undefined bits Block Lock-Bit Status register active Block Lock-Down Status active logic supply highest performance program/erase voltage bits value bits value volts optimum program/erase supply voltage bits value bits value volts Add. Code Value
(P+5)h (P+6)h (P+7)h (P+8)h
1(1)
Yes(1)
(P+9)h
(P+A)h (P+B)h
(P+C)h
(P+D)h
NOTE: Future devices support described "Legacy Lock/Unlock" function. Thus would have value "0."
28F256J3, 28F128J3, 28F640J3, 28F320J3
Table Protection Register Information
Offset(1) (P+E)h Length Description (Optional Flash Features Commands) Number Protection register fields JEDEC space. "00h," indicates that protection bytes available Protection Field Protection Description This field describes user-available Time Programmable (OTP) Protection Register bytes. Some pre-programmed with device-unique serial numbers. Others userprogrammable. Bits 0-15 point Protection Register lock byte, section's first byte. following bytes factory pre-programmed user-programmable. bits Lock/bytes JEDEC-plane physical address bits 8-15 Lock/bytes JEDEC-plane physical high address bits 16-23 such that factory pre-programmed bytes bits 24-31 such that user-programmable bytes Add. Code Value
8bytes 8bytes
(P+F)h (P+10)h (P+11)h (P+12)h
NOTE: variable pointer which defined offset 15h.
Table Burst Read Information
Offset(1) Length Description (Optional Flash Features Commands) Page Mode Read capability (P+13)h bits such that value represents number read-page bytes. offset device word width determine page-mode data output width. indicates read page buffer. Number synchronous mode read configuration fields that follow. indicates burst capability. Reserved future byte Add. Code Value
(P+14)h
(P+15)h NOTE: variable pointer which defined offset 15h.
28F256J3, 28F128J3, 28F640J3, 28F320J3
Appendix Flow Charts
Figure Write Buffer Flowchart
Start
Setup Write 0xE8 Block Address
Check Buffer Status Perform read operation Read Ready Status signal
Word Count Address block address Data word count minus (Valid range 0x00 to0x1F)
Load Buffer Fill write buffer word count Address within buffer range Data user data
Confirm Write 0xD0 Block address
Read Status Register (SR)
Full Status Register Check desired)
28F256J3, 28F128J3, 28F640J3, 28F320J3
Figure Status Register Flowchart
Start
Command Cycle Issue Status Register Command Address address Data 0x70
Data Cycle Read Status Register SR[7:0]
Set/Reset
Erase Suspend Suspend/Resume Flowchart
Program Suspend Suspend/Resume Flowchart
Error Command Sequence
Error Erase Failure
Error Program Failure
Reset user Clear Status Register Command
Error VPENLK
Error Block Locked
0606_07A
28F256J3, 28F128J3, 28F640J3, 28F320J3 Figure Byte/Word Program Flowchart
Start
Operation Write Write
Command Setup Byte/ Word Program Byte/Word Program
Comments Data Addr Location Programmed Data Data Programmed Addr Location Programmed Status Register Data Check SR.7 Ready Busy
Write 40H, Address Write Data Address Read Status Register Full Status Check Desired Byte/Word Program Complete
Read (Note Standby
SR.7
Toggling (low high low) updates status register. This done place issuing Read Status Register command. Repeat subsequent programming operations. full status check done after each program operation, after sequence programming operations. Write after last program operation place device read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.1 SR.4 Byte/Word Program Successful Programming Error Voltage Range Error
Standby Operation Standby Command Comments Check SR.3 Programming Voltage Error Detect Check SR.1 Device Protect Detect Block Lock-Bit Only required systems implemeting lock-bit configuration. Check SR.4 Programming Error
Device Protect Error
Standby
Toggling (low high low) updates status register. This done place issuing Read Status Register command. Repeat subsequent programming operations. SR.4, SR.3 SR.1 only cleared Clear Status Register command cases where multiple locations programmed before full status checked. error detected, clear status register before attempting retry other error recovery.
28F256J3, 28F128J3, 28F640J3, 28F320J3
Figure Program Suspend/Resume Flowchart
Operation Write Write Read
Start
Command Program Suspend
Comments Data Addr Status Register Data Addr Check SR.7 Ready Busy Check SR.6 Programming Suspended Programming Completed
Read Status Register
Standby
SR.7
Standby
Write SR.2 Programming Completed Write Write Read
Read Array
Data Addr Read array locations other than that being programmed.
Program Resume
Data Addr
Read Data Array
Done Reading Write Write
Programming Resumed
Read Array Data
0606_08
28F256J3, 28F128J3, 28F640J3, 28F320J3
Figure Block Erase Flowchart
Operation Write Issue Single Block Erase Command 20H, Block Address Write (Note
Start
Command Erase Block Erase Confirm
Comments Data Addr Block Address Data Addr Status register data With device enabled, updates Addr Check SR.7 Ready Busy
Read
Standby Write Confirm Block Address
Erase Confirm byte must follow Erase Setup. This device does support erase queuing. Please Application note AP-646 software erase queuing compatibility. Full status check done after erase write sequences complete. Write after last operation reset device read array mode. Suspend Erase Loop
Read Status Register
SR.7
Suspend Erase
Full Status Check Desired
Erase Flash Block(s) Complete
0606_09
28F256J3, 28F128J3, 28F640J3, 28F320J3
Figure Block Erase Suspend/Resume Flowchart
Operation Write Write Read
Start
Command Erase Suspend
Comments Data Addr Status Register Data Addr Check SR.7 Ready Busy Check SR.6 Block Erase Suspended Block Erase Completed
Read Status Register
Standby
SR.7
Standby
Write SR.6 Block Erase Completed
Erase Resume
Data Addr
Read Read Program? Read Array Data Done? Write Write Program Loop Program
Block Erase Resumed
Read Array Data
0606_10
28F256J3, 28F128J3, 28F640J3, 28F320J3
Figure Block Lock-Bit Flowchart
Start
Operation Write
Command Block Lock-Bit Setup Block Lock-Bit Confirm
Comments Data Addr =Block Address Data Addr Block Address Status Register Data Check SR.7 Ready Busy
Write 60H, Block Address Write 01H, Block Address
Write
Read
Read Status Register
Standby
SR.7 Full Status Check Desired
Repeat subsequent lock-bit operations. Full status check done after each lock-bit operation after sequence lock-bit operations. Write after last lock-bit operation place device read array mode.
Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.4,5 SR.4 Lock-Bit Successful Lock-Bit Error Command Sequence Error Voltage Range Error
Standby Operation Standby Command Comments Check SR.3 Programming Voltage Error Detect Check SR.4, Both Command Sequence Error Check SR.4 Lock-Bit Error
Standby
SR.5, SR.4 SR.3 only cleared Clear Status Register command, cases where multiple lock-bits before full status checked. error detected, clear status register before attempting retry other error recovery.
28F256J3, 28F128J3, 28F640J3, 28F320J3
Figure Clear Lock-Bit Flowchart
Start
Operation Write
Command Clear Block Lock-Bits Setup Clear Block Lock-Bits Confirm
Comments Data Addr Data Addr Status Register Data Check SR.7 Ready Busy
Write
Write
Write
Read
Read Status Register
Standby
SR.7 Full Status Check Desired Clear Block Lock-Bits Complete
Write after clear lock-bits operation place device read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.4,5 SR.5 Clear Block Lock-Bits Successful Clear Block Lock-Bits Error Command Sequence Error Voltage Range Error
Standby Operation Standby Command Comments Check SR.3 Programming Voltage Error Detect Check SR.4, Both Command Sequence Error Check SR.5 Clear Block Lock-Bits Error
Standby
SR.5, SR.4, SR.3 only cleared Clear Status Register command. error detected, clear status register before attempting retry other error recovery.
28F256J3, 28F128J3, 28F640J3, 28F320J3
Figure Protection Register Programming Flowchart
Start
Operation Write Write
Command Protection Program Setup Protection Program
Comments Data Data Data Program Addr Location Program Status Register Data Toggle Update Status Register Data Check SR.7 Ready Busy
Write (Protection Reg. Program Setup) Write Protect. Register Address/Data
Read
Standby
Read Status Register
SR.7 Full Status Check Desired
Protection Program operations only addressed within protection register address space. Addresses outside defined space will return error. Repeat subsequent programming operations. Full Status Check done after each program after sequence program operations. Write after last program operation reset device read array mode.
Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3, SR.4 VPEN Range Error SR.1, SR.4
Standby Operation Standby Command Comments SR.1 SR.3 SR.4 Prot. Reg. Prog. Error Register Locked: Aborted
Protection Register Programming Error Attempted Program Locked Register Aborted
Standby
SR.3 MUST cleared, during program attempt, before further attempts allowed Write State Machine.
SR.1, SR.4
SR.1, SR.3 SR.4 only cleared Clear Staus Register Command, cases multiple protection register program operations before full status checked. error detected, clear status register before attempting retry other error recovery.
Program Successful
28F256J3, 28F128J3, 28F640J3, 28F320J3
Appendix Design Considerations
Three-Line Output Control
device will often used large memory arrays. Intel provides five control inputs (CE0, CE1, CE2, OE#, RP#) accommodate multiple memory connections. This control provides for:
Lowest possible memory power dissipation. Complete assurance that data contention will occur.
these control inputs efficiently, address decoder should enable device (see Table while should connected memory devices system's READ# control line. This assures that only selected memory devices have active outputs while de-selected memory devices standby mode. should connected system POWERGOOD signal prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.
Block Erase, Program, Lock-Bit Configuration Polling
open drain output that should connected VCCQ pull-up resistor provide hardware method detecting block erase, program, lock-bit configuration completion. recommended that 2.5k resister used between STS# VCCQ. default mode, transitions after block erase, program, lock-bit configuration commands returns High when finished executing internal algorithm. alternate configurations signal, Configuration command. connected interrupt input system controller. active times. STS, default mode, also High when device block erase suspend (with programming inactive), program suspend, reset/power-down mode.
Input Signal Transitions-Reducing Overshoots Undershoots When Using Buffers Transceivers
faster, high-drive devices such transceivers buffers drive input signals flash memory devices, overshoots undershoots sometimes cause input signals exceed flash memory specifications. (See Voltage Characteristics" page 20.) Many buffer/transceiver vendors carry bus-interface devices with internal output-damping resistors reduced-drive outputs. Internal output-damping resistors diminish nominal output drive currents, while still leaving sufficient drive capability most applications. These internal output-damping resistors help reduce unnecessary overshoots undershoots. Transceivers buffers with balanced- lightdrive outputs also reduce overshoots undershoots diminishing output-drive currents. When considering buffer/transceiver interface design flash, devices with internal output-damping resistors reduced-drive outputs should used minimize overshoots undershoots. additional information, please refer AP-647, Volt Intel StrataFlash® Memory Design Guide (Order Number: 292205).
28F256J3, 28F128J3, 28F640J3, 28F320J3
VCC, VPEN, Transitions
Block erase, program, lock-bit configuration guaranteed VPEN falls outside specified operating ranges, VIH. transitions during block erase, program, lock-bit configuration, default mode) will remain maximum time tPLPH tPHRH until reset operation complete. Then, operation will abort device will enter reset/power-down mode. aborted operation leave data partially corrupted after programming, partially altered after erase lock-bit configuration. Therefore, block erase lock-bit configuration commands must repeated after normal operation restored. Device power-off clears Status Register. latches commands issued system software altered VPEN, CE0, CE1, transitions, actions. state read array mode upon power-up, after exit from reset/ power-down mode, after transitions below VLKO. must kept above VPEN during transitions. After block erase, program, lock-bit configuration, even after VPEN transitions down VPENLK, must placed read array mode Read Array command subsequent access memory array desired. VPEN must kept below during VPEN transitions.
Power Dissipation
When designing portable systems, designers must consider battery power consumption only during device operation, also data retention during system idle time. Flash memory's nonvolatility increases usable battery life because data retained when system power removed.
28F256J3, 28F128J3, 28F640J3, 28F320J3
Appendix Additional Information
Order Number
Document/Tool Intel StrataFlashMemory (J3); 28F256J3, 28F128J3, 28F640J3, 28F320J3 Specification Update Intel® Persistent Storage Manager (IPSM) User's Guide Software Manual Intel® Flash Data Integrator (FDI) User's Guide Software Manual Intel StrataFlash® Synchronous Memory (K3/K18); 28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18 AP-732 Volt Intel StrataFlash® Memory K3/K18 Migration Guide AP-689 Using Intel® Persistent Storage Manager Volt Intel® StrataFlashMemoryI28F320J5 28F640J5 datasheet AP-677 Intel® StrataFlashMemory Technology AP-664 Designing Intel® StrataFlashMemory into Intel® Architecture AP-663 Using Intel® StrataFlashMemory Write Buffer AP-660 Migration Guide Volt Intel® StrataFlashMemory AP-646 Common Flash Interface (CFI) Command Sets Intel® Wireless Communications Computing Package User's Guide
298130 298136 297833 290737 292280 292237 290606 297859 292222 292221 292218 292204 253418
Please call Intel Literature Center (800) 548-4725 request Intel documentation. International customers should contact their local Intel distribution sales office. Visit Intel's World Wide home page http://www.intel.com technical documentation tools. most current information Intel StrataFlash memory, visit website http://
28F256J3, 28F128J3, 28F640J3, 28F320J3
Appendix Ordering Information
Package 56-Lead TSOP (J3A, 802) 56-Lead TSOP (J3C, 803) Pb-Free 56-TSOP 64-Ball Easy 48-Ball VFBGA 64-Ball Pb-Free Easy
Access Speed (ns) Mbit Mbit 150, Mbit 120, Mbit
Intel® 0.25 micron lithography Intel® 0.18 micron lithography Voltage PEN) Product Family Intel® StrataFlashmemory, bits-per-cell
Product line designator Intel Flash products
Device Density x8/x16 (256 Mbit) x8/x16 (128 Mbit) x8/x16 Mbit) x8/x16 Mbit)
NOTE: These speeds either standard asynchronous read access times first access pagemode read sequence.
VALID COMBINATIONS
56-Lead TSOP E28F320J3A-110 E28F640J3A-120 E28F128J3A-150 TE28F320J3C-110 TE28F640J3C-115 TE28F640J3C-120 TE28F128J3C-120 TE28F128J3C-150 TE28F256J3C-125 56-Lead Pb-Free TSOP JS28F256J3C125 JS28F128J3C120 JS28F640J3C115 JS28F320J3C110 64-Ball Easy RC28F320J3A-110 RC28F640J3A-120 RC28F128J3A-150 RC28F320J3C-110 RC28F640J3C-115 RC28F640J3C-120 RC28F128J3C-120 RC28F128J3C-150 RC28F256J3C-125 64-Ball Pb-Free Easy PC28F256J3C125 PC28F128J3C120 PC28F640J3C115 PC28F320J3C110 48-Ball GE28F320J3A-110 GE28F320J3C-110 GE28F640J3C-115 GE28F640J3C-120
28F256J3, 28F128J3, 28F640J3, 28F320J3
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