Code Compatible with 80960Jx Processors High-Performance Embedded Arch

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80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Code Compatible with 80960Jx Processors High-Performance Embedded Architecture Instruction/Clock Execution Core Clock Rate Clock 80960JA/JF/JS Clock 80960JD/JC Clock 80960JT Load/Store Programming Model Sixteen 32-Bit Global Registers Sixteen 32-Bit Local Registers sets) Nine Addressing Modes User/Supervisor Protection Model Two-Way Associative Instruction Cache 80960JA Kbyte 80960JF/JD Kbyte 80960JS/JC/JT Kbyte Programmable Cache-Locking Mechanism Direct Mapped Data Cache 80960JA Kbyte 80960JF/JD Kbyte 80960JS/JC/JT Kbyte Write Through Operation On-Chip Stack Frame Cache Seven Register Sets Saved Automatic Allocation Call/Return Frames Reserved High-Priority Interrupts
On-Chip Data Kbyte Critical Variable Storage Single-Cycle Access Supply Voltage Tolerant Inputs Compatible Outputs High Bandwidth Burst 32-Bit Multiplexed Address/Data Programmable Memory Configuration Selectable 16-, 32-Bit Widths Supports Unaligned Accesses Little Endian Byte Ordering High-Speed Interrupt Controller Programmable Priorities Eight Maskable Pins plus NMI# Vectors Expanded Mode On-Chip Timers Independent 32-Bit Counting Clock Prescaling Internal Interrupt Sources Halt Mode Power IEEE 1149.1 (JTAG) Boundary Scan Compatibility Packages 132-Lead Grid Array (PGA) 132-Lead Plastic Quad Flat Pack (PQFP) 196-Ball Mini Plastic Ball Grid Array (MPBGA)
Order Number: 273159-006 August 2004
INFORMATION THIS DOCUMENT PROVIDED CONNECTION WITH INTEL® PRODUCTS. LICENSE, EXPRESS IMPLIED, ESTOPPEL OTHERWISE, INTELLECTUAL PROPERTY RIGHTS GRANTED THIS DOCUMENT. EXCEPT PROVIDED INTEL'S TERMS CONDITIONS SALE SUCH PRODUCTS, INTEL ASSUMES LIABILITY WHATSOEVER, INTEL DISCLAIMS EXPRESS IMPLIED WARRANTY, RELATING SALE AND/OR INTEL PRODUCTS INCLUDING LIABILITY WARRANTIES RELATING FITNESS PARTICULAR PURPOSE, MERCHANTABILITY, INFRINGEMENT PATENT, COPYRIGHT OTHER INTELLECTUAL PROPERTY RIGHT. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. 80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com. AlertVIEW, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Connect, Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, LANDesk, LanRover, MCS, MMX, logo, Optimizer logo, OverDrive, Paragon, Dads, Parents, PDCharm, Pentium, Pentium Xeon, Pentium Xeon, Performance Your Command, RemoteExpress, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, Computer Inside., Journey Inside, TokenExpress, Trillium, VoiceBrick, Vtune, Xircom trademarks registered trademarks Intel Corporation subsidiaries United States other countries. *Other names brands claimed property others. Copyright Intel Corporation, 2002, 2004
Contents
Contents
Introduction. 80960Jx Overview. 2.10 80960 Processor Core. Burst Timer Unit Priority Interrupt Controller.11 Instruction Summary Faults Debugging.12 Power Operation Test Features.12 Memory-Mapped Control Registers Data Types Memory Addressing Modes.13 Available Processors Packages Descriptions 3.2.1 Functional Definitions 3.2.2 80960Jx 132-Lead Pinout 3.2.3 80960Jx 132-Lead PQFP Pinout 3.2.4 80960Jx 196-Ball MPBGA Pinout Absolute Maximum Ratings Operating Conditions Connection Recommendations.36 VCC5 Requirements (VDIFF) VCCPLL Requirements D.C. Specifications A.C. Specifications.42 4.7.1 A.C. Test Conditions Derating Curves 4.7.1.1 Output Delay Hold Load Capacitance.46 4.7.1.2 Load Capacitance.47 4.7.1.3 Active Frequency 4.7.2 A.C. Timing Waveforms 80960JS/JC/JT Device Identification Register.60 80960JD Device Identification Register 80960JA/JF Device Identification Register Thermal Management Accessories 6.1.1 Heatsinks Basic States.79 Boundary-Scan Register.80
Packaging Information.15
Electrical Specifications
Device Identification.59
Thermal Specifications
Functional Waveforms
Contents
Figures
80960Jx Microprocessor Package Options 80960Jx Block Diagram. 132-Lead Grid Array View-Pins Facing Down. 132-Lead Grid Array Bottom View-Pins Facing 132-Lead PQFP View 196-Ball Mini Plastic Ball Grid Array View-Balls Facing Down 196-Ball Mini Plastic Ball Grid Array Bottom View-Balls Facing VCC5 Current-Limiting Resistor VCCPLL Lowpass Filter A.C. Test Load. Output Delay Hold Load Capacitance-80960JS/JC/JT (3.3 Signals) Output Delay Hold Load Capacitance-80960JS/JC/JT Signals) Output Delay Hold Load Capacitance-80960JA/JF/JD Load Capacitance-80960JS/JC/JT (3.3 Signals) Load Capacitance-80960JS/JC/JT Signals) Load Capacitance-80960JA/JF/JD. Active (Power Supply) Frequency-80960JA/JF 80960JA/JF Active (Thermal) Frequency 80960JD Active (Power Supply) Frequency 80960JD Active (Thermal) Frequency 80960JC Active (Power Supply) Frequency 80960JC Active (Thermal) Frequency 80960JS Active (Power Supply) Frequency 80960JS Active (Thermal) Frequency CLKIN Waveform. TOV1 Output Delay Waveform Output Float Waveform TIS1 TIH1 Input Setup Hold Waveform TIS2 TIH2 Input Setup Hold Waveform TIS3 TIH3 Input Setup Hold Waveform TIS4 TIH4 Input Setup Hold Waveform TLX, TLXL TLXA Relative Timings Waveform DT/R# DEN# Timings Waveform. Waveform TBSIS1 TBSIH1 Input Setup Hold Waveforms. TBSOV1 TBSOF1 Output Delay Output Float Waveform TBSOV2 TBSOF2 Output Delay Output Float Waveform TBSIS2 TBSIH2 Input Setup Hold Waveform. 80960JS/JC/JT Device Identification Register Fields 80960JD Device Identification Register Fields 80960JA/JF Device Identification Register Fields Non-Burst Read Write Transactions Without Wait States, 32-Bit Bus. Burst Read Write Transactions Without Wait States, 32-Bit Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Burst Read Write Transactions Without Wait States, 8-Bit Burst Read Write Transactions With Wait States Extra State Read, 16-Bit Double Word Read Request, Misaligned Byte From Quad Word Boundary, 32-Bit Bus, Little Endian
Contents
HOLD/HOLDA Waveform Arbitration Cold Reset Waveform.76 Warm Reset Waveform Entering ONCE State.78 States with Arbitration.80 Summary Aligned Unaligned Accesses (32-Bit Bus).84 Summary Aligned Unaligned Accesses (32-Bit Bus) (Continued)
Tables
80960Jx 3.3-V Microprocessor Family 80960Jx Instruction 80960Jx Processors Available 132-Pin Package.15 80960Jx Processors Available 132-Pin PQFP Package.15 80960Jx Processors Available Extended Temperature 80960Jx Processors Available 196-Ball MPBGA Package.16 Description Nomenclature Description-External Signals.18 Description-Processor Control Signals, Test Signals, Power Description-Interrupt Unit Signals 132-Lead Pinout-In Signal Order 132-Lead Pinout-In Order.26 132-Lead PQFP Pinout-In Signal Order.28 132-Lead PQFP Pinout-In Order.29 196-Ball MPBGA Pinout-In Signal Order.32 196-Ball MPBGA Pinout-In Order Absolute Maximum Ratings 80960Jx Operating Conditions VDIFF Parameters.37 80960Jx D.C. Characteristics 80960Jx Characteristics 80960Jx A.C. Characteristics Note Definitions Table 80960Jx Characteristics.45 80960Jx Device Type Stepping Reference 80960JS/JC/JT Device Register Field Definitions.60 80960JS/JC/JT Device Model Types 80960JD Device Field Definitions 80960JD Device Model Types 80960JA/JF Device Field Definitions 80960JA/JF Device Model Types Thermal Resistance Reference Table Maximum Ambient Temperature Reference Table.63 132-Lead Package Thermal Characteristics 80960JA/JF/JD 196-Ball MPBGA Package Thermal Characteristics 80960JS/JC/JT 196-Ball MPBGA Package Thermal Characteristics 132-Lead PQFP Package Thermal Characteristics.65 Maximum Various Airflows (80960JT) Maximum Various Airflows (80960JC).66 Maximum Various Airflows (80960JD).67 Maximum Various Airflows (80960JS) Maximum Various Airflows (80960JA/JF)
Contents
Boundary-Scan Register-Bit Order Natural Boundaries Load Store Accesses. Summary Byte Load Store Accesses Summary Short Word Load Store Accesses Summary n-Word Load Store Accesses
Revision History
Date August 2004 Revision Description address fact that many package prefix variables have changed, package prefix variables this document indicated with "x". Removed reference A80960JF-16 from Table page Removed reference NG80960JC-40, NG80960JC-33, NG80960JS-16, NG80960JF-16 from Table page Removed reference GD80960JC-40, GD80960JC-33, 80960JS-16 Table page September 2002 Removed reference 80960JC-40, 80960JC-33, 80960JS-16, 80960JF-16 Table page Removed reference 80960JC-40, 80960JC-33, 80960JS-16, 80960JF-16 from Table page Removed reference 80960JC-40, 80960JC-33, 80960JS-16 80960JF-16 from Table page Added extended temp device offerings. Table page September 1999 Removed package availability from JS/JC/JT processors. Changed timing parameter TOV1 (min) extended temp devices only. Table page Merged 80960JS/JC datasheet information into this datasheet (previously named 80960JA/JF/JD/JT Embedded 32-Bit Microprocessor datasheet). Increased TIH1 specification 80960JS/JC/JT processors. Updated MPBGA thermal specifications. Corrected orientation MPBGA package diagrams (Figure page Figure page 31). December 1998 Added Figure page Figure page Figure page Figure page distinguish 80960JT 3.3-V signal derating curves from 80960JA/JF/JD derating curves. This datasheet supersedes revisions following 80960Jx datasheets: #273109 (JT), #272971-002 (JD), #276146-001 (JA/JF). addition combining documents into one, following content changed: March 1998 Figure page Added MPBGA package diagram. Section 3.2.4, "80960Jx 196-Ball MPBGA Pinout" page Added Figures Tables Figure page Added with note that follows figure. Updated values 80960JS/JC/JT processors.
June 1999
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Introduction
This document contains information 80960Jx microprocessors, including electrical characteristics package pinout information. Detailed functional descriptions, other than parametric performance, published i960® Microprocessor Developer's Manual (272483) viewed online
Figure 80960Jx Microprocessor Package Options
x80960JX
XXXXXXXXSS
19xx
i960
x80960JX
x80960JX XXXXXXXSS 19xx
XXXXXXXX
19xx
196-Ball MPBGA
132-Pin PQFP 132-Pin
Throughout this datasheet, references `80960Jx' indicate features that apply 3.3-V processors only:
NOTE: address fact that many package prefix variables have changed, package prefix variables this document indicated with "x".
Table 80960Jx 3.3-V Microprocessor Family
Processor 80960JA 80960JF 80960JD 80960JS 80960JC 80960JT Voltage Tolerant) Tolerant) Tolerant) Tolerant) Tolerant) Tolerant) Instruction Cache Kbyte Kbyte Kbyte Kbyte Kbyte Kbyte Data Cache Kbyte Kbyte Kbyte Kbyte Kbyte Kbyte Core Clock
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
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80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
80960Jx Overview
80960Jx processor offers high performance cost-sensitive 32-bit embedded applications. 80960Jx object code compatible with 80960 core architecture capable sustained execution rate instruction clock. This processor's features include generous instruction cache, data cache, data RAM. also boasts fast interrupt mechanism dual-programmable timer units. 80960Jx processor's clock multiplication operates processor core three times clock rate improve execution performance without increasing complexity board designs. Memory subsystems cost-sensitive embedded applications often impose substantial wait state penalties. 80960Jx integrates considerable storage resources on-chip decouple execution from external bus. 80960Jx rapidly allocates de-allocates local register sets during context switches. processor must flush register stack only when saves more than seven sets local register cache. 32-bit multiplexed burst provides high-speed interface system memory I/O. full complement control signals simplifies connection 80960Jx external components. user programs physical logical memory attributes through memory-mapped control registers (MMRs), extension found i960® processors. Physical logical configuration registers enable processor operate with combinations width data object alignment. processor supports homogeneous byte ordering model. This processor integrates important peripherals: timer unit interrupt controller. These other hardware resources programmed through memory-mapped control registers, extension familiar i960 processor architecture. timer unit (TU) offers independent 32-bit timers real-time system clocks general-purpose system timing. These operate either single-shot auto-reload mode generate interrupts. interrupt controller unit (ICU) provides flexible, low-latency means requesting interrupts. provides full programmability interrupt sources into priority levels. takes advantage cached priority table optional routine caching minimize interrupt latency. Clock doubling 80960JD/JC processors reduces interrupt latency compared 80960JA/JF, clock tripling 80960JT reduces interrupt latency compared 80960JD/JC. Local registers dedicated high-priority interrupts further reduce latency. Acting independently from core, compares priorities posted interrupts with current process priority, off-loading this task from core. also supports integrated timer interrupts. 80960Jx features Halt mode designed support applications where power consumption critical. halt instruction shuts down instruction execution, resulting power savings percent. 80960Jx's testability features, including ONCE (On-Circuit Emulation) mode Boundary Scan (JTAG), provide powerful environment design debug fault diagnosis.
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Solutions960® program features wide variety development tools which support i960 processor family. Many these tools developed partner companies; some developed Intel, such profile-driven optimizing compilers. more information these products, contact your local Intel representative. Figure 80960Jx Block Diagram
Physical Region Configuration Control Unit Request Queues Control Address/ Data
CLKIN
PLL, Clocks, Power Mgmt
32-bit buses address data
Instruction Cache 80960JA 80960JF/JD
Boundary Scan Controller
80960JS/JC/JT
Instruction Sequencer
Constants Control
32-Bit Timers Interrupt Port
8-Set Local Register Cache Multiply Divide Unit Execution Address Generation Unit
effective address
Programmable Interrupt Controller Memory Interface Unit
Memory-Mapped Register Interface
Global Local Register File
SRC1 SRC2 DEST
32-bit Address 32-bit Data
Data
SRC1
SRC2
DEST
DEST
SRC1
SRC2
SRC1
DEST
Independent 32-Bit SRC1, SRC2, DEST Buses
Direct Mapped Data Cache 80960JA 80960JF/JD 80960JS/JC/JT
80960 Processor Core
80960Jx family scalar implementation 80960 core architecture. Intel designed this processor core very high performance device that also cost-effective. Factors that contribute core's performance include:
Core operates speed with 80960JA/JF/JS Core operates three times speed with 80960JD/JC 80960JT,
respectively
Single-clock execution most instructions Independent Multiply/Divide Unit Efficient instruction pipeline minimizes pipeline break latency Register resource scoreboarding allow overlapped instruction execution 128-bit register speeds local register caching Two-way associative, integrated instruction cache Direct-mapped, integrated data cache 1-Kbyte integrated data delivers zero wait state program data
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Burst
32-bit high-performance Controller Unit (BCU) interfaces 80960Jx external memory peripherals. fetches instructions transfers data rate four 32-bit words clock cycles. external address/data multiplexed. Users configure 80960Jx's controller match application's fundamental memory organization. Physical width register-programmed eight regions. Byte ordering data caching programmed through group logical memory templates defaults register. BCU's features include:
Multiplexed external minimize count 32-, 16-, 8-bit widths simplify interfaces External ready control address-to-data, data-to-data data-to-next-address wait state
types
Support little endian byte ordering facilitate porting existing program code Unaligned accesses performed transparently Three-deep load/store queue decouple from core
Upon reset, 80960Jx conducts internal self-test. Then, before executing first instruction, performs external confidence test performing checksum first words initialization boot record (IBR).
Timer Unit
timer unit (TU) contains independent 32-bit timers that capable counting several clock rates generating interrupts. Each programmed registers. These memory-mapped registers addressable 32-bit boundaries. timers have single-shot mode auto-reload capabilities continuous operation. Each timer independent interrupt request 80960Jx's interrupt controller. generate fault when unauthorized writes from user mode detected. Clock prescaling supported.
Priority Interrupt Controller
programmable interrupt controller manages external sources through 8-bit external interrupt port. Alternatively, interrupt inputs configured individual edge- leveltriggered inputs. interrupt unit (IU) also accepts interrupts from on-chip timer channels single Non-Maskable Interrupt (NMI#) pin. Interrupts serviced according their priority levels relative current process priority. interrupt latency critical many embedded applications. part highly flexible interrupt mechanism, 80960Jx exploits several techniques minimize latency:
Interrupt vectors interrupt handler routines reserved on-chip. Register frames high-priority interrupt handlers cached on-chip. interrupt stack placed cacheable memory space. Interrupt microcode executes three times frequency 80960JD/JC 80960JT, respectively.
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Instruction Summary
80960Jx adds several instructions i960 processor core architecture. instructions are:
Conditional Move Conditional Conditional Subtract Byte Swap Halt Cache Control Interrupt Control
Table identifies instructions that 80960Jx supports. Refer i960® Microprocessor Developer's Manual (272483) detailed description each instruction.
Faults Debugging
80960Jx employs comprehensive fault model. processor responds faults making implicit calls fault handling routine. Specific information collected each fault allows fault handler diagnose exceptions recover appropriately. processor also built-in debug capabilities. software, 80960Jx configured detect many seven different trace event types. Alternatively, mark fmark instructions generate trace events explicitly instruction stream. Hardware breakpoint registers also available trap execution data addresses.
Power Operation
Intel fabricates 80960Jx using advanced sub-micron manufacturing process. processor's sub-micron topology provides circuit density optimal cache size high operating speeds while dissipating modest power. processor also uses dynamic power management turn clocks unused circuits. Users program 80960Jx enter Halt mode maximum power savings. Halt mode, processor core stops completely while integrated peripherals continue function, reducing overall power requirements percent. Processor execution resumes from internally externally generated interrupts.
Test Features
80960Jx incorporates numerous features that enhance user's ability test both processor system which attached. These features include ONCE (On-Circuit Emulation) mode Boundary Scan (JTAG).
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
80960Jx provides testability features compatible with IEEE Standard Test Access Port Boundary Scan Architecture (IEEE Std. 1149.1). boundary scan instructions, HIGHZ, forces processor float output pins (ONCE mode). ONCE mode also initiated reset without using boundary scan mechanism. ONCE mode useful board-level testing. This feature allows mounted 80960Jx electrically "remove" itself from circuit board. This allows system-level testing which remote tester, such in-circuit emulator, exercise processor system. provided test logic does interfere with component circuit board behavior ensures that components function correctly, connections between various components correct, various components interact correctly printed circuit board. JTAG Boundary Scan feature attractive alternative conventional "bed-of-nails" testing. examine connections that might otherwise inaccessible test system.
Memory-Mapped Control Registers
80960Jx, although compliant with i960 processor core, added advantage memory-mapped, internal control registers found i960 processors. These registers give software interface easily read modify internal control registers. Each these registers accessed memory-mapped, 32-bit register. Access accomplished through regular memory-format instructions. processor ensures that these accesses generate external cycles.
2.10
Data Types Memory Addressing Modes
with i960 processors, 80960Jx instruction supports several data types formats:
fields Integer (8-, 16-, 32-, 64-bit) Ordinal (8-, 16-, 32-, 64-bit unsigned integers) Triple word bits) Quad word (128 bits)
80960Jx provides full addressing modes assembly programming: Absolute modes Five Register Indirect modes Index with displacement with displacement
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table
80960Jx Instruction
Data Movement Subtract Multiply Divide Remainder Load Store Move Conditional Select Load Address Modulo Shift Extended Shift Extended Multiply Extended Divide with Carry Subtract with Carry Conditional Conditional Subtract Rotate Comparison Compare Conditional Compare Compare Increment Compare Decrement Test Condition Code Check Debug Processor Management Flush Local Registers Modify Arithmetic Controls Modify Trace Controls Mark Force Mark Modify Process Controls Halt System Control Cache Control Interrupt Control Denotes 80960 instructions unavailable 80960CA/CF, 80960KA/KB 80960SA/SB processors. Atomic Atomic Modify Unconditional Branch Conditional Branch Compare Branch Branch Call Call Extended Call System Return Branch Link Atomic Conditional Fault Synchronize Faults Call/Return Fault Exclusive Exclusive Nand Clear Alter Scan Span Over Extract Modify Scan Byte Equal Byte Swap Arithmetic Logical Bit, Field Byte
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Packaging Information
Available Processors Packages
80960Jx offered various speed grades three package types. 132-pin Grid Array (PGA) device specified operation 0.15 over case temperature range 100° following processor versions available package:
Table
80960Jx Processors Available 132-Pin Package
Processor x80960JD-66 x80960JD-33 x80960JA/JF-33 x80960JF-25 Core Speed Speed
pinout diagrams package, Section 3.2.2, "80960Jx 132-Lead Pinout" page 132-pin Plastic Quad Flatpack (PQFP) devices specified operation 0.15 over case temperature range 100° Table presents 80960Jx processor versions that available 132-pin PQFP package: Table 80960Jx Processors Available 132-Pin PQFP Package
Processor x80960JT-100 x80960JC-66 x80960JC-50 x80960JS-33 x80960JS-25 x80960JD-66 x80960JD-40 x80960JA/JF-33 x80960JA/JF-25 x80960JA-16 Core Speed Speed
pinout diagrams PQFP package, Section 3.2.3, "80960Jx 132-Lead PQFP Pinout" page Extended temperature devices specified operation 0.15 over case temperature range -40° 100° Table presents 80960Jx processor versions that available extended temperature 132-pin PQFP package MPBGA package:
NOTE: address fact that many package prefix variables have changed, package prefix variables this document indicated with "x".
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table
80960Jx Processors Available Extended Temperature
Processor x80960JA-25 x80960JS-25 x80960JS-33 x80960JC-66 x80960JT-100 x80960JC-66ET Core Speed Speed Package Type PQFP PQFP PQFP PQFP PQFP MPBGA
196-ball Mini Plastic Ball Grid Array (MPBGA) device specified operation 0.15 over case temperature range 100° Table presents 80960Jx processor versions that available 196-ball MPBGA package: Table 80960Jx Processors Available 196-Ball MPBGA Package
Processor x80960JT-100 x80960JC-66 x80960JS-33 x80960JS-25 x80960JD-50 x80960JA/JF-33 Core Speed Speed
pinout diagrams PQFP package, Section 3.2.4, "80960Jx 196-Ball MPBGA Pinout" page additional package specifications information, refer Intel Packaging Databook, available individual chapters, http://www.intel.com.
NOTE: address fact that many package prefix variables have changed, package prefix variables this document indicated with "x".
Descriptions
This section describes pins 80960Jx processors. description function, Section 3.2.1, "Functional Definitions" page Refer following sections pinout information three package types:
Section 3.2.2, "80960Jx 132-Lead Pinout" page Section 3.2.3, "80960Jx 132-Lead PQFP Pinout" page Section 3.2.4, "80960Jx 196-Ball MPBGA Pinout" page 3.2.1 Functional Definitions
Table presents legend interpreting three description tables that follow. These tables define pins associated with interface, basic control test functions, Interrupt Unit.
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table
Description Nomenclature
Symbol Input only. Output only. either input output. must connected described. Synchronous. Inputs must meet setup hold times relative CLKIN proper operation. S(E) Edge sensitive input S(L) Level sensitive input Asynchronous. Inputs asynchronous relative CLKIN. A(E) Edge sensitive input A(L) Level sensitive input While processor's RESET# asserted, pin: R(1) driven R(0) driven R(Q) valid output R(X) driven unknown state R(H) pulled While processor hold state, pin: H(1) driven H(0) driven H(Q) Maintains previous state continues valid output H(Z) Floats While processor halted, pin: P(1) driven P(0) driven P(Q) Maintains previous state continues valid output Description
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table
Description-External Signals (Sheet
NAME TYPE DESCRIPTION ADDRESS DATA carries 32-bit physical addresses 32-bit data from memory. During address (Ta) cycle, bits 31:2 contain physical word address (bits indicate SIZE; below). During data (Td) cycle, read write data present more contiguous bytes, comprising AD[31:24], AD[23:16], AD[15:8] AD[7:0]. During write operations, unused pins driven determinate values. SIZE, which comprises bits lines during cycle, specifies number data transfers during transaction. S(L) R(X) H(Z) P(Q) Transfers Transfer Transfers Transfers Transfers
AD[31:0]
When processor enters Halt mode, previous operation write AD[31:2] driven with last data value bus. read AD[31:4] driven with last address value bus; AD[3:2] driven with value A[3:2] from last data cycle. Typically, AD[1:0] reflect SIZE information last transaction (either instruction fetch load/store) that executed before entering Halt mode. R(0) H(Z) P(0) R(1) H(Z) P(1) R(1) H(Z) P(1) ADDRESS LATCH ENABLE indicates transfer physical address. asserted during cycle deasserted before beginning state. active HIGH floats high impedance state during hold cycle (Th). ADDRESS LATCH ENABLE indicates transfer physical address. ALE# inverted version ALE. This signal gives 80960Jx high degree compatibility with existing 80960Kx systems. ADDRESS STROBE indicates valid address start access. processor asserts ADS# entire cycle. External control logic typically samples ADS# cycle. ADDRESS[3:2] comprise partial demultiplexed address bus. 32-bit memory accesses: processor asserts address bits A[3:2] during partial word address increments with each assertion RDYRCV# during burst. A[3:2] R(X) H(Z) P(Q) 16-bit memory accesses: processor asserts address bits A[3:1] during with driven BE1# pin. partial short word address increments with each assertion RDYRCV# during burst. 8-bit memory accesses: processor asserts address bits A[3:0] during with A[1:0] driven BE[1:0]#. partial byte address increments with each assertion RDYRCV# during burst.
ALE#
ADS#
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table
Description-External Signals (Sheet
NAME TYPE DESCRIPTION BYTE ENABLES select which four data bytes participate current access. Byte enable encoding dependent width memory region accessed: 32-bit bus: BE3# enables data AD[31:24] BE2# enables data AD[23:16] BE1# enables data AD[15:8] BE0# enables data AD[7:0] 16-bit bus: BE3# becomes Byte High Enable (enables data AD[15:8]) BE2# used (state high) BE1# becomes Address (A1) BE0# becomes Byte Enable (enables data AD[7:0]) 8-bit bus: BE3# used (state high) BE2# used (state high) BE1# becomes Address (A1) BE0# becomes Address (A0) processor asserts byte enables, byte high enable byte enable during Since unaligned requests split into separate transactions, these signals toggle during burst. They remain active through last cycle. accesses 16-bit memory, processor asserts address bits conjunction with A[3:2] described above. WIDTH/HALTED signals denote physical memory attributes transaction: WIDTH/ HLTD1 WIDTH/ HLTD[1:0] R(0) H(Z) P(1) WIDTH/ HLTD0 Bits Wide Bits Wide Bits Wide Processor Halted
BE[3:0]#
R(1) H(Z) P(1)
processor floats WIDTH/HLTD pins whenever relinquishes response HOLD request, regardless prior operating state. R(X) H(Z) P(Q) R(0) H(Z) P(Q) DATA/CODE indicates that access data access instruction access (0). D/C# same timing W/R#. instruction access data access WRITE/READ specifies, during cycle, whether operation write read (0). latched on-chip remains valid during cycles. read write DATA TRANSMIT RECEIVE indicates direction data transfer from address/data bus. during Tw/Td cycles read; high during Tw/Td cycles write. DT/R# never changes state when DEN# asserted. receive transmit
D/C#
W/R#
DT/R#
R(0) H(Z) P(Q)
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table
Description-External Signals (Sheet
NAME TYPE DESCRIPTION DATA ENABLE indicates data transfer cycles during access. DEN# asserted start first data cycle access deasserted last data cycle. DEN# used with DT/R# provide control data transceivers connected data bus. data cycle data cycle BURST LAST indicates last transfer access. BLAST# asserted last data transfer burst non-burst accesses. BLAST# remains active long wait states inserted through RDYRCV# pin. BLAST# becomes inactive after final data transfer cycle. last data transfer last data transfer READY/RECOVER indicates that data lines sampled removed. When RDYRCV# asserted during cycle, cycle extended next cycle inserting wait state (Tw). sample data don't sample data RDYRCV# S(L) RDYRCV# another function during recovery (Tr) state. processor continues insert additional recovery states until samples HIGH. This function gives slow external devices more time float their buffers before processor begins drive address again. insert wait states recovery complete LOCK indicates that atomic read-modify-write operation progress. LOCK# output asserted first clock atomic operation deasserted last data transfer sequence. processor does grant HOLDA while asserting LOCK#. This prevents external agents from accessing memory involved semaphore operations. S(L) R(H) H(Z) P(1) Atomic read-modify-write progress Atomic read-modify-write progress ONCE MODE: processor samples ONCE# input during reset. When asserted reset, processor enters ONCE mode. ONCE mode, processor stops clocks floats output pins. weak internal pullup which active during reset ensure normal operation when left unconnected. ONCE mode enabled ONCE mode enabled HOLD: request from external master acquire bus. When processor receives HOLD grants control another master, asserts HOLDA, floats address/data control lines enters state. When HOLD deasserted, processor deasserts HOLDA enters either state, resuming control address/data control lines. hold request hold request
DEN#
R(1) H(Z) P(1)
BLAST#
R(1) H(Z) P(1)
LOCK#/ ONCE#
HOLD
S(L)
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table
Description-External Signals (Sheet
NAME TYPE R(Q) H(1) P(Q) DESCRIPTION HOLD ACKNOWLEDGE indicates external master that processor relinquished control bus. processor grant HOLD requests enter state during reset while halted well during regular operation. hold acknowledged hold acknowledged STATUS indicates that processor soon stall unless sufficient access bus; i960® Microprocessor Developer's Manual (272483). Arbitration logic examine this signal determine when external master should acquire/relinquish bus. potential stall potential stall
HOLDA
BSTAT
R(0) H(Q) P(0)
Table
Description-Processor Control Signals, Test Signals, Power (Sheet
NAME CLKIN TYPE DESCRIPTION CLOCK INPUT provides processor's fundamental time base; both processor core external CLKIN rate. input output timings specified relative rising CLKIN edge. RESET initializes processor clears internal logic. During reset, processor places address/data control output pins their idle (inactive) states. RESET# A(L) During reset, input pins ignored with exception LOCK#/ONCE#, STEST HOLD. RESET# internal synchronizer. ensure predictable processor initialization during power RESET# must asserted minimum 10,000 CLKIN cycles with CLKIN stable. warm reset, RESET# should asserted minimum cycles. SELF TEST enables disables processor's internal self-test feature initialization. STEST examined reset. When STEST asserted, processor performs internal self-test external confidence test. When STEST deasserted, processor performs only external confidence test. self test disabled self test enabled FAIL indicates failure processor's built-in self-test performed during initialization. FAIL# asserted immediately upon reset toggles during self-test indicate status individual tests: When self-test passes, processor deasserts FAIL# begins operation from user code. When self-test fails, processor asserts FAIL# then stops executing. self test failed self test passed S(L) TEST CLOCK input which provides clocking function IEEE 1149.1 Boundary Scan Testing (JTAG). State information data clocked into processor rising edge; data clocked processor falling edge. TEST DATA INPUT serial input JTAG. sampled rising edge TCK, during SHIFT-IR SHIFT-DR states Test Access Port.
STEST
S(L)
FAIL#
R(0) H(Q) P(1)
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table
Description-Processor Control Signals, Test Signals, Power (Sheet
NAME TYPE R(Q) P(Q) DESCRIPTION TEST DATA OUTPUT serial output JTAG. driven falling edge during SHIFT-IR SHIFT-DR states Test Access Port. other times, floats. does float during ONCE mode. TEST RESET asynchronously resets Test Access Port (TAP) controller function IEEE 1149.1 Boundary Scan testing (JTAG). When using Boundary Scan feature, connect pull-down resistor between this VSS. When used, this must connected VSS; however, resistor required. Section 4.3, "Connection Recommendations" page TEST MODE SELECT sampled rising edge select operation test logic IEEE 1149.1 Boundary Scan testing. POWER pins intended external connection board plane. POWER separate supply phase lock loop clock generator. intended external connection board plane. noisy environments, simple bypass filter circuit reduce noise-induced clock jitter effects timing relationships. REFERENCE VOLTAGE input reference voltage V-tolerant buffers. This signal should connected with inputs which exceed When inputs from components, this should connected GROUND pins intended external connection board plane. CONNECT pins. make system connections these pins.
TRST#
A(L)
VCCPLL
S(L)
VCC5
Table Description-Interrupt Unit Signals
NAME TYPE DESCRIPTION EXTERNAL INTERRUPT pins used request interrupt service. XINT[7:0]# pins configured three modes: Dedicated Mode: Each assigned dedicated interrupt level. Dedicated inputs programmed level (low) edge (falling) sensitive. XINT[7:0]# A(E/L) Expanded Mode: eight pins vectored interrupt source. interrupt pins level sensitive this mode. Mixed Mode: XINT[7:5]# pins dedicated sources XINT[4:0]# pins five most significant bits vectored source. least significant bits vectored source 0102 internally. Unused external interrupt pins should connected VCC. NMI# A(E) NON-MASKABLE INTERRUPT causes non-maskable interrupt event occur. NMI# highest priority interrupt source falling edge-triggered. when NMI# unused, should connected VCC.
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
3.2.2
80960Jx 132-Lead Pinout
Figure 132-Lead Grid Array View-Pins Facing Down
XINT2# XINT5#XINT7# NMI# VSSRDYRCV# RESET# VCC5 FAIL# CLKIN AD12 AD14 AD15 AD16 AD17 AD21 AD23 AD29 AD30 AD10 AD20 AD24 AD26 AD27 AD11 AD13 AD18 AD19 AD22 AD25
AD28 BE3# AD31 BE2# BE1# BE0#
VCCPLL
x80960Jx
19xx
XXXXXXXX
BSTAT DEN# DT/R#
STESTTRST# XINT0#XINT1# HOLD XINT3#XINT4# XINT6#
BLAST# HOLDA LOCK#/ ONCE# W/R#
WIDTH/ D/C# HLTD0
ALE# WIDTH/ ADS# HLTD1
NOTE: address fact that many package prefix variables have changed, package prefix variables this document indicated with "x".
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure 132-Lead Grid Array Bottom View-Pins Facing
AD25 AD27 AD30 BE2# LOCK#/ HOLDA BLAST# ONCE# W/R# ADS# WIDTH/ ALE# HLTD1 NMI# XINT7#XINT5# XINT2# D/C# WIDTH/ HLTD0 XINT6#XINT4# XINT3# FAIL# VCC5 HOLD XINT1# XINT0# TRST#STEST DT/R# DEN# RESET# BSTAT RDYRCV#VSS BE0# VCCPLL CLKIN BE1# AD31 BE3# AD28 AD29 AD23 AD21 AD17 AD16 AD15 AD14 AD12 AD26 AD24 AD20 AD10 AD22 AD19 AD18 AD13 AD11
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table 132-Lead Pinout-In Signal Order
Signal AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 Signal AD31 ADS# ALE# BE0# BE1# BE2# BE3# BLAST# BSTAT CLKIN D/C# DEN# DT/R# FAIL# HOLD HOLDA LOCK#/ONCE# NMI# RDYRCV# RESET# STEST Signal TRST# VCCPLL VCC5 Signal W/R# WIDTH/HLTD0 WIDTH/HLTD1 XINT0# XINT1# XINT2# XINT3# XINT4# XINT5# XINT6# XINT7#
NOTE: connect external logic pins marked connect pins).
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table 132-Lead Pinout-In Order
Signal ADS# WIDTH/HLTD1 ALE# NMI# XINT7# XINT5# XINT2# W/R# D/C# WIDTH/HLTD0 XINT6# XINT4# XINT3# LOCK#/ONCE# HOLDA BLAST# Signal FAIL# VCC5 HOLD XINT1# XINT0# TRST# STEST DT/R# DEN# RESET# BSTAT RDYRCV# Signal BE0# VCCPLL CLKIN BE1# AD31 BE2# BE3# AD28 AD30 AD29 AD23 AD21 AD17 AD16 AD15 AD14 Signal AD12 AD27 AD26 AD24 AD20 AD10 AD25 AD22 AD19 AD18 AD13 AD11
NOTE: connect external logic pins marked connect pins).
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
3.2.3
80960Jx 132-Lead PQFP Pinout
Figure 132-Lead PQFP View
(I/O) (I/O) (I/O) (I/O) (Core) (Core) (Core) (Core) CLKIN (CLK) VCCPLL (CLK) (Core) (Core) RESET# STEST (I/O) VSS(I/O) RDYRCV#
(I/O) (I/O) AD10 AD11 (I/O) (I/O) (Core) (Core) AD12 AD13 AD14 AD15 (I/O) (I/O) AD16 AD17 AD18 AD19 (I/O) (I/O) AD20 AD21 AD22 AD23 (Core) (Core) (I/O) (I/O) AD24 AD25 AD26
TRST# HOLD XINT0# XINT1# XINT2# XINT3# (I/O) (I/O) XINT4# XINT5# XINT6# XINT7# NMI# (Core) (Core) VCC5 FAIL# ALE# (I/O) VSS(I/O) WIDTH/HLTD1 VCC(Core) (Core) WIDTH/HLTD0
BLAST#
i960
x80960Jx
XXXXXXXX 19xx
NOTE: address fact that many package prefix variables have changed, package prefix variables this document indicated with "x".
AD27 (I/O) (I/O) AD28 AD29 AD30 AD31 (Core) (Core) (I/O) (I/O) BE3# BE2# BE1# BE0# BSTAT LOCK#/ONCE# (I/O) (I/O) (Core) (Core) HOLDA DEN# DT/R# (I/O) (I/O) (Core) (Core) W/R# ADS# D/C#
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table 132-Lead PQFP Pinout-In Signal Order
Signal AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 Signal ALE# ADS# BE3# BE2# BE1# BE0# WIDTH/HLTD1 WIDTH/HLTD0 D/C# W/R# DT/R# DEN# BLAST# RDYRCV# LOCK#/ONCE# HOLD HOLDA BSTAT CLKIN RESET# STEST FAIL# TRST# (CLK) (Core) (Core) (Core) Signal (Core) (Core) (Core) (Core) (Core) (Core) (Core) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) VCCPLL VCC5 (CLK) (Core) (Core) (Core) (Core) (Core) (Core) (Core) (Core) (Core) Signal (Core) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) (I/O) XINT7# XINT6# XINT5# XINT4# XINT3# XINT2# XINT1# XINT0# NMI#
NOTE: connect external logic pins marked connect pins).
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table 132-Lead PQFP Pinout-In Order
Signal TRST# HOLD XINT0# XINT1# XINT2# XINT3# (I/O) (I/O) XINT4# XINT5# XINT6# XINT7# NMI# (Core) (Core) VCC5 FAIL# ALE# (I/O) (I/O) WIDTH/HLTD1 (Core) (Core) WIDTH/HLTD0 Signal BLAST# D/C# ADS# W/R# (Core) (Core) (I/O) (I/O) DT/R# DEN# HOLDA (Core) (Core) (I/O) (I/O) LOCK#/ONCE# BSTAT BE0# BE1# BE2# BE3# (I/O) (I/O) (Core) (Core) AD31 AD30 AD29 AD28 (I/O) (I/O) AD27 Signal AD26 AD25 AD24 (I/O) (I/O) (Core) (Core) AD23 AD22 AD21 AD20 (I/O) (I/O) AD19 AD18 AD17 AD16 (I/O) (I/O) AD15 AD14 AD13 AD12 (Core) (Core) (I/O) (I/O) AD11 AD10 (I/O) (I/O) Signal (I/O) (I/O) (I/O) (I/O) (Core) (Core) (Core) (Core) CLKIN (CLK) VCCPLL (CLK) (Core) (Core) RESET# STEST (I/O) (I/O) RDYRCV#
NOTE: connect external logic pins marked connect pins).
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
3.2.4
80960Jx 196-Ball MPBGA Pinout
Figure 196-Ball Mini Plastic Ball Grid Array View-Balls Facing Down
BE1# HOLDA DEN# DT/R# W/R# ADS# BLAST# WIDTH0 WIDTH1 FAIL# NMI# XINT7#XINT5# D/C# XINT4# XINT6#XINT1#XINT3# HOLD ALE# VCC5 XINT2# XINT0# TRST# RDYRCV# LOCK#/ ONCE# STEST BE0# BSTAT RESET# BE2# BE3# CLKIN VCCPLL AD31 AD26 AD25 AD24 AD21 AD19 AD16 AD11 AD30 AD27 AD29 AD23 AD20 AD17 AD14 AD12 AD10 AD28 AD22 AD18 AD15 AD13
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure 196-Ball Mini Plastic Ball Grid Array Bottom View-Balls Facing
VCCPLL RESET# STEST RDYRCV# HOLD XINT3# XINT1# XINT6# XINT4# XINT5# XINT7# NMI# FAIL# WIDTH1 WIDTH0 BLAST# ADS# D/C# W/R# TRST# XINT0# XINT2# VCC5 ALE# DT/R# DEN# HOLDA LOCK#/ ONCE# BSTAT BE0# BE3# BE2# BE1# CLKIN AD11 AD16 AD19 AD21 AD24 AD25 AD26 AD31 AD10 AD12 AD14 AD17 AD20 AD23 AD29 AD27 AD30 AD13 AD15 AD18 AD22 AD28
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table 196-Ball MPBGA Pinout-In Signal Order (Sheet
Signal AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 ADS# ALE# Signal BE0# BE1# BE2# BE3# BLAST# BSTAT CLKIN DEN# D/C# DT/R# FAIL# HOLD HOLDA LOCK#/ONCE# Signal NMI# RDYRCV# RESET# STEST TRST# VCC5 Signal VCCPLL
NOTE: connect external logic pins marked connect pins).
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table 196-Ball MPBGA Pinout-In Signal Order (Sheet
Signal Signal Signal Signal WIDTH0 WIDTH1 W/R# XINT0# XINT1# XINT2# XINT3# XINT4# XINT5# XINT6# XINT7#
NOTE: connect external logic pins marked connect pins).
Table 196-Ball MPBGA Pinout-In Order (Sheet
Signal AD28 AD22 AD18 AD15 AD13 AD30 AD27 AD29 AD23 Signal AD11 Signal VCCPLL Signal BSTAT RESET# LOCK#/ONCE#
NOTE: connect external logic pins marked connect pins).
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table 196-Ball MPBGA Pinout-In Order (Sheet
Signal AD20 AD17 AD14 AD12 AD10 AD31 AD26 AD25 AD24 AD21 AD19 AD16 RDYRCV# DT/R# ALE# VCC5 Signal XINT2# XINT0# TRST# W/R# D/C# Signal CLKIN BE1# BE2# BE3# BE0# XINT4# XINT6# XINT1# XINT3# HOLD ADS# BLAST# Signal STEST HOLDA DEN# WIDTH0 WIDTH1 FAIL# NMI# XINT7# XINT5#
NOTE: connect external logic pins marked connect pins).
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Electrical Specifications
Absolute Maximum Ratings
This document contains information products production phase development. specifications within this datasheet subject change without prior notice. Verify with your local Intel sales office world wide ensure that have latest datasheet device specification update before finalizing design.
Warning:
Stressing device beyond Absolute Maximum Ratings cause permanent damage. These stress ratings only. Table presents absolute maximum ratings.
Table Absolute Maximum Ratings
Parameter Storage Temperature Case Temperature Under Bias Supply Voltage wrt. Voltage VCC5 wrt. Voltage Other Pins wrt. Maximum Rating -65o +150o -65o +110o -0.5 -0.5 -0.5
Warning:
Operating Conditions
Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect device reliability. Table presents operating conditions 80960Jx processors.
Table 80960Jx Operating Conditions
Symbol VCC5 Parameter 3.45 33.3 33.3 33.3 16.67 33.3 Units Notes Supply Voltage 3.15 Input Protection Bias 3.15 Input Clock Frequency 80960JT-100 80960JC-66 80960JC-50 80960JS-33 80960JS-25 fCLKIN 80960JD-66 80960JD-50 80960JD-40 80960JD-33 80960JA/JF-33 80960JA/JF-25 80960JA-16 Operating Case Temperature PGA, MPBGA, PQFP Extended temp PQFP MPBGA Section 4.4, "VCC5 Requirements (VDIFF)" page
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Connection Recommendations
clean on-chip power distribution, pins separately feed device's functional units. Power ground connections must made 80960Jx power ground pins. circuit board, every should connect power plane every should connect ground plane. Place liberal decoupling capacitance near 80960Jx, since processor cause transient power surges. 80960JS/JC/JT processors produced Intel's advanced CMOS process. Proper bulk decoupling must used prevent device damage during initial power during transitions from power mode normal processor operation. Power supply behavior during these transitions cause power supply exceed maximum specification cause device damage. special attention Test Reset (TRST#) pin. essential that JTAG Boundary Scan Test Access Port (TAP) controller initializes known state whether used not. When JTAG Boundary Scan function used, connect pull-down resistor between TRST# VSS. When JTAG Boundary Scan function used (even board-level testing), connect TRST# VSS. connect TDI, TDO, pins when Controller used. Note: Pins identified must connected system.
VCC5 Requirements (VDIFF)
only systems where 80960Jx input pins driven from logic, connect VCC5 directly plane. mixed voltage systems where processor powered interfaces with components, VCC5 must connected This allows proper tolerant buffer operation, prevents damage input pins. voltage differential between 80960Jx VCC5 pins must exceed 2.25 When this requirement met, current flow through exceed value which processor damaged. Instances when voltage exceed 2.25 during power power down, where source reaches level faster than other, briefly causing excess voltage differential. Another instance during steady-state operation, where differential voltage regulator (provided regulator used) cannot maintained within 2.25 methods possible prevent this from happening:
regulator that designed prevent voltage differential from exceeding 2.25
shown Figure place resistor series with VCC5 limit current
through VCC5. Figure VCC5 Current-Limiting Resistor
(±0.25 VCC5
(±5%,
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
When regulator cannot prevent 2.25 differential, addition resistor simple reliable method limiting current. resistor also prevent damage case power failure, where supply remains supply goes zero. Table VDIFF Parameters
Symbol VDIFF Parameter VCC5-VCC Difference 2.25 Units Notes VCC5 input should exceed more than 2.25 during power-up power-down, during steadystate operation.
VCCPLL Requirements
reduce clock skew 80960Jx processor, VCCPLL Phase Lock Loop (PLL) circuit isolated pinout. lowpass filter, shown Figure reduces noise induced clock jitter effects timing relationships system designs. capacitor must solid tantalum; 0.01 capacitor must type node connecting VCCPLL must short possible. When voltage VCCPLL power supply exceeds voltage time, including power power down sequences, excessive currents permanently damage on-chip electrostatic discharge (ESD) protection diodes. damage accumulate over multiple episodes. actual applications, this problem occurs only when VCCPLL pins driven separate power supplies voltage regulators. Applications that power supply VCCPLL typically risk. Verify that your application does allow VCCPLL voltage exceed VCCPLL low-pass filter recommendation does promote this problem.
Figure VCCPLL Lowpass Filter
(80960JA/JF/JD) (80960JS/JC/JT)
(Board Plane)
0.01
VCCPLL 80960Jx)
F_CA078A
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
D.C. Specifications
Table 80960Jx D.C. Characteristics
Symbol VOLP Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage Output Ground Bounce Input Capacitance PQFP MPBGA Output Capacitance PQFP MPBGA CLKIN Capacitance PQFP MPBGA <0.8 -0.3 VCC5 Units (1,2) Notes
fCLKIN fMIN
COUT
fCLKIN fMIN
CCLK
fCLKIN fMIN
NOTES: Typical measured with temperature 25°C. tested.
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table 80960Jx Characteristics (Sheet
Symbol ILI1 Parameter Input Leakage Current each except TCK, TDI, TRST# Input Leakage Current TCK, TDI, TRST# 80960 JA/JF/JD 80960 JS/JC/JT Output Leakage Current Internal Pull-UP Resistance ONCE#, TMS, TRST# 80960JT-100 80960JC-66 80960JC-50 80960JS-33 80960JS-25 Active (Power Supply) 80960JD-66 80960JD-50 80960JD-40 80960JD-33 80960JA/JF-33 80960JA/JF-25 80960JA-16 80960JT-100 80960JC-66 80960JC-50 80960JS-33 80960JS-25 Active (Thermal) 80960JD-66 80960JD-50 80960JD-40 80960JD-33 80960JA/JF-33 80960JA/JF-25 80960JA-16 (2,4) Units Notes
ILI2
-140 -250
-250 -300
0.45V VOUT
(2,3)
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table 80960Jx Characteristics (Sheet
Symbol Reset mode 80960JT-100 80960JC-66 80960JC-50 80960JS-33 80960JS-25 80960JD-66 80960JD-50 80960JD-40 80960JD-33 80960JA/JF-33 80960JA/JF-25 80960JA-16 Test (Power modes) Halt mode 80960JT-100 80960JC-66 80960JC-50 80960JS-33 80960JS-25 80960JD-66 80960JD-50 80960JD-40 80960JD-33 80960JA/JF-33 80960JA/JF-25 80960JA-16 ONCE mode Parameter Units Notes
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table 80960Jx Characteristics (Sheet
Symbol Parameter 80960JT-100 80960JC-66 80960JC-50 80960JS-33 80960JS-25 ICC5 Current VCC5 80960JD-66 80960JD-50 80960JD-40 80960JD-33 80960JA/JF-33 80960JA/JF-25 80960JA-16 NOTES: These pins have internal pullup devices. Typical leakage current tested. Measured with device operating outputs loaded test condition Figure "A.C. Test Load" page Active (Power Supply) value provided selecting your system's power supply. measured using worst case instruction mixes with 3.45 This parameter characterized tested. Active (Thermal) value provided your system's thermal management. Typical measured with =3.3 temperature This parameter characterized tested. Test (Power modes) refers values that tested when 80960JD Reset mode, Halt mode ONCE mode with 3.45 ICC5 tested VCC5 5.25 Units Notes
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
A.C. Specifications
80960Jx A.C. timings based upon device characterization.
Table 80960Jx A.C. Characteristics (Sheet
Symbol Parameter Input Clock Timings CLKIN Frequency 80960JT-100 80960JC-66 80960JC-50 80960JS-33 80960JS-25 80960JD-66 80960JD-50 80960JD-40 80960JD-33 80960JA/JF-33 80960JA/JF-25 80960JA-16 CLKIN Period 80960JT-100 80960JC-66 80960JC-50 80960JS-33 80960JS-25 80960JD-66 80960JD-50 80960JD-40 80960JD-33 80960JA/JF-33 80960JA/JF-25 80960JA-16 CLKIN Period Stability CLKIN High Time CLKIN Time CLKIN Rise Time CLKIN Fall Time 62.5 66.7 66.7 66.7 66.7 66.7 83.3 83.3 83.3 83.3 83.3 83.3 83.3 33.3 33.3 33.3 33.3 16.67 33.3 Unit Notes
Measured Measured
NOTE: Table page note definitions this table.
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table 80960Jx A.C. Characteristics (Sheet
Symbol Parameter Unit Notes
Synchronous Output Timings Output Valid Delay, Except ALE/ALE# Inactive DT/R# input signals Same above, input signals TOV1 Extended Temp MPBGA PQFP (JS/JC/JT only): Output Valid Delay, Except ALE/ALE# Inactive DT/R# input signals Same above, input signals TOV2 Output Valid Delay, DT/R# 80960JS/JC/JT 80960JD 80960JA/JF Output Float Delay 0.5TC 0.5TC 0.5TC 0.5TC 0.5TC 0.5TC 13.5 1.75 1.75 13.5 16.5 13.5 16.5
Synchronous Input Timings Input Setup CLKIN AD[31:0], NMI#, XINT[7:0]# 80960JS/JC/JT 80960JD 80960JA/JF Input Hold from CLKIN AD[31:0], NMI#, XINT[7:0]# 80960JS/JC/JT 80960JD 80960JA/JF Input Setup CLKIN RDYRCV# HOLD 80960JS/JC/JT 80960JD 80960JA/JF Input Hold from CLKIN RDYRCV# HOLD Input Setup CLKIN RESET# 80960JS/JC/JT 80960JD 80960JA/JF Input Hold from CLKIN RESET# 80960JS/JC/JT 80960JD 80960JA/JF Input Setup RESET# ONCE#, STEST 80960JS/JC/JT 80960JD 80960JA/JF
TIS1
TIH1
TIS2
10.0
TIH2
TIS3
TIH3
TIS4
NOTE: Table page note definitions this table.
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table 80960Jx A.C. Characteristics (Sheet
Symbol Parameter Input Hold from RESET# ONCE#, STEST 80960JS/JC/JT 80960JD 80960JA/JF Unit Notes
TIH4
Relative Output Timings TLXL TLXA TDXD Address Valid ALE/ALE# Inactive Data Input Signals Data Input Signals ALE/ALE# Width Address Hold from ALE/ALE# Inactive DT/R# Valid DEN# Active Boundary Scan Test Signal Timings TBSF TBSCH TBSCL TBSCR TBSCF TBSIS1 TBSIH1 TBSOV1 TBSOF1 TBSOV2 TBSOF2 TBSIS2 TBSIH2 Frequency High Time Time Rise Time Fall Time Input Setup TDI, Input Hold from TDI, Valid Delay Float Delay Outputs (Non-Test) Valid Delay Outputs (Non-Test) Float Delay Input Setup Inputs (Non-Test) Input Hold from Inputs (Non-Test) 0.5TF Measured Measured 0.5TC Equal Loading 0.5TC 0.5TC
NOTE: Table page note definitions this table.
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table Note Definitions Table 80960Jx Characteristics
NOTES: tested. ensure relationship between amplitude input jitter internal clock, jitter frequency spectrum should have power peaking between CLKIN frequency. Inactive ALE/ALE# refers falling edge rising edge ALE#. inactive ALE/ALE# timings, refer Relative Output Timings this table. float condition occurs when output current becomes less than IOL. Float delay tested, designed longer than valid delay. AD[31:0] synchronous inputs. Setup hold times must proper processor operation. NMI# XINT[7:0]# synchronous asynchronous. Meeting setup hold time guarantees recognition particular clock edge. asynchronous operation, NMI# XINT[7:0]# must asserted minimum CLKIN periods ensure recognition. RDYRCV# HOLD synchronous inputs. Setup hold times must proper processor operation. RESET# synchronous asynchronous. Meeting setup hold time guarantees recognition particular clock edge. ONCE# STEST# must stable rising edge RESET# proper operation. Guaranteed design. 100% tested. 10.Relative falling edge TCK. Worst-case condition occurs pins when pins transition from floating high input driving output state. Address/Data pins encounter this condition between last access read, address cycle following write. signals take longer discharge than signals loads.
4.7.1
A.C. Test Conditions Derating Curves
A.C. Specifications Section 4.7, "A.C. Specifications" tested with load indicated Figure
Figure A.C. Test Load
Output signals
Refer following sections specified derating curves:
Section 4.7.1.1, "Output Delay Hold Load Capacitance" page Section 4.7.1.2, "TLX Load Capacitance" page
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
4.7.1.1
Output Delay Hold Load Capacitance
Figure Output Delay Hold Load Capacitance-80960JS/JC/JT (3.3 Signals)
Timings Load Capacitance (3.3 Signals)
(ns)
Capacitive Load (pF)
Figure Output Delay Hold Load Capacitance-80960JS/JC/JT Signals)
Timings Load Capacitance Signals)
Capacitive Load (pF)
(ns)
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure Output Delay Hold Load Capacitance-80960JA/JF/JD
Timings Load Capacitance
(ns)
Rise Fall times identical.
Capacitive Load (pF)
4.7.1.2
Load Capacitance
Figure Load Capacitance-80960JS/JC/JT (3.3 Signals)
Timings Load Capacitance (3.3 Signals)
(ns) Capacitive Load (pF)
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Note:
Derating curve applies only when imbalance capacitive load occurs between ALE. derating based load ALE. derating applies ALE#.
Figure Load Capacitance-80960JS/JC/JT Signals)
Timings Load Capacitance Signals)
(ns) Capacitive Load (pF)
Note:
Derating curve applies only when imbalance capacitive load occurs between ALE. derating based load ALE. derating applies ALE#.
Figure Load Capacitance-80960JA/JF/JD
Timings Load Capacitance
(ns) Capacitive Load (pF)
Rise Fall times identical.
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Note:
Derating curve applies only when imbalance capacitive load occurs between ALE. derating based load ALE. derating applies ALE#.
4.7.1.3
Active Frequency
Figure Active (Power Supply) Frequency-80960JA/JF
Active upply)
Active (Power Supply) (mA)
Figure 80960JA/JF Active (Thermal) Frequency
Active (Therm quency
Active (Thermal) (mA) CLKIN
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure 80960JD Active (Power Supply) Frequency
Active upply)
Active (Power Supply) (mA)
Figure 80960JD Active (Thermal) Frequency
Active (The
Active (Thermal) (mA)
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure 80960JC Active (Power Supply) Frequency
Active (Power Supply) Frequency 80960
Active (Power Supply) (mA) CLKIN Frequency
Figure 80960JC Active (Thermal) Frequency
Active (Thermal) Frequency 80960
Active (Thermal) (mA) CLKIN Frequency
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure 80960JS Active (Power Supply) Frequency
Active (Power Supply) Frequency 80960
Active (Power Supply) (mA)
CLKIN Frequency
Figure 80960JS Active (Thermal) Frequency
Active (Thermal) Frequency 80960
CLKIN Frequency
Active (Thermal) (mA)
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
4.7.2
A.C. Timing Waveforms
Figure CLKIN Waveform
Figure TOV1 Output Delay Waveform
CLKIN
TOV1
AD[31:0], (active), ALE# (active), ADS#, A[3:2], BE[3:0]#, WIDTH/HLTD[1:0], D/C#, W/R#, DEN#, BLAST#, LOCK#, HOLDA, BSTAT, FAIL#
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure Output Float Waveform
CLKIN
AD[31:0], ALE, ALE# ADS#, A[3:2], BE[3:0]#, WIDTH/HLTD[1:0], D/C#, W/R#, DT/R#, DEN#, BLAST#, LOCK#
Figure TIS1 TIH1 Input Setup Hold Waveform
CLKIN
TIH1 TIS1
AD[31:0] NMI# XINT[7:0]#
Valid
Figure TIS2 TIH2 Input Setup Hold Waveform
CLKIN
TIH2 TIS2
HOLD, RDYRCV#
Valid
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure TIS3 TIH3 Input Setup Hold Waveform
CLKIN
TIH3
TIS3
RESET#
Figure TIS4 TIH4 Input Setup Hold Waveform
RESET#
TIH4 TIS4
ONCE#, STEST
Valid
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure TLX, TLXL TLXA Relative Timings Waveform
Tw/Td
CLKIN
TLXL
ALE#
Valid
TLXA
AD[31:0]
Valid
Figure DT/R# DEN# Timings Waveform
Tw/Td
CLKIN
TOV2
DT/R#
Valid
TDXD
DEN#
TOV1
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure Waveform
TBSCR TBSCF
TBSCH
TBSCL
Figure TBSIS1 TBSIH1 Input Setup Hold Waveforms
TBSIS1
TBSIH1
1.5V
Valid
1.5V
Figure TBSOV1 TBSOF1 Output Delay Output Float Waveform
TBSOV1
TBSOF1
Valid
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure TBSOV2 TBSOF2 Output Delay Output Float Waveform
TBSOV2
TBSOF2
Non-Test Outputs
Valid
Figure TBSIS2 TBSIH2 Input Setup Hold Waveform
TBSIS2 TBSIH2
Non-Test Inputs
Valid
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Device Identification
80960Jx processors identified electrically, according device type stepping (see Figure Table through Table 30). Table identifies device type stepping 80960Jx processors. Figure Table through Table identify V-tolerant 80960Jx processors. device enhanced differentiate between supply voltages, between non-clock-doubled clock-doubled cores when stepping from stepping stepping. 32-bit identifier accessible several ways:
Upon reset, identifier placed into register. identifier accessed from supervisor mode time reading DEVICEID
register address FF008710H.
IEEE Standard 1149.1 Test Access Port select DEVICE register through
IDCODE instruction.
device stepping letter also printed side product package.
Table 80960Jx Device Type Stepping Reference
Device Stepping 80960JT 80960JC
80960JS
Version Number 0000 0011
0011
Part Number 0000 1000 0010 1011 0000 1000 0011 0011 0000 1000 0010 0011 0000 1000 0011 0000 0000 1000 0010 0000 0000 1000 0010 0001
Manufacturer 0000 0001 0000 0001
0000 0001
Complete (Hex) 0082B013 30833013
30823013
80960JD 80960JF 80960JA
0011 0011 0011
0000 0001 0000 0001 0000 0001
30830013 30820013 30821013
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
80960JS/JC/JT Device Identification Register
Figure 80960JS/JC/JT Device Identification Register Fields
Part Number
Version
Product Type
Model
Manufacturer
Table 80960JS/JC/JT Device Register Field Definitions
Field Version Product Type Generation Type Table device (Indicates i960 CPU) 0001 J-series DPCC Clock Multiplier (01) Clock-Tripled Product Derivative Cache Size (11) I-cache, D-cache 0000 1001 (Indicates Intel) Value Definition Indicates major stepping changes. Indicates that device Designates type product. Indicates generation series) which product belongs.
Model
Indicates member within series specific model information.
Manufacturer
Manufacturer assigned IEEE.
Table 80960JS/JC/JT Device Model Types
Device 80960JT 80960JC 80960JS Version 0000 0000 0000 Product 000100 000100 000100 Gen. 0001 0001 0001 Model 01011 10011 00011 Manufacturer 00000001001 00000001001 00000001001
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
80960JD Device Identification Register
Figure 80960JD Device Identification Register Fields
Part Number
Version
Product Type
Model
Manufacturer
Table 80960JD Device Field Definitions
Field Version Product Type Generation Type Value Table device device 0100 (Indicates i960 CPU) 0001 J-series D000C Clock Doubled Clock-Doubled Clock Doubled Cache Size I-cache, D-cache I-cache, D-cache 0000 1001 (Indicates Intel) Definition Indicates major stepping changes. Indicates that device Designates type product. Indicates generation series) which product belongs.
Model
Indicates member within series specific model information.
Manufacturer
Manufacturer assigned IEEE.
Table 80960JD Device Model Types
Device 80960JD Version 0011 Product 000100 Gen. 0001 Model 10000 Manufacturer 00000001001
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
80960JA/JF Device Identification Register
Figure 80960JA/JF Device Identification Register Fields
Part Number
Version
Product Type
Model
Manufacturer
Table 80960JA/JF Device Field Definitions
Field Version Product Type Generation Type Table device device 0100 (Indicates i960 CPU) 0001 J-series 0000C Cache Size I-cache, D-cache I-cache, D-cache 0000 1001 (Indicates Intel) Value Definition Indicates major stepping changes. Indicates that device Designates type product. Indicates generation series) which product belongs. Indicates member within series specific model information.
Model
Manufacturer
Manufacturer assigned IEEE.
Table 80960JA/JF Device Model Types
Device 80960JA 80960JF Version 0011 0011 Product 000100 000100 Gen. 0001 0001 Model 00001 00000 Manufacturer 00000001001 00000001001
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Thermal Specifications
80960Jx specified operation when (case temperature) within range 100° PGA, MPBGA PQFP packages. Extended temperature devices also available PQFP package MPBGA package with -40° 100° Case temperature measured environment determine whether 80960Jx within specified operating range. case temperature should measured center surface, opposite pins.
thermal resistance from case ambient. following equation calculate maximum ambient temperature conform particular case temperature: (CA)
Junction temperature (TJ) commonly used reliability calculations. calculated from (thermal resistance from junction case) using following equation: (JC) Similarly, when known, corresponding case temperature (TC) calculated follows: (CA) Compute multiplying from Table "80960Jx Characteristics" page VCC. following tables values: Table Thermal Resistance Reference Table
Package package MPBGA package PQFP package Table Table page Table page Table page Table page
high speed operation, processor's significantly reduced adding heatsink and/or increasing airflow. Refer following tables maximum ambient temperature (TA) permitted without exceeding PGA, MPBGA, PQFP packages. values based typical +3.3 with +100° Table Maximum Ambient Temperature Reference Table
Processor 80960JT processor 80960JC processor 80960JD processor 80960JS processor 80960JA/JF processor Table Table page Table page Table page Table page Table page
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table 132-Lead Package Thermal Characteristics
Thermal Resistance °C/Watt Airflow ft./min (m/sec) Parameter
J-PIN J-CAP
(1.01)
(2.03)
(3.04)
(4.06)
1000 (5.08)
(Junction-to-Case) (Case-to-Ambient) Heatsink) (Case-to-Ambient) (Omnidirectional Heatsink) (Case-to-Ambient) (Unidirectional Heatsink)
NOTES:
This table applies device plugged into socket soldered directly into board. J-CAP 5.6° (approximate) heatsink) J-PIN 6.4° (inner pins) (approximate) heatsink) J-PIN 6.2° (outer pins) (approximate) heatsink) J-CAP (approximate) (with heatsink) J-PIN 3.3° (inner pins) (approximate) (with heatsink) J-PIN 3.3° (outer pins) (approximate) (with heatsink)
Table 80960JA/JF/JD 196-Ball MPBGA Package Thermal Characteristics
Thermal Resistance °C/Watt Airflow ft./min (m/sec) Parameter (1.01) (2.03) (3.04) (4.06) 1000 (5.08)
(Junction-to-Case) (Case-to-Ambient) Heatsink)
NOTES: This table applies MPBGA device soldered directly into board with connections.
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table 80960JS/JC/JT 196-Ball MPBGA Package Thermal Characteristics
Thermal Resistance °C/Watt Airflow ft./min (m/sec) Parameter
(Junction-to-Case) (Case-to-Ambient) Heatsink)
(1.01)
(2.03)
(3.04)
(4.06)
1000 (5.08)
NOTES: This table applies MPBGA device soldered directly into board with connections.
Table 132-Lead PQFP Package Thermal Characteristics
Thermal Resistance °C/Watt Airflow ft./min (m/sec) Parameter (0.25)
(0.50)
(1.01)
(2.03)
(3.04)
(4.06)
(Junction-to-Case) (Case-to-Ambient Heatsink)
NOTES: This table applies PQFP device soldered directly into board. (approx.) 13.5° (approx.)
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table Maximum Various Airflows (80960JT)
Airflow-ft/min (m/sec) fCLKIN (MHz) PQFP Package without Heatsink without Heatsink Package with Omnidirectional Heatsink1 with Unidirectional Heatsink2 MPBGA Package without Heatsink (1.01) (2.03) (3.04) (4.06) 1000 (5.07)
NOTES: 0.248 inch high omnidirectional heatsink alloy 6061, width, center-to-center spacing). 0.250 inch high unidirectional heatsink alloy 6061, width, center-to-center spacing).
Table Maximum Various Airflows (80960JC)
Airflow-ft/min (m/sec) fCLKIN (MHz) 16.67 16.67 16.67 16.67 16.67 (1.01) (2.03) (3.04) (4.06) 1000 (5.07)
PQFP Package
without Heatsink
without Heatsink
Package
with Omnidirectional Heatsink1
with Unidirectional Heatsink2
MPBGA Package
without Heatsink
NOTES: 0.248 inch high omnidirectional heatsink alloy 6061, width, center-to-center spacing). 0.250 inch high unidirectional heatsink alloy 6061, width, center-to-center spacing).
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table Maximum Various Airflows (80960JD)
Airflow-ft/min (m/sec) fCLKIN (MHz) 16.67 16.67 16.67 16.67 (1.01) (2.03) (3.04) (4.06) 1000 (5.07)
PQFP Package
without Heatsink
without Heatsink
Package
with Omnidirectional Heatsink1
with Unidirectional Heatsink2 MPBGA Package
without Heatsink
NOTES: 0.248 inch high omnidirectional heatsink alloy 6061, width, center-to-center spacing). 0.250 inch high unidirectional heatsink alloy 6061, width, center-to-center spacing).
Table Maximum Various Airflows (80960JS)
Airflow-ft/min (m/sec) fCLKIN (MHz) PQFP Package 16.67 16.67 16.67 16.67 16.67 (1.01) (2.03) (3.04) (4.06) 1000 (5.07)
without Heatsink
without Heatsink Package with Omnidirectional Heatsink1 with Unidirectional Heatsink2 MPBGA Package
without Heatsink
NOTES: 0.248 inch high omnidirectional heatsink alloy 6061, width, center-to-center spacing). 0.250 inch high unidirectional heatsink alloy 6061, width, center-to-center spacing).
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table Maximum Various Airflows (80960JA/JF)
Airflow-ft/min (m/sec) fCLKIN (MHz) x80960JA/JF without Heatsink x80960JA-25 without Heatsink without Heatsink with Omnidirectional Package Heatsink1 with Unidirectional Heatsink2 MPBGA without Heatsink Package (1.01) (2.03) (3.04) (4.06) 1000 (5.07)
PQFP Package
NOTES: 0.248 inch high omnidirectional heatsink alloy 6061, width, center-to-center spacing). 0.250 inch high unidirectional heatsink alloy 6061, width, center-to-center spacing). address fact that many package prefix variables have changed, package prefix variables this document indicated with "x".
Thermal Management Accessories
following list suggested sources 80960Jx thermal solutions. This neither endorsement warranty performance listed products and/or companies.
6.1.1
Heatsinks
Thermalloy, Inc. 2021 West Valley View Lane Dallas, 75234-8993 (972) 243-4321 Wakefield Engineering Audubon Road Wakefield, 01880 (617) 245-5900 Aavid Thermal Technologies, Inc. Kool Path Laconia, 03247-0400 (603) 528-3400
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Functional Waveforms
Figure through Figure illustrate typical 80960Jx transactions. Figure depicts arbitration sequence. Figure illustrates processor reset sequence from time power applied device. Figure illustrates processor reset sequence when processor operation. Figure illustrates processor ONCE# sequence from time power applied device. Figure Figure also show accesses 32-bit buses. Table through Table summarize possible combinations accesses across 16-, 32-bit buses according data alignment.
Figure Non-Burst Read Write Transactions Without Wait States, 32-Bit
CLKIN
AD31:0
ADDR
Invalid
ADDR
DATA
ADS#
A3:2
BE3:0#
WIDTH1:0
D/C#
W/R#
BLAST#
DT/R#
DEN#
RDYRCV#
F_JF030A
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure Burst Read Write Transactions Without Wait States, 32-Bit
CLKIN
AD31:0
ADDR
ADDR
DATA DATA DATA
DATA
ADS#
A3:2
BE3:0#
WIDTH1:0
D/C#
W/R#
BLAST#
DT/R#
DEN#
RDYRCV#
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit
CLKIN
AD31:0
ADDR
DATA
DATA
DATA
DATA
ADS#
A3:2
BE3:0#
WIDTH1:0
D/C#
W/R#
BLAST#
DT/R#
DEN#
RDYRCV#
F_JF032A
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure Burst Read Write Transactions Without Wait States, 8-Bit
CLKIN
AD31:0
ADDR
ADDR DATA DATA DATA
DATA
ADS#
A3:2
00,01,10
00,01,10
BE1#/A1 BE0#/A0
WIDTH1:0
D/C#
W/R#
BLAST#
DT/R#
DEN#
RDYRCV#
F_JF033A
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure Burst Read Write Transactions With Wait States Extra State Read, 16-Bit
CLKIN
AD31:0
ADDR
ADDR
DATA
DATA
ADS#
A3:2
00,01,10,
00,01,10,
BE1#/A1
BE3#/BHE BE0#/BLE
WIDTH1:0
D/C#
W/R#
BLAST#
DT/R#
DEN#
RDYRCV#
F_JF034A
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure Double Word Read Request, Misaligned Byte From Quad Word Boundary, 32-Bit Bus, Little Endian
CLKIN
AD31:0
ADS#
A3:2
BE3:0#
1101
0011
0000
1110
WIDTH1:0
D/C#
Valid
W/R#
BLAST#
DT/R#
DEN#
RDYRCV#
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure HOLD/HOLDA Waveform Arbitration
CLKIN
Outputs: AD31:0, ALE, ALE#, ADS#, A3:2, BE3:0#, WIDTH/HLTD1:0, D/C#, W/R#, DT/R#, DEN#, BLAST#, LOCK#
Valid
Valid
HOLD
HOLDA
(Note)
NOTE: HOLD sampled rising edge CLKIN. processor asserts HOLDA grant same edge which recognizes HOLD when last state last transaction. Similarly, processor deasserts HOLDA same edge which recognizes deassertion HOLD.
CLKIN ALE#, ADS#, BE3:0#, DEN#, BLAST# ALE#,W/R#, DT/R# WIDTH/HLTD1:0 FAIL# AD31:0, A3:2,D/C#
Idle (Note Valid Input (Note Valid Output (Note (Input)
HOLD HOLDA
LOCK#/ ONCE# STEST RESET#
(Output)
Valid
Figure Cold Reset Waveform
(Note CLKIN stable RESET High, minimum 10,000 CLKIN periods, stabilization.
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Built-in self-test (Note
First Activity
Notes: processor asserts FAIL# during built-in self-test. When self- test passes, FAIL# deasserted.The processor also asserts FAIL# during confidence test. When confidence test passes, FAIL# deasserted processor begins user program execution. processor fails built-in self-test, initiates dummy load access. load address indicates point self-test failure. Since idle, hold requests honored during reset built-in self-test. When selected, built-in self test requires approximately CLKIN periods): 393,000 80960JT, 580,012 80960JC, 1,176,025 80960JS, 207,000 80960JD, 414,000 80960JA/JF.
ALE#, ADS#, BE3:0#, DEN#, BLAST# ALE, W/R#,DT/R#, BSTAT, WIDTH/HLTD1:0 FAIL# AD31:0, A3:2, D/C#
HOLD
HOLDA LOCK#/ONCE# STEST
Valid
Maximum RESET# Reset State CLKIN Cycles RESET#
Minimum RESET# Time CLKIN Cycles
RESET# High First Activity: (CLKIN cycles) 80960JT 80960JC 80960JS 80960JD 80960JA/JF
CLKIN
Figure Warm Reset Waveform
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
CLKIN ALE#, ADS#, BE3:0#, DEN#, BLAST# ALE,W/R,# DT/R#, WIDTH/HLTD1:0 FAIL#
HOLD
HOLDA
AD31:0, A3:2, D/C#
STEST
RESET#
(Note
CLKIN stable RESET# High, minimum 10,000 CLKIN periods, stabilization. NOTES: ONCE# mode entered prior rising edge RESET#: ONCE# input latched until rising edge RESET#.
ONCE# input removed after processor enters ONCE# Mode.
LOCK#/ ONCE#
(Input)
Figure Entering ONCE State
CLKIN allowed float. must driven high continue run.
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Basic States
five basic states: idle (Ti), address (Ta), wait/data (Tw/Td), recovery (Tr), hold (Th). During system operation, processor continuously enters exits different states. Figure shows five states. occupies idle (Ti) state when address/data transactions progress when RESET# asserted. When processor needs initiate access, enters state transmit address. Following state, enters Tw/Td state transmit receive data address/data lines. Assertion RDYRCV# input signal indicates completion each transfer. When data ready, processor wait long necessary memory device respond. After data transfer, exits Tw/Td state enters recovery (Tr) state. case burst transaction, exits state re-enters Td/Tw state transfer next data word. processor asserts BLAST# signal during last Tw/Td states access. Once data words transfer burst access four), enters state allow devices recover. processor remains state until RDYRCV# deasserted. When recovery state completes, enters state when accesses required. When access pending, enters state transmit address.
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure States with Arbitration
(READY BURST) READY
Tw/Td RECOVERED REQUEST PENDING HOLD LOCKED) READY BURST
REQUEST PENDING HOLD LOCKED) REQUEST PENDING HOLD RECOVERED REQUEST HOLD LOCKED)
RECOVERED
REQUEST HOLD LOCKED) ONCE RESET DEASSERTION
REQUEST HOLD
RECOVERED HOLD LOCKED
RESET HOLD LOCKED HOLD RDYRCV# ASSERTED RDYRCV# ASSERTED BLAST# ASSERTED BLAST# ASSERTED RDYRCV# ASSERTED RDYRCV# ASSERTED TRANSACTION TRANSACTION HOLD REQUEST ASSERTED HOLD REQUEST ASSERTED ATOMIC EXECUTION (ATADD, ATMOD) PROGRESS ATOMIC EXECUTION PROGRESS RESET# ASSERTED ONCE# ASSERTED
IDLE STATE ADDRESS STATE WAIT/DATA STATE RECOVERY STATE HOLD STATE ONCE STATE
READY READY BURST BURST RECOVERED RECOVERED REQUEST PENDING REQUEST HOLD HOLD LOCKED LOCKED RESET ONCE
Boundary-Scan Register
Boundary-Scan register contains cell each well cells control HIGHZ pins. Table shows order 80960Jx processor Boundary-Scan register. table cells that contain `CTL' select direction bidirectional pins HIGHZ output pins. When loaded into control cell, associated pin(s) HIGHZ selected input.
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table Boundary-Scan Register-Bit Order
Signal RDYRCV# (TDI) HOLD XINT0# XINT1# XINT2# XINT3# XINT4# XINT5# XINT6# XINT7# NMI# FAIL# ALE# WIDTH/HLTD1 WIDTH/HLTD0 CONTROL1 CONTROL2 BLAST# D/C# ADS# W/R# DT/R# Input/ Output Enable cell Enable cell Signal DEN# HOLDA LOCK#/ ONCE# cell LOCK#/ ONCE# BSTAT BE0# BE1# BE2# BE3# AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 Input/ Output Enable cell Signal AD17 AD16 AD15 AD14 AD13 AD12 cells AD11 AD10 CLKIN RESET# STEST (TDO) Input/ Output Enable cell
Enable cells active low.
Table Natural Boundaries Load Store Accesses
Data Width Byte Short Word Word Double Word Triple Word Quad Word Natural Boundary (Bytes)
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table Summary Byte Load Store Accesses
Address Offset from Natural Boundary Bytes) (aligned) Accesses 8-Bit (WIDTH1:0=00) Byte access Accesses (WIDTH1:0=01) Byte access Accesses (WIDTH1:0=10) Byte access
Table Summary Short Word Load Store Accesses
Address Offset from Natural Boundary Bytes) (aligned) Accesses 8-Bit (WIDTH1:0=00) Burst bytes byte accesses Accesses (WIDTH1:0=01) Short-word access byte accesses Accesses (WIDTH1:0=10) Short-word access byte accesses
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Table Summary n-Word Load Store Accesses
Address Offset from Natural Boundary Bytes Accesses 8-Bit (WIDTH1:0=00) Accesses (WIDTH1:0=01) Case n=1: burst short words (aligned) Case n=2: burst short words burst(s) bytes Case n=3: burst short words burst short words Case n=4: bursts short words Byte access Burst bytes burst(s) bytes Byte access Burst bytes burst(s) bytes Burst bytes Byte access burst(s) bytes Burst bytes Byte access Byte access Short-word access burst(s) short words Byte access Short-word access burst(s) short words Short-word access Byte access burst(s) short words Short-word access Byte access burst(s) short words Byte access Short-word access word access(es) Byte access Short-word access word access(es) Short-word access Byte access word access(es) Short-word access Byte access word access(es) Burst word(s) Accesses (WIDTH1:0=10)
burst(s) bytes
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure Summary Aligned Unaligned Accesses (32-Bit Bus)
Byte Offset
Word Offset
Short Access (Aligned)
Byte, Byte Accesses Short-Word Load/Store Short Access (Aligned)
Byte, Byte Accesses
Word Access (Aligned) Byte, Short, Byte, Accesses Word Load/Store Short, Short Accesses
Byte, Short, Byte Accesses
Double-Word Burst (Aligned) Byte, Short, Word, Byte Accesses Short, Word, Short Accesses Double-Word Load/Store Byte, Word, Short, Byte Accesses Word, Word Accesses
Double-Word Burst (Aligned)
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
Figure Summary Aligned Unaligned Accesses (32-Bit Bus) (Continued)
Byte Offset Three-Word Burst (Aligned) Byte, Short, Word, Word, Byte Accesses Triple-Word Load/Store Short, Word, Word, Short Accesses Byte, Word, Word, Short, Byte Accesses Word, Word, Word Accesses Word, Word, Word Accesses Word, Word, Word Accesses
Word Offset
Four-Word Burst (Aligned) Byte, Short, Word, Word, Word, Byte Accesses Quad-Word Load/Store Short, Word, Word, Word, Short Accesses Byte, Word, Word, Word, Short, Byte Accesses Word, Word, Word, Word Accesses Word, Word, Word, Word, Accesses
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor
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