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Embedded Intel486 SX Processor

32-Bit RISC Technology Core 8-Kbyte Write-Through Cache Four Internal Write Buffers Burst Bus Cycles Dynamic Bus Sizing for 8- and 16-bit Data Bus Devices SL Technology

Embedded Intel486 SX Processor
Datasheet
Product Features
32-Bit RISC Technology Core 8-Kbyte Write-Through Cache Four Internal Write Buffers Burst Bus Cycles Dynamic Bus Sizing for 8- and 16-bit Data Bus Devices SL Technology
Data Bus Parity Generation and Checking Boundary Scan (JTAG) 5-Volt Processor - 196-Lead Plastic Quad Flat Pack (PQFP) - 168-Pin Pin Grid Array (PGA) Binary Compatible with Large Software Base
64-Bit Interunit Transfer Bus
32-Bit Data Bus 32-Bit Data Bus Linear Address 32 PCD PWT
Barrel Shifter Register File ALU
Base / Index Bus 32
Segmentation Unit Descriptor Registers Limit and Attribute PLA
Bus Interface
Paging Unit
Cache Unit
Address Drivers Write Buffers 4 x 32 Data Bus Transceivers Bus Control
A31-A2 BE3#- BE0#
Physical Address Translation Lookaside Buffer
8 Kbyte Cache
D31-D0
Displacement Bus
Prefetcher MicroInstruction 32-Byte Code Queue 2x16 Bytes Bus Size Control Cache Control Parity Generation and Control Boundary Scan Control Request Sequencer Code Stream Instruction Decode Decoded Instruction Path
ADS# W / R# D / C# M / IO# PCD PWT RDY# LOCK# PLOCK# BOFF# A20M# BREQ HOLD HLDA RESET SRESET INTR NMI SMI# SMIACT# FERR# IGNNE# STPCLK#
Burst Bus Control
BRDY# BLAST#
Control & Protection Test Unit
BS16# BS8#
KEN# FLUSH# AHOLD EADS#
Control ROM
DP3-DP0 PCHK#
TCK TMS TDI TD0
A5443-01
Order Number: 272769-004 August 2004
Datasheet
Contents
1.0 Introduction.................................................................. 5 1.1 1.2 2.0 3.0 Features................................................................ 5 Family Members .......................................................... 6
How To Use This Document ..................................................... 7 Pin Descriptions .............................................................. 7 3.1 3.2 Pin Assignments .......................................................... 7 Pin Quick Reference ......................................................16 CPUID Instruction ........................................................23 4.1.1 Operation of the CPUID Instruction ....................................23 Identification After Reset...................................................24 Boundary Scan (JTAG)....................................................24 4.3.1 Device Identification................................................24 4.3.2 Boundary Scan Register Bits and Bit Order..............................25 Maximum Ratings ........................................................25 DC Specifications ........................................................26 AC Specifications........................................................27 Capacitive Derating Curves ................................................33 Package Dimensions ..................................................... 34 Package Thermal Specifications ............................................37
Architectural and Functional Overview ...........................................22 4.1 4.2 4.3
Electrical Specifications .......................................................25 5.1 5.2 5.3 5.4
Mechanical Data .............................................................34 6.1 6.2
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Package Diagram for 168-Pin PGA Embedded Intel486 SX Processor .................. 8 Package Diagram for 196-Lead PQFP Embedded Intel486 SX Processor ..............12 CLK Waveform ..............................................................29 Input Setup and Hold Timing ...................................................30 Input Setup and Hold Timing ...................................................30 PCHK# Valid Delay Timing.....................................................31 Output Valid Delay Timing .....................................................31 Maximum Float Delay Timing ...................................................32 TCK Waveform ..............................................................32 Test Signal Timing Diagram ....................................................32 Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a Low-to-High Transition, 5 V Processor.....................33 Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a High-to-Low Transition, 5 V Processor.....................33 168-Pin PGA Package Dimensions ..............................................34 Principal Dimensions and Data for 196-Lead Plastic Quad Flat Pack Package.............36 Typical Lead for 196-Lead PQFP Package ........................................37
Datasheet
Contents
Tables
Revision History
Date August 2004 Revision 004 Description To address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x". Removed 3.3 V device. Added 5 V PGA information. Updated related documents list. First release of this datasheet for embedded.
September 2001 December 1997 October 1995
Datasheet
Intel486 SX Processor
Introduction
· 196-lead Plastic Quad Flat Pack (PQFP) · 168-pin Pin Grid Array (PGA).
Features
The embedded Intel486 SX processor offers these features:
· 32-bit RISC-Technology Core - The embedded Intel486 SX processor performs a complete
set of arithmetic and logical operations on 8-, 16-, and 32-bit data types using a full-width ALU and eight general purpose registers.
· Single Cycle Execution - Many instructions execute in a single clock cycle. · Instruction Pipelining - Overlapped instruction fetching, decoding, address translation and
execution.
· On-Chip Cache with Cache Consistency Support - An 8-Kbyte, write-through, internal
cache is used for both data and instructions. Cache hits provide zero wait-state access times for data within the cache. Bus activity is tracked to detect alterations in the memory represented by the internal cache. The internal cache can be invalidated or flushed so that an external cache controller can maintain cache consistency.
· External Cache Control - Write-back and flush controls for an external cache are provided
so the processor can maintain cache consistency.
· On-Chip Memory Management Unit - Address management and memory space protection
mechanisms maintain the integrity of memory in a multitudinous and virtual memory environment. Both memory segmentation and paging are supported.
· Burst Cycles - Burst transfers allow a new double-word to be read from memory on each
bus clock cycle. This capability is especially useful for instruction prefetch and for filling the internal cache.
Datasheet
Intel486 SX Processor
· Write Buffers - The processor contains four write buffers to enhance the performance of
consecutive writes to memory. The processor can continue internal operations after a write to these buffers, without waiting for the write to be completed on the external bus.
· Bus Backoff - When another bus master needs control of the bus during a processor initiated
bus cycle, the embedded Intel486 SX processor floats its bus signals, then restarts the cycle when the bus becomes available again.
· Instruction Restart - Programs can continue execution following an exception generated by
an unsuccessful attempt to access memory. This feature is important for supporting demandpaged virtual memory applications.
· Dynamic Bus Sizing - External controllers can dynamically alter the effective width of the
data bus. Bus widths of 8, 16, or 32 bits can be used.
· Boundary Scan (JTAG) - Boundary Scan provides in-circuit testing of components on
· Intel System Management Mode (SMM) - A unique Intel architecture operating mode
provides a dedicated special purpose interrupt and address space that can be used to implement intelligent power management and other enhanced functions in a manner that is completely transparent to the operating system and applications software. automatically be restarted following the execution of the RSM instruction.
· I / O Restart - An I / O instruction interrupted by a System Management Interrupt (SMI#) can · Stop Clock - The embedded Intel486 SX processor has a stop clock control mechanism that
provides two low-power states: a Stop Grant state (20-40 mA typical, depending on input clock frequency) and a Stop Clock state (~100-200 µA typical, with input clock frequency of 0 MHz).
· Auto HALT Power Down - After the execution of a HALT instruction, the embedded
Intel486 SX processor issues a normal Halt bus cycle and the clock input to the processor core is automatically stopped, causing the processor to enter the Auto HALT Power Down state (20-40 mA typical, depending on input clock frequency).
Table 1.
Family Members
Table 1 shows the embedded Intel486 SX processors and briefly describes their characteristics. The Embedded Intel486 SX Processor Family
Product x80486SXSA33 x80486SXSA33 Supply Voltage
Maximum Processor Frequency 33 MHz 33 MHz
Package 168-Pin PGA 196-Lead PQFP
NOTE: To address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".
Datasheet
Intel486 SX Processor
How To Use This Document
For a complete set of documentation related to the embedded Intel486 SX processor, use this document in conjunction with the following reference documents:
The information in the reference documents for the Intel486 SX processor, 1X Clock (CLK), applies to the embedded Intel486 SX processor. Some of the Intel486 SX processor information is duplicated in this document to minimize the dependence on the reference documents.
Pin Descriptions
Pin Assignments
The following figures and tables show the pin assignments of each package type for the embedded Intel486 SX processor. Tables are provided showing the pin differences between the embedded Intel486 SX processor and other embedded Intel486 processor products. 168-Pin PGA - Pin Grid Array
Figure 1, Package Diagram for 168-Pin PGA Embedded Intel486 SX Processor (pg. 8) Table 2, Pinout Differences for 168-Pin PGA Package (pg. 9) Table 3, Pin Assignment for 168-Pin PGA Package (pg. 9) Table 4, Pin Cross Reference for 168-Pin PGA Package (pg. 11)
196-Lead PQFP - Plastic Quad Flat Pack
· Figure 2, Package Diagram for 196-Lead PQFP Embedded Intel486 SX Processor (pg. 12) · Table 5, Pin Assignment for 196-Lead PQFP Package (pg. 13) · Table 6, Pin Cross Reference for 196-Lead PQFP Package (pg. 14)
Datasheet
Intel486 SX Processor
Figure 1. Package Diagram for 168-Pin PGA Embedded Intel486 SX Processor
VCC VSS
168-Pin PGA Embedded Intel486 SX Processor
SRESET
Pin Side View
RESERVED
SMIACT#
FLUSH# A20M# HOLD KEN# STPCLK# BRDY#
LOCK#
RESET
VCC PLOCK# BLAST# A4
AHOLD EADS# BS16# BOFF#
PCHK#
Datasheet
Intel486 SX Processor
Table 2.
Pinout Differences for 168-Pin PGA Package
Pin # A3 A10 A12 A14 A15 B12 B13 B14 B15 B16 C14 J1 R17 S4 Embedded Intel486 SX Processor NC INC INC
Embedded IntelDX2 Processor TCK INC INC
Embedded Write-Back Enhanced IntelDX4 Processor TCK INV HITM# TDI IGNNE# CACHE# WB / WT# TMS NMI TDO FERR# VCC5 CLKMUL VOLDET
NC NMI INC INC
TDI IGNNE# INC INC
NC INC NC INC
TMS NMI TDO FERR# VCC INC NC
VCC INC NC
INC. Internal No Connect. These pins are not connected to any internal pad in the embedded Intel486 SX processor. However, new signals are defined for the location of the INC pins in the embedded IntelDX2 and IntelDX4 processors. One system design can accommodate any one of these processors provided the purpose of each INC pin is understood before it is used.
Table 3.
Pin Assignment for 168-Pin PGA Package (Sheet 1 of 2)
Pin # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 Description D20 D22 NC D23 DP3 D24 VSS D29 VSS INC
Pin # D17 E1 E2 E3 E15 E16 E17 F1 F2 F3 F15 F16 F17 G1 G2 G3 G15 G16
Description BOFF# VSS
Pin # P2 P3 P15 P16 P17 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13
Description A29 A30 HLDA
D10 HOLD
VSS A31 VSS A17 A19 A21 A24 A22 A20 A16 A13 A9 A5 A7
VSS DP1 D8 D15 KEN# RDY# BE3# VSS
VSS INC1 INC1 NC NMI INTR AHOLD D19
D12 STPCLK#
Datasheet
Intel486 SX Processor
Table 3.
Pin Assignment for 168-Pin PGA Package (Sheet 2 of 2)
Pin # B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D15 D16 Description D21 VSS VSS VSS D25
Pin # G17 H1 H2 H3 H15 H16 H17 J1 J2 J3 J15 J16 J17 K1 K2 K3 K15 K16 K17 L1 L2 L3 L15 L16 L17 M1 M2 M3 M15 M16 M17 N1 N2 N3 N15 N16 N17 P1
Description VSS VSS D3 DP2 BRDY#
Pin # Q14 Q15 Q16 Q17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17
Description A2 BREQ PLOCK# PCHK# A28 A25
VSS A18
D5 D16 BE2# BE1# PCD VSS
INC1 INC1 NC INC1 NC EADS# D11 D18 CLK
VCC VCC
VCC VCC VCC VCC
D14 BE0#
A11 A8
VSS VSS D6 D7 PWT
A3 BLAST# INC1 A27 A26 A23 NC2 A14 VSS A12 VSS VSS VSS VSS VSS A10 VSS A6 A4 ADS#
D27 D26 D28 D30 SRESET RESERVED# SMIACT# NC INC1 FLUSH# RESET BS16# D9 D13 D17 A20M# BS8#
VSS VSS
VSS D2 D1 DP0 LOCK# M / IO# W / R# D0
NOTES: 1. INC. Internal No Connect. These pins are not connected to any internal pad in the embedded IntelDX2 processors. However, signals are defined for the location of the INC pins in the IntelDX4 processor. One system design can accommodate any one of these processors provided the purpose of each INC pin is understood before it is used. 2. NC. Do Not Connect. These pins should always remain unconnected. Connection of NC pins to VCC, or VSS or to any other signal can result in component malfunction or incompatibility with future steppings of the Intel486 processors.
Datasheet
Intel486 SX Processor
Table 4.
Pin Cross Reference for 168-Pin PGA Package
Address A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pin # Q14 R15 S16 Q12 S15 Q13 R13 Q11 S13 R12 S7 Q10 S5 R7 Q9 Q3 R5 Q4 Q8 Q5 Q7 S3 Q6 R2 S2 S1 R1 P2 P3 Q1 Data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Pin # P1 N2 N1 H2 M3 J2 L2 L3 F2 D1 E3 C1 G3 D2 K3 F3 J3 D3 C2 B1 A1 B2 A2 A4 A6 B6 C7 C6 C8 A8 C9 B8 Control A20M# ADS# AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ BS16# BS8# CLK D / C# DP0 DP1 DP2 DP3 EADS# FLUSH# HLDA HOLD INTR KEN# LOCK# M / IO# PCD PCHK# PLOCK# PWT RDY# RESERVED# RESET SMI# SMIACT# SRESET STPCLK# W / R# Pin # D15 S17 A17 K15 J16 J15 F17 R16 D17 H15 Q15 C17 D16 C3 M15 N3 F1 H3 A5 B17 C15 P15 E15 A16 F15 N15 N16 J17 Q17 Q16 L15 F16 C11 C16 B10 C12 C10 G15 N17 NC A3 A14 B16 B14 C13 S4 INC A10 A12 A13 B12 B13 B15 C14 R17 Vcc B7 B9 B11 C4 C5 E2 E16 G2 G16 H16 J1 K2 K16 L16 M2 M16 P16 R3 R6 R8 R9 R10 R11 R14 Vss A7 A9 A11 B3 B4 B5 E1 E17 G1 G17 H1 H17 K1 K17 L1 L17 M1 M17 P17 Q2 R4 S6 S8 S9 S10 S11 S12 S14
Datasheet
Intel486 SX Processor
Figure 2. Package Diagram for 196-Lead PQFP Embedded Intel486 SX Processor
VCC A2 ADS# BLAST# PLOCK# LOCK# VSS NC PCHK# BRDY# BOFF# BS16# BS8# NC RDY# KEN# VCC HOLD AHOLD TCK NC VSS VCC NC CLK HLDA VSS W / R# VCC BREQ BE0# BE1# BE2# VSS BE3# VCC M / IO# D / C# VSS PWT VCC PCD EADS# A20M# RESET FLUSH# INTR NMI VSS 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 197 106 105 104 103 102 101 100 99
VSS NC A3 NC A4 NC A5 NC RESERVED# NC A6 A7 NC A8 NC A9 VCC A10 NC VSS VSS NC VCC NC A11 NC A12 VCC A13 VSS A14 VCC A15 A16 VSS A17 VCC TDI NC TMS NC A18 NC A19 NC A20 VSS NC VCC 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50
196-Lead PQFP Embedded Intel486 SX Processor
Top View
VCC NC VSS VSS SRESET VCC SMIACT# NC NC NC NC NC VSS SMI# VCC NC NC INC TDO NC NC INC NC STPCLK# D31 NC NC D30 VCC D29 NC D28 VSS D27 NC D26 VCC D25 NC D24 VSS DP3 NC D23 VCC D22 NC D21 VSS
VSS A21 A22 A23 A24 VCC A25 A26 A27 A28 VSS A29 A30 A31 NC DP0 D0 D1 VCC D2 VSS VSS D3 VCC D4 D5 D6 VCC D7 DP1 D8 D9 VSS NC D10 VCC D11 D12 D13 VSS D14 D15 DP2 D16 D17 D18 D19 D20 VCC
A3220-01
Datasheet
Intel486 SX Processor
Table 5.
Pin Assignment for 196-Lead PQFP Package
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Description VSS A21 A22 A23 A24 VCC A25 A26 A27 A28 VSS A29 A30 A31 NC1 DP0 D0 D1 VCC D2 VSS VSS D3 VCC D4 D5 D6 VCC D7 DP1 D8 D9 VSS Pin # 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 Description VSS D21 NC1 D22 VCC D23 NC1 DP3 VSS D24 NC1 D25 VCC D26 NC1 D27 VSS D28 NC1 D29 VCC D30 NC1 NC
(Sheet 1 of 2)
Description VSS NMI INTR FLUSH# RESET A20M# EADS# PCD VCC PWT VSS D / C# M / IO# VCC BE3# VSS BE2# BE1# BE0# BREQ VCC W / R# VSS HLDA CLK NC
Pin # 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131
Pin # 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
Description VSS NC1 A3 NC1 A4 NC1 A5 NC1 RESERVED# NC1 A6 A7 NC1 A8 NC1 A9 VCC A10 NC1 VSS VSS NC1 VCC NC1 A11 NC1 A12 VCC A13 VSS A14 VCC A15
D31 STPCLK# NC1 INC NC NC
VCC VSS NC
TCK AHOLD HOLD VCC
TDO INC2 NC
NOTES: 1. NC. Do Not Connect. These pins should always remain unconnected. Connection of NC pins to VCC, or VSS or to any other signal can result in component malfunction or incompatibility with future steppings of the Intel486 processors. 2. INC. Internal No Connect. These pins are not connected to any internal pad in the embedded Intel486 SX processors.
Datasheet
Intel486 SX Processor
Table 5.
Pin Assignment for 196-Lead PQFP Package
Pin # 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Description NC1 D10 VCC D11 D12 D13 VSS D14 D15 DP2 D16 D17 D18 D19 D20 VCC Pin # 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 Description NC1 VCC SMI# VSS NC1 NC1 NC1 NC
(Sheet 2 of 2)
Description KEN# RDY# NC
Pin # 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147
Pin # 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196
Description A16 VSS A17 VCC TDI NC1 TMS NC1 A18 NC1 A19 NC1 A20 VSS NC1 VCC
BS8# BS16# BOFF# BRDY# PCHK# NC1 VSS LOCK# PLOCK# BLAST# ADS# A2 VCC
NC1 SMIACT# VCC SRESET VSS VSS NC
NOTES: 1. NC. Do Not Connect. These pins should always remain unconnected. Connection of NC pins to VCC, or VSS or to any other signal can result in component malfunction or incompatibility with future steppings of the Intel486 processors. 2. INC. Internal No Connect. These pins are not connected to any internal pad in the embedded Intel486 SX processors.
Table 6.
Pin Cross Reference for 196-Lead PQFP Package (Sheet 1 of 2)
Address A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 Pin # 146 150 152 154 158 159 161 163 165 172 174 176 178 180 Data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 Pin # 17 18 20 23 25 26 27 29 31 32 35 37 38 39 Control A20M# ADS# AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ BS16# BS8# CLK Pin # 104 145 129 117 116 115 113 144 137 138 118 136 135 123 NC 15 34 52 56 60 64 68 72 73 76 78 79 82 83 NC 77 81 VCC 6 19 24 28 36 49 54 62 70 84 93 98 107 112 VSS 1 11 21 22 33 40 50 58 66 86 95 96 99 109
Datasheet
Intel486 SX Processor
Table 6.
Pin Cross Reference for 196-Lead PQFP Package (Sheet 2 of 2)
Address A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pin # 181 183 189 191 193 2 3 4 5 7 8 9 10 12 13 14 Data D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Pin # 41 42 44 45 46 47 48 51 53 55 59 61 63 65 67 69 71 74 Control D / C# DP0 DP1 DP2 DP3 EADS# FLUSH# HLDA HOLD INTR KEN# LOCK# M / IO# NMI PCD PCHK# PLOCK# PWT RDY# RESERVED# RESET SMI# SMIACT# SRESET STPCLK# TCK TDI TDO TMS W / R# Pin # 110 16 30 43 57 105 102 122 130 101 132 142 111 100 106 139 143 108 133 156 103 85 92 94 75 128 185 80 187 120 NC 87 88 89 90 91 97 124 127 134 140 149 151 153 155 157 160 162 166 169 171 173 186 188 190 192 195 NC VCC 119 125 131 147 164 170 175 179 184 196 VSS 114 121 126 141 148 167 168 177 182 194
Datasheet
Intel486 SX Processor
Pin Quick Reference
Table 7.
Embedded Intel486 SX Processor Pin Descriptions (Sheet 1 of 5)
Symbol CLK ADDRESS BUS Address Lines A31-A2, together with the byte enable signals, BE3#-BE0#, define the physical area of memory or input / output space accessed. Address lines A31-A4 are used to drive addresses into the embedded Intel486 SX processor to perform cache line invalidation. Input signals must meet setup and hold times t22 and t23. A31-A2 are not driven during bus or address hold. Byte Enable signals indicate active bytes during read and write cycles. During the first cycle of a cache fill, the external system should assume that all byte enables are active. BE3#-BE0# are active LOW and are not driven during bus hold. BE3# applies to D31-D24 BE2# applies to D23-D16 BE1# applies to D15-D8 BE0# applies to D7-D0 DATA BUS Data Lines. D7-D0 define the least significant byte of the data bus D31-D24 define the most significant byte of the data bus. These signals must meet setup and hold times t22 and t23 for proper operation on reads. These pins are driven during the second and subsequent clocks of write cycles. Type I Name and Function Clock provides the fundamental timing and internal operating frequency for the embedded Intel486 SX processor. All external timing parameters are specified with respect to the rising edge of CLK.
A31-A4 A3-A2
BE3# BE2# BE1# BE0#
D31-D0
DATA PARITY There is one Data Parity pin for each byte of the data bus. Data parity is generated on all write data cycles with the same timing as the data driven by the embedded Intel486 SX processor. Even parity information must be driven back into the processor on the data parity pins with the same timing as read information to ensure that the correct parity check status is indicated by the embedded Intel486 SX processor. The signals read on these pins do not affect program execution. Input signals must meet setup and hold times t22 and t23. DP3-DP0 must be connected to VCC through a pull-up resistor in systems that do not use parity. DP3- DP0 are active HIGH and are driven during the second and subsequent clocks of write cycles. Parity Status is driven on the PCHK# pin the clock after ready for read operations. The parity status is for data sampled at the end of the previous clock. A parity error is indicated by PCHK# being LOW. Parity status is only checked for enabled bytes as indicated by the byte enable and bus size signals. PCHK# is valid only in the clock immediately after read data is returned to the processor. At all other times PCHK# is inactive (HIGH). PCHK# is never floated.
DP3-DP0
PCHK#
Datasheet
Intel486 SX Processor
Table 7.
Embedded Intel486 SX Processor Pin Descriptions (Sheet 2 of 5)
Symbol Type Name and Function
BUS CYCLE DEFINITION Memory / Input-Output, Data / Control and Write / Read lines are the primary bus definition signals. These signals are driven valid as the ADS# signal is asserted. M / IO# 0 0 0 0 M / IO# D / C# W / R# O O O 1 1 1 1 D / C# 0 0 1 1 0 0 1 1 W / R# Bus Cycle Initiated 0 1 0 1 0 1 0 1 Interrupt Acknowledge HALT / Special Cycle (see details below) I / O Read I / O Write Code Read Reserved Memory Read Memory Write
HALT / Special Cycle Cycle Name Shutdown HALT Stop Grant bus cycle BE3# - BE0# A4-A2 1110 1011 1011 000 000 100
LOCK#
Bus Lock indicates that the current bus cycle is locked. The embedded Intel486 SX processor does not allow a bus hold when LOCK# is asserted (address holds are allowed). LOCK# goes active in the first clock of the first locked bus cycle and goes inactive after the last clock of the last locked bus cycle. The last locked cycle ends when Ready is returned. LOCK# is active LOW and not driven during bus hold. Locked read cycles are not transformed into cache fill cycles when KEN# is returned active. Pseudo-Lock indicates that the current bus transaction requires more than one bus cycle to complete. For the embedded Intel486 SX processor, examples of such operations are segment table descriptor reads (64 bits) and cache line fills (128 bits).
PLOCK#
The embedded Intel486 SX processor drives PLOCK# active until the addresses for the last bus cycle of the transaction are driven, regardless of whether RDY# or BRDY# have been returned. PLOCK# is a function of the BS8#, BS16# and KEN# inputs. PLOCK# should be sampled only in the clock in which Ready is returned. PLOCK# is active LOW and is not driven during bus hold.
BUS CONTROL Address Status output indicates that a valid bus cycle definition and address are available on the cycle definition lines and address bus. ADS# is driven active in the same clock in which the addresses are driven. ADS# is active LOW and not driven during bus hold. Non-burst Ready input indicates that the current bus cycle is complete. RDY# indicates that the external system has presented valid data on the data pins in response to a read or that the external system has accepted data from the embedded Intel486 SX processor in response to a write. RDY# is ignored when the bus is idle and at the end of the first clock of the bus cycle. RDY# is active during address hold. Data can be returned to the embedded Intel486 SX processor while AHOLD is active. RDY# is active LOW and is not provided with an internal pull-up resistor. RDY# must satisfy setup and hold times t16 and t17 for proper chip operation.
Datasheet
Intel486 SX Processor
Table 7.
Embedded Intel486 SX Processor Pin Descriptions (Sheet 3 of 5)
Symbol Type Name and Function
RESET
SRESET
SMIACT#
Datasheet
Intel486 SX Processor
Table 7.
Embedded Intel486 SX Processor Pin Descriptions (Sheet 4 of 5)
Symbol Type Name and Function Stop Clock Request input signal indicates a request was made to turn off or change the CLK input frequency. When the embedded Intel486 SX processor recognizes a STPCLK#, it stops execution on the next instruction boundary (unless superseded by a higher priority interrupt), empties all internal pipelines and write buffers, and generates a Stop Grant bus cycle. STPCLK# is active LOW. Though STPCLK# has an internal pull-up resistor, an external 10-K pull-up resistor is needed if the STPCLK# pin is not used. STPCLK# is an asynchronous signal, but must remain active until the embedded Intel486 SX processor issues the Stop Grant bus cycle. STPCLK# may be de-asserted at any time after the processor has issued the Stop Grant bus cycle.
STPCLK#
BUS ARBITRATION BREQ O Bus Request signal indicates that the embedded Intel486 SX processor has internally generated a bus request. BREQ is generated whether or not the processor is driving the bus. BREQ is active HIGH and is never floated. Bus Hold Request allows another bus master complete control of the embedded Intel486 SX processor bus. In response to HOLD going active, the processor floats most of its output and input / output pins. HLDA is asserted after completing the current bus cycle, burst cycle or sequence of locked cycles. The embedded Intel486 SX processor remains in this state until HOLD is de-asserted. HOLD is active HIGH and is not provided with an internal pull-down resistor. HOLD must satisfy setup and hold times t18 and t19 for proper operation. Hold Acknowledge goes active in response to a hold request presented on the HOLD pin. HLDA indicates that the embedded Intel486 SX processor has given the bus to another local bus master. HLDA is driven active in the same clock that the processor floats its bus. HLDA is driven inactive when leaving bus hold. HLDA is active HIGH and remains driven during bus hold. Backoff input forces the embedded Intel486 SX processor to float its bus in the next clock. The processor floats all pins normally floated during bus hold but HLDA is not asserted in response to BOFF#. BOFF# has higher priority than RDY# or BRDY# if both are returned in the same clock, BOFF# takes effect. The embedded Intel486 SX processor remains in bus hold until BOFF# is negated. If a bus cycle is in progress when BOFF# is asserted the cycle is restarted. BOFF# is active LOW and must meet setup and hold times t18 and t19 for proper operation.
BOFF#
AHOLD
EADS#
CACHE CONTROL Cache Enable pin is used to determine whether the current cycle is cacheable. When the embedded Intel486 SX processor generates a cycle that can be cached and KEN# is active one clock before RDY# or BRDY# during the first transfer of the cycle, the cycle becomes a cache line fill cycle. Returning KEN# active one clock before RDY# during the last read in the cache line fill causes the line to be placed in the on-chip cache. KEN# is active LOW and is provided with a small internal pullup resistor. KEN# must satisfy setup and hold times t14 and t15 for proper operation.
Datasheet
Intel486 SX Processor
Table 7.
Embedded Intel486 SX Processor Pin Descriptions (Sheet 5 of 5)
Symbol Type Name and Function Cache Flush input forces the embedded Intel486 SX processor to flush its entire internal cache. FLUSH# is active LOW and need only be asserted for one clock. FLUSH# is asynchronous but setup and hold times t20 and t21 must be met for recognition in any specific clock.
FLUSH#
PAGE CACHEABILITY Page Write-Through and Page Cache Disable pins reflect the state of the page attribute bits, PWT and PCD, in the page table entry, page directory entry or control register 3 (CR3) when paging is enabled. When paging is disabled, the embedded Intel486 SX processor ignores the PCD and PWT bits and assumes they are zero for the purpose of caching and driving PCD and PWT pins. PWT and PCD have the same timing as the cycle definition pins (M / IO#, D / C#, and W / R#). PWT and PCD are active HIGH and are not driven during bus hold. PCD is masked by the cache disable bit (CD) in Control Register 0.
PWT PCD
BUS SIZE CONTROL Bus Size 16 and Bus Size 8 pins (bus sizing pins) cause the embedded Intel486 SX processor to run multiple bus cycles to complete a request from devices that cannot provide or accept 32 bits of data in a single cycle. The bus sizing pins are sampled every clock. The processor uses the state of these pins in the clock before Ready to determine bus size. These signals are active LOW and are provided with internal pull-up resistors. These inputs must satisfy setup and hold times t14 and t15 for proper operation.
BS16# BS8#
ADDRESS MASK Address Bit 20 Mask pin, when asserted, causes the embedded Intel486 SX processor to mask physical address bit 20 (A20) before performing a lookup to the internal cache or driving a memory cycle on the bus. A20M# emulates the address wraparound at 1 Mbyte, which occurs on the 8086 processor. A20M# is active LOW and should be asserted only when the embedded Intel486 SX processor is in real mode. This pin is asynchronous but should meet setup and hold times t20 and t21 for recognition in any specific clock. For proper operation, A20M# should be sampled HIGH at the falling edge of RESET.
A20M#
TMS RESERVED PINS
RESERVED#
Reserved is reserved for future use. This pin MUST be connected to an external pull-up resistor circuit. The recommended resistor value is 10 k. The pull-up resistor must be connected only to the RESERVED# pin. Do not share this resistor with other pins requiring pull-ups.
Datasheet
Intel486 SX Processor
Table 8.
Output Pins
Output Signal Name Active Level Floated During Address Hold Floated During Bus Hold During Stop Grant and Stop Clock States Previous State As per HOLD · · · · · · · Previous State Previous State Previous State HIGH (inactive) HIGH (inactive) HIGH (inactive) Previous State Previous State · · Previous State Previous State
BREQ HLDA BE3#-BE0# PWT, PCD W / R#, M / IO#, D / C# LOCK# PLOCK# ADS# BLAST# PCHK# A3-A2 SMIACT#
HIGH HIGH LOW HIGH HIGH / LOW LOW LOW LOW LOW LOW HIGH LOW
NOTE: The term "Previous State" means that the processor maintains the logic level applied to the signal pin just before the processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.
Table 9.
Input / Output Pins
Output Signal Name Active Level Floated During Address Hold Floated During Bus Hold · · · · During Stop Grant and Stop Clock States Floated Floated Previous State
D31-D0 DP3-DP0 A31-A4
HIGH HIGH HIGH
NOTE: The term "Previous State" means that the processor maintains the logic level applied to the signal pin just before the processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.
Table 10. Test Pins
Name TCK TDI TDO TMS Input or Output Input Input Output Input Sampled / Driven On N / A Rising Edge of TCK Failing Edge of TCK Rising Edge of TCK
Datasheet
Intel486 SX Processor
Table 11. Input Pins
Name CLK RESET SRESET HOLD AHOLD EADS# BOFF# FLUSH# A20M# BS16#, BS8# KEN# RDY# BRDY# INTR NMI RESERVED# SMI# STPCLK# TCK TDI TMS
HIGH HIGH HIGH HIGH LOW LOW LOW LOW LOW LOW LOW LOW HIGH HIGH LOW LOW LOW HIGH HIGH HIGH Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Pull-Up Pull-Up Pull-Up1 Pull-Up Pull-Up Pull-Up Pull-Up Pull-Down Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Down
Active Level
Synchronous / Asynchronous
Internal Pull-Up / Pull-Down
NOTES: 1. Though STPCLK# has an internal pull-up resistor, an external 10-K pull-up resistor is needed if the STPCLK# pin is not used.
Architectural and Functional Overview
Datasheet
Intel486 SX Processor
CPUID Instruction
Operation of the CPUID Instruction
The CPUID instruction requires the software developer to pass an input parameter to the processor in the EAX register. The processor response is returned in registers EAX, EBX, EDX, and ECX.
Table 12. CPUID Instruction Description
OP CODE Instruction Processor Core Clocks 9 0F A2 CPUID 14 9 Parameter passed in EAX
(Input Value)
Description Vendor (Intel) ID String Processor Identification Undefined (Do Not Use)
Vendor ID String - When the parameter passed in EAX is 0 (zero), the register values returned upon instruction execution are shown in the following table.
Vendor ID String (ASCII Characters)
EBX EDX ECX
u (75) I (49) l (6C)
n (6E) e (65) e (65)
e (65) n (6E) t (74)
G (47) i (69) n (6E)
The values in EBX, EDX and ECX indicate an Intel processor. When taken in the proper order, they decode to the string "GenuineIntel." Processor Identification - When the parameter passed to EAX is 1 (one), the register values returned upon instruction execution are:
Datasheet
Intel486 SX Processor
31--------------14 Processor Signature EAX (Do Not Use) Intel Reserved
13, 12 00 Processor Type
11--8 0100 Family
7--4 0010 Model
3--0 XXXX Stepping
(Intel releases information about stepping numbers as needed) 31-------------------------------------------------0 Intel Reserved (Do Not Use) EBX ECX Intel Reserved Intel Reserved 31--------------------------------------2
Feature Flags
Identification After Reset
Processor Identification - Upon reset, the EDX register contains the processor signature:
31--------------14 Processor Signature EDX (Do Not Use) Intel Reserved 13, 12 00 Processor Type 11--8 0100 Family 7--4 0010 Model 3--0 XXXX Stepping
(Intel releases information about stepping numbers as needed)
Boundary Scan (JTAG)
Device Identification
Table 13 shows the 32-bit code for the embedded Intel486 SX processor. This code is loaded into the Device Identification Register.
Table 13. Boundary Scan Component Identification Code (5 Volt Processor)
(Intel releases information about version numbers as needed)
Datasheet
Intel486 SX Processor
Boundary Scan Register Bits and Bit Order
The boundary scan register contains a cell for each pin as well as cells for control of bidirectional and three-state pins. There are "Reserved" bits which correspond to no-connect (N / C) signals of the embedded Intel486 SX processor. Control registers WRCTL, ABUSCTL, BUSCTL, and MISCCTL are used to select the direction of bidirectional or three-state output signal pins. A "1" in these cells designates that the associated bus or bits are floated if the pins are three-state, or selected as input if they are bidirectional.
· WRCTL controls D31-D0 and DP3-DP0 · ABUSCTL controls A31-A2 · BUSCTL controls ADS#, BLAST#, PLOCK#, LOCK#, W / R#, BE0#, BE1#, BE2#, BE3#, M /
IO#, D / C#, PWT, and PCD
· MISCCTL controls PCHK#, HLDA, and BREQ
The following is the bit order of the embedded Intel486 SX processor boundary scan register: TDO A2, A3, A4, A5, RESERVED#, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, DP0, D0, D1, D2, D3, D4, D5, D6, D7, DP1, D8, D9, D10, D11, D12, D13, D14, D15, DP2, D16, D17, D18, D19, D20, D21, D22, D23, DP3, D24, D25, D26, D27, D28, D29, D30, D31, STPCLK#, Reserved, Reserved, SMI#, SMIACT#, SRESET, NMI, INTR, FLUSH#, RESET, A20M#, EADS#, PCD, PWT, D / C#, M / IO#, BE3#, BE2#, BE1#, BE0#, BREQ, W / R#, HLDA, CLK, Reserved, AHOLD, HOLD, KEN#, RDY#, BS8#, BS16#, BOFF#, BRDY#, PCHK#, LOCK#, PLOCK#, BLAST#, TDI ADS#, MISCCTL, BUSCTL, ABUSCTL, WRCTL
Electrical Specifications
Maximum Ratings
Table 14 is a stress rating only. Extended exposure to the Maximum Ratings may affect device reliability. Furthermore, although the embedded Intel486 SX processor contains protective circuitry to resist damage from electrostatic discharge, always take precautions to avoid high static voltages or electric fields. Functional operating conditions are given in Section 5.2, DC Specifications and Section 5.3, AC Specifications.
Table 14. Absolute Maximum Ratings
Case Temperature under Bias Storage Temperature DC Voltage on Any Pin with Respect to Ground Supply Voltage VCC with Respect to VSS -65 °C to +110 °C -65 °C to +150 °C -0.5 V to VCC + 0.5 V -0.5 V to +6.5 V
Datasheet
Intel486 SX Processor
DC Specifications
The following tables show the operating supply voltages, DC I / O specifications, and component power consumption for the embedded Intel486 SX processor.
Table 15. Operating Supply Voltages
Product x80486SXSA33 x80486SXSA33 5.0 V 5.0 V VCC
NOTE: To address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".
Table 16. 5 V DC Specifications
Datasheet
Intel486 SX Processor
Table 17. 5 V ICC Values
AC Specifications
The AC specifications for the embedded Intel486 SX processor are given in this section.
Table 18. AC Characteristics
t7 t8 t8a t9
Note 2
Datasheet
Intel486 SX Processor
Table 18. AC Characteristics
Note 3
t22 t23
Datasheet
Intel486 SX Processor
Table 19. AC Specifications for the Test Access Port
NOTES: 1. TCK period CLK period. 2. Rise / Fall times are measured between 0.8 V and 2.0 V. Rise / Fall times can be relaxed by 1 ns per 10-ns increase in TCK period. 3. Parameters t30 - t37 are measured from TCK.
Figure 3. CLK Waveform
Datasheet
Intel486 SX Processor
Figure 4. Input Setup and Hold Timing
Tx CLK Tx Tx Tx
EADS#
BS8#, BS16#, KEN#
BOFF#, AHOLD, HOLD
RESET, FLUSH#, A20M#, INTR, NMI, SMI#, STPCLK#, SRESET A31-A4 (READ)
Figure 5. Input Setup and Hold Timing
T2 CLK
RDY#, BRDY#
D31-D0, DP3-DP0
Datasheet
Intel486 SX Processor
Figure 6. PCHK# Valid Delay Timing
T2 CLK
RDY#, BRDY#
D31-D0 DP3-DP0
VALID
MIN MAX
PCHK#
VALID
Figure 7. Output Valid Delay Timing
Tx CLK
A2-A31, PWT, PCD, BE0-3#, M / IO#, D / C#, W / R#, ADS#, LOCK#, BREQ, HLDA, SMIACT#
VALID n
VALID n+1
D31-D0, DP3-DP0
VALID n
VALID n+1
BLAST#, PLOCK#
VALID n
VALID n+1
Datasheet
Intel486 SX Processor
Figure 8. Maximum Float Delay Timing
Tx CLK
A2-A31, PWT, PCD, BE0-3#, M / IO#, D / C#, W / R#, ADS#, LOCK#, BREQ, HLDA
VALID
D31-D0, DP3-DP0
VALID
BLAST#, PLOCK#
VALID
Figure 9. TCK Waveform
0.8 V t28 t26 t29
Figure 10. Test Signal Timing Diagram
TCK t30 TMS TDI t32 TDO t34 OUTPUT t36 INPUT VALID VALID t37 VALID t35 VALID VALID t33 t31
Datasheet
Intel486 SX Processor
Capacitive Derating Curves
The following graphs are the capacitive derating curves for the embedded Intel486 SX processor.
Figure 11. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a Low-to-High Transition, 5 V Processor
nom+5 nom+4 nom+3 Delay (ns) nom+2 nom+1 nom nom-1 nom-2 25 50 75 100 125 150
Figure 12. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a High-to-Low Transition, 5 V Processor
nom+7 nom+6 nom+5 nom+4 Delay (ns) nom+3 nom+2 nom+1 nom nom-1 nom-2 25 50 75 100 125 150
Datasheet
Intel486 SX Processor
Mechanical Data
This section describes the packaging dimensions and thermal specifications for the embedded Intel486 SX processor.
Package Dimensions
Figure 13. 168-Pin PGA Package Dimensions
Datasheet
Intel486 SX Processor
Table 20. 168-Pin Ceramic PGA Package Dimensions
Millimeters Symbol Min A A1 A2 A3 B D D1 e1 L N S1 1.52 3.56 0.64 2.8 1.14 0.43 44.07 40.51 2.29 2.54 168 2.54 0.060 Max 4.57 1.14 3.5 1.40 0.51 44.83 40.77 2.79 3.30 SOLID LID SOLID LID Notes Min 0.140 0.025 0.110 0.045 0.017 1.735 1.595 0.090 0.100 168 0.100 Max 0.180 0.045 0.140 0.055 0.020 1.765 1.605 0.110 0.130 SOLID LID SOLID LID Notes Inches
Table 21. Ceramic PGA Package Dimension Symbols
Letter or Symbol A A1 A2 A3 B D D1 e1 L S1 Description of Dimensions Distance from seating plane to highest point of body Distance between seating plane and base plane (lid) Distance from base plane to highest point of body Distance from seating plane to bottom of body Diameter of terminal lead pin Largest overall package dimension of length A body length dimension, outer lead center to outer lead center Linear spacing between true lead position centerlines Distance from seating plane to end of lead Other body dimension, outer lead center to edge of body
NOTES: 1. Controlling dimension: millimeter. 2. Dimension "e1" ("e") is non-cumulative. 3. Seating plane (standoff) is defined by P.C. board hole size: 0.0415-0.0430 inch. 4. Dimensions "B", "B1" and "C" are nominal. 5. Details of Pin 1 identifier are optional.
Datasheet
Intel486 SX Processor
Figure 14. Principal Dimensions and Data for 196-Lead Plastic Quad Flat Pack Package
NOTE: Interpret dimensions and tolerances in accordance with ANSI Y14.5M-1982.
Table 22. Symbol List and Dimensions for 196-Lead PQFP Package
Symbol A A1 D, E D1, E1 D2, E2 Description of Dimensions Package Height: Distance from the seating plane to the highest point of body. Standoff: The distance from the seating plane to the base plane. Overall Package Dimension: Lead tip to lead tip. Plastic Body Dimension Bumper Distance Without FLASH With FLASH CP Seating Plane Coplanarity 1.497 1.497 0.000 1.503 1.510 0.004 Min 0.160 0.020 1.470 1.347 Max 0.175 0.035 1.485 1.353
NOTES: 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Dimensions are in inches.
Datasheet
Intel486 SX Processor
Figure 15. Typical Lead for 196-Lead PQFP Package
240950-B0
240950-B1
Package Thermal Specifications
Datasheet
Intel486 SX Processor
Values for JA and JC are given in the following tables for each product operating at 33 MHz. Maximum TA is shown in Table 26 for each product operating at 33 MHz. Table 23. Thermal Resistance, JA (°C / W) for the 196-Lead PQFP Package
JA vs. Airflow - ft / min. (m / sec) 0 (0) 196-Lead PQFP (5V) - Without Heat Sink 196-Lead PQFP (5V) - With Heat Sink
0.350" high omnidirectional heat sink.
Table 24. Thermal Resistance, JC (°C / W) for the 196-Lead PQFP Package
JC vs. Airflow - ft / min. (m / sec) 0 (0) 196-Lead PQFP (5V) 3.5 200 (1.01) 400 (2.03) 600 (3.04) -
Table 25. Thermal Resistance, JA (°C / W) for the 168-Lead PQFP Package
JA vs. Airflow - ft / min. (m / sec) JC 0 (0) 17.0 13.0 200 (1.01) 14.5 8.0 400 (2.03) 12.5 6.0 600 (3.04) 11.0 5.0 800 (4.06) 10.0 4.5 1000 (5.07) 9.5 4.25
168-Pin PGA (5V) - Without Heat Sink 168-Pin PGA (5V) - With Heat Sink
0.350" high omnidirectional heat sink.
Table 26. Maximum Tambient (TA, °C)
Airflow - ft / min. (m / sec) Freq. (MHz) 196-Lead PQFP (5V) Without Heat Sink 196-Lead PQFP (5V) With Heat Sink 168-Pin PGA (5 V) Without Heat Sink 168-Pin PGA (5 V) With Heat Sink 33 33 33 33 0 (0) 29 41 34 47 200 (1.01) 42 62 42 64 400 (2.03) 51 69 49 70 600 (3.04) 56 70 57 74
Datasheet