32-Bit RISC Technology Core 8-Kbyte Write-Through Cache Four Internal

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Embedded Intel486SX Processor
32-Bit RISC Technology Core 8-Kbyte Write-Through Cache Four Internal Write Buffers Burst Cycles Dynamic Sizing 16-bit Data Devices Technology
Data Parity Generation Checking Boundary Scan (JTAG) 5-Volt Processor 196-Lead Plastic Quad Flat Pack (PQFP) 168-Pin Grid Array (PGA) Binary Compatible with Large Software Base
64-Bit Interunit Transfer
32-Bit Data 32-Bit Data Linear Address
Barrel Shifter Register File
Base/ Index
Segmentation Unit Descriptor Registers Limit Attribute
Interface
Paging Unit
Cache Unit
Address Drivers Write Buffers Data Transceivers Control
A31-A2 BE3#- BE0#
Physical Address Translation Lookaside Buffer
Kbyte Cache
D31-D0
Displacement
Prefetcher MicroInstruction 32-Byte Code Queue 2x16 Bytes Size Control Cache Control Parity Generation Control Boundary Scan Control Request Sequencer Code Stream Instruction Decode Decoded Instruction Path
ADS# W/R# D/C# M/IO# RDY# LOCK# PLOCK# BOFF# A20M# BREQ HOLD HLDA RESET SRESET INTR SMI# SMIACT# FERR# IGNNE# STPCLK#
Burst Control
BRDY# BLAST#
Control Protection Test Unit
BS16# BS8#
KEN# FLUSH# AHOLD EADS#
Control
DP3-DP0 PCHK#
A5443-01
Order Number: 272769-004 August 2004
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Contents
Contents
Introduction. Features. Family Members
This Document Descriptions Assignments Quick Reference CPUID Instruction 4.1.1 Operation CPUID Instruction Identification After Reset.24 Boundary Scan (JTAG).24 4.3.1 Device Identification.24 4.3.2 Boundary Scan Register Bits Order.25 Maximum Ratings Specifications Specifications.27 Capacitive Derating Curves Package Dimensions Package Thermal Specifications
Architectural Functional Overview
Electrical Specifications
Mechanical Data
Figures
Package Diagram 168-Pin Embedded Intel486SX Processor Package Diagram 196-Lead PQFP Embedded Intel486SX Processor Waveform Input Setup Hold Timing Input Setup Hold Timing PCHK# Valid Delay Timing.31 Output Valid Delay Timing Maximum Float Delay Timing Waveform Test Signal Timing Diagram Typical Loading Delay versus Load Capacitance under Worst-Case Conditions Low-to-High Transition, Processor.33 Typical Loading Delay versus Load Capacitance under Worst-Case Conditions High-to-Low Transition, Processor.33 168-Pin Package Dimensions Principal Dimensions Data 196-Lead Plastic Quad Flat Pack Package.36 Typical Lead 196-Lead PQFP Package
Contents
Tables
Embedded Intel486SX Processor Family Pinout Differences 168-Pin Package Assignment 168-Pin Package Cross Reference 168-Pin Package Assignment 196-Lead PQFP Package Cross Reference 196-Lead PQFP Package Embedded Intel486SX Processor Descriptions Output Pins Input/Output Pins. Test Pins. Input Pins. CPUID Instruction Description. Boundary Scan Component Identification Code Volt Processor) Absolute Maximum Ratings Operating Supply Voltages Specifications. Values Characteristics Specifications Test Access Port 168-Pin Ceramic Package Dimensions Ceramic Package Dimension Symbols Symbol List Dimensions 196-Lead PQFP Package Thermal Resistance, 196-Lead PQFP Package. Thermal Resistance, 196-Lead PQFP Package. Thermal Resistance, 168-Lead PQFP Package. Maximum Tambient (TA,
Revision History
Date August 2004 Revision Description address fact that many package prefix variables have changed, package prefix variables this document indicated with "x". Removed device. Added information. Updated related documents list. First release this datasheet embedded.
September 2001 December 1997 October 1995
Intel486SX Processor
Introduction
embedded Intel486SX processor provides high performance 32-bit, embedded applications. Designed applications that need floating-point unit, processor ideal embedded designs running DOS*, Microsoft* Windows*, OS/2*, UNIX* applications written Intel architecture. Projects completed quickly utilizing wide range software tools, utilities, assemblers compilers that available desktop computer systems. Also, developers find advantages using existing chip sets peripheral components their embedded designs. embedded Intel486 processor binary compatible with Intel386and earlier Intel processors. Compared with Intel386 processor, provides faster execution many commonlyused instructions. also provides benefits integrated, 8-Kbyte, write-through cache code data. data operate burst mode which provides 106-Mbyte-per-second transfers cache-line fills instruction prefetches. Intel's technology incorporated embedded Intel486 processor. Utilizing Intel's System Management Mode (SMM), enables designers develop energy-efficient systems. component packages available 5-Volt designs. Both products operate MHz.
196-lead Plastic Quad Flat Pack (PQFP) 168-pin Grid Array (PGA).
Features
embedded Intel486 processor offers these features:
32-bit RISC-Technology Core embedded Intel486 processor performs complete
arithmetic logical operations 16-, 32-bit data types using full-width eight general purpose registers.
Single Cycle Execution Many instructions execute single clock cycle. Instruction Pipelining Overlapped instruction fetching, decoding, address translation
execution.
On-Chip Cache with Cache Consistency Support 8-Kbyte, write-through, internal
cache used both data instructions. Cache hits provide zero wait-state access times data within cache. activity tracked detect alterations memory represented internal cache. internal cache invalidated flushed that external cache controller maintain cache consistency.
External Cache Control Write-back flush controls external cache provided
processor maintain cache consistency.
On-Chip Memory Management Unit Address management memory space protection
mechanisms maintain integrity memory multitudinous virtual memory environment. Both memory segmentation paging supported.
Burst Cycles Burst transfers allow double-word read from memory each
clock cycle. This capability especially useful instruction prefetch filling internal cache.
Intel486SX Processor
Write Buffers processor contains four write buffers enhance performance
consecutive writes memory. processor continue internal operations after write these buffers, without waiting write completed external bus.
Backoff When another master needs control during processor initiated
cycle, embedded Intel486 processor floats signals, then restarts cycle when becomes available again.
Instruction Restart Programs continue execution following exception generated
unsuccessful attempt access memory. This feature important supporting demandpaged virtual memory applications.
Dynamic Sizing External controllers dynamically alter effective width
data bus. widths bits used.
Boundary Scan (JTAG) Boundary Scan provides in-circuit testing components
printed circuit boards. Intel Boundary Scan implementation conforms with IEEE Standard Test Access Port Boundary Scan Architecture. Intel's technology provides these features:
Intel System Management Mode (SMM) unique Intel architecture operating mode
provides dedicated special purpose interrupt address space that used implement intelligent power management other enhanced functions manner that completely transparent operating system applications software. automatically restarted following execution instruction.
Restart instruction interrupted System Management Interrupt (SMI#) Stop Clock embedded Intel486 processor stop clock control mechanism that
provides low-power states: Stop Grant state (20-40 typical, depending input clock frequency) Stop Clock state (~100-200 typical, with input clock frequency MHz).
Auto HALT Power Down After execution HALT instruction, embedded
Intel486 processor issues normal Halt cycle clock input processor core automatically stopped, causing processor enter Auto HALT Power Down state (20-40 typical, depending input clock frequency).
Table
Family Members
Table shows embedded Intel486 processors briefly describes their characteristics. Embedded Intel486SX Processor Family
Product x80486SXSA33 x80486SXSA33 Supply Voltage
Maximum Processor Frequency
Package 168-Pin 196-Lead PQFP
NOTE: address fact that many package prefix variables have changed, package prefix variables this document indicated with "x".
Intel486SX Processor
This Document
complete documentation related embedded Intel486 processor, this document conjunction with following reference documents:
Embedded Intel486Processor Family Developer's Manual Order 273021 Embedded Intel486Processor Hardware Reference Manual Order 273025 Intel486Microprocessor Family Programmer's Reference Manual Order 240486 Intel Application Note AP-485 Intel Processor Identification with CPUID Instruction Order 241618
information reference documents Intel486 processor, Clock (CLK), applies embedded Intel486 processor. Some Intel486 processor information duplicated this document minimize dependence reference documents.
Descriptions
Assignments
following figures tables show assignments each package type embedded Intel486 processor. Tables provided showing differences between embedded Intel486 processor other embedded Intel486 processor products. 168-Pin Grid Array
Figure Package Diagram 168-Pin Embedded Intel486SX Processor (pg. Table Pinout Differences 168-Pin Package (pg. Table Assignment 168-Pin Package (pg. Table Cross Reference 168-Pin Package (pg.
196-Lead PQFP Plastic Quad Flat Pack
Figure Package Diagram 196-Lead PQFP Embedded Intel486SX Processor (pg. Table Assignment 196-Lead PQFP Package (pg. Table Cross Reference 196-Lead PQFP Package (pg.
Intel486SX Processor
Figure Package Diagram 168-Pin Embedded Intel486SX Processor
168-Pin Embedded Intel486SX Processor
SMI#
SRESET
Side View
RESERVED
SMIACT#
FLUSH# A20M# HOLD KEN# STPCLK# BRDY#
BE2#
BE0#
D/C#
LOCK#
HLDA
BREQ
INTR
RESET
BS8#
RDY#
BE1#
M/IO#
PLOCK# BLAST#
AHOLD EADS# BS16# BOFF#
BE3#
W/R#
PCHK#
ADS#
Intel486SX Processor
Table
Pinout Differences 168-Pin Package
Embedded Intel486SX Processor
Embedded IntelDX2Processor
Embedded Write-Back Enhanced IntelDX4Processor HITM# IGNNE# CACHE# WB/WT# FERR# VCC5 CLKMUL VOLDET
IGNNE#
FERR#
INC. Internal Connect. These pins connected internal embedded Intel486 processor. However, signals defined location pins embedded IntelDX2 IntelDX4 processors. system design accommodate these processors provided purpose each understood before used.
Table
Assignment 168-Pin Package (Sheet
Description
Description BOFF#
Description HLDA
HOLD
KEN# RDY# BE3#
INC1 INC1 INTR AHOLD
STPCLK#
Intel486SX Processor
Table
Assignment 168-Pin Package (Sheet
Description
Description BRDY#
Description BREQ PLOCK# PCHK#
SMI#
BE2# BE1#
INC1 INC1 INC1 EADS#
BE0#
BLAST# INC1 ADS#
SRESET RESERVED# SMIACT# INC1 FLUSH# RESET BS16# A20M# BS8#
D/C#
LOCK# M/IO# W/R#
NOTES: INC. Internal Connect. These pins connected internal embedded IntelDX2 processors. However, signals defined location pins IntelDX4 processor. system design accommodate these processors provided purpose each understood before used. Connect. These pins should always remain unconnected. Connection pins VCC, other signal result component malfunction incompatibility with future steppings Intel486 processors.
Intel486SX Processor
Table
Cross Reference 168-Pin Package
Address Data Control A20M# ADS# AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ BS16# BS8# D/C# EADS# FLUSH# HLDA HOLD INTR KEN# LOCK# M/IO# PCHK# PLOCK# RDY# RESERVED# RESET SMI# SMIACT# SRESET STPCLK# W/R#
Intel486SX Processor
Figure Package Diagram 196-Lead PQFP Embedded Intel486SX Processor
ADS# BLAST# PLOCK# LOCK# PCHK# BRDY# BOFF# BS16# BS8# RDY# KEN# HOLD AHOLD HLDA W/R# BREQ BE0# BE1# BE2# BE3# M/IO# D/C# EADS# A20M# RESET FLUSH# INTR
RESERVED#
196-Lead PQFP Embedded Intel486SX Processor
View
SRESET SMIACT# SMI# STPCLK#
A3220-01
Intel486SX Processor
Table
Assignment 196-Lead PQFP Package
Description Description
(Sheet
Description INTR FLUSH# RESET A20M# EADS# D/C# M/IO# BE3# BE2# BE1# BE0# BREQ W/R# HLDA
Description RESERVED#
STPCLK#
AHOLD HOLD
INC2
NOTES: Connect. These pins should always remain unconnected. Connection pins VCC, other signal result component malfunction incompatibility with future steppings Intel486 processors. INC. Internal Connect. These pins connected internal embedded Intel486 processors.
Intel486SX Processor
Table
Assignment 196-Lead PQFP Package
Description Description SMI#
(Sheet
Description KEN# RDY#
Description
BS8# BS16# BOFF# BRDY# PCHK# LOCK# PLOCK# BLAST# ADS#
SMIACT# SRESET
NOTES: Connect. These pins should always remain unconnected. Connection pins VCC, other signal result component malfunction incompatibility with future steppings Intel486 processors. INC. Internal Connect. These pins connected internal embedded Intel486 processors.
Table
Cross Reference 196-Lead PQFP Package (Sheet
Address Data Control A20M# ADS# AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ BS16# BS8#
Intel486SX Processor
Table
Cross Reference 196-Lead PQFP Package (Sheet
Address Data Control D/C# EADS# FLUSH# HLDA HOLD INTR KEN# LOCK# M/IO# PCHK# PLOCK# RDY# RESERVED# RESET SMI# SMIACT# SRESET STPCLK# W/R#
Intel486SX Processor
Quick Reference
following brief description. detailed signal descriptions refer Appendix "Signal Descriptions," Embedded Intel486Processor Family Developer's Manual, order 273021.
Table
Embedded Intel486SX Processor Descriptions (Sheet
Symbol ADDRESS Address Lines A31-A2, together with byte enable signals, BE3#-BE0#, define physical area memory input/output space accessed. Address lines A31-A4 used drive addresses into embedded Intel486 processor perform cache line invalidation. Input signals must meet setup hold times t23. A31-A2 driven during address hold. Byte Enable signals indicate active bytes during read write cycles. During first cycle cache fill, external system should assume that byte enables active. BE3#-BE0# active driven during hold. BE3# applies D31-D24 BE2# applies D23-D16 BE1# applies D15-D8 BE0# applies D7-D0 DATA Data Lines. D7-D0 define least significant byte data bus; D31-D24 define most significant byte data bus. These signals must meet setup hold times proper operation reads. These pins driven during second subsequent clocks write cycles. Type Name Function Clock provides fundamental timing internal operating frequency embedded Intel486 processor. external timing parameters specified with respect rising edge CLK.
A31-A4 A3-A2
BE3# BE2# BE1# BE0#
D31-D0
DATA PARITY There Data Parity each byte data bus. Data parity generated write data cycles with same timing data driven embedded Intel486 processor. Even parity information must driven back into processor data parity pins with same timing read information ensure that correct parity check status indicated embedded Intel486 processor. signals read these pins affect program execution. Input signals must meet setup hold times t23. DP3-DP0 must connected through pull-up resistor systems that parity. DP3- active HIGH driven during second subsequent clocks write cycles. Parity Status driven PCHK# clock after ready read operations. parity status data sampled previous clock. parity error indicated PCHK# being LOW. Parity status only checked enabled bytes indicated byte enable size signals. PCHK# valid only clock immediately after read data returned processor. other times PCHK# inactive (HIGH). PCHK# never floated.
DP3-DP0
PCHK#
Intel486SX Processor
Table
Embedded Intel486SX Processor Descriptions (Sheet
Symbol Type Name Function
CYCLE DEFINITION Memory/Input-Output, Data/Control Write/Read lines primary definition signals. These signals driven valid ADS# signal asserted. M/IO# M/IO# D/C# W/R# D/C# W/R# Cycle Initiated Interrupt Acknowledge HALT/Special Cycle (see details below) Read Write Code Read Reserved Memory Read Memory Write
HALT/Special Cycle Cycle Name Shutdown HALT Stop Grant cycle BE3# BE0# A4-A2 1110 1011 1011
LOCK#
Lock indicates that current cycle locked. embedded Intel486 processor does allow hold when LOCK# asserted (address holds allowed). LOCK# goes active first clock first locked cycle goes inactive after last clock last locked cycle. last locked cycle ends when Ready returned. LOCK# active driven during hold. Locked read cycles transformed into cache fill cycles when KEN# returned active. Pseudo-Lock indicates that current transaction requires more than cycle complete. embedded Intel486 processor, examples such operations segment table descriptor reads bits) cache line fills (128 bits).
PLOCK#
embedded Intel486 processor drives PLOCK# active until addresses last cycle transaction driven, regardless whether RDY# BRDY# have been returned. PLOCK# function BS8#, BS16# KEN# inputs. PLOCK# should sampled only clock which Ready returned. PLOCK# active driven during hold.
CONTROL Address Status output indicates that valid cycle definition address available cycle definition lines address bus. ADS# driven active same clock which addresses driven. ADS# active driven during hold. Non-burst Ready input indicates that current cycle complete. RDY# indicates that external system presented valid data data pins response read that external system accepted data from embedded Intel486 processor response write. RDY# ignored when idle first clock cycle. RDY# active during address hold. Data returned embedded Intel486 processor while AHOLD active. RDY# active provided with internal pull-up resistor. RDY# must satisfy setup hold times proper chip operation.
ADS#
RDY#
Intel486SX Processor
Table
Embedded Intel486SX Processor Descriptions (Sheet
Symbol Type Name Function
BURST CONTROL Burst Ready input performs same function during burst cycle that RDY# performs during non-burst cycle. BRDY# indicates that external system presented valid data response read that external system accepted data response write. BRDY# ignored when idle first clock cycle. BRDY# BRDY# sampled second subsequent clocks burst cycle. Data presented data strobed into embedded Intel486 processor when BRDY# sampled active. RDY# returned simultaneously with BRDY#, BRDY# ignored burst cycle prematurely aborted. BRDY# active provided with small pull-up resistor. BRDY# must satisfy setup hold times t17. BLAST# INTERRUPTS Reset input forces embedded Intel486 processor begin execution known state. processor cannot begin executing instructions until least after VCC, have reached their proper specifications. RESET must remain active during this time ensure proper processor operation. However, warm resets, RESET should remain active least periods. RESET active HIGH. RESET asynchronous must meet setup hold times recognition specific clock. Maskable Interrupt indicates that external interrupt been generated. When internal interrupt flag EFLAGS, active interrupt processing initiated. embedded Intel486 processor generates locked interrupt acknowledge cycles response INTR going active. INTR must remain active until interrupt acknowledges have been performed ensure processor recognition interrupt. INTR active HIGH provided with internal pull-down resistor. INTR asynchronous, must meet setup hold times recognition specific clock. Non-Maskable Interrupt request signal indicates that external non-maskable interrupt been generated. rising-edge sensitive must held least four periods before this rising edge. provided with internal pull-down resistor. asynchronous, must meet setup hold times recognition specific clock. Soft Reset duplicates functionality RESET except that SMBASE register retains previous value. soft resets, SRESET must remain active least periods. SRESET active HIGH. SRESET asynchronous must meet setup hold times recognition specific clock. System Management Interrupt input invokes System Management Mode (SMM). SMI# falling-edge triggered signal which forces embedded Intel486 processor into completion current instruction. SMI# recognized instruction boundary each iteration repeat string instructions. SMI# does break LOCKed cycles cannot interrupt currently executing SMM. embedded Intel486 processor latches falling edge pending SMI# signal while executing existing SMI#. nested SMI# recognized until after execution Resume (RSM) instruction. System Management Interrupt Active, active output, indicates that embedded Intel486 processor operating SMM. asserted when processor begins execute SMI# state save sequence remains active until processor executes last state restore cycle SMRAM. Burst Last signal indicates that next time BRDY# returned, burst cycle complete. BLAST# active both burst non-burst cycles. BLAST# active driven during hold.
RESET
INTR
SRESET
SMI#
SMIACT#
Intel486SX Processor
Table
Embedded Intel486SX Processor Descriptions (Sheet
Symbol Type Name Function Stop Clock Request input signal indicates request made turn change input frequency. When embedded Intel486 processor recognizes STPCLK#, stops execution next instruction boundary (unless superseded higher priority interrupt), empties internal pipelines write buffers, generates Stop Grant cycle. STPCLK# active LOW. Though STPCLK# internal pull-up resistor, external 10-K pull-up resistor needed STPCLK# used. STPCLK# asynchronous signal, must remain active until embedded Intel486 processor issues Stop Grant cycle. STPCLK# de-asserted time after processor issued Stop Grant cycle.
STPCLK#
ARBITRATION BREQ Request signal indicates that embedded Intel486 processor internally generated request. BREQ generated whether processor driving bus. BREQ active HIGH never floated. Hold Request allows another master complete control embedded Intel486 processor bus. response HOLD going active, processor floats most output input/output pins. HLDA asserted after completing current cycle, burst cycle sequence locked cycles. embedded Intel486 processor remains this state until HOLD de-asserted. HOLD active HIGH provided with internal pull-down resistor. HOLD must satisfy setup hold times proper operation. Hold Acknowledge goes active response hold request presented HOLD pin. HLDA indicates that embedded Intel486 processor given another local master. HLDA driven active same clock that processor floats bus. HLDA driven inactive when leaving hold. HLDA active HIGH remains driven during hold. Backoff input forces embedded Intel486 processor float next clock. processor floats pins normally floated during hold HLDA asserted response BOFF#. BOFF# higher priority than RDY# BRDY#; both returned same clock, BOFF# takes effect. embedded Intel486 processor remains hold until BOFF# negated. cycle progress when BOFF# asserted cycle restarted. BOFF# active must meet setup hold times proper operation.
HOLD
HLDA
BOFF#
CACHE INVALIDATION Address Hold request allows another master access embedded Intel486 processor's address cache invalidation cycle. processor stops driving address clock following AHOLD going active. Only address floated during address hold, remainder remains active. AHOLD active HIGH provided with small internal pull-down resistor. proper operation, AHOLD must meet setup hold times t19. External Address This signal indicates that valid external address been driven onto embedded Intel486 processor address pins. This address used perform internal cache invalidation cycle. EADS# active provided with internal pull-up resistor. EADS# must satisfy setup hold times proper operation.
AHOLD
EADS#
CACHE CONTROL Cache Enable used determine whether current cycle cacheable. When embedded Intel486 processor generates cycle that cached KEN# active clock before RDY# BRDY# during first transfer cycle, cycle becomes cache line fill cycle. Returning KEN# active clock before RDY# during last read cache line fill causes line placed on-chip cache. KEN# active provided with small internal pullup resistor. KEN# must satisfy setup hold times proper operation.
KEN#
Intel486SX Processor
Table
Embedded Intel486SX Processor Descriptions (Sheet
Symbol Type Name Function Cache Flush input forces embedded Intel486 processor flush entire internal cache. FLUSH# active need only asserted clock. FLUSH# asynchronous setup hold times must recognition specific clock.
FLUSH#
PAGE CACHEABILITY Page Write-Through Page Cache Disable pins reflect state page attribute bits, PCD, page table entry, page directory entry control register (CR3) when paging enabled. When paging disabled, embedded Intel486 processor ignores bits assumes they zero purpose caching driving pins. have same timing cycle definition pins (M/IO#, D/C#, W/R#). active HIGH driven during hold. masked cache disable (CD) Control Register
SIZE CONTROL Size Size pins (bus sizing pins) cause embedded Intel486 processor multiple cycles complete request from devices that cannot provide accept bits data single cycle. sizing pins sampled every clock. processor uses state these pins clock before Ready determine size. These signals active provided with internal pull-up resistors. These inputs must satisfy setup hold times proper operation.
BS16# BS8#
ADDRESS MASK Address Mask pin, when asserted, causes embedded Intel486 processor mask physical address (A20) before performing lookup internal cache driving memory cycle bus. A20M# emulates address wraparound Mbyte, which occurs 8086 processor. A20M# active should asserted only when embedded Intel486 processor real mode. This asynchronous should meet setup hold times recognition specific clock. proper operation, A20M# should sampled HIGH falling edge RESET.
A20M#
TEST ACCESS PORT Test Clock, input embedded Intel486 processor, provides clocking function required JTAG Boundary scan feature. used clock state information (via TMS) data (via TDI) into component rising edge TCK. Data clocked component (via TDO) falling edge TCK. provided with internal pull-up resistor. Test Data Input serial input used shift JTAG instructions data into processor. sampled rising edge TCK, during SHIFT-IR SHIFT-DR Test Access Port (TAP) controller states. During other controller states, "don't care." provided with internal pull-up resistor. Test Data Output serial output used shift JTAG instructions data component. driven falling edge during SHIFT-IR SHIFT-DR controller states. other times driven high impedance state. Test Mode Select decoded JTAG select test logic operation. sampled rising edge TCK. guarantee deterministic behavior controller, provided with internal pull-up resistor.
RESERVED PINS
RESERVED#
Reserved reserved future use. This MUST connected external pull-up resistor circuit. recommended resistor value pull-up resistor must connected only RESERVED# pin. share this resistor with other pins requiring pull-ups.
Intel486SX Processor
Table
Output Pins
Output Signal Name Active Level Floated During Address Hold Floated During Hold During Stop Grant Stop Clock States Previous State HOLD Previous State Previous State Previous State HIGH (inactive) HIGH (inactive) HIGH (inactive) Previous State Previous State Previous State Previous State
BREQ HLDA BE3#-BE0# PWT, W/R#, M/IO#, D/C# LOCK# PLOCK# ADS# BLAST# PCHK# A3-A2 SMIACT#
HIGH HIGH HIGH HIGH/LOW HIGH
NOTE: term "Previous State" means that processor maintains logic level applied signal just before processor entered Stop Grant state. This conserves power preventing signal from floating.
Table
Input/Output Pins
Output Signal Name Active Level Floated During Address Hold Floated During Hold During Stop Grant Stop Clock States Floated Floated Previous State
D31-D0 DP3-DP0 A31-A4
HIGH HIGH HIGH
NOTE: term "Previous State" means that processor maintains logic level applied signal just before processor entered Stop Grant state. This conserves power preventing signal from floating.
Table Test Pins
Name Input Output Input Input Output Input Sampled/ Driven Rising Edge Failing Edge Rising Edge
Intel486SX Processor
Table Input Pins
Name RESET SRESET HOLD AHOLD EADS# BOFF# FLUSH# A20M# BS16#, BS8# KEN# RDY# BRDY# INTR RESERVED# SMI# STPCLK#
HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Pull-Up Pull-Up Pull-Up1 Pull-Up Pull-Up Pull-Up Pull-Up Pull-Down Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Down
Active Level
Synchronous/ Asynchronous
Internal Pull-Up/ Pull-Down
NOTES: Though STPCLK# internal pull-up resistor, external 10-K pull-up resistor needed STPCLK# used.
Architectural Functional Overview
embedded Intel486 processor architecture essentially same Intel486 processor with clock (CLK) input. Refer Embedded Intel486Processor Family Developer's Manual (order number 273021) description Intel486 processor. Note that embedded Intel486 processor reserved possible future use. This pin, input signal, called RESERVED# must connected 10-K pull-up resistor. pull-up resistor must connected only RESERVED# pin. share this resistor with other pins requiring pull-ups.
Intel486SX Processor
CPUID Instruction
embedded Intel486 processor supports CPUID instruction (see Table 12). Because Intel processors support CPUID instruction, simple test determine instruction supported. test involves processor's Flag, which EFLAGS register. software change value this flag, CPUID instruction available. actual state Flag irrelevant provides significance hardware. This cleared (reset zero) upon device reset (RESET SRESET) compatibility with Intel486 processor designs that support CPUID instruction. CPUID-instruction details provided here embedded Intel486 processor. Refer Intel Application Note AP-485 Intel Processor Identification with CPUID Instruction (Order 241618) description that covers aspects CPUID instruction pertains other Intel processors.
4.1.1
Operation CPUID Instruction
CPUID instruction requires software developer pass input parameter processor register. processor response returned registers EAX, EBX, EDX, ECX.
Table CPUID Instruction Description
CODE Instruction Processor Core Clocks CPUID Parameter passed
(Input Value)
Description Vendor (Intel) String Processor Identification Undefined Use)
Vendor String When parameter passed (zero), register values returned upon instruction execution shown following table.
31-24 High Value 23-16 15-8
Vendor String (ASCII Characters)
(75) (49) (6C)
(6E) (65) (65)
(65) (6E) (74)
(47) (69) (6E)
values EBX, indicate Intel processor. When taken proper order, they decode string "GenuineIntel." Processor Identification When parameter passed (one), register values returned upon instruction execution are:
Intel486SX Processor
31-14 Processor Signature Use) Intel Reserved
13,12 Processor Type
11-8 0100 Family
0010 Model
XXXX Stepping
(Intel releases information about stepping numbers needed) 31-0 Intel Reserved Use) Intel Reserved Intel Reserved 31-2
Feature Flags
Identification After Reset
Processor Identification Upon reset, register contains processor signature:
31-14 Processor Signature Use) Intel Reserved 13,12 Processor Type 11-8 0100 Family 0010 Model XXXX Stepping
(Intel releases information about stepping numbers needed)
4.3.1
Boundary Scan (JTAG)
Device Identification
Table shows 32-bit code embedded Intel486 processor. This code loaded into Device Identification Register.
Table Boundary Scan Component Identification Code Volt Processor)
Version 1=3.3 31-28 XXXX Intel Architecture Type 26-21 000001 Part Number Family 0100 Intel486 Family 20-17 0100 Model 00010 embedded Intel486 processor 16-12 00010 009H Intel
11-1 00000001001
(Intel releases information about version numbers needed)
Boundary Scan Component Identification Code x028 2013 (Hex)
Intel486SX Processor
4.3.2
Boundary Scan Register Bits Order
boundary scan register contains cell each well cells control bidirectional three-state pins. There "Reserved" bits which correspond no-connect (N/C) signals embedded Intel486 processor. Control registers WRCTL, ABUSCTL, BUSCTL, MISCCTL used select direction bidirectional three-state output signal pins. these cells designates that associated bits floated pins three-state, selected input they bidirectional.
WRCTL controls D31-D0 DP3-DP0 ABUSCTL controls A31-A2 BUSCTL controls ADS#, BLAST#, PLOCK#, LOCK#, W/R#, BE0#, BE1#, BE2#, BE3#,
IO#, D/C#, PWT,
MISCCTL controls PCHK#, HLDA, BREQ
following order embedded Intel486 processor boundary scan register: RESERVED#, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, DP0, DP1, D10, D11, D12, D13, D14, D15, DP2, D16, D17, D18, D19, D20, D21, D22, D23, DP3, D24, D25, D26, D27, D28, D29, D30, D31, STPCLK#, Reserved, Reserved, SMI#, SMIACT#, SRESET, NMI, INTR, FLUSH#, RESET, A20M#, EADS#, PCD, PWT, D/C#, M/IO#, BE3#, BE2#, BE1#, BE0#, BREQ, W/R#, HLDA, CLK, Reserved, AHOLD, HOLD, KEN#, RDY#, BS8#, BS16#, BOFF#, BRDY#, PCHK#, LOCK#, PLOCK#, BLAST#, ADS#, MISCCTL, BUSCTL, ABUSCTL, WRCTL
Electrical Specifications
Maximum Ratings
Table stress rating only. Extended exposure Maximum Ratings affect device reliability. Furthermore, although embedded Intel486 processor contains protective circuitry resist damage from electrostatic discharge, always take precautions avoid high static voltages electric fields. Functional operating conditions given Section 5.2, Specifications Section 5.3, Specifications.
Table Absolute Maximum Ratings
Case Temperature under Bias Storage Temperature Voltage with Respect Ground Supply Voltage with Respect +110 +150 -0.5 -0.5 +6.5
Intel486SX Processor
Specifications
following tables show operating supply voltages, specifications, component power consumption embedded Intel486 processor.
Table Operating Supply Voltages
Product x80486SXSA33 x80486SXSA33
0.25 0.25
NOTE: address fact that many package prefix variables have changed, package prefix variables this document indicated with "x".
Table Specifications
Symbol COUT CCLK Functional operating range: 0.25 TCASE +85° Parameter Input Voltage Input HIGH Voltage Output Voltage Output HIGH Voltage Input Leakage Current Input Leakage Current SRESET Input Leakage Current Output Leakage Current Input Capacitance Output Capacitance Capacitance -0.3 +0.8 VCC+0.3 0.45 Unit Note Note Note Note Note Note Note Note Note Notes
NOTES: This parameter measured Address, Data, BEn# Definition, Control This parameter measured Address, Data, BEn# -1.0 Definition, Control -0.9 This parameter inputs without pull-ups pull-downs VCC. This parameter inputs with pull-downs This parameter inputs with pull-ups 0.45 FC=1 MHz; 100% tested.
Intel486SX Processor
Table Values
Functional Operating Range: ±0.25 TCASE +85° Parameter Active (Power Supply) Active (Thermal Design) Stop Grant Stop Clock Operating Frequency Maximum Notes Note Notes Note Note
NOTES: This parameter proper power supply selection. measured using worst case instruction 5.25 maximum current column thermal design power dissipation. measured using worst case instruction typical current column typical operating current system. This value measured system using typical device running Microsoft Windows idle condition. This typical value dependent upon specific system configuration. Typical values 100% tested. Stop Grant specification refers value once embedded Intel486 processor enters Stop Grant Auto HALT Power Down state. Stop Clock specification refers value once processor enters Stop Clock state. levels must equal respectively, order meet Stop Clock specifications.
Specifications
specifications embedded Intel486 processor given this section.
Table Characteristics
TCASE +85° unless otherwise specified. (Sheet Frequency Period Period Stability High Time Time Fall Time Rise Time A31-A2, PWT, PCD, BE3-BE0#, IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA, SMIACT# Valid Delay A31-A2, PWT, PCD, BE3-BE0#, IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA Float Delay PCHK# Valid Delay BLAST#, PLOCK# Valid Delay BLAST#, PLOCK# Float Delay ±250 Adjacent clocks 0.8V 0.8V 0.8V Note
Note
Note
Intel486SX Processor
Table Characteristics
TCASE +85° unless otherwise specified. (Sheet t18a D31-D0, DP3-DP0 Write Data Valid Delay D31-D0, DP3-DP0 Write Data Float Delay EADS# Setup Time EADS# Hold Time KEN#, BS16#, BS8# Setup Time KEN#, BS16#, BS8# Hold Time RDY#, BRDY# Setup Time RDY#, BRDY# Hold Time HOLD, AHOLD Setup Time BOFF# Setup Time HOLD, AHOLD, BOFF# Hold Time FLUSH#, A20M#, NMI, INTR, SMI#, STPCLK#, SRESET, RESET Setup Time FLUSH#, A20M#, NMI, INTR, SMI#, STPCLK#, SRESET, RESET Hold Time D31-D0, DP3-DP0, A31-A4 Read Setup Time D31-D0, DP3-DP0, A31-A4 Read Hold Time Note Note
Note
NOTES: 0-MHz operation guaranteed when STPCLK# Stop Grant cycle protocol used. 100% tested, guaranteed design characterization. reset pulse width cycles required warm resets (RESET SRESET). Power-up resets (cold resets) require RESET asserted least after stable.
Intel486SX Processor
Table Specifications Test Access Port
PQFP Processors) TCASE +85° Symbol Frequency Period High Time Time Rise Time Fall Time TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Outputs (except TDO) Valid Delay Outputs (except TDO) Float Delay Inputs (except TDI, TMS, TCK) Setup Time Inputs (except TDI, TMS, TCK) Hold Time Parameter Unit 2.0V 0.8V Note Note Note Note Note Note Note Note Note Note Figure Notes Note
NOTES: period period. Rise/Fall times measured between Rise/Fall times relaxed 10-ns increase period. Parameters measured from TCK.
Figure Waveform
input setup times input hold times, output float, valid hold times
Intel486SX Processor
Figure Input Setup Hold Timing
EADS#
BS8#, BS16#, KEN#
BOFF#, AHOLD, HOLD
RESET, FLUSH#, A20M#, INTR, NMI, SMI#, STPCLK#, SRESET A31-A4 (READ)
Figure Input Setup Hold Timing
RDY#, BRDY#
D31-D0, DP3-DP0
Intel486SX Processor
Figure PCHK# Valid Delay Timing
RDY#, BRDY#
D31-D0 DP3-DP0
VALID
PCHK#
VALID
Figure Output Valid Delay Timing
A2-A31, PWT, PCD, BE0-3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA, SMIACT#
VALID
VALID
D31-D0, DP3-DP0
VALID
VALID
BLAST#, PLOCK#
VALID
VALID
Intel486SX Processor
Figure Maximum Float Delay Timing
A2-A31, PWT, PCD, BE0-3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA
VALID
D31-D0, DP3-DP0
VALID
BLAST#, PLOCK#
VALID
Figure Waveform
Figure Test Signal Timing Diagram
OUTPUT INPUT VALID VALID VALID VALID VALID
Intel486SX Processor
Capacitive Derating Curves
following graphs capacitive derating curves embedded Intel486 processor.
Figure Typical Loading Delay versus Load Capacitance under Worst-Case Conditions Low-to-High Transition, Processor
nom+5 nom+4 nom+3 Delay (ns) nom+2 nom+1 nom-1 nom-2
Capacitive Load (pF) NOTE: This graph will linear outside capacitive range shown. nominal value from Characteristics table.
Figure Typical Loading Delay versus Load Capacitance under Worst-Case Conditions High-to-Low Transition, Processor
nom+7 nom+6 nom+5 nom+4 Delay (ns) nom+3 nom+2 nom+1 nom-1 nom-2
Capacitive Load (pF) NOTE: This graph will linear outside capacitive range shown. nominal value from Characteristics table.
Intel486SX Processor
Mechanical Data
This section describes packaging dimensions thermal specifications embedded Intel486 processor.
Package Dimensions
Figure 168-Pin Package Dimensions
Intel486SX Processor
Table 168-Pin Ceramic Package Dimensions
Millimeters Symbol 1.52 3.56 0.64 1.14 0.43 44.07 40.51 2.29 2.54 2.54 0.060 4.57 1.14 1.40 0.51 44.83 40.77 2.79 3.30 SOLID SOLID Notes 0.140 0.025 0.110 0.045 0.017 1.735 1.595 0.090 0.100 0.100 0.180 0.045 0.140 0.055 0.020 1.765 1.605 0.110 0.130 SOLID SOLID Notes Inches
Table Ceramic Package Dimension Symbols
Letter Symbol Description Dimensions Distance from seating plane highest point body Distance between seating plane base plane (lid) Distance from base plane highest point body Distance from seating plane bottom body Diameter terminal lead Largest overall package dimension length body length dimension, outer lead center outer lead center Linear spacing between true lead position centerlines Distance from seating plane lead Other body dimension, outer lead center edge body
NOTES: Controlling dimension: millimeter. Dimension "e1" ("e") non-cumulative. Seating plane (standoff) defined P.C. board hole size: 0.0415-0.0430 inch. Dimensions "B", "B1" nominal. Details identifier optional.
Intel486SX Processor
Figure Principal Dimensions Data 196-Lead Plastic Quad Flat Pack Package
NOTE: Interpret dimensions tolerances accordance with ANSI Y14.5M-1982.
Table Symbol List Dimensions 196-Lead PQFP Package
Symbol Description Dimensions Package Height: Distance from seating plane highest point body. Standoff: distance from seating plane base plane. Overall Package Dimension: Lead lead tip. Plastic Body Dimension Bumper Distance Without FLASH With FLASH Seating Plane Coplanarity 1.497 1.497 0.000 1.503 1.510 0.004 0.160 0.020 1.470 1.347 0.175 0.035 1.485 1.353
NOTES: dimensions tolerances conform ANSI Y14.5M-1982. Dimensions inches.
Intel486SX Processor
Figure Typical Lead 196-Lead PQFP Package
240950-B0
240950-B1
Package Thermal Specifications
embedded Intel486 processor specified operation when case temperature (TC) within range measured environment determine whether processor within specified operating range. ambient temperature (TA) calculated from from following equations: Where equals Junction, Ambient Case Temperature respectively. equals Junction-to-Case Junction-to-Ambient thermal Resistance, respectively. defined Maximum Power Consumption.
Intel486SX Processor
Values given following tables each product operating MHz. Maximum shown Table each product operating MHz. Table Thermal Resistance, (°C/W) 196-Lead PQFP Package
Airflow ft/min. (m/sec) 196-Lead PQFP (5V) Without Heat Sink 196-Lead PQFP (5V) With Heat Sink
(1.01) 16.5 10.5
(2.03) 14.0
(3.04) 12.5
20.5 17.0
0.350" high omnidirectional heat sink.
Table Thermal Resistance, (°C/W) 196-Lead PQFP Package
Airflow ft/min. (m/sec) 196-Lead PQFP (5V) (1.01) (2.03) (3.04)
Table Thermal Resistance, (°C/W) 168-Lead PQFP Package
Airflow ft/min. (m/sec) 17.0 13.0 (1.01) 14.5 (2.03) 12.5 (3.04) 11.0 (4.06) 10.0 1000 (5.07) 4.25
168-Pin (5V) Without Heat Sink 168-Pin (5V) With Heat Sink
0.350" high omnidirectional heat sink.
Table Maximum Tambient (TA,
Airflow ft/min. (m/sec) Freq. (MHz) 196-Lead PQFP (5V) Without Heat Sink 196-Lead PQFP (5V) With Heat Sink 168-Pin Without Heat Sink 168-Pin With Heat Sink (1.01) (2.03) (3.04)

32-Bit RISC Technology Core 8-Kbyte Write-Through Cache Four Internal

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