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Ultra-Low Power Version Intel486s 176-Lead Thin Quad Flat Pack (TQFP)


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EMBEDDED ULTRA-LOW POWER Intel486SX PROCESSOR
Ultra-Low Power Version Intel486s 176-Lead Thin Quad Flat Pack (TQFP)
Processor 32-Bit RISC Technology Core 8-Kbyte Write-Through Cache Four Internal Write Buffers Burst Cycles Dynamic Sizing 16-bit Data Devices Intel System Management Mode (SMM) Boundary Scan (JTAG)
64-Bit Interunit Transfer
32-Bit Data 32-Bit Data Linear Address
Separate Voltage Supply Core Circuitry Fast Core-Clock Restart Auto Clock Freeze Ideal Embedded Battery-Operated Hand-Held Applications
Core Clock
Clock Control
Input
Barrel Shifter
Register File
Base/ Index
Segmentation Unit
Descriptor Registers
Limit Attribute
Interface
Paging Unit
Cache Unit
Address Drivers
A31-A2 BE3#- BE0#
Physical Address
Translation Lookaside Buffer
Kbyte Cache
Write Buffers
Data Transceivers
D31-D0
Control
Displacement
Prefetcher
MicroInstruction
Control Protection Test Unit
Code Stream
Instruction Decode Decoded Instruction Path
32-Byte Code Queue 2x16 Bytes
Request Sequencer
ADS# W/R# D/C# M/IO# RDY# LOCK# PLOCK# BOFF# A20M# BREQ HOLD HLDA RESET SRESET INTR SMI# SMIACT# STPCLK#
Burst Control
BRDY# BLAST#
Control
Size Control
BS16# BS8#
Cache Control Boundary Scan Control
KEN# FLUSH# AHOLD EADS#
A5850-01
Figure Embedded Ultra-Low Power Intel486SX Processor Block Diagram INTEL CORPORATION, 2004 August 2004 Order Number: 272731-003
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Embedded Ultra-Low Power Intel486SX processor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 1997, 2004 *Third-party brands names property their respective owners.
Contents
Embedded Ultra-Low Power Intel486SX Processor
INTRODUCTION Features Family Members THIS DOCUMENT DESCRIPTIONS Assignments Quick Reference ARCHITECTURAL FUNCTIONAL OVERVIEW Separate Supply Voltages Fast Clock Restart Level-Keeper Circuits Low-Power Features 4.4.1 Auto Clock Freeze CPUID Instruction 4.5.1 Operation CPUID Instruction Identification After Reset Boundary Scan (JTAG) 4.7.1 Device Identification 4.7.2 Boundary Scan Register Bits Order ELECTRICAL SPECIFICATIONS Maximum Ratings Specifications Specifications Capacitive Derating Curves MECHANICAL DATA Package Dimensions Package Thermal Specifications FIGURES Figure Figure Figure Figure Figure Figure Figure Figure Figure Embedded Ultra-Low Power Intel486SX Processor Block Diagram Package Diagram 176-Lead TQFP Package Embedded Intel486SX Processor Example Supply Voltage Power Sequence Stop Clock State Diagram with Typical Power Consumption Values Waveform Input Setup Hold Timing Input Setup Hold Timing Output Valid Delay Timing Maximum Float Delay Timing
Contents
Figure Figure Figure Figure Figure TABLES Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Waveform Test Signal Timing Diagram Typical Loading Delay versus Load Capacitance under Worst-Case Conditions Low-to-High Transition Typical Loading Delay versus Load Capacitance under Worst-Case Conditions High-to-Low Transition Package Mechanical Specifications Lead TQFP Package
Embedded Ultra-Low Power Intel486SX Processor Assignment 176-Lead TQFP Package Embedded Intel486SX Processor Cross Reference 176-Lead TQFP Package Embedded Intel486SX Processor Embedded Intel486SX Processor Descriptions Output Pins Input/Output Pins Test Pins Input Pins CPUID Instruction Description Boundary Scan Component Identification Code Absolute Maximum Ratings Operating Supply Voltages Specifications Active Values Clock Stop, Stop Grant, Auto HALT Power Down Values Characteristics Specifications Test Access Port Thermal Resistance Maximum Ambient Temperature (TA)
Embedded Ultra-Low Power Intel486SX Processor
INTRODUCTION
This data sheet describes embedded Ultra-Low Power (ULP) Intel486SX processor. intended embedded battery-operated hand-held applications. embedded Intel486 processor provides features Intel486 processor except external data-bus parity logic processor-upgrade pin. processor typically uses less power than Intel486 processor. Additionally, embedded Intel486 processor external data level-keeper circuitry fast-recovery core clock which vital ultra-low-power system designs. processor available Thin Quad Flat Package (TQFP) enabling low-profile component implementation. embedded Intel486 processor consists 32-bit integer processing unit, on-chip cache, memory management unit. design ensures full instruction-set compatibility with 8086, 8088, 80186, 80286, Intel386SX, Intel386 versions Intel486 processors.
On-Chip Memory Management Unit Address management memory space protection mechanisms maintain integrity memory multitasking virtual memory environment. Both segmentation paging supported. Burst Cycles Burst transfers allow double word read from memory each clock cycle. This capability especially useful instruction prefetch filling internal cache. Write Buffers processor contains four write buffers enhance performance consecutive writes memory. processor continue internal operations after write these buffers, without waiting write completed external bus. Backoff When another master needs control during processor initiated cycle, embedded Intel486 processor floats signals, then restarts cycle when becomes available again. Instruction Restart Programs continue execution following exception generated unsuccessful attempt access memory. This feature important supporting demand-paged virtual memory applications. Dynamic Sizing External controllers dynamically alter effective width data bus. widths bits used. Boundary Scan (JTAG) Boundary Scan provides in-circuit testing components printed circuit boards. Intel Boundary Scan implementation conforms with IEEE Standard Test Access Port Boundary Scan Architecture. Intel System Management Mode (SMM) unique Intel architecture operating mode provides dedicated special purpose interrupt address space that used implement intelligent power management other enhanced functions manner that completely transparent operating system applications software. Restart instruction interrupted System Management Interrupt (SMI#) automatically restarted following execution instruction. Stop Clock embedded Intel486 processor stop clock control mechanism that provides low-power states: Stop Grant state (40-85 typical, depending input clock frequency) Stop Clock state (~60 typical, with input clock frequency MHz).
Features
embedded Intel486 processor offers these features Intel486 processor: 32-bit RISC-Technology Core embedded Intel486 processor performs complete arithmetic logical operations 16-, 32-bit data types using full-width eight general purpose registers. Single Cycle Execution Many instructions execute single clock cycle. Instruction Pipelining Overlapped instruction fetching, decoding, address translation execution. On-Chip Cache with Cache Consistency Support 8-Kbyte, write-through, internal cache used both data instructions. Cache hits provide zero wait-state access times data within cache. activity tracked detect alterations memory represented internal cache. internal cache invalidated flushed that external cache controller maintain cache consistency. External Cache Control Write-back flush controls external cache provided processor maintain cache consistency.
Embedded Ultra-Low Power Intel486SX Processor
Auto HALT Power Down After execution HALT instruction, embedded Intel486 processor issues normal Halt cycle clock input processor core automatically stopped, causing processor enter Auto HALT Power Down state (40-85 typical, depending input clock frequency). embedded Intel486 processor differs from Intel486 processor following areas: Processor Upgrade Removed signal provided. Parity Signals Removed DP3-DP0 PCHK# signals provided. Separate Processor-Core Power While embedded Intel486 processor requires supply voltage processor core dedicated pins operates with supply voltage Small, Low-Profile Package 176-Lead Thin Quad Flat Pack (TQFP) package approximately square only height. This approximately diameter thickness U.S. quarter. embedded Intel486 processor ideal embedded hand-held battery-powered applications.
Level Keeper Circuits embedded Intel486 processor level-keeper circuits 32-bit external data signals. They retain valid high logic voltage levels when processor Stop Grant Stop Clock states. This power-saving improvement from floating data Intel486 processor. Auto Clock Freeze embedded Intel486 processor monitors events internal activity. Auto Clock Freeze feature automatically controls internal clock distribution, turning clocks internal units when they idle. This power-saving function transparent embedded system. Fast Clock Restart embedded Intel486 processor requires only eight clock periods synchronize internal clock with input signal. This provides faster transition from Stop Clock State Normal State. 33-MHz operation, this synchronization time only compared with (PLL startup latency) Intel486 processor.
Family Members
Table shows embedded Intel486 processor briefly describes characteristics.
Table Embedded Ultra-Low Power Intel486SX Processor Supply Voltage
(VCCP)
Product
Processor Core Supply Voltage
(VCC)
Processor Frequency
(MHz)
Package
x80486SXSF-33
176-Lead TQFP
NOTE: address fact that many package prefix variables have changed, package prefix variables this document indicated with "x".
Embedded Ultra-Low Power Intel486SX Processor
THIS DOCUMENT
DESCRIPTIONS Assignments
embedded Intel486 processor characteristics similar Intel486 processor. This document describes features embedded Intel486 processor. Some Intel486 processor information also included minimize dependence reference documents. complete documentation related embedded Intel486 processor, this document conjunction with following reference documents: Embedded Intel486Processor Family Developer's Manual Order 273021 Embedded Intel486Processor Hardware Reference Manual Order 273025 Intel Application Note AP-485 Intel Processor Identification with CPUID Instruction Order 241618
following figures tables show assignments 176-pin Thin Quad Flat Pack (TQFP) package embedded Intel486 processor. Included are: Figure Package Diagram 176-Lead TQFP Package Embedded Intel486SX Processor (pg. Table Assignment 176-Lead TQFP Package Embedded Intel486SX Processor (pg. Table Cross Reference 176-Lead TQFP Package Embedded Intel486SX Processor (pg. Table Embedded Intel486SX Processor Descriptions (pg. Table Output Pins (pg. Table Input/Output Pins (pg. Table Test Pins (pg. Table Input Pins (pg. tables figures show "no-connects" "N/C." These pins should always remain unconnected. Connecting pins VCC, VCCP, VSS, other signal result component malfunction incompatibility with future steppings embedded Intel486 processor.
Embedded Ultra-Low Power Intel486SX Processor
Figure Package Diagram 176-Lead TQFP Package Embedded Intel486SX Processor
EADS# A20M# RESET FLUSH# INTR SRESET SMIACT# VCCP SMI# STPCLK# VCCP VCCP VCCP VCCP
BLAST# PLOCK# LOCK# VCCP BRDY# BOFF# BS16# BS8# RDY# KEN# HOLD AHOLD HLDA W/R# VCCP BREQ BE0# BE1# BE2# BE3# M/IO# D/C# VCCP
ADS# VCCP VCCP RESERVED# VCCP VCCP VCCP VCCP VCCP
176-Lead TQFP (top view)
VCCP VCCP VCCP VCCP VCCP
Embedded Ultra-Low Power Intel486SX Processor
Table Assignment 176-Lead TQFP Package Embedded Intel486SX Processor
Description
BLAST# PLOCK# LOCK# VCCP BRDY# BOFF# BS16# BS8# RDY# KEN# HOLD AHOLD HLDA W/R# VCCP BREQ BE0# BE1# BE2# BE3# M/IO# D/C# VCCP
Description
EADS# A20M# RESET FLUSH# INTR SRESET SMIACT# VCCP SMI# STPCLK# VCCP VCCP VCCP VCCP
Description
VCCP VCCP VCCP VCCP VCCP
Description
VCCP VCCP VCCP VCCP VCCP RESERVED# VCCP VCCP ADS#
Embedded Ultra-Low Power Intel486SX Processor
Table Cross Reference 176-Lead TQFP Package Embedded Intel486SX Processor Address
Data
Control
AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ BS16# BS8# D/C# HLDA HOLD KEN# LOCK# M/IO# PLOCK# RESERVED# RDY# W/R# A20M# EADS# FLUSH# INTR RESET SMI# SMIACT# SRESET STPCLK# ADS# W/R#
VCCP
Embedded Ultra-Low Power Intel486SX Processor
Quick Reference
following brief description. detailed signal descriptions refer Appendix "Signal Descriptions," Embedded Intel486Processor Family Developer's Manual, order 273021. Table Embedded Intel486SX Processor Descriptions (Sheet Symbol Type Name Function Clock provides fundamental timing internal operating frequency embedded Intel486 processor. external timing parameters specified with respect rising edge CLK. Address Lines A31-A2, together with byte enable signals, BE3#-BE0#, define physical area memory input/output space accessed. Address lines A31-A4 used drive addresses into embedded Intel486 processor perform cache line invalidation. Input signals must meet setup hold times t23. A31-A2 driven during address hold. Byte Enable signals indicate active bytes during read write cycles. During first cycle cache fill, external system should assume that byte enables active. BE3#-BE0# active driven during hold. BE3# applies D31-D24 BE2# applies D23-D16 BE1# applies D15-D8 BE0# applies D7-D0 DATA D31-D0 Data Lines. D7-D0 define least significant byte data bus; D31-D24 define most significant byte data bus. These signals must meet setup hold times proper operation reads. These pins driven during second subsequent clocks write cycles.
ADDRESS A31-A4 A3-A2
BE3# BE2# BE1# BE0#
Embedded Ultra-Low Power Intel486SX Processor
Table Embedded Intel486SX Processor Descriptions (Sheet Symbol M/IO# D/C# W/R# Type Name Function Memory/Input-Output, Data/Control Write/Read lines primary definition signals. These signals driven valid ADS# signal asserted. M/IO# Cycle Name Shutdown HALT Stop Grant cycle LOCK# D/C# HALT/Special Cycle BE3# BE0# 1110 1011 1011 A4-A2 W/R# Cycle Initiated Interrupt Acknowledge HALT/Special Cycle (see details below) Read Write Code Read Reserved Memory Read Memory Write
CYCLE DEFINITION
Lock indicates that current cycle locked. embedded Intel486 processor does allow hold when LOCK# asserted (address holds allowed). LOCK# goes active first clock first locked cycle goes inactive after last clock last locked cycle. last locked cycle ends when Ready returned. LOCK# active driven during hold. Locked read cycles transformed into cache fill cycles when KEN# returned active. Pseudo-Lock indicates that current transaction requires more than cycle complete. embedded Intel486 processor, examples such operations segment table descriptor reads bits) cache line fills (128 bits). embedded Intel486 processor drives PLOCK# active until addresses last cycle transaction driven, regardless whether RDY# BRDY# have been returned. PLOCK# function BS8#, BS16# KEN# inputs. PLOCK# should sampled only clock which Ready returned. PLOCK# active driven during hold.
PLOCK#
CONTROL ADS# Address Status output indicates that valid cycle definition address available cycle definition lines address bus. ADS# driven active same clock which addresses driven. ADS# active driven during hold.
Embedded Ultra-Low Power Intel486SX Processor
Table Embedded Intel486SX Processor Descriptions (Sheet Symbol RDY# Type Name Function Non-burst Ready input indicates that current cycle complete. RDY# indicates that external system presented valid data data pins response read that external system accepted data from embedded Intel486 processor response write. RDY# ignored when idle first clock cycle. RDY# active during address hold. Data returned embedded Intel486 processor while AHOLD active. RDY# active provided with internal pull-up resistor. RDY# must satisfy setup hold times proper chip operation. BURST CONTROL BRDY# Burst Ready input performs same function during burst cycle that RDY# performs during non-burst cycle. BRDY# indicates that external system presented valid data response read that external system accepted data response write. BRDY# ignored when idle first clock cycle. BRDY# sampled second subsequent clocks burst cycle. Data presented data strobed into embedded Intel486 processor when BRDY# sampled active. RDY# returned simultaneously with BRDY#, BRDY# ignored burst cycle prematurely aborted. BRDY# active provided with small pull-up resistor. BRDY# must satisfy setup hold times t17. BLAST# Burst Last signal indicates that next time BRDY# returned, burst cycle complete. BLAST# active both burst non-burst cycles. BLAST# active driven during hold. Reset input forces embedded Intel486 processor begin execution known state. processor cannot begin executing instructions until least after VCC, VCCP, have reached their proper specifications. RESET must remain active during this time ensure proper processor operation. However, warm resets, RESET should remain active least periods. RESET active HIGH. RESET asynchronous must meet setup hold times recognition specific clock. Maskable Interrupt indicates that external interrupt been generated. When internal interrupt flag EFLAGS, active interrupt processing initiated. embedded Intel486 processor generates locked interrupt acknowledge cycles response INTR going active. INTR must remain active until interrupt acknowledges have been performed ensure processor recognition interrupt. INTR active HIGH provided with internal pull-down resistor. INTR asynchronous, must meet setup hold times recognition specific clock. Non-Maskable Interrupt request signal indicates that external non-maskable interrupt been generated. rising-edge sensitive must held least four periods before this rising edge. provided with internal pull-down resistor. asynchronous, must meet setup hold times recognition specific clock.
INTERRUPTS RESET
INTR
Embedded Ultra-Low Power Intel486SX Processor
Table Embedded Intel486SX Processor Descriptions (Sheet Symbol SRESET Type Name Function Soft Reset duplicates functionality RESET except that SMBASE register retains previous value. soft resets, SRESET must remain active least periods. SRESET active HIGH. SRESET asynchronous must meet setup hold times recognition specific clock. System Management Interrupt input invokes System Management Mode (SMM). SMI# falling-edge triggered signal which forces embedded Intel486 processor into completion current instruction. SMI# recognized instruction boundary each iteration repeat string instructions. SMI# does break LOCKed cycles cannot interrupt currently executing SMM. embedded Intel486 processor latches falling edge pending SMI# signal while executing existing SMI#. nested SMI# recognized until after execution Resume (RSM) instruction. System Management Interrupt Active, active output, indicates that embedded Intel486 processor operating SMM. asserted when processor begins execute SMI# state save sequence remains active until processor executes last state restore cycle SMRAM. Stop Clock Request input signal indicates request made turn change input frequency. When embedded Intel486 processor recognizes STPCLK#, stops execution next instruction boundary (unless superseded higher priority interrupt), empties internal pipelines write buffers, generates Stop Grant cycle. STPCLK# active LOW. Though STPCLK# internal pull-up resistor, external 10-K pull-up resistor needed STPCLK# used. STPCLK# asynchronous signal, must remain active until embedded Intel486 processor issues Stop Grant cycle. STPCLK# de-asserted time after processor issued Stop Grant cycle. Request signal indicates that embedded Intel486 processor internally generated request. BREQ generated whether processor driving bus. BREQ active HIGH never floated. Hold Request allows another master complete control embedded Intel486 processor bus. response HOLD going active, processor floats most output input/output pins. HLDA asserted after completing current cycle, burst cycle sequence locked cycles. embedded Intel486 processor remains this state until HOLD de-asserted. HOLD active HIGH provided with internal pull-down resistor. HOLD must satisfy setup hold times proper operation. Hold Acknowledge goes active response hold request presented HOLD pin. HLDA indicates that embedded Intel486 processor given another local master. HLDA driven active same clock that processor floats bus. HLDA driven inactive when leaving hold. HLDA active HIGH remains driven during hold.
SMI#
SMIACT#
STPCLK#
ARBITRATION BREQ
HOLD
HLDA
Embedded Ultra-Low Power Intel486SX Processor
Table Embedded Intel486SX Processor Descriptions (Sheet Symbol BOFF# Type Name Function Backoff input forces embedded Intel486 processor float next clock. processor floats pins normally floated during hold HLDA asserted response BOFF#. BOFF# higher priority than RDY# BRDY#; both returned same clock, BOFF# takes effect. embedded Intel486 processor remains hold until BOFF# negated. cycle progress when BOFF# asserted cycle restarted. BOFF# active must meet setup hold times proper operation. Address Hold request allows another master access embedded Intel486 processor's address cache invalidation cycle. processor stops driving address clock following AHOLD going active. Only address floated during address hold, remainder remains active. AHOLD active HIGH provided with small internal pull-down resistor. proper operation, AHOLD must meet setup hold times t19. External Address This signal indicates that valid external address been driven onto embedded Intel486 processor address pins. This address used perform internal cache invalidation cycle. EADS# active provided with internal pull-up resistor. EADS# must satisfy setup hold times proper operation. Cache Enable used determine whether current cycle cacheable. When embedded Intel486 processor generates cycle that cached KEN# active clock before RDY# BRDY# during first transfer cycle, cycle becomes cache line fill cycle. Returning KEN# active clock before RDY# during last read cache line fill causes line placed on-chip cache. KEN# active provided with small internal pull-up resistor. KEN# must satisfy setup hold times proper operation. Cache Flush input forces embedded Intel486 processor flush entire internal cache. FLUSH# active need only asserted clock. FLUSH# asynchronous setup hold times must recognition specific clock. Page Write-Through Page Cache Disable pins reflect state page attribute bits, PCD, page table entry, page directory entry control register (CR3) when paging enabled. When paging disabled, embedded Intel486 processor ignores bits assumes they zero purpose caching driving pins. have same timing cycle definition pins (M/IO#, D/C#, W/R#). active HIGH driven during hold. masked cache disable (CD) Control Register
CACHE INVALIDATION AHOLD
EADS#
CACHE CONTROL KEN#
FLUSH#
PAGE CACHEABILITY
Embedded Ultra-Low Power Intel486SX Processor
Table Embedded Intel486SX Processor Descriptions (Sheet Symbol BS16# BS8# Type Name Function Size Size pins (bus sizing pins) cause embedded Intel486 processor multiple cycles complete request from devices that cannot provide accept bits data single cycle. sizing pins sampled every clock. processor uses state these pins clock before Ready determine size. These signals active provided with internal pull-up resistors. These inputs must satisfy setup hold times proper operation. Address Mask pin, when asserted, causes embedded Intel486 processor mask physical address (A20) before performing lookup internal cache driving memory cycle bus. A20M# emulates address wraparound Mbyte, which occurs 8086 processor. A20M# active should asserted only when embedded Intel486 processor real mode. This asynchronous should meet setup hold times recognition specific clock. proper operation, A20M# should sampled HIGH falling edge RESET. Test Clock, input embedded Intel486 processor, provides clocking function required JTAG Boundary scan feature. used clock state information (via TMS) data (via TDI) into component rising edge TCK. Data clocked component (via TDO) falling edge TCK. provided with internal pull-up resistor. Test Data Input serial input used shift JTAG instructions data into processor. sampled rising edge TCK, during SHIFT-IR SHIFT-DR controller states. During other Test Access Port (TAP) controller states, "don't care." provided with internal pull-up resistor. Test Data Output serial output used shift JTAG instructions data component. driven falling edge during SHIFT-IR SHIFT-DR controller states. other times driven high impedance state. Test Mode Select decoded JTAG select test logic operation. sampled rising edge TCK. guarantee deterministic behavior controller, provided with internal pull-up resistor. Reserved reserved future use. This MUST connected external pull-up resistor circuit. recommended resistor value kOhms.
SIZE CONTROL
ADDRESS MASK A20M#
TEST ACCESS PORT
RESERVED PINS RESERVED#
Embedded Ultra-Low Power Intel486SX Processor
Table Output Pins Output Signal Name BREQ HLDA BE3#-BE0# PWT, W/R#, M/IO#, D/C# LOCK# PLOCK# ADS# BLAST# A3-A2 SMIACT# Active Level HIGH HIGH HIGH HIGH/LOW HIGH Floated During Address Hold Floated During Hold During Stop Grant Stop Clock States1 Previous State HOLD Previous State Previous State Previous State HIGH (inactive) HIGH (inactive) HIGH (inactive) Previous State Previous State Previous State
NOTES: term "Previous State" means that processor maintains logic level applied signal just before processor entered Stop Grant state. This conserves power preventing signal from floating.
Table Input/Output Pins Output Signal Name D31-D0 A31-A4 Active Level HIGH HIGH Floated During Address Hold Floated During Hold During Stop Grant Stop Clock States1,2 Level-Keeper Previous State
NOTES: term "Level-Keeper" means that processor maintains most recent logic level applied signal pin. This conserves power preventing signal from floating. system component, other than processor, temporarily drives these signal pins then floats them, processor forces maintains most recent logic levels that were applied system component. term "Previous State" means that processor maintains logic level applied signal just before processor entered Stop Grant state. This conserves power preventing signal from floating.
Embedded Ultra-Low Power Intel486SX Processor
Table Test Pins Name Input Output Input Input Output Input Table Input Pins Name RESET SRESET HOLD AHOLD EADS# BOFF# FLUSH# A20M# BS16#, BS8# KEN# RDY# BRDY# INTR RESERVED# SMI# STPCLK# HIGH HIGH HIGH Asynchronous Asynchronous Pull-Up Pull-Up1 Pull-Up Pull-Up Pull-Up HIGH HIGH HIGH HIGH HIGH HIGH Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Pull-Up Pull-Down Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Down Active Level Synchronous/ Asynchronous Internal Pull-Up/ Pull-Down Sampled/ Driven Rising Edge Failing Edge Rising Edge
NOTE: Though STPCLK# internal pull-up resistor, external 10-K pull-up resistor needed STPCLK# used.
Embedded Ultra-Low Power Intel486SX Processor
ARCHITECTURAL FUNCTIONAL OVERVIEW
embedded Intel486 processor architecture essentially same Intel486 processor with clock (CLK) input. Refer Embedded Intel486Processor Family Developer's Manual, order number 273032, description Intel486 processor. following notes supplement information manual. information pertaining parity signals external data does apply. embedded Intel486 processor does have DP0#, DP1#, DP2#, DP3# PCHK# signal pins. References Upgrade Power Down Mode apply. embedded Intel486 processor does have signal does support Intel OverDrive® processor. References "VCC" called "VCCP" embedded Intel486 processor when supply voltage pertains processor's external interface drivers receivers. term "VCC" pertains only processor core supply voltage embedded Intel486 processor. Information about split-supply voltage provided this datasheet. Phase-Locked Loop (PLL) clock (CLK) input been replaced proprietary Differential Delay Line (DDL) that faster startup recovery time. Datasheet references recovery time replaced with circuit eight-CLK recovery time. Information about startup recovery latency provided this datasheet. embedded Intel486 processor level-keeper circuits external 32-bit data signals (D31-D0). Intel486 processor floats data instead. More information about level-keeper circuitry provided this datasheet. datasheet describes processor supplycurrent consumption Auto HALT Power Down, Stop Grant, Stop Clock states. This supply-current consumption embedded Intel486 processor much less than that Intel486 processor. Information about power consumption these states provided this datasheet. Boundary-Scan (JTAG) boundary-scan register bits embedded Intel486 processor this datasheet.
embedded Intel486 processor reserved possible future use. This input signal, 166. called RESERVED# must connected 10-K pull-up resistor.
Separate Supply Voltages
embedded Intel486 processor separate voltage-supply planes internal coreprocessor circuits external driver/receiver circuits. supply voltage internal core processor named supply voltage external circuits named VCCP. single-supply voltage design, embedded Intel486 processor functional this type system design, processor's VCCP pins must tied same power plane. Even though VCCP must processor's external-output circuits drive TTLcompatible components. However, processor's external-input circuits allow connection TTL-compatible components. Section 5.2, Specifications (pg. contains specifications processor's input output signals. lower-power operation, separate, lower voltage chosen, VCCP must voltage value between chosen guaranteed processor operation MHz. embedded Intel486 processor also operate MHz, provided value chosen between Section 5.2, Specifications (pg. defines supply voltage specifications. systems with separate VCCP power planes, processor-core voltage supply must always less than equal processor's external-interface voltage supply; e.g., system design must guarantee: VCCP Violating this relationship causes excessive power consumption. Limited testing shown component damage when this relationship violated. However, prolonged violation recommended component integrity guaranteed.
Embedded Ultra-Low Power Intel486SX Processor
VCCP relationship must also guaranteed system design during power-up power-down sequences. Refer Figure Even though must less than equal VCCP, recommended that system's power-on sequence allows quickly achieve operational level once VCCP achieves operational level. Similarly, power-down sequence should allow
VCCP power down quickly after below operational voltage level. These recommendations given keep power consumption minimum. Deviating from recommendations does create component reliability problem, power consumption processor's external interface circuits increases beyond normal operating values.
VCCP
VCCP
VCCP
TIME
POWER POWER
Figure Example Supply Voltage Power Sequence
Embedded Ultra-Low Power Intel486SX Processor
Fast Clock Restart
embedded Intel486 processor integrated proprietary differential delay line (DDL) circuit internal clock generation. driven input signal provided external system. During normal operation, external system must guarantee that signal maintains frequency that clock period deviates more than ps/CLK. This state, called Normal State, shown Figure increase decrease frequency more quickly than this, system must interrupt processor with STPCLK# signal. Once processor indicates that Stop Grant State, system adjust signal frequency, wait minimum eight periods, then force processor return normal
operational state deactivating STPCLK# interrupt. This wait eight periods much faster than wait required earlier Intel486 processor products. While Stop Grant State, external system deactivate signal processor. This forces processor Stop Clock State state which processor consumes least power. Once system reactivates signal, processor transitions Stop Grant State within eight periods. Normal operation resumed deactivating STPCLK# interrupt signal. Here again, embedded Intel486 processor recovers from Stop Clock State much faster than recovery earlier Intel486 processors.
Auto HALT Power Down State
Running mWatts
HALT asserted HALT cycle generated
Normal State
Normal Execution
INTR, NMI, SMI# RESET, SRESET STPCLK# asserted Stop Grant cycle generated
EADS# STPCLK# deasserted HALT cycle generated STPCLK# asserted Stop Grant cycle generated
STPCLK# deasserted
EADS#
Stop Grant State
Running mWatts
Stop Clock Snoop State
Clock PowerUp Perform Cache Invalidation
Stop
Start plus Startup Latency
Stop Clock State
Internal Powerdown Stopped µWatts
Figure Stop Clock State Diagram with Typical Power Consumption Values
Embedded Ultra-Low Power Intel486SX Processor
Level-Keeper Circuits
obtain lowest possible power consumption during Stop Grant Stop Clock states, system designers must ensure that: input signals with pull-up resistors driven input signals with pull-down resistors driven HIGH Table Input Pins (pg. list signals with internal pull-up pull-down resistors. other input pins except A31-A4 D31-D0 must driven power supply rails ensure lowest possible current consumption. During Stop Grant Stop Clock states, most processor output signals maintain their previous condition, which level they held when entering Stop Grant state. response HOLD driven active during Stop Grant state when input running, embedded Intel486 processor generates HLDA floats output input/output signals which floated during HOLD/HLDA state. When HOLD deasserted, processor signals which maintain their previous state return state they were prior HOLD/HLDA sequence. data (D31-D0) also maintains previous state during Stop Grant Stop Clock states, does differently, described following paragraphs. embedded Intel486 processor's data pins (D31-D0) have level keepers which maintain their previous states while Stop Grant Stop Clock states. response HOLD driven active during Stop Grant state when input running, embedded Intel486 processor generates HLDA floats D31-D0 throughout HOLD/HLDA cycles. When HOLD deasserted, processor's D31-D0 signals return states they were prior HOLD/HLDA sequence.
other times during Stop Grant Stop Clock states, processor maintains logic levels D31-D0. When external system circuitry drives D31-D0 different logic levels, processor flips D31-D0 logic levels match ones driven external system. processor maintains (keeps) these levels even after external circuitry stops driving D31-D0. some system designs, external resistors required D31- (they required previous Intel486 processor designs). System designs that never request Hold during Stop Grant Stop Clock states might require external resistors. system design uses Hold during these states, processor disables level-keepers floats data bus. This type design would require some kind data termination minimize power consumption. strongly recommended that D31-D0 pins have network resistors connected. External resistors used system design must sufficient resistance value "flip" level-keeper circuitry eliminate potential paths. level-keeper circuit designed allow external 27-K pull-up resistor switch D31-D0 circuits logic-HIGH level even though levelkeeper attempts keep logic-LOW level. general, pull-up resistors smaller than used well those greater than equal Pull-down resistors, when connected D31-D0, should least
Embedded Ultra-Low Power Intel486SX Processor
Low-Power Features
with other Intel486 processors, embedded Intel486 processor minimizes power consumption providing Auto HALT Power Down, Stop Grant, Stop Clock states (see Figure embedded Intel486 processor Auto Clock Freeze feature that further conserves power judiciously deactivating internal clocks while Normal Execution Mode. power-conserving mechanism designed such that does degrade processor performance require changes timing specifications. 4.4.1 Auto Clock Freeze
embedded Intel486 processor also reduces power consumption temporarily freezing clocks internal logic blocks. When logic block idle wait state, clock frozen.
CPUID Instruction
reduce power consumption, during following cycles under certain conditions processor slows-up freezes some internal clocks: Data-Read Wait Cycles (Memory, Interrupt Acknowledge) Data-Write Wait Cycles (Memory, I/O) HOLD/HLDA Cycles AHOLD Cycles BOFF Cycles Power conserved during wait periods these cycles until appropriate external-system signals sent processor. These signals include: READY NMI, SMI#, INTR, RESET BOFF# FLUSH# EADS# BS8#, BS16# KEN# transitions
embedded Intel486 processor supports CPUID instruction (see Table Because Intel processors support CPUID instruction, simple test determine instruction supported. test involves processor's Flag, which EFLAGS register. software change value this flag, CPUID instruction available. actual state Flag irrelevant provides significance hardware. This cleared (reset zero) upon device reset (RESET SRESET) compatibility with Intel486 processor designs that support CPUID instruction. CPUID-instruction details provided here embedded Intel486 processor. Refer Intel Application Note AP-485 Intel Processor Identification with CPUID Instruction (Order 241618) description that covers aspects CPUID instruction pertains other Intel processors. 4.5.1 Operation CPUID Instruction
CPUID instruction requires software developer pass input parameter processor register. processor response returned registers EAX, EBX, EDX, ECX.
Table CPUID Instruction Description CODE Instruction CPUID Processor Core Clocks Parameter passed
(Input Value)
Description Vendor (Intel) String Processor Identification Undefined Use)
Embedded Ultra-Low Power Intel486SX Processor
Vendor String When parameter passed (zero), register values returned upon instruction execution shown following table. 31-24 High Value 23-16 15-8
Vendor String (ASCII Characters)
(75) (49) (6C)
(6E) (65) (65)
(65) (6E) (74)
(47) (69) (6E)
values EBX, indicate Intel processor. When taken proper order, they decode string "GenuineIntel." Processor Identification When parameter passed (one), register values returned upon instruction execution are: 31-14 Processor Signature Use) Intel Reserved 13,12 Processor Type 11-8 0100 Family 0010 Model XXXX Stepping
(Intel releases information about stepping numbers needed) 31-0 Intel Reserved Use) Intel Reserved Intel Reserved 31-2 Feature Flags
Identification After Reset
31-14 Processor Signature Use) Intel Reserved 13,12 Processor Type 11-8 0100 Family 0010 Model XXXX Stepping
Processor Identification Upon reset, register contains processor signature:
(Intel releases information about stepping numbers needed)
Embedded Ultra-Low Power Intel486SX Processor
4.7.1
Boundary Scan (JTAG)
Device Identification
Table shows 32-bit code embedded Intel486 processor which loaded into Device Identification Register. Table Boundary Scan Component Identification Code Version
0=5V 1=3.3
Part Number Intel Architecture Type Family 0100 Intel486 Family Model 00010 embedded Intel486 processor 16-12 00010
009H Intel
31-28 XXXX
26-21 000001
20-17 0100
11-1 00000001001
(Intel releases information about version numbers needed) Boundary Scan Component Identification Code x828 2013 (Hex)
4.7.2
Boundary Scan Register Bits Order
following order embedded Intel486 processor boundary scan register: RESERVED#, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, Reserved, Reserved, D10, D11, D12, D13, D14, D15, Reserved, D16, D17, D18, D19, D20, D21, D22, D23, Reserved, D24, D25, D26, D27, D28, D29, D30, D31, STPCLK#, Reserved, Reserved, SMI#, SMIACT#, SRESET, NMI, INTR, FLUSH#, RESET, A20M#, EADS#, PCD, PWT, D/C#, M/IO#, BE3#, BE2#, BE1#, BE0#, BREQ, W/R#, HLDA, CLK, Reserved, AHOLD, HOLD, KEN#, RDY#, BS8#, BS16#, BOFF#, BRDY#, Reserved, LOCK#, PLOCK#, BLAST#, ADS#, MISCCTL, BUSCTL, ABUSCTL, WRCTL
boundary scan register contains cell each well cells control bidirectional three-state pins. There "Reserved" bits which correspond no-connect (N/C) signals embedded Intel486 processor. Control registers WRCTL, ABUSCTL, BUSCTL, MISCCTL used select direction bidirectional three-state output signal pins. these cells designates that associated bits floated pins three-state, selected input they bidirectional. WRCTL controls D31-D0 ABUSCTL controls A31-A2 BUSCTL controls ADS#, BLAST#, PLOCK#, LOCK#, W/R#, BE0#, BE1#, BE2#, BE3#, M/IO#, D/C#, PWT, MISCCTL controls HLDA, BREQ
Embedded Ultra-Low Power Intel486SX Processor
ELECTRICAL SPECIFICATIONS Maximum Ratings
Table Absolute Maximum Ratings Case Temperature under Bias Storage Temperature +110 +150 -0.5 VCCP -0.5 +4.6 -0.5 +4.6
Table stress rating only. Extended exposure Maximum Ratings affect device reliability. Furthermore, although embedded Intel486 processor contains protective circuitry resist damage from electrostatic discharge, always take precautions avoid high static voltages electric fields. Functional operating conditions given Section 5.2, Specifications Section 5.3, Specifications.
Voltage with Respect Ground Supply Voltage with Respect Supply Voltage VCCP with Respect
Specifications
following tables show operating supply voltages, specifications, component power consumption embedded Intel486 processor.
Table Operating Supply Voltages Product VCCP Range1 Max. Frequency x80486SXSF-33 Range2
NOTES: cases, VCCP must VCC. voltage within Range. setting determines allowed Fluctuation address fact that many package prefix variables have changed, package prefix variables this document indicated with "x".
Fluctuation
±0.2 +0.3 V/-0.2 ±0.3
Embedded Ultra-Low Power Intel486SX Processor
Table Specifications TCASE=0 Symbol VIHC Parameter Input Voltage Input HIGH Voltage Input HIGH Voltage Output Voltage Output HIGH Voltage -2.0 -100 COUT CCLK Input Leakage Current Input Leakage Current Input Leakage Current Output Leakage Current Input Capacitance Output Capacitance Capacitance VCCP -0.2 Note Note Note Note Note Note Min. -0.3 -0.6 Max. +0.8 VCCP +0.3 VCCP +0.3 Unit Note Notes
NOTES: inputs except CLK. This parameter inputs without pull-up pull-down resistors VCCP. This parameter inputs with pull-down resistors 2.4V, level-keeper pins V=0.4V. This parameter inputs with pull-up resistors 0.4V, level-keeper pins V=2.4V. FC=1 MHz. 100% tested.
Embedded Ultra-Low Power Intel486SX Processor
Table Active Values TCASE=0 Symbol ICC1 Parameter Active (VCC pins) Frequency Supply Voltage ICC2 Active (VCCP pins) VCCP VCCP Typical Max. Notes
NOTES: These parameters
Table Clock Stop, Stop Grant, Auto HALT Power Down Values TCASE= Symbol ICCS0 Parameter Stop Clock (VCC pins) Frequency Supply Voltage ICCS2 ICCS1 Stop Clock (VCCP pins) Stop Grant, Auto HALT Power Down (VCC pins) ICCS3 Stop Grant, Auto HALT Power Down (VCCP pins) VCCP VCCP VCCP Typical Max. Notes Note
NOTES: Stop Clock specification refers value once processor enters Stop Clock state. input signals, levels must equal VCCP respectively, meet Stop Clock specifications.
Embedded Ultra-Low Power Intel486SX Processor
Specifications
specifications embedded Intel486 processor given this section. Table Characteristics (Sheet valid over operating supply voltages listed Table Operating Supply Voltages (pg. 22). TCASE= Symbol Parameter Frequency Period Period Stability High Time Time Fall Time Rise Time A2-A31, PWT, PCD, BE0#BE3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA, SMIACT# Valid Delay A2-A31, PWT, PCD, BE0#BE3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, Float Delay BLAST#, PLOCK# Valid Delay BLAST#, PLOCK# Float Delay D0-D31 Write Delay D0-D31 Float Delay EADS# Setup Time EADS# Hold Time BS16#, BS8#, KEN# Setup Time BS16#, BS8#, KEN# Hold Time RDY#, BRDY# Setup Time RDY#, BRDY# Hold Time HOLD, AHOLD Setup Time BOFF# Setup Time 2.4V 2.7V 2.7V 3.3V Unit ps/CLK Notes Note Note Note 0.8V 0.8V Note 0.8V Note
Note
t18a
Note Note
Embedded Ultra-Low Power Intel486SX Processor
Table Characteristics (Sheet valid over operating supply voltages listed Table Operating Supply Voltages (pg. 22). TCASE= Symbol Parameter HOLD, AHOLD, BOFF# Hold Time FLUSH#, A20M#, NMI, INTR, SMI#, STPCLK#, SRESET, RESET Setup Time FLUSH#, A20M#, NMI, INTR, SMI#, STPCLK#, SRESET, RESET Hold Time D0-D31, A4-A31 Read Setup Time D0-D31, A4-A31 Read Hold Time 2.4V 2.7V 2.7V 3.3V Unit Notes
NOTES:
operation tested guaranteed STPCLK# Stop Grant cycle protocol. operation confirmed design characterization, 100% tested production. Specification applicable only when frequency changed without STPCLK# STOP GRANT cycle protocol. 100% tested, guaranteed design characterization. reference voltage timing measurement except through Other signals measured
Embedded Ultra-Low Power Intel486SX Processor
Table Specifications Test Access Port Symbol Parameter Frequency Period High Time Time Rise Time Fall Time TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Outputs (except TDO) Valid Delay Outputs (except TDO) Float Delay Inputs (except TDI, TMS, TCK) Setup Time Inputs (except TDI, TMS, TCK) Hold Time Unit Figure Note 2.0V @0.8V Note Note Note Note Note Notes Note Notes Note Note Notes
NOTES: period period. Rise/Fall Times measured between Rise/Fall times relaxed increase period. Parameter measured from TCK. 100% tested, guaranteed design characterization.
Embedded Ultra-Low Power Intel486SX Processor
input setup times input hold times, output float, valid hold times Figure Waveform
EADS#
BS8#, BS16#, KEN#
BOFF#, AHOLD, HOLD
RESET, FLUSH#, A20M#, INTR, NMI, SMI#, STPCLK#, SRESET A4-A31 (READ)
Figure Input Setup Hold Timing
Embedded Ultra-Low Power Intel486SX Processor
RDY#, BRDY#
D0-D31
Figure Input Setup Hold Timing
A2-A31, PWT, PCD, BE0-3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA, SMIACT#
VALID
VALID
D0-D31
VALID
VALID
BLAST#, PLOCK#
VALID
VALID
Figure Output Valid Delay Timing
Embedded Ultra-Low Power Intel486SX Processor
A2-A31, PWT, PCD, BE0-3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ
VALID
D31-D0
VALID
BLAST#, PLOCK#
VALID
Figure Maximum Float Delay Timing
Figure Waveform
Embedded Ultra-Low Power Intel486SX Processor
OUTPUT INPUT VALID VALID VALID VALID VALID
Figure Test Signal Timing Diagram
Embedded Ultra-Low Power Intel486SX Processor
Capacitive Derating Curves
following graphs capacitive derating curves embedded Intel486 processor. nom+7 nom+6 nom+5 Delay (ns) nom+4 nom+3 nom+2 nom+1 nom-1 nom-2 Capacitive Load (pF) NOTE: This graph will linear outside capacitive range shown. nominal value from Characteristics table. Figure Typical Loading Delay versus Load Capacitance under Worst-Case Conditions Low-toHigh Transition
nom+5 Delay (ns) nom+4 nom+3 nom+2 nom+1 nom-1 nom-2 Capacitive Load (pF)
NOTE: This graph will linear outside capacitive range shown. nominal value from Characteristics table. Figure Typical Loading Delay versus Load Capacitance under Worst-Case Conditions Highto-Low Transition
Embedded Ultra-Low Power Intel486SX Processor
MECHANICAL DATA
This section describes packaging dimensions thermal specifications embedded Intel486 processor.
Package Dimensions
26.0 0.40 24.0 0.10
0.10 0.10
0.60 0.20
0.50 0.10
1.50 0.20
0.16 o.28
0.10 0.10
NOTES: Height measurements same width measurements Units:
A4586-01
Figure Package Mechanical Specifications 176-Lead TQFP Package
Embedded Ultra-Low Power Intel486SX Processor
Package Thermal Specifications
embedded Intel486 processor specified operation when case temperature (TC) within range 85°C. measured environment determine whether processor within specified operating range. ambient temperature (TA) calculated from from following equations:
Where equals Junction, Ambient Case Temperature respectively. equals Junction-to-Case Junction-to-Ambient thermal Resistance, respectively. Maximum Power Consumption defined where: (typ) (max) [VCC (typ) ICC1 (max)] [VCCP (typ) ICC2(max)] ICC1 supply current ICC2 VCCP supply current Values given following tables each product maximum operating frequencies.
Table Thermal Resistance (°C/W) 176-Lead TQFP Package (°C/W) (°C/W) with airflow 33.6
following table shows maximum ambient temperatures embedded Intel486 processor each product maximum operating frequencies. These temperatures calculated using ICC1 ICC2 values measured during component-validation testing using VCCP=3.6 worst-case values.
Table Maximum Ambient Temperature (TA) 176-Lead TQFP Package Frequency (°C) with airflow

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