General Description NIS6111 Simplified Block Diagram NIS6111 simp

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AND8174/D NIS6111 Better ORing Diode Operation Notes
General Description NIS6111 Simplified Block Diagram
NIS6111 simple reliable device consisting integrated control with RDS(on) power MOSFET, using hybrid technology. designed replace Schottky diodes ORing applications obtain higher system power efficiency. connected allow load sharing with automatic switchover load between more input power supplies. single NIS6111 able without flow. meet high current requirement i.e. NIS6111 designed drive more than four paralleled additional NTD110N02 MOSFETs. unique package design NIS6111 offers higher thermal efficiency minimize cooling requirements. This application note presents more details demonstration boards. Both them easily connected power sources loads test purpose.
Applications
Paralleled Redundant Power Supplies Telecommunications Power Systems High-Reliability, Distributed Power Networks
Reg_in (Pin Input internal voltage regulator. Bias (Pin Output internal voltage regulator. under normal operating conditions. provides power internal components only. external connections necessary this pin. Gate (Pin Gate driver output internal external N-Channel MOSFET. gate turn time typically Source (Pin Power input, connected system power source output. This anode rectifier. Drain (Pin Power output, connected system load. This cathode rectifier will common cathodes other rectifiers, when used high side configuration. UVLO Function: UVLO trip point 3.85 rising 3.65 falling bias supply. Before bias voltage reaches 3.85 UVLO logic "1", which disables gate driver. gate voltage remains zero; soon bias voltage reaches 3.85 more, UVLO changes logic "0", enables gate driver. gate voltage will then switch device forward biased (see Figure
V_reg_in
V_cap
V_gate
Drain
Voltage Regulator UVLO NTD011N02 MOSFET
Source
Figure
Semiconductor Components Industries, LLC, 2004
August, 2004 Rev.
Publication Order Number: AND8174/D
AND8174/D
V_reg_in Typically
UVLO "1'' "0'' V_gate 3.65 3.85 V_cap
Figure NIS6111 Basic Operating Circuit Sequence
disable UVLO circuit, V_reg_in higher than source more than
V_reg_in V_reg_in Source V_cap Drain V_gate
Timing Sequence: recommended that V_reg_in energized before device turned that control circuit quickly respond correct polarity gate drive signal. also possible bring V_reg_in simultaneously. this case will until UVLO reaches threshold. Under this condition, body diode will conduct normal rectifier would. V_reg_in voltage comes after supply, body diode will conduct forward biased. This will damage device long long power dissipation does cause maximum junction temperature NIS6111 exceeded. Under conditions should V_reg_in more negative than source (anode) this device. that situation occur, signal diode should connected series with V_reg_in pin. Table number external MOSFETs based flow heat sink. test data from demonstration board. system applications, required number external MOSFET decreased flow system external heat sink.
Table Recommended Selection External MOSFETs Based Load Currents
Under Flow Heat Sink Condition Recommended Selection Single NIS6111 Load Current Rating
NIS6111
Output Load
NIS110N02 (Optional)
NIS6111 NTD110N02 NIS6111 NTD110N02 NIS6111 Three NTD110N02
Figure Basic Operation Circuit
NIS6111 Four NTD110N02
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AND8174/D
TEST CIRCUIT
V_reg_in Vin_1 Reg_in Source V_cap Drain Gate Jump_1
NIS6111
NTD110N02 Vin_2 Reg_in
Jump_2
Output Load
Source V_cap
Drain Gate
NIS6111
NTD110N02
Figure Test Circuit
Basic Test Circuit
test circuit Figure test peak reverse current recovery time multiple power source operation. With Vin_2 Vin_1, load current will flow through paralleled MOSFETs. After switching (Shut Vin_2), paralleled MOSFETs will take over power transfer path, current will through them instead paralleled MOSFETs. Meanwhile, since Vin_2 (after shutting Vin_2) small amount reverse current will forced through
MOSFETs which will terminate conduction this switch. Since NIS6111 does have reverse applied voltage protection (such when voltage higher than Vreg_in's), needed diode (e.g. 1N4148) serial with Pin5 (Reg_in). Also, since system noises, snubber circuit between Pin1 (Source) Pin4 (Drain) strongly recommended, avoid gate signal ringing. details seen schematics demo boards follows.
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V_reg_in_1
1N4148 +C11 Source V_cap
DEMONSTRATION BOARD
Reg_in Drain Gate
Vin_1
+C12
NIS6111 1N4148
BAS16LT1
BAS16LT1 BAS16LT1 PWRGND COMP PWRGND VREG SIGGND DRIVE PWRGND NIS6201
NTD110N02 Vin_2 V_reg_in_2
Figure Demonstration Board Schematic
Source V_cap
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Reg_in Drain Gate
AND8174/D
+C24
NIS6111
mF/50 Charge Pump Circuit (Optional)
BAS16LT1 BAS16LT1 PWRGND COMP PWRGND VREG SIGGND DRIVE PWRGND NIS6201 BAS16LT1
NTD110N02
Charge Pump Circuit (Optional)
mF/50
AND8174/D
DEMONSTRATION BOARD (continued)
NOTE: selection input output capacitors vary, based layout maximum load applications.
Figure
Figure Layout
Figure Bottom Layout
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AND8174/D
DEMONSTRATION BOARD (continued)
Table Figure present current sharing data different load conditions.
CURRENT RATING Table Current Sharing Test Results
Current Sharing Rating Load Current NIS6111 10.5 NTD110N02
NTD110N02 NIS6111
LOAD CURRENT Figure Current Sharing Load Current
Table Thermal Test Results
Under Flow Heat Sink Condition Thermal Data Load Current NIS6111 Temp (5C) NTD112N02 Temp (5C)
Reverse Current Recovery Time Test Results
Figure shows waveforms typical load condition reverse current recovery time Figure slope (di/dt) waveform (Ch3) function parasitic inductance capacitance system. With increasing current path length component spaces PCB, decreasing slope (di/dt).
Ch1: Gate Voltage NIS6111 V/DIV) Ch2: Output Voltage V/DIV) Ch3: Current Through NIS6111 (5.0 A/DIV)
Figure
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V_reg_in_1 JUMPER JUMPER NTD110N02 1N4148 Vin_2 JUMPER C101 C102 C103 C104 C105 R101 JUMPER D104 M101
1N4148
Vin_1 Source V_cap Drain Gate NIS6111 Reg_in
+C22
JUMPER
DEMONSTRATION BOARD
V_reg_in_2
NTD110N02 NTD110N02 +C120 C106 C107 C108 NTD110N02 JUMPER C117 IC101
BAS16LT1 BAS16LT1 NIS6201 PWRGND
BAS16LT1 SIGGND
COMP PWRGND
JUMPER JUMPER L101 L106 Reg_in Drain Gate +C121 C114 C115 C116
DRIVE PWRGND
Source V_cap
NIS6111 R105 C118
C109 C110
C111 C112 C113 NTD110N02 R102 JUMPER L103 JUMPER L102
AND8174/D
Figure Demonstration Board Schematic
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C125 D102 BAS16LT1 D103 BAS16LT1 BAS16LT1 IC101 NIS6201 PWRGND COMP PWRGND SIGGND DRIVE PWRGND R106 R107 C124 mF/50 Charge Pump Circuit (Optional) M104 M103 M102 C119
mF/50
Charge Pump Circuit (Optional)
NTD110N02 R103 NTD110N02 R104 NTD110N02 JUMPER L105 JUMPER L104
AND8174/D
DEMONSTRATION BOARD (continued)
Figure
Figure Layout
Figure Bottom Layout
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AND8174/D
DEMONSTRATION BOARD (continued)
Table Figure present current sharing data different load conditions.
Table Current Sharing Test Results
Current Sharing Ratings NIS6111 12.4 13.5 M101 10.8 M102 10.6 11.5 12.5 M103
CURRENT RATING NIS6111 NTD110N02 (M103) NTD110N02 (M104) NTD110N02 (M101) NTD110N02 (M102)
LOAD CURRENT Figure Current Sharing Load Currents
Table Thermal Test Results
Under Flow Heat Sink Condition Load Current Rating Thermal Rating Typical
Reverse Current Recovery Time Test Results
Figure presents waveforms typical load condition (1.0 reverse current recovery time
Conclusion
Devices Single NIS6111 NIS6111 NTD110N02 NIS6111 NTD110N02 NIS6111 Three NTD110N02 NIS6111 Four NTD110N02
application note describes NIS6111 device operation details demonstration boards.
Ch1: Gate Voltage NIS6111 V/DIV) Ch2: Output Voltage V/DIV) Ch3: Output Current (5.0 A/DIV)
Figure
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AND8174/D
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AND8174/D

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