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4519G-C3
Preliminary Data Sheet Supplement
Subject: Data Sheet Concerned: Supplement: Edition:
Version Change 4519G 6251-512-1PD, Edition Oct. 2000 6251-512-1PDS June 2002
Changes from 4519G Version A1/B2 4519G Version Release Note: Revision bars indicate significant changes information given data sheet. section, table, figure numbers refer data sheet concerned. 4519G-C3 hardware software compatible 4519G-A1/B2.
Functional Description 2.1. Architecture 4519G Family Fig. shows simplified block diagram
Micronas
page
I2S_CL I2S_WS I2S_DA_IN2
Prescale
(16hex)
Source Select
I2S_3 Resorting Matrix
Internal/External Switch
(4Chex)
SC1_IN_L SC1_IN_R SC2_IN_L SC2_IN_R SC3_IN_L SC3_IN_R SC4_IN_L SC4_IN_R MONO_IN
SCART Output Select
page
I2S_DA_IN1 I2S_DA_IN3 I2S_DA_IN4 I2S_CL3 I2S_WS3
4519G-C3
Main Channel Matrix (sync. kHz) Interface I2S1
(08hex)
(01hex)
Bass/ Treble/ Loudness/ Equalizer
(02/03/04hex) (20.25hex)
Volume Balance Acoustical Compens.
(26/27/28hex)
DACM_L DACM_R
(14hex)
Subwoofer Level
(2Chex) (00hex)
DACM_SUB
Beeper Bass/ Treble/ Loudness/ Equalizer
(31/32/33hex)
Interface
I2S2
Prescale
(12hex)
Channel Matrix
(09hex)
Volume Balance
(30hex)
Acoustical Compens.
(06hex) (38/39/3Ahex)
DACA_L
DACA_R
(Subaddress Register 40hex)
Interface (async. 8-48 kHz) I2S3 synchronization
(11hex) (36hex) (36hex)
Channel Matrix
(0Bhex)
Interface
I2S_DA_OUT (sync. kHz)
June 2002; 6251-512-1PDS
Prescale
(29hex)
Quasi-Peak Channel Matrix
(0Chex)
Quasi-Peak Detector
Read Register
(19hex)(1Ahex)
Bass Management
(4Ehex)
SCART1 Channel Matrix
(0Ahex)
Volume
SCART1_L/R
PRELIMINARY DATA SHEET SUPPLEMENT
Noise Generator
Surround Processing
(07hex)
(4Dhex)
(49hex) (4Ahex) (4Bhex)
Surround Channel Matrix
(48hex)
SC1_OUT_L
SC1_OUT_R
SC2_OUT_L
Micronas
SC2_OUT_R
Fig. 2-1: Signal flow block diagram 4519G (input output names correspond names)
PRELIMINARY DATA SHEET SUPPLEMENT
4519G-C3
Control Interface 3.3. 4519G Programming Interface 3.3.1. User Registers Overview Note: Unused parts 16-bit write registers must zero.
Table 3-5: List 4519G Write Registers
Write Register Address (hex) Bits Description Adjustable Range Reset Page1)
Subaddress 10hex Registers readable MODUS CONFIGURATION
[15:0] [15:0]
options, D_CTR_I/O modes Configuration format
Subaddress 12hex Registers readable using Subaddress 13hex Volume Main channel Volume Mode Main channel Balance Main channel [L/R] Balance mode Main Bass Main channel Treble Main channel Loudness Main channel Loudness filter characteristic Volume channel Volume Mode channel Volume SCART1 output channel Main source select Main channel matrix source select channel matrix SCART1 source select SCART1 channel matrix source select channel matrix Quasi-peak detector source select Quasi-peak detector matrix Prescale Prescale I2S2 ACB: SCART Switches D_CTR_I/O Beeper Prescale I2S1
[15:8] [7:0]
[+12 -114 MUTE] Steps, Reduce Volume Tone Control Compromise Dynamic [0.100 100% 0.100%] [-127.0 -127.0 [Linear logarithmic mode] [+20 [+15 [NORMAL, SUPER_BASS] [+12 -114 MUTE] Steps, Reduce Volume Tone Control Compromise Dynamic [+12 -114 MUTE]
2S1, I2S2, I2S3
MUTE 00hex 100%/100% linear mode NORMAL MUTE 00hex MUTE ch3&4,.] undefined SOUNDA undefined SOUNDA undefined SOUNDA undefined SOUNDA FM/AM SOUNDA 10hex 10hex 00hex 00/00hex 10hex
[15:8] [7:0]
[15:8] [15:8] [15:8] [7:0]
[15:8] [7:0]
[15:8] [15:8] [7:0]
ch1&2,
I2S3
[SOUNDA, SOUNDB, STEREO, MONO] ch1&2, ch3&4,.] [SOUNDA, SOUNDB, STEREO, MONO] [I2S1, I2S2, I2S3 ch1&2, I2S3 ch3&4,.] [SOUNDA, SOUNDB, STEREO, MONO] [I2S1, I2S2, I2S3 ch1&2, I2S3 ch3&4,.] [SOUNDA, SOUNDB, STEREO, MONO] [FM/AM, NICAM, SCART,
2S1, I2S2]
[15:8] [7:0]
[15:8] [7:0]
[15:8] [7:0]
[15:8] [7:0]
[SOUNDA, SOUNDB, STEREO, MONO.] [00hex 7Fhex] [00hex 7Fhex] Bits [15:0] [00hex 7Fhex]/[00hex 7Fhex] [00hex 7Fhex]
[15:8] [15:8] [15:0] [15:0] [15:8]
Single-digit page numbers refer this supplement, double-digit page numbers data sheet concerned.
Micronas
June 2002; 6251-512-1PDS
page
4519G-C3
Table 3-5: List 4519G Write Registers, continued
Write Register Mode tone control Equalizer Main band Equalizer Main band Equalizer Main band Equalizer Main band Equalizer Main band Acoustical Compensation Main channel Acoustical Compensation Main channel Acoustical Compensation Main channel Automatic Volume Correction Surround Processing Subwoofer level adjust Balance channel [L/R] Balance mode Bass channel Treble channel Loudness channel Loudness filter characteristic Resorting Acoustical Compensation channel Acoustical Compensation channel Acoustical Compensation channel Surround source select Surround channel matrix Spatial effect surround processing Virtual surround effect strength Decoder matrix Surround reproduction Center mode Surround delay Surround Noise Generator Surround Bass Crossover Frequency Subwoofer characteristics Subwoofer complementary high-pass
PRELIMINARY DATA SHEET SUPPLEMENT
Address (hex)
Bits [15:8] [15:8] [15:8] [15:8] [15:8] [15:8] [15:0] [15:0] [15:0] [15:8] [7:0]
Description Adjustable Range [BASS/TREBLE, EQUALIZER, EQUALIZER CHANNELS] [+12 [+12 [+12 [+12 [+12 C0_Main C1_Main C2_Main [off, decay time] [level; attenuation; gain] [+12 mute] [0.100 100% 0.100%] [-127.0 -127.0 [Linear mode logarithmic mode] [+20 [+15 [NORMAL, SUPER_BASS] through, straight eight, eight, six, four, through C0_Aux C1_Aux C2_Aux
2S1, I2S2, I2S3
Reset BASS/TREB -18; 100% 100% linear mode NORMAL 00hex
Page1)
[15:8] [15:8] [7:0]
[15:8] [15:8] [15:8] [7:0]
[15:8] [15:0] [15:0] [15:0] [15:8] [7:0]
ch1&2,
I2S3
ch3&4,.]
undefined SOUNDA 00hex 00hex 00hex 0hex 0hex 00hex 00hex 00hex
[SOUNDA, SOUNDB, STEREO, MONO] 100%] 100%] [ADAPTIVE/PASSIVE/EFFECT] 3D_PANORAMA] [PHANTOM/NORMAL/WIDE/OFF] [5.31 [NOISEL, NOISEC, NOISER, NOISES] [SHARP/MEDIUM/SOFT/VERY SOFT EDGE] [off,
[15:8] [15:8] [15:8] [7:4] [3:0]
[15:0] [15:0] [15:8] [7:4] [3:0]
Single-digit page numbers refer this supplement, double-digit page numbers data sheet concerned.
page
June 2002; 6251-512-1PDS
Micronas
PRELIMINARY DATA SHEET SUPPLEMENT
4519G-C3
3.3.2. Description User Registers 3.3.2.1. Write Registers Subaddress 10hex Table 3-7: Write Registers Subaddress 10hex Register Address MODUS 30hex MODUS Register bit[15:8] bit[7] bit[6] bit[5] bit[4] bit[3] bit[2] bit[1:0] undefined, must active/tristate state audio clock output AUD_CL_OUT word strobe alignment (synchronous I2S) changes data word boundary changes clock cycle advance master/slave mode interface active/tristate state output pins state digital output pins D_CTR_I/O_0 active: D_CTR_I/O_0 output pins (can means register) tristate: D_CTR_I/O_0 input pins (level read STATUS[4,3]) word strobe polarity right, high left high right, low= left undefined, must MODUS Function Name
Micronas
June 2002; 6251-512-1PDS
page
4519G-C3
Table 3-7: Write Registers Subaddress 10hex, continued Register Address Function
PRELIMINARY DATA SHEET SUPPLEMENT
Name
CONFIGURATION 40hex CONFIGURATION Register I2S31) bit[11] bit[10] data alignment (must bit[2] left/right aligned wordstrobe polarity (asynchronous I2S3) right, high= left high right, low= left wordstrobe alignment (asynchronous I2S3) changes data word boundary changes clock cycle advance bit[2] bit[6] MODUS Register same value) Sample Mode Two/Multi sample Word length each data packet (n-2)/2 bit[3]=0, bit[8]=1 (multi-sample input mode) 0111 1000 1111 bit[3]=0, bit[8]=0 (two-sample input mode) xxxx 16.32 bit, 18-bit valid bit[3]=1, bit[8]=1 (multi-sample output mode) 1111 bit[3]=1, bit[8]=0 (two-sample output mode) 0111 1111 bit[3] I2S3CL/WS Mode output (I2S3 CL/WS active) input (I2S3 CL/WS tristate) I2S3_MODE I2S3_ALIGN I2S3_WS_POL I2S_CONFIG
bit[9]
I2S3_WS_MODE
bit[8] bit[7:4]
I2S3_MSAMP I2S3_MBIT
I2S1/2/3/4 bit[2] I2S1/2/3/4 Timing I2S3 timing inputs (1/2/3/4) default mode I2S_TIMING
bit[1:0] I2S_CL frequency I2S_DA_OUT sample length (1.536 Clk) (3.072 Clk) (12.288 Clk)
I2S_CL3 frequency depends bit[8] bits[7:4] follows: [7:4] 0111 fs*(2*16) [7:4] else fs*(2*32) fs*(8*32)
page
June 2002; 6251-512-1PDS
Micronas
PRELIMINARY DATA SHEET SUPPLEMENT
4519G-C3
3.3.2.3. Write Registers Subaddress 12hex Table 3-9: Write Registers Subaddress 12hex Register Address Function Name
SOURCE SELECT OUTPUT CHANNEL MATRIX 08hex 09hex 0Ahex 0Bhex 0Chex 48hex Source for: Main Output Output SCART1 Output Output Quasi-Peak Detector Surround Processing bit[15:8] 05hex 06hex 07hex 08hex 09hex 0Ahex 0Chex 0Dhex 08hex 09hex 0Ahex 0Bhex 0Chex 48hex I2S1 input I2S2 input I2S3 input channels (e.g. Rt)1) I2S3 input channels (e.g. R)1) Logic processed I2S3 input channels (e.g. SR)1)or Logic processed (both channels same signal) I2S3 input channels (e.g. SUB)1)or Logic processed Main channel: baseband processed signal with volume channel: baseband processed signal with volume MAT_MAIN MAT_AUX MAT_SCART1 MAT_I2S MAT_QPEAK MAT_DPL SRC_MAIN SRC_AUX SRC_SCART1 SRC_I2S SRC_QPEAK SRC_DPL
Channel Matrix for: Main Output Output SCART1 Output Output Quasi-Peak Detector Surround Processing bit[7:0] 00hex 10hex 20hex 30hex Sound Mono Left Mono) Sound Mono Right Mono) Stereo (transparent mode) Mono (L+R)/2
Usually matrix modes should "Stereo" (transparent).
Exemplary channel assignment Micronas digital multichannel sound system with 3528E 44x0G.
Micronas
June 2002; 6251-512-1PDS
page
4519G-C3
Table 3-9: Write Registers Subaddress 12hex, continued Register Address Function
PRELIMINARY DATA SHEET SUPPLEMENT
Name
MAIN PROCESSING 00hex 06hex Volume Main Volume bit[15:8] volume table with step size 7Fhex (maximum volume) 7Ehex 74hex 73hex 72hex 02hex -113 01hex -114 00hex Mute (reset condition) FFhex Fast Mute (needs about until signal completely ramped down) higher resolution volume table +0.125 increase addition volume table +0.875 increase addition volume table must VOL_MAIN VOL_AUX
bit[7:5]
bit[4] bit[3:0]
clipping mode reduce volume reduce tone control compromise dynamic
With large scale input signals, positive volume settings lead signal clipping. 4519G loudspeaker headphone volume function divided into digital analog section. With Fast Mute, volume reduced mute position digital volume only. Analog volume changed. This reduces audible plops. turn volume again, volume step that been used before Fast Mute activated must transmitted. clipping mode "reduce volume", following rule used: prevent severe clipping effects with bass, treble, equalizer boosts, internal volume automatically limited level where, combination with either bass, treble, equalizer setting, amplification does exceed clipping mode "reduce tone control", bass treble value reduced amplification exceeds equalizer switched gain those bands reduced, where amplification together with volume exceeds clipping mode "compromise", bass treble value volume reduced half half amplification exceeds equalizer switched gain those bands reduced half half, where amplification together with volume exceeds clipping mode "dynamic", volume reduced automatically signal amplitudes would exceed dBFS within
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June 2002; 6251-512-1PDS
Micronas
PRELIMINARY DATA SHEET SUPPLEMENT
4519G-C3
Table 3-9: Write Registers Subaddress 12hex, continued Register Address 29hex Function Automatic Volume Correction (AVC) Surround Processing bit[15:12] 0hex 8hex bit[11:8] (and reset internal variables) AVC_DECAY Name
decay time 8hex decay time 4hex decay time 2hex decay time 1hex decay time (should used approx. after channel change) output level 0hex dBFS 1hex dBFS Fhex dBFS maximum attenuation 0hex 1hex 2hex maximum gain 0hex 1hex 3hex
bit[7:4]
AVC_LEVEL
bit[3:2]
AVC_MIN
bit[1:0]
AVC_MAX
Micronas
June 2002; 6251-512-1PDS
page
4519G-C3
Table 3-9: Write Registers Subaddress 12hex, continued Register Address 20hex Function Tone Control Mode Main Channel/Aux Channel bit[15:8] 00hex FFhex 80hex
PRELIMINARY DATA SHEET SUPPLEMENT
Name TONE_MODE
bass treble active Main channel) equalizer active Main channel) equalizer active Main channel
Defines whether Bass/Treble Equalizer activated Main channel channel. Bass Equalizer cannot work simultaneously. Equalizer used, Bass Treble coefficients must zero vice versa.
equalizer active Main channel, clipping mode both channels must same (see registers 00hex 06hex). ACF_M0 ACF_M1 ACF_M2
26hex 27hex 28hex 38hex 39hex 3Ahex
Acoustical Compensation Filter Main Channel: C0_Main C1_Main C2_Main Acoustical Compensation Filter Channel: C0_Aux C1_Aux C2_Aux These cells determine coefficients second order filter acoustical compensation loudspeaker responses. transfer function this filter
ACF_A0 ACF_A1 ACF_A2
transfer function must have more than gain. Micronas will supply design tool these coefficients. This feature switched setting coefficients zero (reset state). mute fastmute operation should precede change these coefficients. coefficients two's complement numbers ranging from [-1.0.1.0 2-9]. bit[15:6] bit[5:3] bit[2:0] 10-bit coefficient LSBs coefficient (together with this forms 9-bit coefficient LSBs coefficient (together with this forms 9-bit coefficient
bit[15:6] bit[5:0] bit[15:6] bit[5:0] 10-bit coefficient MSBs coefficient 10-bit coefficient MSBs coefficient
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June 2002; 6251-512-1PDS
Micronas
PRELIMINARY DATA SHEET SUPPLEMENT
4519G-C3
Table 3-9: Write Registers Subaddress 12hex, continued Register Address Function Name
SUBWOOFER OUTPUT CHANNEL 2Chex Subwoofer Level Adjustment bit[15:8] 0Chex 01hex 00hex FFhex E3hex E2hex 80hex 00hex (default) Mute must zero SUR_BASS SUBW_LEVEL
bit[7:0] 4Ehex
Surround Bass Crossover Frequency bit[15:8] 5.40 corner frequency steps (range: 50.400
Subwoofer Characteristics bit[7:4] 0hex 1hex 2hex 3hex sharp edge (default) medium edge soft edge very soft edge
SUBW_CHAR
Four different filter sets selected. complementary filter design, output high- lowpass filter crossover region filter sets. Subwoofer Complementary High-Pass Filter bit[3:0] 0hex 1hex loudspeaker channel unfiltered complementary high-pass processed loudspeaker output channel SUBW_HP
Bass Management within Surround Processing Block
compl. ON/OFF
Phantom Normal
-3.0
Wide
-4.5
100Hz
50.400Hz
Micronas
June 2002; 6251-512-1PDS
page
4519G-C3
3.3.2.4. Read Registers Subaddress 13hex Table 3-10: Read Registers Subaddress 13hex Register Address Function
PRELIMINARY DATA SHEET SUPPLEMENT
Name
QUASI-PEAK DETECTOR READOUT 19hex 1Ahex Quasi-Peak Detector Readout Left Quasi-Peak Detector Readout Right bit[15:0] 0hex. 7FFFhex values two's complement (only positive) QPEAK_L QPEAK_R
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June 2002; 6251-512-1PDS
Micronas
PRELIMINARY DATA SHEET SUPPLEMENT
4519G-C3
Specifications 4.4. Configurations
SC2_IN_L SC2_IN_R SC1_IN_L SC1_IN_R VREFTOP MONO_IN AVSS AVSS
SC3_IN_R SC3_IN_L SC4_IN_R SC4_IN_L AGNDC AHVSS AHVSS
AVSUP AVSUP ANA_IN1+ ANA_IN- ANA_IN2+ TESTEN XTAL_IN XTAL_OUT AUD_CL_OUT D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ
CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R DACM_SUB DACM_L DACM_R VREF2 DACA_L
4519G
I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSUP I2S_DA_IN2 DVSS DVSS DVSS DVSUP
DACA_R I2S_DA_IN4 I2S_DA_IN3 RESETQ I2S_WS3 I2S_CL3
Fig. 4-4: PQFP80 package
Micronas
June 2002; 6251-512-1PDS
page
4519G-C3
PRELIMINARY DATA SHEET SUPPLEMENT
SC2_IN_L SC2_IN_R SC1_IN_L SC1_IN_R VREFTOP MONO_IN AVSS
SC3_IN_R SC3_IN_L SC4_IN_R SC4_IN_L AGNDC AHVSS
AVSUP ANA_IN1+ ANA_IN- ANA_IN2+ TESTEN XTAL_IN XTAL_OUT AUD_CL_OUT D_CTR_I/O_1 C_CTR_I/O_0 ADR_SEL STANDBYQ I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 I2S_DA_IN3 I2S_DA_IN4 I2S_DA_IN2 DVSS DVSUP ADR_CL RESETQ I2S_WS3 I2S_CL3 CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R DACM_SUB DACM_L DACM_R VREF2 DACA_L DACA_R
4519G
Fig. 4-5: PMQFP64 package
page
June 2002; 6251-512-1PDS
Micronas
PRELIMINARY DATA SHEET SUPPLEMENT
4519G-C3
AUD_CL_OUT D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 I2S_DA_IN3 I2S_DA_IN4 DVSUP DVSS I2S_DA_IN2 I2S_CL3 I2S_WS3 RESETQ DACA_R DACA_L VREF2 DACM_R DACM_L DACM_SUB
XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN- ANA_IN+ AVSUP AVSS MONO_IN SC1_IN_R SC1_IN_L SC2_IN_R SC2_IN_L SC3_IN_R SC3_IN_L SC4_IN_R SC4_IN_L AGNDC AHVSS CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R
4519G
Fig. 4-6: PSDIP64 package
Micronas
June 2002; 6251-512-1PDS
page

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