ENHANCED MINIATURE ADVANCED COMMUNICATION ENGINE (PCI ENHANCED MINI-AC
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BU-62743/62843/62864
ENHANCED MINIATURE ADVANCED COMMUNICATION ENGINE (PCI ENHANCED MINI-ACE
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FEATURES
32-Bit/33MHz, 3.3Volt, Target Interface Fully Integrated 1553A/B Notice McAir, STANAG 3838 Interface Terminal Compatible with Enhanced Mini-ACE, Mini-ACE (Plus) Generations Choice only with (BU-62743) BC/RT/MT with (BU-62843) BC/RT/MT with RAM, with Parity (BU-62864)
Actual Size: 1.0" Square Package
3.3V Logic Transceiver. Available with 1760 McAir Compatible Options 1.0-inch square, 72-Pin Flatpack Formed Gull Lead Ceramic Package Choice 20MHz 1553 Clock Highly Autonomous with Built-in Message Sequence Control: Frame Scheduling Branching Asynchronous Message Insertion General Purpose Queue User-defined Interrupts Advanced Functions: Global Circular Buffering Interrupt Status Queue Circular Buffer Rollover Interrupts Selective Message Monitor RT/Monitor
DESCRIPTION
Enhanced Mini-ACE family MIL-STD-1553 terminals provides complete interface between 32-Bit 33MHz MIL-STD-1553 bus. These terminals integrate dual transceiver, protocol logic, words words RAM. With 1.0-inch square package, Enhanced Mini-ACE nearly 100% footprint software compatible with Enhanced MiniACE, previous generation Mini-ACE (Plus) terminals, software compatible with older series. portion Enhanced Mini-ACE powered 3.3V. interface tolerant. Multiprotocol support MIL-STD-1553A/B STANAG 3838, including versions incorporating McAir compatible transmitters, provided. There choice 1553 clocks. BC/RT/MT versions with words include built-in parity checking. features include built-in message sequence control engine, with instructions. This provides autonomous means implementing multi-frame message scheduling, message retry schemes, data double buffering, asynchronous message insertion, reporting host CPU. Enhanced Mini-ACE offers choices single circular buffering, along with global circular buffering option, rollover interrupt circular buffers, interrupt status queue.
MORE INFORMATION CONTACT:
Data Device Corporation Wilbur Place Bohemia, York 11716 631-567-5600 Fax: 631-567-7358 www.ddc-web.com
Technical Support: 1-800-DDC-5757 ext. 7771
2002 Data Device Corporation
Data Device Corporation www.ddc-web.com
TX/RX_A SHARED TRANSCEIVER WRITE FIFO AD31 TX/RX_A TX_INH_A/B TX/RX_B DATA DUAL ENCODER/DECODER, MULTIPROTOCOL MEMORY MANAGEMENT
Address/Data, Parity, Command/Byte Enable
C/BE3# C/BE#0 ADDRESS FRAME#, IRDY#, IDSEL MHZ, 32-BIT SLAVE INTERFACE
TRANSCEIVER
Control
TRDY#, STOP#, DEVSEL#, PERR#, SERR#
TX/RX_B ADDRESS ADDRESS LATCH MISCELLANEOUS
(PCI) RTAD4-RTAD0, RTADP RT-AD-LAT INCMD/MCRST
Interrupt
CLK_IN, MSTCLR, SSFLAG/EXT_TRG
BU-62743/62843/62864 B-05/04-0
FIGURE ENHANCED MINI-ACE BLOCK DIAGRAM
TABLE ENHANCED MINI-ACE SPECIFICATIONS
PARAMETER ABSOLUTE MAXIMUM RATINGS Supply Voltage Logic +3.3V Transceiver (Note Logic Voltage Input Range Voltage Input Range, Tolerant pins (Note RECEIVER Differential Input Resistance (Notes 1-6) Differential Input Capacitance (Notes 1-6) Threshold Voltage, Transformer Coupled Common Mode Voltage (Note TRANSMITTER Differential Output Voltage Direct Coupled Across ohms Measured Transformer Coupled Across ohms (BU-62XXXXX-XX0, BU-62XXXXX-XX2) (Note Output Noise, Differential (Direct Coupled) Output Offset Voltage, Transformer Coupled Across ohms Rise/Fall Time (BU-62XXXX3, BU-62XXXX4) LOGIC signals except signals except Schmidt Hysteresis signals except IIH, signals except (Vcc=3.6V, VIN=Vcc) (Vcc=3.6V, VIN=2.7V) (Vcc=3.6V, VIN=0.4V) (Vcc=3.0V, IOH=max) (Vcc=3.0V, IOL=max) (Input Capacitance) LOGIC (see spec 3.3V signaling environment) (Input Capacitance) except PCI_CLK&IDSEL (Input Capacitance)PCI_CLK (Input Capacitance) IDSEL POWER SUPPLY REQUIREMENTS Voltages/Tolerances (RAM 62864), +3.3V (Logic) (Ch. UNITS
TABLE ENHANCED MINI-ACE SPECIFICATIONS (CONT.)
PARAMETER Current Drain (Total Hybrid) BU-62864XX-XX0 (RAM, Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle 3.3V (Logic) BU-62864XX-XX2 (RAM, Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle 3.3V (Logic) BU-62743XX-XX0, BU-62843XX-XX0 (Ch. Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle 3.3V Logic BU-62743XX-XX0, BU-62843XX-XX2 (Ch. Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle 3.3V Logic POWER DISSIPATION (NOTE Total Hybrid BU-62864XX-XX0 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-62864XX-XX2 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-62743XX-XX0, BU-62843XX-XX0 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-62743XX-XX2, BU-62843XX-XX2 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle Hottest BU-62XXXXX-XX0 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-62XXXXX-XX2 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle UNITS
-0.3 -0.3 -0.3 -0.3 -0.3
Vdd+0.3
0.200 0.860
Vp-p Vpeak
Vp-p
Vp-p Vp-p mVp-p mVp-p
-250
nsec nsec
0.80 1.03 1.26 1.71 0.80 1.09 1.39 1.97 0.69 0.92 1.15 1.60 0.69 0.98 1.28 1.86
-100 -100
-3.4
0.28 0.51 0.75 1.22 0.28 0.58 0.88 1.48
4.75
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BU-62743/62843/62864 B-05/04-0
TABLE ENHANCED MINI-ACE SPECIFICATIONS (CONT.)
PARAMETER CLOCK INPUTS Clock Input Frequency 1553 Clock Frequency Default Mode Option Option Option Long Term Tolerance 1553A Compliance 1553B Compliance Short Term Tolerance, second 1553A Compliance 1553B Compliance 1553 MESSAGE TIMING Completion Write Start)-to-Start Next Message (for Non-enhanced Mode) Intermessage (Note Non-enhanced (Mini-ACE compatible) mode Enhanced mode (Note UNITS 33.3 16.0 12.0 10.0 20.0 -0.01 -0.10 -0.001 -0.01 0.01 0.10 0.001 0.01
TABLE NOTES: (Cont'd) Minimum resistance maximum capacitance parameters guaranteed over operating range, tested. Assumes common mode voltage within frequency range MHz, applied pins isolation transformer stub side (either direct transformer coupled), referenced hybrid ground. Transformer must recommended transformer other transformer that provides equivalent minimum CMRR. Typical value minimum intermessage time. Under software control, this lengthened 65,535 message time) increments ENHANCED ACCESS, Configuration Register logic "1", then host accesses during Start-of-Message (SOM) End-of-Message (EOM) transfer sequences could have effect lengthening intermessage time. each host access during sequence, intermessage time will lengthened clock cycles. Since there internal transfers during during EOM, this could theoretically lengthen intermessage clock cycles; i.e., with clock, with clock, with clock, with clock. Enhanced mode, typical value intermessage time approximately clock cycles longer than non-enhanced mode. That addition MHz, MHz, MHz, MHz.
10.0 10.5 17.5 21.5 49.5 18.5 22.5 50.5 129.5 19.5 23.5 51.5
BC/RT/MT Response Timeout (Note 18.5 nominal 22.5 nominal 50.5 nominal 128.0 nominal Response Time (mid-parity mid-sync) (Note Transmitter Watchdog Timeout THERMAL 72-Pin, Ceramic Flatpack Gull Lead Thermal Resistance, Junction-to-Case, Hottest (JC) (Note Operating Junction Temperature Storage Temperature Lead Temperature (soldering, sec.) PHYSICAL CHARACTERISTICS 72-Pin, Ceramic Flatpack Gull Lead Size Weight TABLE NOTES:
660.5
+300
°C/W
(10) Software programmable options). Includes RT-to-RT Timeout (measured mid-parity transmit Command Word mid-sync transmitting Status Word). (11) Measured from mid-parity crossing Command Word mid-sync crossing RT's Status Word. (12) measured bottom case. (13) External tantalum capacitors should located close possible Pins BU62864 should also have (14) MIL-STD-1760 requires that Enhanced Mini-ACE produce Vp-p minimum output stub connection. (15) Power dissipation specifications assume transformer coupled configuration with external dissipation (while transmitting) 0.14 watts active isolation transformer, 0.08 watts active coupling transformer, 0.45 watts each isolation resistors 0.15 watts each termination resistors. (16) tolerant pins CLOCK_IN, RTAD0-5, RTAD_PAR, RTAD_LAT, TXINH_A/B, SSFLAG/EXT_TRIG.
0.155 (25.4 25.4 3.94) (17)
(mm)
Notes through applicable Receiver Differential Resistance Differential Capacitance specifications:
Specifications include both transmitter receiver (tied together internally). Impedance parameters specified directly between pins TX/RX_A(B) TX/RX_A(B) Enhanced Mini-ACE hybrid. assumed that power ground inputs hybrid connected. specifications applicable both unpowered powered conditions. specifications assume volt balanced, differential, sinusoidal input. applicable frequency range MHz.
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BU-62743/62843/62864 B-05/04-0
INTRODUCTION
BU-62743 BU-62843/62864 BC/RT/MT Enhanced Mini-ACE family MIL-STD-1553 terminals comprise complete integrated interface between host processor MIL-STD-1553 bus. members Enhanced Mini-ACE family packaged same square inch flatpack package. Enhanced Mini-ACE hybrids provide footprint software compatibility with Enhanced Mini-ACE, Mini-ACE (Plus) terminals, well software compatibility with older series. Enhanced Mini-ACE provides complete multiprotocol support MIL-STD-1553A/B/McAir STANAG 3838. versions integrate dual transceiver; along with protocol, host interface, memory management logic; minimum words RAM. addition, BU-62864 BC/RT/MT terminals include words internal RAM, with built-in parity checking. Enhanced Mini-ACEs include voltage source transceiver improved line driving capability, with options MIL-STD-1760 McAir compatibility. provide further flexibility, Enhanced Mini-ACE operate with choice clock inputs. Enhanced Mini-ACEs fully compliant targets, defined Local Specification Revision 2.2, using interface that operates clock speeds MHz, from 3.3V bus. interface supports interrupts contains FIFO that handles burst write transfer cycles. FIFO deep enough accept entire 1553 message. interface tolerant cannot used signaling environment. interface powered 3.3V. RAM, version, powered salient features Enhanced Mini-ACE Enhanced Controller architecture. Enhanced BC's highly autonomous message sequence control engine provides means offloading host processor implementing multiframe message scheduling, message retry schemes, data double buffering, asynchronous message insertion. purpose performing messaging host processor, Enhanced mode includes General Purpose Queue, along with user-defined interrupts. Enhanced Mini-ACE offers choice single circular buffering individual subaddresses. enhancements architecture include global circular buffering option multiple all) receive subaddresses, rollover interrupt circular buffers, interrupt status queue logging interrupt events, option automatically initialize mode with Busy set. interrupt status queue rollover interrupt features also included improvements Enhanced Mini-ACE's Monitor architecture. Data Device Corporation www.ddc-web.com
Enhanced Mini-ACE series terminals operate over full military temperature range -55°C +125°C. Available screened MIL-PRF-38534C, terminals ideal military industrial processor-to-1553 applications.
TRANSCEIVERS
transceivers Enhanced Mini-ACE series terminals fully monolithic, requiring only power input. transmitters voltage sources, which provide improved line driving capability over current sources. This serves improve performance long buses with many taps. transmitters also offer option which satisfies MIL-STD-1760 requirement minimum volts peak-to-peak, transformer coupled output. Besides eliminating demand additional power supply, +5V-only transceiver requires step-up, rather than step-down, isolation transformer. This provides advantage higher terminal input impedance than possible volt volt transmitter. result, there greater margin input impedance test, mandated 1553 validation test. This characteristic allows longer cable lengths between system connector isolation transformers embedded 1553 terminal. provide compatibility McAir specs, Enhanced MiniACE available with option transmitters with increased rise fall times. Additionally, MIL-STD-1760 applications, Enhanced Mini-ACE provides option minimum stub voltage level volts peak-to-peak, transformer coupled. receiver sections Enhanced Mini-ACE fully compliant with MIL-STD-1553B Notice terms front-end overvoltage protection, threshold, common mode rejection, word error rate.
REGISTER MEMORY ADDRESSING
Interface contains "Type 00h" configuration registers that used device into host system. There Base Address Registers that used implement memory space (BAR0) register space (BAR1). configuration register space mapped accordance with revision specifications. Enhanced Mini-ACE acts target responds commands listed TABLE Enhanced Mini-ACE does implement Memory Read Multiple, Memory Read Line Memory Write Invalidate commands. However, accordance with rules, Enhanced Mini-ACE will accept these requests alias them basic memory commands. example, Memory BU-62743/62843/62864 B-05/04-0
TABLE TARGET COMMAND CODES
COMMAND TYPE Memory Read Memory Write Configuration Read Configuration Write Memory Read Multiple Memory Read Line Memory Write Invalidate CODE (C/BE[3:0]#) 0110 (6h) 0111 (7h) 1010 (Ah) 1011 (Bh) 1100 (Ch) 1110 (Eh) 1111 (Fh)
This data sheet describes registers that specific configuring integrated terminal shared RAM. specifics definitions other configuration registers, please Local specification revision 2.2.
VENDOR Vendor field contains vendor's configuration register. Data Device Corporation's code 4DDCh. DEVICE Device field used indicate device being used. This field configured reflect part value device. TABLE represents possible combinations Device field. RESERVED These bits read-only return zeroes when read. SERR# ENABLE This enable SERR# driver. value disables driver. value enables driver. value after RST# PARITY ERROR CONTROL This controls device's response parity errors. When device will take normal action when parity error detected. When this device will ignore parity errors that detects continue normal operation. value after RST#
Read Multiple Memory Read Line commands will accepted treated Memory Read commands. Similarly, Enhanced Mini-ACE will accept memory Write Invalidate command treat Memory Write command. memory accessed internally 16-bit words, memory accessed sequentially allowing 32-bits data read from bus. other words, 32-bit read requested first bits data would read from requested internal address, next bits data would read from initial internal address then resulting 32-bit double word would transferred bus. Enhanced Mini-ACE supports 32-bit 16-bit read write operations, 8-bit reads will return 16-bit data, 8-bit writes illegal will cause target-aborts. register mapping located memory space. Although Enhanced Mini-ACE accessed 32-bit words, registers accessed word reads writes. 32-bit read performed from register space only first bits data valid.
TABLE CONFIGURATION REGISTER SPACE ENHANCED MINI-ACE
ADDRESS BIST
Device varies with part text) Status Register Class Code 078000 Header Type text Latency Timer
Vendor Manufacturer Device value (4DDCH) Command Register Cache Line Size
Base Address Register (for memory)
Base Address Register (for Registers) Lat. text
Base Address Registers through (not Used) 00000000h Card pointer (Not Used) 00000000h Subsystem Device Subsystem Vendor Same Configuration Register Alias Reads Configuration Register Expansion Base Address (Not Used, Reserved Interrupt Interrupt Line
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TABLE DEVICE FIELD MAPPING
DEVICE 0400h 0402h 0404h PART VALUE BC/RT/MT with (BU-62843) BC/RT/MT with (BU-62864) Only with (BU-62743)
TABLE STATUS REGISTER
29:28 26:25 22:21 20:16 DESCRIPTION Detected Parity Error Signaled System Error Signaled Target Abort DEVSEL# Timing (medium) Fast Back-to-Back Capable Reserved,
MEMORY SPACE This controls device's response memory space accesses. value disables device response. value allows device respond memory space accesses. value after RST# STATUS REGISTER This register records status information related events. Reads this register behave normally, writes only reset bits. reset whenever register written data corresponding location DETECTED PARITY ERROR This will device whenever detects parity error, even Parity Error Control Control register SIGNALED SYSTEM ERROR This indicates when device asserted SERR#. value after RST# SIGNALED TARGET ABORT This whenever device terminates transaction with Target-Abort. value after RST# DEVSEL# TIMING enhanced Mini-ACE 01b, medium. FAST BACK-TO-BACK CAPABLE This indicates that device capable accepting fast back-to-back transactions. RESERVED These bits read-only return zeroes when read. SUBSYSTEM VENDOR ID/SUBSYSTEM DEVICE This field alias Vendor ID/Device fields Configuration Register 00h.
BASE ADDRESS REGISTERS Base Address Registers used implement memory space (BAR0) register space (BAR1). Base Address Registers through used. BAR0 BAR0 used access memory space. allotted maximum words, 128K bytes, memory space. BAR0 will read back FFFE0000 after written BAR0 will read back same both word parts (BU-62743/843) word (BU-62864).
TABLE (BAR0) MEMORY
ADDRESS OFFSET 00000 1FFFC DEFINITION ENHANCED Mini-ACE Memory Space
ENHANCED MINI-ACE MEMORY SPACE least significant (LSB) address dropped form memory address. BAR1 BAR1 used access register locations. allotted maximum bytes register space. BAR1 will read back FFFFF000h after written register locations accessible through host BAR1 offsets 000h 0FCh. PCI-to-ACE interface control/status registers 800h 81Ch. accesses outside these specific regions (e.g., offset 100h 820h, etc.) will produce Target Aborts. ENHANCED MINI-ACE REGISTER SPACE Register accesses 32-bit boundary: last bits address dropped form address. (e.g. Reg1, Reg2, etc.). PCI_INTERRUPT ACTIVE When '1', indicates that Enhanced Mini-ACE asserted it's interrupt pin. three possible sources enabled active) Enhanced Mini-ACE, fail-safe timer BAR1 DRR_DATA_DISCARD.
TABLE COMMAND REGISTER
15:10 (LSB) SERR# Enable Parity Error Control Memory Space DESCRIPTION Reserved,
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TABLE (BAR1) CONTROL REGISTERS BYTE TOTAL SPACE
ADDRESS NAME OFFSET 000-0FC 100-7FC 820-FFC REG0 REG1 REG2 REG3 REG4 REG5 REG7 DEFINITION ACCESSIBILITY ENHANCED MINI-ACE Register Space RESERVED (Target-Abort accessed) GLOBAL ACTIVITY (RD) FAIL-SAFE OPERATION INTERRUPT (RD/WR) FAIL-SAFE TIMER (RD) FAIL-SAFE TIMER PRELOAD (RD/WR) DISCARD TIMER (RD) DISCARD TIMER PRELOAD (RD/WR) CLEAR FAIL-SAFE INT/RESET (WR) RESERVED (Target-Abort accessed)
FAIL-SAFE ERROR FAIL_SAFE mode fail-safe error occurs (ACE does respond), this will set. Fail-safe errors extremely unlikely. DRR_HOLD When '0', delayed read request discarded Enhanced Mini-ACE obtained requested data different transaction requested. When '1', delayed read request held until master repeats original request timeout occurs. BITS Reserved, write ENHANCED MINI-ACE INTERRUPT ENABLE Must "1". BAR1 DRR_DATA_DISCARD INTERRUPT ENABLE Enables interrupt occur BAR1 delayed read timeout. FAIL-SAFE INTERRUPT ENABLE When "1", interrupt generated FAILSAFE mode fail-safe error detected. FAIL-SAFE INTERRUPT AUTOCLEAR ENABLE set, causes interrupt FAIL_SAFE ERROR (REG0bit cleared whenever upper word REG0 read MASTER. set, must used clear fail-safe interrupts.
REG6 GENERAL PURPOSE, CUSTOMER (RD/WR)
FIFO EMPTY When '1', indicates that write FIFO empty. BAR1 DRR_DATA_DISCARD data discard timer times while waiting retry BAR1 access, this will set. BAR1 read discarded, have caused action (for example clearing interrupt) that been recognized MASTER.
TABLE REG0 GLOBAL ACTIVITY REGISTER (READ 800H)
(MSB) (LSB) DESCRIPTION INTERRUPT ACTIVE FIFO EMPTY BAR1 DRR_DATA_DISCARD FAIL_SAFE ERROR ENHANCED MINI-ACE INTERRUPT ACTIVE
TABLE REG1 FAIL-SAFE OPERATION INTERRUPT REGISTER (READ/WRITE 804H)
(MSB) (LSB) DRR_HOLD RESERVED, WRITE RESERVED, WRITE ENHANCED MINI-ACE INTERRUPT ENABLE BAR1 DRR_DATA_DISCARD INTERRUPT ENABLE FAILSAFE INTERRUPT ENABLE FAILSAFE INTERRUPT AUTOCLEAR ENABLE FAILSAFE MODE (MSB) FAILSAFE MODE (LSB) RESERVED, WRITE RESERVED, WRITE DESCRIPTION
This register will after RST#, except
This register will after RST#, except that will (Failsafe mode Failsafe Halt). Note that Fail-safe errors extremely unlikely.
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TABLE FAIL-SAFE MODE
FAIL-SAFE MODE Fail-safe Fail-safe Retry Fail-safe Halt Fail-safe Skip
TABLE REG3 FAIL-SAFE TIMER PRELOAD REGISTER (READ/WRITE 80CH)
(MSB) (LSB) DESCRIPTION FAIL-SAFE TIMER VALUE (MSB) FAIL-SAFE TIMER VALUE (LSB)
NOTE: Fail-safe errors extremely unlikely.
FAIL-SAFE MODE Fail-safe Errors occur when internal fails assert it's hand-shake signal within millisecond (programmable) when internal Strobe Request signal asserted. Four possible FAIL-SAFE Modes determine this situation handled: MODE FAIL-SAFE Enhanced Mini-ACE will wait indefinitely transaction complete. local could hang result. FAILSAFE ERROR interrupt will generated even enable set. MODE FAIL-SAFE RETRY Enhanced Mini-ACE will retry transfer local when FAIL-SAFE timer times out. MODE FAIL-SAFE HALT Once FAIL-SAFE timer times out, future transfers will terminated with target abort until master clears interrupt. MODE FAIL-SAFE SKIP Once FAIL-SAFE timer times out, current transaction discarded skipped next transaction, whether stored write FIFO transaction, will attempted.
FAIL-SAFE TIMER VALUE Write this register value fail-safe timer. default value 8400h access this register needed normal applications.
TABLE REG4 DISCARD TIMER REGISTER (READ 810H)
(MSB) (LSB) DESCRIPTION DISCARD TIMER CURRENT (MSB) DISCARD TIMER CURRENT (LSB)
DISCARD TIMER CURRENT Read this register obtain current value DISCARD TIMER. Default 0000h.
TABLE REG2 FAIL-SAFE TIMER REGISTER (READ 808H)
(MSB) (LSB) FAIL-SAFE TIMER COUNT (MSB) FAIL-SAFE TIMER COUNT (LSB) DESCRIPTION
TABLE REG5 DISCARD TIMER PRELOAD REGISTER (READ/WRITE 814H)
(MSB) (LSB) DESCRIPTION DISCARD TIMER VALUE (MSB) DISCARD TIMER VALUE (LSB)
FAIL-SAFE TIMER COUNT Read this register obtain current value fail-safe timer. Default 8400h.
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DISCARD TIMER VALUE Write this register value used discard timer. default value "0". default value meets spec access this register needed normal applications.
BU-62743/62843/62864 B-05/04-0
TABLE REG6 GENERAL PURPOSE REGISTER (READ/WRITE 818H)
(MSB) (LSB) DESCRIPTION RESERVED (MSB) RESERVED (LSB)
TABLE REG7 RESERVED REGISTER (WRITE 81CH)
(MSB) (LSB) DESCRIPTION RESERVED, WRITE (MSB) CLEAR FAILSAFE INTERRUPT RESET (LSB)
Note: This register will after RST#. This read/write register available customer use, perhaps flag register signaling between masters.
Note: This register will after RST#. access this register needed normal applications.
BITS 15-0 RESERVED Write these bits BITS 31-2 RESERVED Must written CLEAR FAIL-SAFE INTERRUPT Clears Fail-safe Interrupt when "1". Fail-safe interrupts also cleared Fail-safe Interrupt Autoclear mechanism, enabled RESET Resets when "1".
normal operation, host processor only needs access lower register address locations (00-1Fh, BAR1 offset 00-7Ch). next locations (20-3F, BAR1 offset 80hFCh) should reserved, since many these used factory test.
INTERNAL 1553 REGISTERS
internal address mapping Enhanced Mini-ACE registers illustrated TABLE Note that address lines shown Enhanced Mini-ACE's internal register left shifted bits with respect address: etc. example, Interrupt mask register located address BAR1 offset Configuration Register BAR1 offset etc. Note that TABLE does show internal register address line, which normally only access reserved factory test registers. configuration registers will cleared 0000h after hardware software reset, with exception Enhanced Access (bit Configuration register #6).
ENHANCED MINI-ACE REGISTER MEMORY ADDRESSING
software interface Enhanced Mini-ACE portion host processor consists internal operational registers normal operation, additional test registers, plus words shared memory address space. Enhanced Mini-ACE's internal resides this address space.
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TABLE 1553 REGISTER ADDRESS MAPPING
INTERNAL ADDRESS LINES
BAR1 ADDR OFFSET
REGISTER DESCRIPTION ACCESSIBILITY Interrupt Mask Register (RD/WR) Configuration Register (RD/WR) Configuration Register (RD/WR) Start/Reset Register (WR) Non-Enhanced Command Stack Pointer Enhanced Instruction List Pointer Register (RD) Control Word Subaddress Control Word Register (RD/WR) Time Register (RD/WR) Interrupt Status Register (RD) Configuration Register (RD/WR) Configuration Register (RD/WR) Configuration Register (RD/WR) Monitor Data Stack Address Register (RD/WR) Frame Time Remaining Register (RD) Time Remaining Next Message Register (RD) Non-Enhanced Frame Time Enhanced Initial Instruction Pointer Last Command Trigger Word Register(RD/WR) Status Word Register (RD) Word Register (RD) Test Mode Register Test Mode Register Test Mode Register Test Mode Register Test Mode Register Test Mode Register Test Mode Register Test Mode Register Configuration Register (RD/WR) Configuration Register (RD/WR) RESERVED Condition Code Register (RD) General Purpose Flag Register (WR) Test Status Register (RD) Interrupt Mask Register (RD/WR) Interrupt Status Register (RD) General Purpose Queue Pointer RT-MT Interrupt Status Queue Pointer Register (RD/WR)
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TABLE INTERRUPT MASK REGISTER (READ/WRITE 00H, 00H)
15(MSB) 0(LSB) RESERVED PARITY ERROR BC/RT TRANSMITTER TIMEOUT BC/RT COMMAND STACK ROLLOVER COMMAND STACK ROLLOVER DATA STACK ROLLOVER HANDSHAKE FAIL RETRY ADDRESS PARITY ERROR TIME ROLLOVER CIRCULAR BUFFER ROLLOVER SUBADDRESS CONTROL WORD FRAME FORMAT ERROR STATUS SET/RT MODE CODE/MT PATTERN TRIGGER MESSAGE DESCRIPTION
TABLE CONFIGURATION REGISTER (READ/WRITE 01H, 04H)
FUNCTION (Bits 11-0 Enhanced Mode Only) WITHOUT ALTERNATE STATUS (logic (logic CURRENT AREA WITH ALTERNATE STATUS (Enhanced Only) (logic (logic CURRENT AREA MONITOR FUNCTION (Enhanced mode only bits 12-0) (logic (logic CURRENT AREA MESSAGE MONITOR ENABLED TRIGGER WORD ENABLED START-ON-TRIGGER STOP-ON-TRIGGER USED EXTERNAL TRIGGER ENABLED USED USED USED USED MONITOR ENABLED(Read Only) MONITOR TRIGGERED (Read Only) MONITOR ACTIVE (Read Only)
(MSB) RT/BC-MT (logic (LSB) MT/BC-RT (logic CURRENT AREA MESSAGE STOP-ON-ERROR FRAME STOP-ON-ERROR STATUS STOP-ON-MESSAGE STATUS STOP-ON-FRAME FRAME AUTO-REPEAT
MESSAGE MONITOR ENABLED MESSAGE MONITOR (MMT) ENABLED DYNAMIC CONTROL ACCEPTANCE BUSY SERVICE REQUEST SSFLAG
EXTERNAL TRIGGER ENABLED RTFLAG (Enhanced Mode Only) INTERNAL TRIGGER ENABLED INTERMESSAGE TIMER ENABLED RETRY ENABLED DOUBLED/SINGLE RETRY ENABLED (Read Only) FRAME PROGRESS (Read Only) MESSAGE PROGRESS (Read Only) USED USED USED USED USED USED
MESSAGE PROGRESS MESSAGE (Enhanced mode only,Read Only) PROGRESS (Read Only)
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TABLE CONFIGURATION REGISTER (READ/WRITE 02H, 08H)
DESCRIPTION 15(MSB) ENHANCED INTERRUPTS 0(LSB) PARITY ENABLE BUSY LOOKUP TABLE ENABLE RESERVED FUTURE USE, must OVERWRITE INVALID DATA 256-WORD BOUNDARY DISABLE TIME RESOLUTION TIME RESOLUTION TIME RESOLUTION CLEAR TIME SYNCHRONIZE LOAD TIME SYNCHRONIZE INTERRUPT STATUS AUTO CLEAR LEVEL/PULSE INTERRUPT REQUEST CLEAR SERVICE REQUEST ENHANCED MEMORY MANAGEMENT SEPARATE BROADCAST DATA
TABLE CONTROL WORD REGISTER (READ/WRITE 04H, 10H)
15(MSB) RESERVED 0(LSB) MESSAGE ERROR MASK SERVICE REQUEST MASK BUSY MASK SUBSYSTEM FLAG MASK TERMINAL FLAG MASK RESERVED BITS MASK RETRY ENABLED CHANNEL OFF-LINE SELF-TEST MASK BROADCAST INTERRUPT ENABLE 1553A/B SELECT MODE CODE FORMAT BROADCAST FORMAT RT-to-RT FORMAT DESCRIPTION
TABLE START/RESET REGISTER (WRITE 03H, 0CH)
15(MSB) RESERVED 0(LSB) RESERVED RESERVED RESERVED CLEAR HALT CLEAR SELF-TEST REGISTER INITIATE SELF-TEST RESERVED RESERVED BC/MT STOP-ON-MESSAGE STOP-ON-FRAME TIME TEST CLOCK TIME RESET INTERRUPT RESET BC/MT START RESET DESCRIPTION
TABLE SUBADDRESS CONTROL WORD (READ 04H, 10H)
0(LSB) CIRC MEMORY MANAGEMENT (MM2) MEMORY MANAGEMENT (MM1) MEMORY MANAGEMENT (MM0) CIRC MEMORY MANAGEMENT (MM2) MEMORY MANAGEMENT (MM1) MEMORY MANAGEMENT (MM0) BCST: BCST: CIRC BCST: MEMORY MANAGEMENT (MM2) BCST: MEMORY MANAGEMENT (MM1) BCST: MEMORY MANAGEMENT (MM0) DESCRIPTION 15(MSB) GLOBAL CIRCULAR BUFFER ENABLE
TABLE BC/RT COMMAND STACK POINTER REG. (READ 03H, 0CH)
0(LSB) COMMAND STACK POINTER DESCRIPTION 15(MSB) COMMAND STACK POINTER
TABLE TIME REGISTER (READ/WRITE 05H, 14H)
DESCRIPTION TIME 15(MSB) TIME 0(LSB)
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TABLE INTERRUPT STATUS REGISTER (READ/WRITE 06H, 18H)
DESCRIPTION 15(MSB) MASTER INTERRUPT 0(LSB) PARITY ERROR TRANSMITTER TIMEOUT BC/RT COMMAND STACK ROLLOVER COMMAND STACK ROLLOVER DATA STACK ROLLOVER HANDSHAKE FAILURE RETRY ADDRESS PARITY ERROR TIME ROLLOVER CIRCULAR BUFFER ROLLOVER SUBADDRESS CONTROL WORD FRAME FORMAT ERROR STATUS MODE CODE PATTERN TRIGGER MESSAGE
TABLE CONFIGURATION REGISTER (READ/WRITE 08H, 20H)
DESCRIPTION 15(MSB) EXTERNAL WORD ENABLE 0(LSB) INHIBIT WORD BUSY MODE COMMAND OVERRIDE BUSY EXPANDED CONTROL WORD ENABLE BROADCAST MASK ENA/XOR RETRY M.E. RETRY STATUS RETRY ALT/SAME RETRY ALT/SAME VALID M.E./NO DATA VALID BUSY/NO DATA OPTION LATCH ADDRESS WITH CONFIG TEST MODE TEST MODE TEST MODE
TABLE CONFIGURATION REGISTER (READ/WRITE 09H, 24H)
DESCRIPTION
TABLE CONFIGURATION REGISTER (READ/WRITE 07H, 1CH)
DESCRIPTION 15(MSB) ENHANCED MODE ENABLE 0(LSB) BC/RT COMMAND STACK SIZE BC/RT COMMAND STACK SIZE COMMAND STACK SIZE COMMAND STACK SIZE DATA STACK SIZE DATA STACK SIZE DATA STACK SIZE ILLEGALIZATION DISABLED OVERRIDE MODE ERROR ALTERNATE STATUS WORD ENABLE ILLEGAL TRANSFER DISABLE RESERVED, zero RTFAIL RTFLAG WRAP ENABLE 1553A MODE CODES ENABLE ENHANCED MODE CODE HANDLING
15(MSB) CLOCK SELECT 0(LSB) SINGLE-ENDED SELECT EXTERNAL INHIBIT EXTERNAL INHIBIT EXPANDED CROSSING ENABLED RESPONSE TIMEOUT SELECT RESPONSE TIMEOUT SELECT CHECK ENABLED BROADCAST DISABLED ADDRESS LATCH/TRANSPARENT ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS PARITY
TABLE MONITOR DATA STACK ADDRESS REGISTER (READ/WRITE 0AH, 28H)
0(LSB) MONITOR DATA STACK ADDRESS DESCRIPTION 15(MSB) MONITOR DATA STACK ADDRESS
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TABLE FRAME TIME REMAINING REGISTER (READ/WRITE 0BH, 2CH)
DESCRIPTION 15(MSB) FRAME TIME REMAINING 0(LSB) FRAME TIME REMAINING
TABLE WORD REGISTER (READ 0FH, 3CH)
DESCRIPTION 15(MSB) TRANSMITTER TIMEOUT LOOP TEST FAILURE LOOP TEST FAILURE HANDSHAKE FAILURE TRANSMITTER SHUTDOWN TRANSMITTER SHUTDOWN TERMINAL FLAG INHIBITED TEST FAIL HIGH WORD COUNT WORD COUNT INCORRECT SYNC RECEIVED PARITY MANCHESTER ERROR RECEIVED RT-to-RT SYNC ADDRESS ERROR RT-to-RT RESPONSE ERROR RT-to-RT COMMAND WORD ERROR COMMAND WORD CONTENTS ERROR
Note: resolution
TABLE MESSAGE TIME REMAINING REGISTER (READ 0CH, 30H)
DESCRIPTION 15(MSB) MESSAGE TIME REMAINING 0(LSB) MESSAGE TIME REMAINING
0(LSB)
Note: resolution
TABLE FRAME TIME LAST COMMAND TRIGGER REGISTER (READ/WRITE 0DH, 34H)
15(MSB) 0(LSB) DESCRIPTION
TABLE CONFIGURATION REGISTER (READ/WRITE 18H, 60H)
DESCRIPTION 15(MSB) ENHANCED CONTROLLER ENHANCED ACCESS COMMAND STACK POINTER INCREMENT (RT, GLOBAL CIRCULAR BUFFER ENABLE GLOBAL CIRCULAR BUFFER SIZE GLOBAL CIRCULAR BUFFER SIZE GLOBAL CIRCULAR BUFFER SIZE DISABLE INVALID MESSAGES INTERRUPT STATUS QUEUE DISABLE VALID MESSAGES INTERRUPT STATUS QUEUE INTERRUPT STATUS QUEUE ENABLE ADDRESS SOURCE ENHANCED MESSAGE MONITOR RESERVED 64-WORD REGISTER SPACE CLOCK SELECT CLOCK SELECT
TABLE STATUS WORD REGISTER (READ 0EH, 38H)
15(MSB) LOGIC 0(LSB) LOGIC LOGIC LOGIC LOGIC MESSAGE ERROR INSTRUMENTATION SERVICE REQUEST RESERVED RESERVED RESERVED BROADCAST COMMAND RECEIVED BUSY SSFLAG DYNAMIC CONTROL ACCEPT TERMINAL FLAG DESCRIPTION
0(LSB)
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TABLE CONFIGURATION REGISTER (READ/WRITE 19H, 64H)
DESCRIPTION 15(MSB) MEMORY MANAGEMENT BASE ADDRESS 0(LSB) MEMORY MANAGEMENT BASE ADDRESS MEMORY MANAGEMENT BASE ADDRESS MEMORY MANAGEMENT BASE ADDRESS MEMORY MANAGEMENT BASE ADDRESS MEMORY MANAGEMENT BASE ADDRESS RESERVED RESERVED RESERVED RESERVED RESERVED HALT ENABLE 1553B RESPONSE TIME ENHANCED TIMETAG SYNCHRONIZE ENHANCED WATCHDOG TIMER ENABLED MODE CODE RESET INCMD SELECT
TABLE GENERAL PURPOSE FLAG REGISTER (WRITE 1BH, 6CH)
DESCRIPTION 15(MSB) CLEAR GENERAL PURPOSE FLAG 0(LSB) CLEAR GENERAL PURPOSE FLAG CLEAR GENERAL PURPOSE FLAG CLEAR GENERAL PURPOSE FLAG CLEAR GENERAL PURPOSE FLAG CLEAR GENERAL PURPOSE FLAG CLEAR GENERAL PURPOSE FLAG CLEAR GENERAL PURPOSE FLAG GENERAL PURPOSE FLAG GENERAL PURPOSE FLAG GENERAL PURPOSE FLAG GENERAL PURPOSE FLAG GENERAL PURPOSE FLAG GENERAL PURPOSE FLAG GENERAL PURPOSE FLAG GENERAL PURPOSE FLAG
TABLE CONDITION CODE REGISTER (READ 1BH, 6CH)
15(MSB) ALWAYS 0(LSB) RETRY RETRY MESSAGE MESSAGE STATUS GOOD BLOCK TRANSFER FORMAT ERROR RESPONSE GENERAL PURPOSE FLAG GENERAL PURPOSE FLAG GENERAL PURPOSE FLAG GENERAL PURPOSE FLAG GENERAL PURPOSE FLAG GENERAL PURPOSE FLAG LESS THAN FLAG GENERAL PURPOSE FLAG EQUAL FLAG GENERAL PURPOSE FLAG DESCRIPTION
TABLE TEST STATUS REGISTER (READ 1CH, 70H)
DESCRIPTION 15(MSB) LOGIC 0(LSB) LOGIC LOGIC LOGIC LOGIC LOGIC LOGIC LOGIC BUILT-IN TEST COMPLETE BUILT-IN TEST IN-PROGRESS BUILT-IN TEST PASSED LOGIC LOGIC LOGIC LOGIC LOGIC
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TABLE INTERRUPT MASK REGISTER (READ/WRITE 1DH, 74H)
15(MSB) USED 0(LSB) CODE PARITY ERROR ILLEGAL COMMAND GENERAL PURPOSE QUEUE INTERRUPT STATUS QUEUE ROLLOVER CALL STACK POINTER REGISTER ERROR TRAP CODE COMMAND STACK ROLLOVER CIRCULAR BUFFER ROLLOVER MONITOR COMMAND STACK ROLLOVER MONITOR DATA STACK ROLLOVER ENHANCED IRQ3 ENHANCED IRQ2 ENHANCED IRQ1 ENHANCED IRQ0 TEST COMPLETE USED DESCRIPTION
TABLE GENERAL PURPOSE QUEUE POINTER REGISTER INTERRUPT STATUS QUEUE POINTER REGISTER (READ/WRITE 1FH, 7CH)
DESCRIPTION 15(MSB) QUEUE POINTER BASE ADDRESS 0(LSB) QUEUE POINTER BASE ADDRESS QUEUE POINTER BASE ADDRESS QUEUE POINTER BASE ADDRESS QUEUE POINTER BASE ADDRESS QUEUE POINTER BASE ADDRESS QUEUE POINTER BASE ADDRESS QUEUE POINTER BASE ADDRESS QUEUE POINTER BASE ADDRESS QUEUE POINTER BASE ADDRESS QUEUE POINTER BASE ADDRESS QUEUE POINTER BASE ADDRESS QUEUE POINTER BASE ADDRESS QUEUE POINTER BASE ADDRESS QUEUE POINTER BASE ADDRESS QUEUE POINTER BASE ADDRESS
TABLE INTERRUPT STATUS REGISTER (READ 1EH, 78H)
DESCRIPTION 15(MSB) MASTER INTERRUPT 0(LSB) CODE PARITY ERROR ILLEGAL COMMAND GENERAL PURPOSE QUEUE INTERRUPT STATUS QUEUE ROLLOVER CALL STACK POINTER REGISTER ERROR TRAP CODE COMMAND STACK ROLLOVER CIRCULAR BUFFER ROLLOVER MONITOR COMMAND STACK ROLLOVER MONITOR DATA STACK ROLLOVER ENHANCED IRQ3 ENHANCED IRQ2 ENHANCED IRQ1 ENHANCED IRQ0 TEST COMPLETE INTERRUPT CHAIN
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NOTE: TABLES REGISTERS, THEY WORDS STORED RAM.
TABLE MODE BLOCK STATUS WORD
15(MSB) 0(LSB) CHANNEL ERROR FLAG STATUS FORMAT ERROR RESPONSE TIMEOUT LOOP TEST FAIL MASKED STATUS RETRY COUNT RETRY COUNT GOOD DATA BLOCK TRANSFER WRONG STATUS ADDRESS WORD COUNT ERROR INCORRECT SYNC TYPE INVALID WORD DESCRIPTION
TABLE 1553 COMMAND WORD
DESCRIPTION 15(MSB) REMOTE TERMINAL ADDRESS 0(LSB) REMOTE TERMINAL ADDRESS REMOTE TERMINAL ADDRESS REMOTE TERMINAL ADDRESS REMOTE TERMINAL ADDRESS TRANSMIT RECEIVE SUBADDRESS MODE CODE SUBADDRESS MODE CODE SUBADDRESS MODE CODE SUBADDRESS MODE CODE SUBADDRESS MODE CODE DATA WORD COUNT MODE CODE DATA WORD COUNT MODE CODE DATA WORD COUNT MODE CODE DATA WORD COUNT MODE CODE DATA WORD COUNT MODE CODE
TABLE MODE BLOCK STATUS WORD
15(MSB) 0(LSB) CHANNEL ERROR FLAG RT-to-RT FORMAT FORMAT ERROR RESPONSE TIMEOUT LOOP TEST FAIL DATA STACK ROLLOVER ILLEGAL COMMAND WORD WORD COUNT ERROR INCORRECT DATA SYNC INVALID WORD RT-to-RT SYNC ADDRESS ERROR RT-to-RT COMMAND ERROR COMMAND WORD CONTENTS ERROR DESCRIPTION
TABLE WORD MONITOR IDENTIFICATION WORD
15(MSB) TIME (MSB) TIME (LSB) WORD FLAG THIS BROADCAST ERROR COMMAND DATA CHANNEL CONTIGUOUS DATA MODE_CODE DESCRIPTION
0(LSB)
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TABLE MESSAGE MONITOR MODE BLOCK STATUS WORD
15(MSB) 0(LSB) CHANNEL ERROR FLAG RT-to-RT TRANSFER FORMAT ERROR RESPONSE TIMEOUT GOOD DATA BLOCK TRANSFER DATA STACK ROLLOVER RESERVED WORD COUNT ERROR INCORRECT SYNC INVALID WORD RT-to-RT SYNC ADDRESS ERROR RT-to-RT COMMAND ERROR COMMAND WORD CONTENTS ERROR DESCRIPTION
TABLE RT/MONITOR INTERRUPT STATUS WORD (FOR INTERRUPT STATUS QUEUE)
DEFINITION MESSAGE INTERRUPT EVENT TRANSMITTER TIMEOUT ILLEGAL COMMAND MONITOR DATA STACK ROLLOVER MONITOR DATA STACK ROLLOVER CIRCULAR BUFFER ROLLOVER CIRCULAR BUFFER ROLLOVER MONITOR COMMAND (DESCRIPTOR) STACK ROLLOVER MONITOR COMMAND (DESCRIPTOR) STACK ROLLOVER COMMAND (DESCRIPTOR) STACK ROLLOVER COMMAND (DESCRIPTOR) STACK ROLLOVER HANDSHAKE FAIL FORMAT ERROR MODE CODE INTERRUPT SUBADDRESS CONTROL WORD END-OF-MESSAGE (EOM) DEFINITION NON-MESSAGE INTERRUPT EVENT USED USED USED USED USED USED USED
USED USED USED USED TIME ROLLOVER ADDRESS PARITY ERROR USED PARITY ERROR
TABLE 1553B STATUS WORD
DESCRIPTION
15(MSB) REMOTE TERMINAL ADDRESS 0(LSB) REMOTE TERMINAL ADDRESS REMOTE TERMINAL ADDRESS REMOTE TERMINAL ADDRESS REMOTE TERMINAL ADDRESS MESSAGE ERROR INSTRUMENTATION SERVICE REQUEST RESERVED RESERVED RESERVED BROADCAST COMMAND RECEIVED BUSY SSFLAG DYNAMIC CONTROL ACCEPTANCE TERMINAL FLAG
MESSAGE INTERRUPT EVENT NON-MESSAGE INTERRUPT EVENT
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NON-TEST REGISTER FUNCTION SUMMARY
summary Enhanced Mini-ACE's non-test registers follows.
used select memory management scheme enable interrupts current message.
TIME REGISTER
Time Register maintains value real-time clock. resolution this register programmable from among µs/LSB. Start-of-Message (SOM) Endof-Message (EOM) sequences Message Monitor modes cause write current value Time Register stack area RAM.
INTERRUPT MASK REGISTERS
Interrupt Mask Registers used enable disable interrupt requests various events conditions.
NOTE: Please Appendix Enhanced Mini-ACE Users Guide important information applicable only MODE operation, enabling interrupt status queue specific non-message interrupts.
INTERRUPT STATUS REGISTERS
Interrupt Status Registers allow host processor determine cause interrupt request means read accesses. interrupt events Interrupt Status Registers mapped correspond respective positions Interrupt Mask Registers. Interrupt Status Register contains INTERRUPT CHAIN bit, used indicate interrupt event from Interrupt Status Register
CONFIGURATION REGISTERS
Configuration Registers used select Enhanced Mini-ACE's mode operation, software control Status Word bits, Active Memory Area, Stop-OnError, Memory Management mode selection, control Time operation. Note that LEVEL/PULSE INTERRUPT REQUEST Configuration Register MUST correct operation.
CONFIGURATION REGISTERS
Configuration Registers used enable many Enhanced Mini-ACE's advanced features that were implemented prior generation products, MiniACE (Plus). modes, ENHANCED MODE enables various read-only bits Configuration Register mode, ENHANCED mode features include expanded Control Word Block Status Word, additional Stop-On-Error Stop-On-Status functions, frame auto-repeat, programmable intermessage times, automatic retries, expanded Status Word Masking, capability generate interrupts following completion selected message. mode, enhanced mode features include expanded Block Status Word, combined RT/Selective Message Monitor mode, internal wrapping RTFAIL output signal RTFLAG Status Word bit, alternate (fully software programmable) Status Word. mode, enhanced mode enables Selective Message Monitor, combined RT/Selective Monitor modes, monitor triggering capability.
START/RESET REGISTER
Start/Reset Register used "command" type functions such software reset, BC/MT Start, Interrupt reset, Time Reset, Time Register Test, Initiate self-test, Clear selftest register, Clear Halt. Start/Reset Register also includes provisions stopping auto-repeat mode, either current message current frame.
BC/RT COMMAND STACK REGISTER
BC/RT Command Stack Register allows host determine pointer location current most recent message.
INSTRUCTION LIST POINTER REGISTER
Instruction List Pointer Register read determine current location Instruction List Pointer Enhanced mode.
RT/MONITOR DATA STACK ADDRESS REGISTER
RT/Monitor Data Stack Address Register provides read/writable indication last data word stored Monitor modes.
CONTROL WORD/RT SUBADDRESS CONTROL WORD REGISTER
mode, Control Word/RT Subaddress Control Word Register allows host access current word most recent Control Word. Control Word contains bits that select active message format, enable off-line self-test, masking Status Word bits, enable retries interrupts, specify MIL-STD-1553A -1553B error handling. mode, this register allows host access current most recent Subaddress Control Word. Subaddress Control Word
FRAME TIME REMAINING REGISTER
Frame Time Remaining Register provides read-only indication time remaining current frame. enhanced mode, this timer used minor major frame control, watchdog timer message sequence control processor. resolution this register µs/LSB.
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TIME REMAINING NEXT MESSAGE REGISTER
Time Remaining Next Message Register provides read-only indication time remaining before start next message frame. enhanced mode, this timer also used message sequence control processor's Delay (DLY) instruction, minor major frame control. resolution this register µs/LSB.
CONDITION CODE REGISTER
Condition Code Register used enable host processor read current value Enhanced Message Sequence Control Engine's condition flags.
GENERAL PURPOSE FLAG REGISTER
General Purpose Flag Register allows host processor able set, clear, toggle Enhanced Message Sequence Control Engine's General Purpose condition flags.
FRAME TIME/RT LAST COMMAND/MT TRIGGER WORD REGISTER
mode, this register used program frame time, frame auto-repeat mode. resolution this register µs/LSB, with range 6.55 seconds. mode, this register stores current most previous) 1553 Command Word processed Enhanced Mini-ACE Word Monitor mode, this register used specify 16bit Trigger (Command) Word. Trigger Word used start stop monitor, generate interrupts.
TEST STATUS REGISTER
Test Status Register used provide read-only access status built-in self-tests (BIT).
GENERAL PURPOSE QUEUE POINTER
General Purpose Queue Pointer provides means initializing pointer General Purpose Queue, Enhanced mode. addition, this register enables host determine current location General Purpose Queue pointer, which incremented internally Enhanced message sequence control engine.
INITIAL INSTRUCTION LIST POINTER REGISTER
Initial Instruction List Pointer Register enables host assign starting address enhanced Instruction List.
STATUS WORD REGISTER WORD REGISTERS
Status Word Register Word Registers provide read-only indications Status Words.
RT/MT INTERRUPT STATUS QUEUE POINTER REGISTER
RT/MT Interrupt Status Queue Pointer Register provides means initializing pointer Interrupt Status Queue, RT/MT modes. addition, this register enables host determine current location Interrupt Status Queue pointer, which incremented internally RT/MT message processor.
TEST MODE REGISTERS
These registers included factory test. normal operation, these registers need accessed host processor.
CONFIGURATION REGISTERS
Configuration Registers used enable Enhanced Mini-ACE features that extend beyond architecture ACE/Mini-ACE (Plus). These include Enhanced mode; Enhanced Access (note that this only configuration that after reset), Global Circular Buffer (including buffer size); RT/MT Interrupt Status Queue, including valid/invalid message filtering; enabling softwareassigned address; clock frequency selection; base address "non-data" portion Enhanced Mini-ACE memory; filtering Synchronize (with data) time operations; enabling watchdog timer Enhanced message sequence control engine.
CONTROLLER (BC) ARCHITECTURE
functionality Enhanced Mini-ACE includes separate architectures: older, non-Enhanced mode, which provides complete compatibility with previous Mini-ACE (Plus) generation products; newer, Enhanced mode. Enhanced mode offers several powerful architectural features. These include incorporation highly autonomous message sequence control engine, which greatly serves offload operation host CPU. Enhanced BC's message sequence control engine provides high degree flexibility implementing major minor frame scheduling; capabilities inserting asynchronous messages middle frame; separate 1553 message data from control/status data purpose implementing double buffering performing bulk data transfers; implementing message retry schemes, including capability automatic channel switchover failed messages; reporting various conditions host processor means userdefined interrupts general purpose queue.
NOTE: Please Appendix Enhanced Mini-ACE Users Guide important information applicable only MODE operation, enabling interrupt status queue specific non-message interrupts.
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both non-Enhanced Enhanced modes, Enhanced Mini-ACE implements MIL-STD-1553B message formats. Message format programmable messageby-message basis means Control Word Command Word respective message. Control Word allows 1553 message format, 1553A/B type channel, self-test, Status Word masking specified individual message basis. addition, automatic retries and/or interrupt requests enabled disabled individual messages. performs error checking required MIL-STD-1553B. This includes validation response time, sync type sync encoding, Manchester encoding, parity, count, word count, Status Word Address field, various RT-to-RT transfer errors. Enhanced Mini-ACE response timeout value programmable with choices longer response timeout values allow operation over long buses and/or repeaters. non-Enhanced mode, Enhanced Mini-ACE programmed process frames messages with processor intervention. Enhanced mode, there explicit limit number messages that processed frame. both modes, possible program either single frame frame auto-repeat operation. auto-repeat mode, frame repetition rate controlled either internally, using programmable frame timer, from external trigger input.
operation Enhanced Mini-ACE's message sequence control engine illustrated FIGURE message sequence control involves instruction list pointer register; instruction list which contains multiple 2-word entries; message control/status stack, which contains multiple 8-word 10-word descriptors; data blocks individual messages. initial value instruction list pointer register initialized host processor (via Register 0D), incremented message sequence processor (host readable Register 03). During operation, message sequence control processor fetches operation referenced instruction list pointer register from instruction list. Note that pointer parameter referencing first word message's control/status block (the Control Word) must contain address value that modulo Also, note that message RT-to-RT transfer, pointer parameter must contain address value that modulo
CODES
instruction list pointer register references pair words instruction list: code word, followed parameter word. format code word, which illustrated FIGURE includes 5-bit code field 5-bit condition code field. code identifies instruction executed message sequence controller. Most operations conditional, with execution dependent contents condition code field. Bits condition code field identify particular condition. condition code field identifies logic sense ("1" "0") selected condition code which conditional execution dependent. TABLE lists codes, along with their respective
ENHANCED MODE: MESSAGE SEQUENCE CONTROL
major architectural features Enhanced Mini-ACE series advanced capability message sequence control. Enhanced Mini-ACE supports highly autonomous operation, which greatly offloads operation host processor.
INSTRUCTION LIST
INSTRUCTION LIST POINTER REGISTER INITIALIZE REGISTER (RD/WR); READ CURRENT VALUE REGISTER ONLY)
MESSAGE CONTROL/STATUS BLOCK
CODE PARAMETER (POINTER) CONTROL WORD COMMAND WORD Command RT-to-RT transfer) DATA BLOCK POINTER DATA BLOCK TIME-TO-NEXT MESSAGE TIME WORD BLOCK STATUS WORD
LOOPBACK WORD STATUS WORD (Tx) COMMAND WORD (for RT-to-RT transfer) STATUS WORD (for RT-to-RT transfer)
FIGURE MESSAGE SEQUENCE CONTROL
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mnemonic, code value, parameter, description. TABLE defines condition codes. Eight condition codes through cleared result most recent message. other eight defined "General Purpose" condition codes through GP7. There three mechanisms programming values General Purpose Condition Code bits: They set, cleared, toggled host processor, means GENERAL PURPOSE FLAG REGISTER; they set, cleared, toggled message sequence control processor, means Flag Bits (FLG) instruction; only (but none others) cleared means message sequence control processor's Compare Frame Timer (CFT) Compare Message Timer (CMT) instructions. host processor also read-only access condition codes means CONDITION CODE REGISTER. Note that four instructions unconditional. These Compare Frame Timer (CFT), Compare Message Timer (CMT), Flag Bits (FLG), Execute Flip (XQF). these instructions, Condition Code Field "don't care". That these instructions always executed, regardless result condition code test. other instructions conditional. That they will only executed condition code specified condition code field code word tests true. condition code field tests false, instruction list pointer will skip down next instruction. shown TABLE many operations include singleword parameter. (execute message) operation, parameter pointer start message's control/status block. other operations, parameter address, time value, interrupt pattern, mechanism clear general purpose flag bits, immediate value. several codes, parameter "don't care" (not used). described above, some codes will cause message sequence control processor execute messages. this case, parameter references first word message control/status block. With exception RT-to-RT transfer messages, message status/control blocks eight words long: block control word, time-to-next-message parameter, data block
pointer, command word, status word, loopback word, block status word, time word. case RT-to-RT transfer message, size message control/status block increases words. However, this case, last words used; ninth tenth words second command word second status word. third word message control/status block pointer that references first word message's data word block. Note that data word block stores only data words, which either transmitted received segregating data words from command words, status words, other control "housekeeping" functions, this architecture enables convenient, usable data structures, such circular buffers double buffers. Other operations support program flow control; i.e., jump call capability. call capability includes maintenance call stack which supports maximum four entries; there also return instruction. case call stack overrun underrun, will issue CALL STACK POINTER REGISTER ERROR interrupt, enabled. Other codes used delay specified time; start frame; wait external trigger start frame; comparisons based frame time time-to-next message; load time frame time registers; halt; issue host interrupts. case host interrupts, message control processor passes 4-bit user-defined interrupt vector host, means Enhanced Mini-ACE's Interrupt Status Register. purpose instruction enable message sequence controller set, clear, toggle value(s) eight general purpose condition flags. code parity encompasses sixteen bits code word. This must programmed parity. message sequence control processor fetches undefined code word, code word with even parity, bits code word have binary pattern 01010, message sequence control processor will immediately halt BC's operation. addition, enabled, TRAP CODE interrupt will issued. Also, enabled, parity error will result CODE PARITY ERROR interrupt. TABLE describes Condition Codes.
Parity
OpCode Field
Condition Code Field
FIGURE CODE FORMAT
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TABLE OPERATIONS MESSAGE SEQUENCE CONTROL
INSTRUCTION MNEMONIC Execute Message Jump CODE (HEX) 0001 CONDITIONAL DESCRIPTION UNCONDITIONAL Message Control Conditional Executes message specified Message Control/Status Status Block (See Note) Block Address condition flag tests TRUE, otherwise conAddress tinue execution next OpCode instruction list. PARAMETER Instruction List Address Instruction List Address Conditional Jump OpCode specified Instruction List condition flag tests TRUE, otherwise continue execution next OpCode instruction list. Jump OpCode specified Instruction List Address push Address Next OpCode Call Stack condition flag tests TRUE, otherwise continue execution next OpCode instruction list. Note that maximum depth subroutine call stack four. Return OpCode popped Call Stack condition flag tests TRUE, otherwise continue execution next OpCode instruction list. Generate interrupt condition flag tests TRUE, otherwise continue execution next OpCode instruction list. passed parameter (Interrupt Pattern) specifies which ENHANCED bit(s) (bits 5-2) will Interrupt Status Register Only four LSBs passed parameter used. parameter where four LSBs logic will generate interrupt. Stop execution Message Sequence Control Program until Start issued host condition flag tests TRUE, otherwise continue execution next OpCode instruction list. Delay time specified Time parameter before executing next OpCode condition flag tests TRUE, otherwise continue execution next OpCode without delay. delay generated will Time Next Message Timer. Wait until Frame Time counter equal Zero before continuing execution Message Sequence Control Program condition flag tests TRUE, otherwise continue execution next OpCode without delay. Compare Time Value Frame Time Counter. LT/GP0 EQ/GP1 flag bits cleared based results compare. value CFT's parameter less than value frame time counter, then LT/GP0 NE/GP1 flags will set, while GT-EQ/GP0 EQ/GP1 flags will cleared. value CFT's parameter equal value frame time counter, then GT-EQ/GP0 EQ/GP1 flags will set, while LT/GP0 NE/GP1 flags will cleared. value CFT's parameter greater than current value frame time counter, then GTEQ/GP0 NE/GP1 flags will set, while LT/GP0 EQ/GP1 flags will cleared. Compare Time Value Message Time Counter. LT/GP0 EQ/GP1 flag bits cleared based results compare. value CMT's parameter less than value message time counter, then LT/GP0 NE/GP1 flags will set, while GT-EQ/GP0 EQ/GP1 flags will cleared. value CMT's parameter equal value message time counter, then GT-EQ/GP0 EQ/GP1 flags will set, while LT/GP0 NE/GP1 flags will cleared. value CMT's parameter greater than current value message time counter, then GT-EQ/GP0 NE/GP1 flags will set, while LT/GP0 EQ/GP1 flags will cleared.
0002
Subroutine Call
0003
Conditional
Subroutine Return Interrupt Request
0004
Used (Don't Care) Interrupt Pattern bits
Conditional
0006
Conditional
Halt
0007
Used (Don't Care)
Conditional
Delay
0008
Delay Time Value (Resolution LSB) Used (Don't Care)
Conditional
Wait Until Frame Timer Compare Frame Timer
0009
Conditional
000A
Delay Time Value (Resolution 100µS LSB)
Unconditional
Compare Message Timer
000B
Delay Time Value (Resolution LSB)
Unconditional
NOTE: While (Execute Message) instruction conditional, condition codes used enable use. ALWAYS NEVER condition codes used. eight general purpose flag bits, through GP7, also used. However, through used, imperative that host processor modify value specific general purpose flag that enabled particular message while that message being processed. Similarly, GT-EQ, flags, which only updates means instructions, also used. However, these flags dual use. Therefore, these used, imperative that host processor modify value specific flag (GP0 GP1) that enabled particular message while that message being processed. NORESP, ERR, XFER, MASKED STATUS SET, MESSAGE, RETRY0, RETRY1 condition codes available with instruction should used enable execution.
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TABLE OPERATIONS MESSAGE SEQUENCE CONTROL (CONT.)
INSTRUCTION Flag Bits MNEMONIC CODE (HEX) 000C PARAMETER Used set, clear, toggle (General Purpose) Flag bits (See description) CONDITIONAL UNCONDITIONAL Unconditional DESCRIPTION Used set, toggle, clear eight general purpose flags. table below illustrates Flag Bits instruction case (General Purpose Flag Bits parameter byte affect flag GP1, bits effect GP2, etc., according following rules: Load Time Counter 000D Time Value. Resolution (µs/LSB) defined bits Configuration Register Time Value (resolution µs/LSB) Used (Don't Care) Used (Don't Care) Conditional Effect Change Flag Clear Flag Toggle Flag
Load Time Counter with Time Value condition flag tests TRUE, otherwise continue execution next OpCode instruction list.
Load Frame Timer Start Frame Timer Push Time Register
000E
Conditional
Load Frame Timer Register with Time Value parameter condition flag tests TRUE, otherwise continue execution next OpCode instruction list. Start Frame Time Counter with Time Value Time Frame register condition flag tests TRUE, otherwise continue execution next OpCode instruction list. Push value Time Register General Purpose Queue condition flag tests TRUE, otherwise continue execution next OpCode instruction list. Push Block Status Word most recent message General Purpose Queue condition flag tests TRUE, otherwise continue execution next OpCode instruction list. Push Immediate data General Purpose Queue condition flag tests TRUE, otherwise continue execution next OpCode instruction list. Push data stored specified memory location General Purpose Queue condition flag tests TRUE, otherwise continue execution next OpCode instruction list. Wait logic "0"-to-logic transition EXT_TRIG input signal before proceeding next OpCode instruction list condition flag tests TRUE, otherwise continue execution next OpCode without delay. Execute (unconditionally) message referenced Message Control/Status Block Address. Following processing this message, condition flag tests TRUE, will toggle Message Control/Status Block Address, store Message Block Address updated value parameter following instruction code. result, next time that this line instruction list executed, Message Control/Status Block updated address (old address 0010h), rather than address, will processed. condition flag tests FALSE, value Message Control/Status Block Address parameter will change.
000F
Conditional
0010
Conditional
Push Block Status Word
0011
Used (Don't Care)
Conditional
Push Immediate Value Push Indirect
0012
Immediate Value
Conditional
0013
Memory Address
Conditional
Wait External Trigger Execute Flip
0014
Used (Don't Care)
Conditional
0015
Message Control Status Block Address
Unconditional
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TABLE CONDITION CODES
CODE NAME (BIT LT/GP0 INVERSE (BIT GT-EQ/ FUNCTIONAL DESCRIPTION Less than flag. This cleared based results compare. value CMT's parameter less than value message time counter, then LT/GP0 NE/GP1 flags will set, while GT-EQ/GP0 EQ/GP1 flags will cleared. value CMT's parameter equal value message time counter, then GT-EQ/GP0 EQ/GP1 flags will set, while LT/GP0 NE/GP1 flags will cleared. value CMT's parameter greater than current value message time counter, then GT-EQ/GP0 NE/GP1 flags will while LT/GP0 EQ/GP1 flags will cleared. Also, General Purpose Flag also cleared operation. Equal Flag. This cleared after operation. value CMT's parameter equal value message time counter, then EQ/GP1 flag will NE/GP1 will cleared. value CMT's parameter equal value message time counter, then NE/GP1 flag will EQ/GP1 will cleared. Also, General Purpose Flag also cleared operation. General Purpose Flags set, cleared, toggled operation. host processor set, clear, toggle these flags same instruction means GENERAL PURPOSE FLAG REGISTER.
EQ/GP1
NE/GP1
NORESP
RESP
NORESP indicates that either responded responded later than Response Timeout time. Enhanced Mini-ACE's Response Timeout Time defined MIL-STD-1553B time from mid-bit crossing parity last word transmitted mid-sync crossing Status Word. value Response Timeout value programmable from among nominal values 18.5, 22.5, 50.5, means bits Configuration Register indicates that received portion most recent message contained more violations 1553 message validation criteria (sync, encoding, parity, count, word count, etc.), RT's status word received from responding contained incorrect address field. most recent message, XFER will logic following completion valid (error-free) RT-to-BC transfer, RT-to-RT transfer, transmit mode code with data message. This logic following invalid message. GOOD DATA BLOCK TRANSFER always logic following BC-to-RT transfer, mode code with data, mode code without data. Loop Test effect GOOD DATA BLOCK TRANSFER. GOOD DATA BLOCK TRANSFER used determine transmitting portion RT-to-RT transfer error free. Indicates that both following conditions have occurred most recent message: more) Status Mask bits through Control Word logic corresponding bit(s) (are) (logic "1") received Status Word. case RESERVED BITS MASK (bit logic "0," Reserved Status Word bits being will result MASKED STATUS condition; and/or BROADCAST MASK ENABLED/XOR (bit Configuration Register logic MASK BROADCAST message's Control Word logic BROADCAST COMMAND RECEIVED received Status Word logic "1". MESSAGE indicates either format error, loop test failure, response error most recent message. Note that "Status Set" condition effect "BAD MESSAGE/GOOD MESSAGE" condition code. These bits reflect retry status most recent message. number times that message retried delineated these bits shown below: RETRY COUNT RETRY COUNT Number (bit (bit Message Retries ALWAYS should asserted (bit designate instruction unconditional. NEVER (bit used implement instruction.
XFER
XFER
MASKED STATUS
MASKED STATUS
MESSAGE RETRY0 RETRY1
GOOD MESSAGE RETRY0 RETRY1
ALWAYS
NEVER
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MESSAGE SEQUENCE CONTROL
Enhanced Mini-ACE message sequence control capability enables high degree offloading host processor. This includes using various timing functions enable autonomous structuring major minor frames. addition, implementing conditional jumps subroutine calls, message sequence control processor greatly simplifies insertion asynchronous, "out-of-band" messages.
(old address 0010h), will processed, rather than address. operation instruction illustrated FIGURE There multiple ways utilizing "execute flip" functionality. facilitate implementation double buffering data scheme individual messages. This allows message sequence control processor "ping-pong" between pair data buffers particular message. doing, host processor access Data Word blocks, while reads writes alternate Data Word block. second application "execute flip" capability association with message retries. This allows only switch buses when retrying failed message, automatically switch buses permanently future times that same message processed. This only provides high degree autonomy from host CPU, saves bandwidth, eliminating future attempts process messages RT's failed channel.
EXECUTE FLIP OPERATION
Enhanced Mini-ACE BC's XQF, "Execute Flip" operation, provides some unique capabilities. Following execution this unconditional instruction, condition code tests TRUE, will modify value current instruction's pointer parameter toggling pointer. That selected condition flag tests true, value parameter will updated value address 0010h. result, next time that this line instruction list executed, Message Control/Status Block updated address
(part INSTRUCTION LIST POINTER
MESSAGE CONTROL/STATUS BLOCK XX00h
POINTER
DATA BLOCK
MESSAGE CONTROL/STATUS BLOCK XX10h
POINTER
DATA BLOCK
FIGURE EXECUTE FLIP (XQF) OPERATION
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GENERAL PURPOSE QUEUE
Enhanced Mini-ACE allows creation general purpose queue. This data structure provides means message sequence processor convey information host. code repertoire provides mechanisms push various items this queue. These include contents Time Register, Block Status Word most recent message, immediate data value, contents specified memory address. FIGURE illustrates operation General Purpose Queue. Note that General Purpose Queue Pointer Register will always point next address location (modulo 64); that location following last location written message sequence control engine. enabled, GENERAL PURPOSE QUEUE ROLLOVER interrupt will issued when value queue pointer address rolls over 64-word boundary.
Enhanced Mini-ACE protocol design implements MIL-STD-1553B message formats dual redundant mode codes. design passed validation testing MILSTD-1553B compliance. Enhanced Mini-ACE performs comprehensive error checking, word format validation, checks various RT-to-RT transfer errors. main features Enhanced Mini-ACE choice memory management options. These include single buffering subaddress, circular buffering individual subaddresses, global circular buffering multiple all) subaddresses. Other features Enhanced Mini-ACE include interrupt conditions, interrupt status queue with filtering based valid and/or invalid messages, internal command illegalization, programmable busy subaddress, multiple options time tagging.
MEMORY ORGANIZATION
TABLE illustrates typical memory Enhanced Mini-ACE with RAM. Stack Pointers reside fixed locations shared address space: address 0100h (PCI BAR0 200h) Area Stack Pointer address 0104h (PCI BAR0 208h) Area Stack Pointer. addition Stack Pointer, there several other areas
REMOTE TERMINAL (RT) ARCHITECTURE
Enhanced Mini-ACE's architecture builds upon that Mini-ACE. Enhanced Mini-ACE provides multiprotocol support, with full compliance commonly used data standards, including MIL-STD-1553A, MILSTD-1553B, Notice STANAG 3838, General Dynamics 16PP303, McAirA3818, A5232, A5690. Enhanced Mini-ACE mode, there programmable flexibility enabling configured fulfill system requirements. This includes capability meet MIL-STD1553A response time requirement multiple options mode code subaddresses, mode codes, status word, word.
TABLE TYPICAL MEMORY (SHOWN RAM)
WORD ADDRESS (HEX) 0000-00FF 0100 0101 0102-0103 0104 0105 0106-0107 0108-010F 0110-013F 0140-01BF 01C0-023F 0240-0247 0248-025F BAR0 OFFSET (HEX) 0000-01FE 0200 0202 0204-0206 0208 020A 020C-020E 0210-021E 0220-027E 0280-037E 0380-047E 0480-048E 0490-04BE 04C0-04FE 0500-05FE 0600-07FE 0800-083E 0840-087E 1FC0-1FFE DESCRIPTION Stack Stack Pointer Global Circular Buffer Pointer RESERVED Stack Pointer Global Circular Buffer Pointer RESERVED Mode Code Selective Interrupt Table Mode Code Data Lookup Table Lookup Table Busy Lookup Table (not used) Data Block Data Block Command Illegalizing Table Data Block Data Block Data Block
GENERAL PURPOSE QUEUE Locations)
LAST LOCATION GENERAL PURPOSE QUEUE POINTER REGISTER
0260-027F 0280-02FF 0300-03FF 0400-041F 0420-043F
NEXT LOCATION
FIGURE GENERAL PURPOSE QUEUE
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TABLE LOOK-UP TABLES
AREA (INTERNAL MEMORY OFFSET) 0140 015F 0160 017F 0180 019F 01A0 01BF AREA (PCI BAR0 OFFSET) 0280 02BE 02C0 02FE 0300 033E 0340 037E AREA (INTERNAL MEMORY OFFSET) 01C0 01DF 01E0 01FF 0200 021F 0220 023F AREA (PCI BAR0 OFFSET) 0380 03BE 03C0 03FE 0400 043E 0440 047E DESCRIPTION COMMENT
Rx(/Bcst) Rx(/Bcst) SA31 SA31 Bcst Bcst SA31 SACW SACW SA31
Receive (/Broadcast) Lookup Pointer Table
Transmit Lookup Pointer Table
Broadcast Lookup Pointer Table (Optional)
Subaddress Control Word Table (Optional)
shared address space that designated fixed locations (all shown bold). These Area Area lookup tables, illegalization lookup table, busy lookup table, mode code data tables. lookup tables (reference TABLE provide mechanism allocating data blocks individual transmit, receive, broadcast subaddresses. lookup tables include subaddress control words well individual data block pointers. command illegalization used, address range 0300-03FF (PCI BAR0 0600-07FEh) used command illegalizing.
descriptor stack area, well individual data blocks, located non-fixed areas shared address space. Note that TABLE there area allocated "Stack This shown purpose illustration. Also, note that TABLE allocated area command stacks words. However, larger stack sizes possible. That command stack size programmed words messages), 512, 1024, 2048 words (512 messages) means bits Configuration Register
TABLE SUBADDRESS CONTROL WORD MEMORY MANAGEMENT OPTIONS
GLOBAL CIRCULAR BUFFER (bit SUBADDRESS CONTROL WORD BITS 128-Word 256-Word 512-Word 1024-Word 2048-Word 4096-Word 8192-Word (for receive broadcast subaddresses only) Global Circular Buffer: buffer size specified Configuration Register bits 11-9. pointer global circular buffer stored address 0101 (BAR0 0202h) Area address 0105 (BAR0 020Ah) Area Subaddress specific circular buffer specified size. MEMORY MANAGEMENT SUBADDRESS BUFFER SCHEME DESCRIPTION Single Message Reserved future
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MEMORY MANAGEMENT
Enhanced Mini-ACE provides variety memory management capabilities. with ACE, Mini-ACE(Plus) Enhanced Mini-ACE, choice memory management scheme fully programmable transmit/receive/broadcast subaddress basis. compliance with MIL-STD-1553B Notice received data from broadcast messages optionally separated from nonbroadcast received data. each receive broadcast subaddress, either single-message data block, variable-sized (128 8192 words) subaddress circular buffer allocated data storage. Single Buffered mode strongly recommended transmitted data words. memory management scheme individual subaddresses designated means subaddress control word (reference TABLE 56). received data, there also global circular buffer mode. this configuration, data words received from multiple all) subaddresses stored common circular buffer structure. Like subaddress circular buffer, size global circular buffer programmable, with range 8192 data words.
addition helping ensure data sample consistency, circular buffer options provide means greatly reducing host processor overhead multi-message bulk data transfer applications. End-of-message interrupts enabled either globally (following messages), following error messages, transmit/receive/broadcast subaddress mode code basis, when circular buffer reaches midpoint (50% boundary) lower (100%) boundary. pair interrupt status registers allow host processor determine cause interrupts means single read operation.
SINGLE BUFFERED MODE
operation single buffered mode illustrated FIGURE single buffered mode, respective lookup table entry must initialized host processor. Received data words written transmitted data words read from data word block with starting address referenced lookup table pointer. single buffered mode, current lookup table pointer updated Enhanced MiniACE memory management logic. Therefore, subsequent message received same subaddress, same Data Word block will overwritten overread.
CONFIGURATION REGISTER
STACK POINTERS
DESCRIPTOR STACKS
LOOK-UP TABLE (DATA BLOCK ADDR)
DATA BLOCKS
CURRENT AREA
BLOCK STATUS WORD TIME WORD DATA BLOCK POINTER RECEIVED COMMAND WORD LOOK-UP TABLE ADDR (See note)
DATA BLOCK
DATA BLOCK
Note: Lookup table used mode commands when enhanced mode codes enabled.
FIGURE SINGLE BUFFERED MODE
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CIRCULAR BUFFER MODE
operation Enhanced Mini-ACE's circular buffer memory management mode illustrated FIGURE single buffered mode, individual lookup table entries initially loaded host processor. start each message, lookup table entry stored third position respective message block descriptor descriptor stack area RAM. Receive transmit data words transferred (from) circular buffer, starting location referenced lookup table pointer. general, location after last data word written read (modulo circular buffer size) during message written respective lookup table location during end-of-message sequence. doing, data next message respective transmit, receive(/broadcast), broadcast subaddress will accessed from next lower contiguous block locations circular buffer. case receive broadcast receive) message with data word error, there option such that lookup table pointer will only updated following receipt valid message. That pointer will updated following receipt message with error data word. This allows failed messages bulk data transfer retried without disrupting circular buffer data structure, without intervention RT's host processor.
GLOBAL CIRCULAR BUFFER
Beyond programmable choice single buffer mode circular buffer mode, programmable individual subaddress basis, Enhanced Mini-ACE architecture provides additional option, variable sized global circular buffer. global circular buffer mode, data multiple receive subaddresses stored same circular buffer data structure. size global circular buffer programmed 128, 256, 512, 1024, 2048, 4096, 8192 words, means bits Configuration Register shown TABLE individual subaddresses mapped global circular buffer means their respective subaddress control words. pointer Global Circular Buffer will stored location 0101 (for Area location 0105 (for Area global circular buffer option provides highly efficient method storing received message data. allows frequently used subaddresses mapped individual data blocks, while also providing method asynchronously received messages infrequently used subaddresses logged common area. Alternatively, global circular buffer provides efficient means storing received data words subaddresses. Under this method, received data words stored chronologically, regardless subaddress.
CONFIGURATION REGISTER
STACK POINTERS
DESCRIPTOR STACK
LOOK-UP TABLES
CIRCULAR DATA BUFFER
CURRENT AREA BLOCK STATUS WORD TIME WORD DATA BLOCK POINTER RECEIVED COMMAND WORD LOOK-UP TABLE ADDRESS POINTER CURRENT DATA BLOCK LOOK-UP TABLE ENTRY POINTER NEXT DATA BLOCK RECEIVED (TRANSMITTED) MESSAGE DATA (NEXT LOCATION)
128,
8192 WORDS
Notes:
TX/RS/BCST_SA look-up table entry updated following valid receive (broadcast) message following completion transmit message Global Circular Buffer Mode, pointer read from re-written Address 0101 (for Area Adress 0105 (for Area
CIRCULAR BUFFER ROLLOVER
FIGURE CIRCULAR BUFFERED MODE
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DESCRIPTOR STACK
descriptor stack provides chronology messages processed Enhanced Mini-ACE Reference FIGURE FIGURE Similar mode, there four-word block descriptor Stack each message processed. four entries each block descriptor Block Status Word, Time Word, pointer start message's data block, 16-bit received Command Word. Block Status Word includes indications whether particular message ongoing been completed, what channel received indications illegal commands, flags denoting various message error conditions. subaddress circular buffering, global circular buffering modes, data block pointer used locating data blocks specific messages. Note that mode code commands, there option store transmitted received data word third word descriptor, place data block pointer. Time Word provides 16-bit indication relative time individual messages. resolution Enhanced Mini-ACE's time programmable from among µs/LSB. There also provision using external clock input time (consult factory). enabled, there time rollover interrupt, which issued when value time rolls over from FFFF(hex) Other time options include capabilities clear time register following receipt Synchronize (without data) mode command and/or time following receipt Synchronize (with data) mode command. latter, there added option filter "set" capability based received data word being equal logic "0".
INTERRUPTS
Enhanced Mini-ACE offers great deal flexibility terms interrupt processing. means Enhanced Mini-ACE's Interrupt Mask Registers, programmed issue interrupt requests following events/conditions: End-of-(every)Message, Message Error, Selected (transmit receive) Subaddress, 100% Circular Buffer Rollover, Circular Buffer Rollover, 100% Descriptor Stack Rollover, Descriptor Stack Rollover, Selected Mode Code, Transmitter Timeout, Illegal Command, Interrupt Status Queue Rollover.
INTERRUPTS ROLLOVERS STACKS, CIRCULAR BUFFERS
Enhanced Mini-ACE Monitor capable issuing host interrupts when subaddress circular buffer pointer stack pointer crosses mid-point boundary. circular buffers, this applicable both transmit receive subaddresses. Reference FIGURE There four interrupt mask interrupt status register bits associated with rollover function: circular buffer; command (descriptor) stack; Monitor command (descriptor) stack; Monitor data stack.
rollover interrupt beneficial performing bulk data transfers. example, when using circular buffering particular receive subaddress, rollover interrupt will inform
DESCRIPTOR STACK
BLOCK STATUS WORD TIME WORD DATA BLOCK POINTER RECEIVED COMMAND WORD
LOOK-UP TABLE
CIRCULAR BUFFER* (128,256,.8192 WORDS)
DATA POINTER
RECEIVED (TRANSMITTED) MESSAGE DATA
ROLLOVER INTERRUPT
Note
example shown Subaddress Circular Buffer. 100% Rollover Interrupts also applicable Global Circular Buffer, Command Stack, Monitor Command Stack, Monitor Data Stack.
100%
100% ROLLOVER INTERRUPT
FIGURE 100% ROLLOVER INTERRUPTS
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host processor when circular buffer half full. that time, host proceed read received data words upper half buffer, while Enhanced Mini-ACE writes received data words lower half circular buffer. Later, when issues 100% circular buffer rollover interrupt, host proceed read received data from lower half buffer, while Enhanced Mini-ACE continues write received data words upper half buffer.
Pointer Register will always point next location (modulo following last vector/pointer pair written Enhanced Mini-ACE Monitor, RT/Monitor. Each event that causes interrupt results two-word entry written queue. first word entry interrupt vector. vector indicates which interrupt event(s)/condition(s) caused interrupt. interrupt events classified into categories: message interrupt events non-message interrupt events. Messagebased interrupt events include End-of-Message, Selected mode code, Format error, Subaddress control word interrupt, Circular buffer rollover, Handshake failure, Command stack rollover, transmitter timeout, data stack rollover, command stack rollover, Command stack rollover, data stack rollover, command stack rollover, Circular buffer rollover. Non-message interrupt events/conditions include time rollover, address parity error, parity error, completed. interrupt vector (interrupt status) word indicates whether entry message interrupt event logic "1") non-message interrupt event logic "0"). possible entry queue indicate both message interrupt non-message interrupt. illustrated FIGURE message interrupt event, parameter word pointer. pointer will reference first word command stack descriptor (i.e., Block Status Word).
INTERRUPT STATUS QUEUE
Enhanced Mini-ACE Monitor, combined RT/Monitor modes include capability generating interrupt status queue. illustrated FIGURE this provides chronological history interrupt generating events conditions. addition Interrupt Mask Register, Interrupt Status Queue provides additional filtering capability, such that only valid messages and/or only invalid messages result creation entry Interrupt Status Queue. Queue entries invalid and/or valid messages individually disabled means bits Configuration Register pointer Interrupt Status Queue stored INTERRUPT VECTOR QUEUE POINTER REGISTER (register address 1F). This register must initialized host, subsequently incremented message processor. interrupt status queue words deep, providing capability store entries messages. queue rolls over addresses modulo events that result queue entries include both message-related nonmessage related events. Note that Interrupt Vector Queue
INTERRUPT STATUS QUEUE Locations)
DESCRIPTOR STACK
INTERRUPT VECTOR PARAMETER (POINTER) INTERRUPT VECTOR QUEUE POINTER REGISTER (IF) NEXT VECTOR BLOCK STATUS WORD TIME DATA BLOCK POINTER RECEIVED COMMAND DATA WORD BLOCK
FIGURE (AND MONITOR) INTERRUPT STATUS QUEUE (SHOWN MESSAGE INTERRUPT EVENT)
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Parity Error non-message interrupt, parameter will address where parity check failed. address Parity Error Time Rollover non-message interrupts, parameter used; will have value 0000. enabled, INTERRUPT STATUS QUEUE ROLLOVER interrupt will issued when value queue pointer address rolls over 64-word address boundary. NOTE: Please Appendix Enhanced Mini-ACE Users Guide important information applicable only MODE operation, enabling interrupt status queue specific non-message interrupts.
shared RAM; transfer data words shared RAM.
ADDRESS
Enhanced Mini-ACE offers several different options designating Remote Terminal address. These include following: hardwired, means ADDRESS inputs, ADDRESS PARITY input; means ADDRESS (and PARITY) inputs, latched hardware, rising edge RT_AD_LAT input signal; input means ADDRESS (and PARITY) inputs, latched host software; fully software programmable, means internal register. four configurations, address readable host processor.
COMMAND ILLEGALIZATION
Enhanced Mini-ACE provides internal mechanism Command Word illegalizing. means 256-word area shared RAM, host processor designate that message illegalized, based command word bit, subaddress, word count/mode code fields. Enhanced Mini-ACE illegalization scheme provides maximum flexibility, allowing subset 4096 possible combinations broadcast/own address, bit, subaddress, word count/mode code illegalized. address Enhanced Mini-ACE's illegalizing table illustrated TABLE
BUILT-IN TEST (BIT) WORD
Enhanced Mini-ACE's internal Builtin-Test (BIT) Word indicated TABLE
OTHER FEATURES
Enhanced Mini-ACE includes options Terminal flag status word either under software control and/or automatically following failure loopback self-test. Other software programmable options include software programmable status words, automatic clearing Service Request following receipt Transmit vector word mode command, options regarding Data Word transfers Busy Message error (illegal) Status word bits, options handling 1553A reserved mode codes.
BUSY
Enhanced Mini-ACE provides different methods setting Busy status word bit: globally, means Configuration Register T/R-bit/subaddress basis, means lookup table. host asserts BUSY Configuration Register Enhanced Mini-ACE will respond non-broadcast commands with Busy Status Word. Alternatively, there Busy lookup table Enhanced Mini-ACE shared RAM. means this table, possible host processor busy selectable subset combinations broadcast/own address, bit, subaddress. busy transmit command, Enhanced Mini-ACE will respond with busy status word, will transmit data words. busy receive command, will also respond with busy status set. There programmable options regarding reception data words non-mode code receive command which busy: transfer received data words
MONITOR ARCHITECTURE
Enhanced Mini-ACE includes three monitor modes: Word Monitor mode. selective message monitor mode. combined RT/message monitor mode.
applications, recommended that selective message monitor mode used, rather than word monitor mode. Besides providing monitor filtering based address, bit, subaddress, message monitor eliminates need determine start messages software.
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TABLE ILLEGALIZATION TABLE MEMORY
INTERNAL ADDRESS BAR0 OFFSET DESCRIPTION Brdcst MC15-0 Brdcst MC31-16 Brdcst WC15-0 Brdcst WC31-16 Brdcst MC15-0 Brdcst MC31-16 Brdcst WC15-0 Brdcst MC31-16 Brdcst WC31-16 Brdcst MC15-0 Brdcst MC31-16 Addr MC15-0 Addr MC31-16 Addr WC15-0 Addr WC31-16 Addr MC15-0 Addr MC31-16 Addr MC15-0 Addr MC31-16 Addr WC15-0 Addr WC31-16 Addr WC15-0 Addr WC31-16 Addr MC15-0 Addr MC31-16
WORD MONITOR MODE
Word Monitor Terminal mode, Enhanced Mini-ACE monitors both 1553 buses. After software initialization Monitor Start sequences, Enhanced Mini-ACE stores Command, Status, Data Words received from both buses. each word received from either bus, pair words stored Enhanced Mini-ACE's shared RAM. first word word received from 1553 bus. second word Monitor Identification (ID), "Tag" word. word contains information relating channel, word validity, inter-word time gaps. data words stored circular buffer using whole shared address space.
WORD MONITOR MEMORY typical word monitor memory illustrated TABLE TABLE assumes address space Enhanced Mini-ACE's monitor. Active Area Stack pointer provides address where first monitored word stored. example, assumed that Active Area Stack Pointer Area (location 0100) initialized 0000. first received data word stored location 0000, word first word stored location 0001, etc.
current Monitor address maintained means counter register. This value read means
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Data Stack Address Register. important note that when counter reaches Stack Pointer address 0100 0104, initial pointer value stored this shared location will overwritten monitored data Words. When internal counter reaches address FFFF 0FFF, Enhanced Mini-ACE with RAM), counter rolls over 0000.
sages begin end, stores messages into RAM, based programmable filter address, bit, subaddress). selective monitor configured just monitor, combined RT/Monitor. combined RT/Monitor mode, Enhanced Mini-ACE functions address (including broadcast messages), selective message monitor other addresses. Enhanced MiniACE Message Monitor contains stacks, command stack data stack, that independent from BC/RT command stack. pointers these stacks located fixed locations RAM.
WORD MONITOR TRIGGER Word Monitor mode, there pattern recognition trigger pattern recognition interrupt. 16-bit compare word both trigger interrupt stored Monitor Trigger Word Register. pattern recognition interrupt enabled setting Pattern Trigger Interrupt Mask Register. pattern recognition trigger enabled setting Trigger Enable Configuration Register selecting either Start-on-trigger Stop-on-trigger Configuration Register
Word Monitor also started means low-to-high transition EXT_TRIG input signal.
MONITOR SELECTION FUNCTION Following receipt valid command word Selective Monitor mode, Enhanced Mini-ACE will reference selective monitor lookup table determine this particular command enabled. address this location determined means offset based Address, bit, Subaddress current command word, concatenating monitor lookup table base address 0280 (hex). location within this word determined subaddress bits current command word.
specified lookup table logic "0", command enabled, Enhanced Mini-ACE will ignore this command. this logic "1", command enabled Enhanced Mini-ACE will create entry monitor command descriptor stack (based monitor command stack
SELECTIVE MESSAGE MONITOR MODE
Enhanced Mini-ACE Selective Message Monitor provides monitoring 1553 messages with filtering based address, bit, subaddress with host processor intervention. autonomously distinguishing between 1553 command status words, Message Monitor determines when mes-
TABLE WORD
0(LSB) DESCRIPTION LOOP TEST FAILURE LOOP TEST FAILURE HANDSHAKE FAILURE TRANSMITTER SHUTDOWN TRANSMITTER SHUTDOWN TERMINAL FLAG INHIBITED TEST FAILURE HIGH WORD COUNT WORD COUNT INCORRECT SYNC RECEIVED PARITY MANCHESTER ERROR RECEIVED RT-to-RT SYNC ADDRESS ERROR RT-to-RT RESPONSE ERROR RT-to-RT COMMAND WORD ERROR COMMAND WORD CONTENTS ERROR 15(MSB) TRANSMITTER TIMEOUT
TABLE TYPICAL WORD MONITOR MEMORY
ADDRESS 0000 0001 0002 0003 0004 0005 0100 FFFF FUNCTION First Received 1553 Word First Identification Word Second Received 1553 Word Second Identification Word Third Received 1553 Word Third Identification Word Stack Pointer (Fixed Location gets overwritten) Received 1553 Words Identification Words
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TABLE MONITOR SELECTION TABLE LOOKUP ADDRESS
15(MSB) 0(LSB) DESCRIPTION Logic Logic Logic Logic Logic Logic Logic Logic Logic RTAD_4 RTAD_3 RTAD_2 RTAD_1 RTAD_0 TRANSMIT RECEIVE SUBADDRESS
address definition Selective Monitor Lookup Table illustrated TABLE
SELECTIVE MESSAGE MONITOR MEMORY ORGANIZATION typical memory Enhanced Mini-ACE, Selective Message Monitor mode, assuming space, illustrated TABLE This mode operation defines several fixed locations RAM. These locations allocated which none them overlap with fixed locations. This allows combined RT/Selective Message Monitor mode.
fixed memory consists Monitor Command Stack Pointers (locations hex), Monitor Data Stack Pointers (locations hex), Selective Message Monitor Lookup Table (locations 0280 through 02FF hex). this example, Monitor Command Stack size assumed words, Monitor Data Stack size assumed words. FIGURE illustrates Selective Message Monitor operation. Upon receipt valid Command Word, Enhanced MiniACE will reference Selective Monitor Lookup Table determine current command enabled. current command disabled, Enhanced Mini-ACE monitor will ignore (and store) current message. command enabled, monitor will create entry Monitor Command Stack address location referenced Monitor Command Stack Pointer, entry monitor data stack starting location referenced monitor data stack pointer.
pointer), store data status words associated with command into sequential locations monitor data stack. addition, RT-to-RT transfer which receive command selected, second command word (the transmit command) stored monitor data stack.
Note: After command discarded monitor will immediately look another "Command." Where only subset Subaddresses enabled, possible that succeeding Status word captured "Command". This will always flagged error because Word Count timing will fail.
CONFIGURATION REGISTER MONITOR COMMAND STACK POINTERS
MONITOR COMMAND STACKS
MONITOR DATA STACKS
CURRENT AREA BLOCK STATUS WORD TIME WORD CURRENT COMMAND WORD DATA BLOCK POINTER RECEIVED COMMAND WORD MONITOR DATA BLOCK MONITOR DATA BLOCK
NOTE
THIS (NOT SELECTED) WORDS STORED EITHER COMMAND STACK DATA STACK. ADDITION, COMMAND DATA STACK POINTERS WILL UPDATED.
MONITOR DATA STACK POINTERS
SELECTIVE MONITOR LOOKUP TABLES OFFSET BASED RTA4-RTA0, T/R, SELECTIVE MONITOR ENABLE (SEE NOTE)
FIGURE SELECTIVE MESSAGE MONITOR MEMORY MANAGEMENT
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TABLE TYPICAL SELECTIVE MESSAGE MONITOR MEMORY (shown "Monitor only" mode)
ADDRESS (HEX) 0100-0101 0102 0103 0104-0105 0106 0107 0108-027F 0280-02FF 0300-03FF 0400-07FF 0800-0FFF DESCRIPTION Used Monitor Command Stack Pointer (fixed location) Monitor Data Stack Pointer (fixed location) Used Monitor Command Stack Pointer (fixed location) Monitor Data Stack Pointer (fixed location) Used Selective Monitor Lookup Table Used Monitor Command Stack Monitor Data Stack
history interrupt generating events. Besides Interrupt Mask Registers, Interrupt Status Queue provides additional filtering capability, such that only valid messages and/or only invalid messages result entries Interrupt Status Queue. interrupt status queue words deep, providing capability store entries monitored messages.
MISCELLANEOUS
1553 CLOCK INPUT
Enhanced Mini-ACE decoder capable operating from clock input. clock frequency specified means host processor writing Configuration Register
ENCODER/DECODERS
format information data stack depends format message that processed. example, BC-to-RT transfer (receive command), monitor will store command word monitor command descriptor stack, with data words receiving RT's status word stored monitor data stack. size monitor command stack programmable, with choices 256, words. monitor data stack size programmable with choices 512, 16K, words. selected clock frequency, there internal logic derive necessary clocks Manchester encoder decoders. clock frequencies, decoders sample receiver outputs both edges input clock. effect doubling decoders' sampling frequency, this serves widen tolerance zero-crossing distortion, reduce error rate.
TIME
Enhanced Mini-ACE includes internal read/writable Time Register. This register read/writable 16-bit counter with programmable resolution either LSB. Another option allows software controlled incrementing Time Register. This supports self-test Time Register. each message processed, value Time Register loaded into second location respective descriptor stack entry ("TIME WORD") BC/RT/MT modes. functionality Time Register compatible with ACE/Mini-ACE (Plus) includes: capability issue interrupt request Interrupt Status Register when Time Register rolls over FFFF 0000; mode, capability automatically clear Time Register following reception Synchronize (without data) mode command, load Time Register following Synchronize (with data) mode command. Additional time features supported Enhanced Mini-ACE include capability transmit contents Time Register data word Synchronize (with data) mode command; capability "filter" data word Synchronize with data mode command, only loading Time Register received data word "0"; instruction enabling Message Sequence Control engine autonomously load
MONITOR INTERRUPTS Selective monitor interrupts issued End-of-message conditions relating monitor command stack pointer monitor data stack pointer. shown FIGURE latter includes Command Stack Rollover, Command Stack 100% Rollover, Data Stack Rollover, Data Stack 100% Rollover.
rollover interrupts used inform host processor when command stack data stack half full. that time, host proceed read received messages upper half respective stack, while Enhanced Mini-ACE monitor writes messages lower half stack. Later, when monitor issues 100% stack rollover interrupt, host proceed read received data from lower half stack, while Enhanced Mini-ACE monitor continues write received data words upper half stack.
INTERRUPT STATUS QUEUE Like Enhanced Mini-ACE Selective Monitor mode includes capability generating interrupt status queue. illustrated FIGURE this provides chronological
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Time Register with specified value; instruction enabling Message Sequence Control engine write value Time Register General Purpose Queue.
INTERRUPTS
Enhanced Mini-ACE series terminals provide many programmable options interrupt generation handling. interrupt output (INT) software programmable modes operation: level output cleared under software control, level output automatically cleared following read Interrupt Status Register #2). Individual interrupts enabled Interrupt Mask Registers. host processor determine cause interrupt reading Interrupt Status Registers, which provide current state interrupt events conditions. Interrupt Status Registers updated ways. interrupt handling mode, particular Interrupt Status Register will updated only event occurs corresponding Interrupt Mask Register enabled. enhanced interrupt handling mode, particular Interrupt Status Registers will updated event/condition occurs regardless value corresponding Interrupt Mask Register bit. either case, respective Interrupt Mask Register used enable interrupt particular event/condition. Enhanced Mini-ACE supports interrupt events from ACE/Mini-ACE (Plus) Enhanced Mini-ACE including Parity Error, Transmitter Timeout, BC/RT Command Stack Rollover, Command Stack Data Stack Rollover, Handshake Error, Retry, Address Parity Error, Time Rollover, Circular Buffer Rollover, Message, Subaddress, End-of-Frame, Format Error, Status Set, Mode Code, Trigger, End-of-Message. Enhanced Mini-ACE's Enhanced mode, there four user-defined interrupt bits. Message Sequence Control Engine includes instruction enabling issue these interrupts time. Monitor modes, Enhanced Mini-ACE architecture includes Interrupt Status Queue. This provides mechanism logging messages that result interrupt requests. Entries Interrupt Status Queue filtered such that only valid and/or invalid messages will result entries queue.
Enhanced Mini-ACE incorporates additional interrupt conditions beyond ACE/Mini-ACE (Plus), based addition Interrupt Mask Register Interrupt Status Register This accomplished chaining Interrupt Status Registers using INTERRUPT CHAIN (bit Interrupt Status Register indicate that interrupt occurred Interrupt Status Register Additional interrupts include "SelfTest Completed", masking bits Enhanced Control Interrupts, Rollover interrupts Command Stack, Circular Buffers, Command Stack, Data Stack; Code Parity Error, (RT) Illegal Command, (BC) General Purpose Queue (RT/MT) Interrupt Status Queue Rollover, Call Stack Pointer Register Error, Trap Code, four UserDefined interrupts Enhanced mode.
PARITY
BC/RT/MT version Enhanced Mini-ACE available with options words internal RAM. option, bits wide. internal allows parity generation write accesses, parity checking read accesses. When Enhanced MiniACE detects parity error, reports host processor means interrupt register bit. Also, Selective Message Monitor modes, address(es) where parity error(s) detected will stored Interrupt Status Queue enabled). FIGURE illustrates generic connection diagram between "Initiator" Enhanced Mini-ACE "Target." following timing diagrams illustrate commands that Enhanced Mini-ACE responds Note that these diagrams meant show basic operation Enhanced Mini-ACE itself show masters inserting wait states, masters burst reading writing past address boundaries, masters writing into full FIFO, etc. help understand following timing diagrams explanation basic architecture Enhanced Mini-ACE helpful. Enhanced Mini-ACE thought very successful Enhanced Mini-ACE terminal family integrated with 3.3V 33MHz target interface. simplify descriptions Enhanced Mini-ACE architecture, term will used substitute "Enhanced Mini-ACE" even though 1553 terminal function really Enhanced Mini-ACE. When reference made memory (BAR0) registers (BAR1
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BU-62743/62843/62864 B-05/04-0
Vcc/GND
AD0-AD31 Tx/Rx_A C/BE[0]#-C/BE[3]#
FRAME# TRDY#
Tx/Rx_A Tx/Rx_B
"Master"
IRDY#
STOP#
Enhanced Mini-ACE "Target"
Tx/Rx_B
DEVSEL# IDSEL INTA# RTAD0-RTAD4 SSFLAG/EXT_TRIG RTADP INCMD/MCRST
PERR# SERR#
RT_AD_LAT
TX_INH_A/B PCI_CLK MSTCLR
FIGURE INITIATOR ENHANCED MINI-ACE TARGET INTERFACE
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00-FCh) these functions part portion die. These functions accessed write FIFO (for writes) delayed read request logic (for reads). "PCI interface registers" (BAR1 800-81Ch) part interface portion written read directly from bus, without write FIFO delayed read request logic. Enhanced Mini-ACE's basic transaction takes clocks, command phase. example, single write location within Enhanced Mini-ACE's mem-
space takes clocks, shown FIGURE Note that this single write, attempted burst write: FRAME# held asserted master. Also note that write registers memory actually write into write FIFO whereas write interface registers (BAR1 800-81Ch) write registers themselves.
PCICLK C/BE[3:0]# FRAME# IRDY# TRDY# STOP# DEVSEL#
ADRS
50ns
100ns
150ns
DATA Byte Enables
single write legal memory location (C/BE#
FIGURE SINGLE MEMORY WRITE ENHANCED MINI-ACE
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TABLE provides timing parameters 3.3V signaling environments applicable Enhanced Mini-ACE, FIGURE shows timing reference points. timing parameters apply other timing diagrams, illustrated. Enhanced Mini-ACE conforms revision Local specification. timing parameters provided here ease reference only.
TABLE INTERFACE TIMINGS
SYMBOL PARAMETER signal valid delay Input setup time Input hold time from UNITS
FIGURE illustrates read from Enhanced Mini-ACE's configuration space. Enhanced Mini-ACE only responds Type Zero configuration access: AD[1:0] must during command phase. Enhanced Mini-ACE will drive full Dword lines independent which byte enables asserted during configuration read.
50ns 100ns 150ns
PCICLK
DATA
ADDRS
C/BE[3:0]# FRAME# IRDY# TRDY# STOP# DEVSEL# IDSEL
single read from PACE configuration space (C/BE# with timing parameters. AD[31:0]: address driven master; data driven PACE
ByteEnables
FIGURE SINGLE READ CONFIGURATION SPACE WITH TIMING
FIGURE illustrates single write Enhanced Mini-ACE configuration space. Enhanced Mini-ACE only responds Type Zero configuration access: AD[1:0] must during command phase. Note that combinations byte enables configuration writes supported. byte enables asserted during burst write configuration space internal write will occur, internal address will incremented.
PCICLK AD[31:0] C/BE[3:0]# FRAME# IRDY# TRDY# STOP# DEVSEL# IDSEL
single write PACE configuration space (C/BE# ADRS DATA
50ns
100ns
150ns
FIGURE SINGLE WRITE CONFIGURATION SPACE
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FIGURE shows specific case memory reads from PCI-ACE interface registers BAR1 800h-81Ch. Note that these registers accessed quickly without Delayed Read Request (DRR) mechanism required reads from other memory locations (see next section).
PCICLK C/BE[3:0]# FRAME# IRDY# TRDY# STOP# DEVSEL#
ADRS Byte Enables DATA
50ns
100ns
150ns
memory read from PCI-ACE interface register space (BAR1 800-81Ch)
FIGURE READ PCI-ACE REGISTERS (BAR1 800-81
FIGURE illustrates process reading memory (BAR0) register (BAR1 00-FCh) location. actual read shown that single word read, ~600 response time shown, following text timing formula tables. write FIFO empty there isn't previous Delayed Read Request (DRR) pending, read from these locations enques DRR, which then processed Enhanced Mini-ACE. either these conditions true, Enhanced Mini-ACE will respond with Retry, will enque DRR.
250ns 500ns 750ns
PCICLK AD[31:0] C/BE[3:0]# FRAME# IRDY# TRDY# STOP# DEVSEL#
memory read from registers/memory with pending FIFO empty produces Retry enques DRR. Master should attempt read soon possible (preferably within clocks). read produces disconnect with data, complete
FIGURE READ MEMORY/REGISTER
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Enhanced Mini-ACE responds first read with Retry. rules master must repeat same exact request until completes. This shown master's second read attempt, which also produces Retry. Each repeated read request from master will target terminated with Retry until data from enqued Delayed Read Request (DRR) present Enhanced Mini-ACE's interface. successful completion shown third read request, which produces Disconnect with Data. This process applies memory read from legal address space OTHER than PCI-ACE interface registers BAR1 offset 800-81Ch. Note that conditions enquing that write FIFO must empty. efficient bandwidth, driver software should written such that checks FIFO condition (BAR1 800-81CH registers directly readable, bypassing mechanism) before reading from other Enhanced Mini-ACE locations. FIFO empty (BAR1 800h FIFO empty flag) read attempted, master will using bandwidth repeating read request while FIFO empties, BEFORE read request actually enqued DRR. When reading memory (BAR0), combination byte enables supported, Enhanced Mini-ACE will drive entire word onto lines when only single byte enable word asserted. When reading registers (BAR 00-FCh), byte enable combinations where only single byte within word requested will cause Enhanced Mini-ACE terminate transaction with target abort. Enhanced Mini-ACE will drive zeros onto lines only upper word byte enables byte enables asserted. With relation actual timing, double word reads memory (BAR0) will take longer complete than single word memory reads because internal memory data path bits wide. addition, read cycles will take longer complete with slower clocks. TABLE min/max formulas calculating completion time various types reads.
third case returns zeroes shown only completeness. following examples have same conditions: clock 33MHz, clock 16MHz, contention. Single word read time 62.5 552.5 time 30nS 62.5 Double word read time 62.5 1077.5 time 30nS 62.5 1167.5 addition, TABLE amount clocks that should added maximum time active.
TABLE ADDITIONAL DELAY CONTESTED ACCESS
OPERATING MODE Enhanced access enabled, single word xfer Enhanced access enabled, double word xfer Enhanced access disabled, single word xfer Enhanced access disabled, double word xfer MAXIMUM ADDITIONAL CLOCKS
Enhanced access controlled Configuration Register
FIGURE illustrates Dword word) memory write burst, with write FIFO empty with enough free space absorb Dwords FIFO). write FIFO accepts memory writes memory (BAR0) registers (BAR1 offset FCh). does accept writes interface registers BAR1 offset 800-81Ch. Writes BAR1 800-81Ch space directly into interface registers. byte write shown could entire 1553 message being written memory. Writes into space must word Dword. only byte enable asserted word, Enhanced Mini-ACE terminates transaction with Target-Abort. Writes into 00-FCh space must word Dword. only byte enable asserted word, Enhanced Mini-ACE terminates transaction with Target-Abort. Since registers this space really registers packed into lower word structure, only lower word Dword writes transfer bits into these registers. addition, spec, Memory Write Invalidate (C/BE[3:0]# command will aliased basic Memory Write command timing diagram would look same FIGURE BU-62743/62843/62864 B-05/04-0
TABLE MIN/MAX DELAYED READ FORMULAS
TYPE READ TIME FORMULA TIME FORMULA
memory (BAR0), PCI_CLKperiod PCI_CLKperiod double word ACE_CLKperiod ACE_CLKperiod memory (BAR0) single word register (BAR1, double word lower word) CBEN# asserted register (BAR1) upper word
PCI_CLKperiod ACE_CLKperiod
PCI_CLKperiod ACE_CLKperiod
PCI_CLKperiod
PCI_CLKperiod
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