SED1797D0B Series SED1575 Series Overview Features Block Dia
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MF1225-01
SED1797D0B Series
SED1575 Series
Overview Features Block Diagram Bump Layout Bump Coordinates Functions Pins Operations Shift Data Transfer Gate Output Timing Chart Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics within Recommended Operating Conditions Characteristics Characteristics Input Timing Characteristics Output Timing Characteristics
SED1797 Series
Overview
SED1797 gate driver drive TFT-LCD panel. amplitude gate output voltage maximum 40V, enabling output negative voltage. This incorporates power circuit internal logic, eliminating need supply separate power source internal logic. bump layout this compatible with implementation, possible achieve narrowframed thin type module.
Features
Gate output voltage level: values (VON/VOFF) Gate output voltage amplitude: Max. Input signal amplitude: Min. 1.8V Number gate drive outputs: selection output shift direction possible. Asynchronous reset data shift register possible. level shift circuit enables output negative voltage from gate outputs Complete with built-in power circuit internal logic. This does incorporate X-ray resistant lightresistant design.
using semiconductor devices, follow precautions below. "Precautions Handling Product against Light" Characteristics semiconductor devices affected when exposed light. Therefore, this product malfunction when exposed light. order prevent malfunction exposure light, take following points consideration substrate other product which this mounted. Develop design implementation methods achieve light-shielding structure actual operation. inspection process, prepare environment where light-shielding feature tested. Light-shielding design should include considerations light-shielding features front backside surfaces well side faces
EPSON
SED1797 Series
Block Diagram
O240
Gate output circuit: bits VOFF
VDDH Level shifter
Level conversion
DIO1 XRES DIO2
Control logic Two-way shift register
EPSON
SED1797 Series
Bump Layout
(0,0)
Shipping form: Chip size: Wafer thickness: Bump shape: Bump height (general standard) Deviation bump height (within chip): Bump hardness: Bump size:
Input Output
Chip 17.1 625µm Straight wall Range (Unit:
Tolerance:
EPSON
SED1797 Series
Bump Coordinates
Unit: Signal Name DUMMY VDDH VDDH VDDH DUMMY DUMMY XRES DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY TEST DUMMY DUMMY DUMMY DUMMY DUMMY VOFF VOFF coordinate coordinate -8172.8 -420.6 -8024.8 -7872.8 -7716.8 -7568.8 -7268.8 -7116.8 -6968.8 -6139.2 -5858.0 -5706.0 -5558.0 -5410.0 -5262.0 -5037.1 -4889.1 -4741.1 -4589.1 -4370.7 -4118.7 -3970.7 -3822.7 -3670.7 -3389.1 -2629.9 -2477.9 -2329.9 -2177.9 -1959.5 -1707.5 -1559.5 -1399.5 -1117.9 -865.9 -717.9 -570.0 136.8 284.8 432.8 580.8 862.4 1114.4 1262.4 1414.4 1562.4 1714.4 1866.4 2018.4 2166.4 2314.4 Signal Name coordinate coordinate VOFF 2466.4 -420.6 DUMMY 2738.4 DUMMY 2867.5 DUMMY 3657.1 3938.7 DUMMY 4086.7 DUMMY 4234.8 DUMMY 4382.7 DUMMY 5074.7 5356.3 DUMMY 5508.3 DUMMY 5656.3 DUMMY 5804.2 DIO2 5952.2 DUMMY 6233.8 DUMMY 6495.4 DUMMY 6643.4 DUMMY 6791.4 DUMMY 7306.5 DUMMY 7454.5 DUMMY 7706.6 DIO1 7988.2 DUMMY 8136.2 DUMMY 8356.0 423.0 8264.8 8200.8 8136.8 8072.8 8008.8 7944.8 7880.8 7816.8 7752.8 7688.8 7624.8 7560.8 7496.8 7432.8 7368.8 7304.8 7240.8 7176.8 7112.8 7048.8 6984.8 6920.8 6856.8 6792.8 6728.8 6664.8 Signal Name coordinate coordinate 6600.8 423.0 6536.8 6472.8 6408.8 6344.8 6280.8 6216.8 6152.8 6088.8 6024.8 5960.8 5896.8 5832.8 5768.8 5704.8 5640.8 5576.8 5512.8 5448.8 5384.8 5320.8 5256.8 5192.8 5128.8 5064.8 5000.8 4936.8 4872.8 4808.8 4744.8 4680.8 4616.8 4552.8 4488.8 4424.8 4360.8 4296.8 4232.8 4168.8 4104.8 4040.8 3976.8 3912.8 3848.8 3784.8 3720.8 3656.8 3592.8 3528.8 3464.8
EPSON
SED1797 Series
Unit: Signal Name coordinate coordinate 3400.8 423.0 3336.8 3272.8 3208.8 3144.8 3080.8 3016.8 2952.8 2888.8 2824.8 2760.8 2696.8 2632.8 2568.8 2504.8 2440.8 2376.8 2312.8 2248.8 2184.8 2120.8 2056.8 1992.8 O100 1928.8 O101 1864.8 O102 1800.8 O103 1736.8 O104 1672.8 O105 1608.8 O106 1544.8 O107 1480.8 O108 1416.8 O109 1352.8 O110 1288.8 O111 1224.8 O112 1160.8 O113 1096.8 O114 1032.8 O115 968.8 O116 904.8 O117 840.8 O118 776.8 O119 712.8 O120 648.8 DUMMY 544.0 DUMMY 480.0 DUMMY 416.0 DUMMY 352.0 DUMMY 288.0 DUMMY 224.0 Signal Name DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY O121 O122 O123 O124 O125 O126 O127 O128 O129 O130 O131 O132 O133 O134 O135 O136 O137 O138 O139 O140 O141 O142 O143 O144 O145 O146 O147 O148 O149 O150 O151 O152 O153 O154 O155 O156 O157 O158 coordinate coordinate 160.0 423.0 96.0 32.0 -32.0 -96.0 -160.0 -224.0 -288.0 -325.0 -416.0 -480.0 -544.0 -648.8 -712.8 -776.8 -840.8 -904.8 -968.8 -1032.8 -1096.8 -1160.8 -1224.8 -1288.8 -1352.8 -1416.8 -1480.8 -1544.8 -1608.8 -1672.8 -1736.8 -1800.8 -1864.8 -1928.8 -1992.8 -2056.8 -2120.8 -2184.8 -2248.8 -2312.8 -2376.8 -2440.8 -2504.8 -2568.8 -2632.8 -2696.8 -2760.8 -2824.8 -2888.8 -2652.8 -3016.8 Signal Name coordinate coordinate O159 -3080.8 423.0 O160 -3144.8 O161 -3208.8 O162 -3272.8 O163 -3336.8 O164 -3400.8 O165 -3464.8 O166 -3528.8 O167 -3592.8 O168 -3656.8 O169 -3270.8 O170 -3784.8 O171 -3848.8 O172 -3912.8 O173 -3976.8 O174 -4040.8 O175 -4104.8 O176 -4168.8 O177 -4232.8 O178 -4296.8 O179 -4360.8 O180 -4424.8 O181 -4488.8 O182 -4552.8 O183 -4616.8 O184 -4680.8 O185 -4744.8 O186 -4808.8 O187 -4872.8 O188 -4936.8 O189 -5000.8 O190 -5064.8 O191 -5128.8 O192 -5192.8 O193 -5256.8 O194 -5320.8 O195 -5384.8 O196 -5448.8 O197 -5512.8 O198 -5576.8 O199 -5640.8 O200 -5704.8 O201 -5768.8 O202 -5832.8 O203 -5896.8 O204 -5960.8 O205 -6024.8 O206 -6088.8 O207 -6152.8 O208 -6216.8
EPSON
SED1797 Series
Unit: Signal Name O209 O210 O211 O212 O213 O214 O215 O216 O217 O218 O219 O220 O221 O222 O223 O224 O225 O226 O227 O228 O229 O230 O231 O232 O233 O234 O235 O236 O237 O238 O239 O240 DUMMY coordinate coordinate -6280.8 423.0 -6344.8 -6408.8 -6472.8 -6536.8 -6600.8 -6664.8 -6728.8 -6792.8 -6856.8 -6920.8 -6984.8 -7048.8 -7112.8 -7176.8 -7240.8 -7304.8 -7368.8 -7432.8 -7496.8 -7560.8 -7624.8 -7688.8 -7752.8 -7816.8 -7880.8 -7944.8 -8008.8 -8072.8 -8136.8 -8200.8 -8264.8 -8356.0
EPSON
SED1797 Series
Functions Pins
Name Function Vertical shift clock input vertical shift clock shift clock shift register. Data shift, synchronizing with rising-edge this shift clock. Shift data input/output pins These data pins from shift registers. When data input, they captured, synchronizing with rising-edge CPV, data output, synchronizing with falling edge. DIO1 DIO2 switched level SHL. output level always "VCC"-"VSS." selecting shift direction switching function shift data This selects shift direction switches shift data pins. Gate Output O240 O240 DIO1 DIO2 Input Output Output Input
Number Pins
DIO1 DIO2
Output enable This that controls gate output pins O240). XOE="VCC" VOFF voltage output XOE="VSS" Normal output status Reset Setting XRES "VSS" resets data shift registers. gate output voltage "VOFF" level.
XRES
TEST
Test this "VEE" level. Built-in power control this "VEE" level.
EPSON
SED1797 Series
Name O240 Function Gate output pins Data shift register output after level conversion.
Number Pins
Power supply
Power gate output VEEVOFFVONVDDH Power gate output VEEVOFFVONVDDH Power supply high-voltage logic VONVDDH Power supply logic (ICs' shared power supply) VEEVOFF Power supply logic VEEVDDH VEEVSS Test internal logic power supply. "OPEN."
VOFF
Power supply
VDDH
Power supply
Power supply
Power supply
Power supply
DUMMY
Dummy bump Auxiliary bump implementation. Electrically, "OPEN."
EPSON
SED1797 Series
Operations
Shift Data Transfer
Data input from pins captured rising-edge shift clock CPV, sequentially shifted, synchronizing with rising-edge CPV, then output other DIO, synchronizing with falling edge 240th CPV.
Data Input DIO1 DIO2 Shift Direction Data Output DIO2 DIO1
cascade-connect more than ICs, connect output first input next
VDDH Logic input Gate Output
VOFF Controller side
output
Driver side
EPSON
SED1797 Series
Gate Output
"VON" voltage output while level signals output data shift registers associated with respective gate output pins, "VOFF" voltage output while level signals output. Inputting level reset (XRES) resets data shift registers "VOFF" voltage applied gate output. reset used, inputting clocks clears data shift registers with shift data input fixed level. Note, however, gate output during this initialization period becomes indefinite.
Timing Chart
Case: "VCC" (reference example)
XRES DIO1
VOFF
O240
DIO2
EPSON
SED1797 Series
Absolute Maximum Ratings (VSS
Item Supply voltage Supply voltage Supply voltage Supply voltage Supply voltage Supply voltage Input voltage Input current Output current operating ambient Temperature range Storing temperature Symbol VDDH VDDH-VEE VON-VOFF VOFF Tstg2 Rating -0.3 +7.0 -0.3 +45.0 -23.0 +0.3 -0.3 +45.0 -0.3 +VDDH+0.3 VEE-0.3 +0.3 -0.3 VCC+0.3 +125 Unit
(Note Unless otherwise noted, reference voltage voltages. (Note permanently damaged operated under conditions beyond above ratings. Also note that reliability affected exposed condition with absolute maximum ratings long time. (Note voltages VDDH, VEE, VSS, always maintain relation VEEVSSVCCVDDH. Additionally, maintain such condition VOFF that relations, VEEVOFF VONVDDH, always present. (Note input power, follow order below: Logic system (VCC, VSS) Logic system (VEE) high-voltage logic system (VDDH) gate output system (VON, VOFF) ogic signals, this order. input power simultaneously. shut down, follow this order inversely disconnect same time. Take care well that relations between levels power voltages would reversed even while power input, disconnected transient. (Note Input logic signals same time power input Logic System (VCC, VSS) during power inputting process. Meanwhile, operations assured operated within recommended operating conditions. (Note Avoid floating logic power while high-voltage logic power gate output power applied. Avoid condition where VCC-VEE becomes 0.7V under well. These conditions affect reliability
VDDH,
VEE, VOFF
Time
EPSON
SED1797 Series
Recommended Operating Conditions (VSS
Item Supply voltage Supply voltage Supply voltage Supply voltage Operating frequency Symbol VDDH, VEE, VOFF VDDH-VEE VON-VOFF fCPV Rating +1.8 +5.5 +10.0 +30.0 -20.0 -5.0 +15.0 +40.0 Unit
(Note operations assured operated within recommended operations conditions. (Note Insert bypass capacitor vicinity power pins countermeasures against noise. (Note voltage VOFF power supply swung, keep VOFF same potential that VEE. (Note swing VOFF power voltage, maintain relation VEEVOFFVON 15[V]. this case, different assurance standards applied output resistance, output rise time output fall time. (Note When inputting power, recommended that reset should fixed level gate output "VOFF" voltage. This prevents gate output from becoming indefinite also prevents overcurrent well faulty display panel.
VDDH
15[V]VDDH-VEE40[V]
1.8[V]VCC5.5[V] 6.8[V]VCCVEE25.5[V]
recommended operating voltages combinations within shaded area figure below.
VDDH-VEE
EPSON
SED1797 Series
Electrical Characteristics within Recommended Operating Conditions
Characteristics
(Ta= +85°C, VCC=3.3±0.3V, VSS=0V, VDDH=30V, VEE= -10V) Item input voltage input voltage output voltage output voltage Symbol ICCS IDDS ISSS IEES Ta=25°C -150 -300 IOL=40µA IOH=40µA VON=0.5V VON=30V VOFF=-10V -1.0 Condition Rating MIN. (VCC-VSS) (VCC-VSS) TYP. MAX. (VCC-VSS) VSS+0.4 +1.0 -450 -600 Unit Applicable input pins input pins DIO1 DIO2 DIO1 DIO2 O240 input pins input pins VDDH VDDH
Output resistance Input leakage current Input capacity Static current consumption Static current consumption Static current consumption Static current consumption Dynamic current consumption Dynamic current consumption Dynamic current consumption Dynamic current consumption
SHL= "H", XRES="H", DIO1=CPV=XOE="L", DIO2="OPEN", load output pins. display, fCPV=36 kHz, fDIO=75 load output pins.
EPSON
SED1797 Series
Characteristics
Input Timing Characteristics
(Ta=-40 +85°C, VCC=3.3±0.3V, VSS=0V, VDDH=30V, VEE=-10V) Item frequency high-level pulse width low-level pulse width Data setup time Data hold time XRES low-level pulse length Reset time High-level pulse length Symbol tCPV tCPVH tCPVL tWOE 1.0(*3) Condition MIN. 1.0(*2) 5.0(*2) MAX. Unit
rise fall times input signals defined 30ns less. This value applied XRES used. This value applied used.
XRES
Internal status Resetting process Resetting process completed
Output Timing Characteristics
(Ta=-40 +85°C, VCC=3.3±0.3V, VSS=0V, VDDH=30V, VEE=-10V) Item CPV-to-DIO output delay time CPV-to-DIO output delay time XOE-to-On output delay time output rise time output fall time Symbol tpd1 tpd2 tpd3 tpd4 tpd5 tpd6 CL=220pF VON=30V VOFF=10V Condition CL=20pF MIN. TYP. MAX. Unit
EPSON
SED1797 Series
tCPV tCPVH tCPVL
(IN)
tpd1 tpd2
(OUT) tpd3 tpd4
tWOE
tpd5
tpd6
EPSON
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