0.5µm Series series ULCs well suited conversion medium- to-large

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0.5µm Series series ULCs well suited conversion medium- to-large

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Series
0.5µm Series
series ULCs well suited conversion medium- to-large sized CPLDs FPGAs. Devices implemented high-performance CMOS technology with 0.5-µm (drawn) channel lengths, capable supporting flip-flop toggle rates 3.3V, operating clock frequencies input output delays fast architecture series allows efficient conversion many architecture FPGA device types with higher count. compact cell, along with large number available gates allows implementation FPGA architectures that support this feature, well JTAG boundary-scan scan-path testing. Conversion series provide significant reduction operating power when compared original FPGA. This especially true when compared many CPLD architecture devices, which typically consume more even when being clocked. series very standby consumption nA/gate typically commercial temp, which would yield standby current nA/gate, 10,000 gate design. Operating consumption strict function clock frequency, which typically results power reduction depending device being compared. series provides several options output buffers, including variety drive levels Schmitt trigger inputs also option. number techniques used improved noise immunity reduced emissions, including: several independent power supply busses internal decoupling isolation; slew rate limited outputs also available required. series designed allow conversions high performance devices well devices. Support mixed supply conversions also possible, allowing optimal trade-offs between speed power consumption.
Features
High performance family suitable medium- large-sized CPLDs FPGAs Conversions over 700,000 FPGA gates counts over pins pin-out matched limited number dedicated pads Full range packages: DIP, SOIC, LCC/PLCC, PQFP/TQFP, PGA/PPGA 3.3V and/or 5.0V operation. quiescent current: 0.04 nA/gate Available commercial, industrial, automotive, military space grades. Drawn CMOS, Metal Layers Library Optimised Synthesis, Floor Plan Automatic Test Generation (ATG) High Speed Performances: Typical Gate Delay Typical Toggle Frequency Vand @3.3 High System Frequency Skew Control: Clock Tree Synthesis Software Volts Operation; Single Dual Supply Modes Power Consumption: µW/Gate/MHz µW/Gate/MHz Power Reset Standard 24mA I/Os CMOS/TTL/PCI Interface Latch-up Protected High Noise Immunity: with Slew Rate Control Internal Decoupling Signal Filtering between Periphery Core Application Dependent Supply Routing Several
Rev.
May.
Series
Product Outline
Part Number*
UG201 UG202 UG204 UG210 UG215 UG222 UG244 UG255 UG291 UG2140 UG2194 UG2265 UG2360 UG2480 UG2590 UG2700 Check with factory availability product type.
Full programmables Pads
Equivalent FPGA Gates
3300 4200 7500 15800 24300 34800 58600 64500 108500 156800 206300 318000 432000 552000 678000 805000
Architecture
basic element family called cell. cell typically implement between three FPGA gates. Cells located contiguously through core device, with routing resources provided three metal layers above cells. Some cell blockage does occur routing, utilization will significantly greater with three metal routing than two. sizes listed Product Outline estimated usable amounts using three metal layers. cells provided each pad, configured inputs, outputs, I/Os, required match FPGA pinout. Special function cells pins located corners which typically unused. order improve noise immunity within device, separate busses provided internal cells cells.
Outputs noise buffers with drive
Options
Inputs Each input programmed TTL, CMOS, Schmitt Trigger, with without pull pull down resistor. Fast Output Buffer Fast output buffers able source sink according chosen option. 24mA achievable, using pads. Slew Rate Controlled Output Buffer this mode, n-output transistor commands delayed, that they never "ON" simultaneously, resulting switching current noise. These buffer dedicated very high load drive.
buffer interfacing 3.3-V Compatibility
Fexibility buffers configured input, output, bi-directional, oscillator supply. level translator could located close each buffer. Rev. series ULCs fully capable supporting high-performance operation performance specifications given design however, must explicitly specified both.
May.
Series
Power Supply Noise Protection
speed density technology causes large switching current spikes example either when: high current output buffers switch simultaneously, gates switching within window 1ns. Sharp edges high currents cause some parasitic elements packaging become significant. this frequency range, package inductance series resistance should taken into account. known that inductor slows down setting time current causes voltage drops power supply lines. These drops affect behaviour circuit itself disturb external application (ground bounce). order improve noise immunity core matrix, several mechanisms have been implemented inside arrays. kinds protection have been added: limit buffer switching noise other protect buffers against switching noise coming from matrix. buffers switching protection Three features implemented limit noise generated switching current: power supplies input output buffers separated. rise fall times output buffers controlled internal regulator. design rule concerning number buffers connected same power supply line been imposed. Matrix switching current protection This noise disturbance caused large number gates switching simultaneously. allow this without impacting functionality circuit, three features have been added: Decoupling capacitors integrated directly silicon reduce power supply drop. power supply network been implemented matrix. This solution reduces number parasitic elements such inductance resistance constitutes artificial Ground plane. mesh network supplies approximately cells. pass filter been added between matrix input output buffer. This limits transmission noise coming from ground supply matrix external world output buffers.
5-10
Rev.
May.
Series
Absolute Maximum Ratings
Supply Voltage (VDD) -0.5 Input Voltage (VIN) -0.5 Storage Temperature 150_C
Recommended Operating Range
Operating Temperature Commercial 70_C Industrial 85_C Military 125_C
Characteristics
Specified
Symbol
Parameter
Input voltage CMOS input input Input high voltage input Output voltage input Output high voltage CMOS input input Scmitt trigger positive threshold CMOS input input Scmitt trigger negative threshold CMOS input input Input leakage pull up/down Pull Pull down 3-State Output Leakage current Output Short circuit current IOSN IOSP Leakage current cell
Unit
Conditions
-12,
+12,
Bout12 VOUT VOUT commercial industrial military
ICCSB
0.04
10.0
ICCOP
Operating current cell
0.45
µA/MHz
According buffer: Bout12, Bout6, Bout3,
Rev.
May.
5-11
Series
Characteristics
Specified
Symbol
Parameter
Input voltage LVCMOS input LVTTL input Input high voltage LVCMOS input LVTTL input Output voltage input Output high voltage input Scmitt trigger positive threshold LVCMOS input LVTTL input Scmitt trigger negative threshold CMOS input input Input leakage pull up/down Pull Pull down 3-State Output Leakage current Output Short circuit current IOSN IOSP Leakage current cell
Unit
Conditions
Bout12 VOUT VOUT commercial industrial military
0.02 0.06
ICCSB
ICCOP
Operating current cell
µA/MHz
According buffer: Bout12, Bout6, Bout3
5-12
Rev.
May.
Series
Characteristics
25°C, Process typical (all values
Buffer
BOUT12
Output buffer with drive
Load
60pf
Transition
Tplh Tphl 3.18 2.35
4.67 3.33
Cell
BINCMOS
CMOS input buffer
Load
Transition
Tplh Tphl 0.75 0.88 0.65 0.54 0.39 0.57 0.49 0.86 0.73 0.44 0.00
1.12 0.98 1.29 1.03 0.85 0.49 0.89 0.67 1.30 1.08 1.06 0.00
BINTTL
input buffer
Tplh Tphl
Inverter
Tplh Tphl
NAND2
input NAND
Tplh Tphl
FDFF
flip-flop,
Tplh Tphl
Power Consumption
Static Power Consumption Series ULCs
There three main factors consider: Leakage core: ICCSB number used gates Leakage inputs tri-stated outputs: PLIO (IIX where: number inputs number tri-stated outputs Care must taken include appropriate figure pins with pull-ups pull-downs. practice, static consumption calculation typically done determine standby current device; this case only those pins sourcing current should included, i.e. where VOUT VDD. power dissipation driving buffers resistive loads: practice, static consumption calculation typically done determine standby current device, under circumstances where Rev. outputs tri-stated input mode. this term zero. Global formula static consumption: PLIO
Dynamic Power Consumption Series ULCs
There four main factors consider: Static power dissipation negligible compared dynamic ignored. power dissipation buffers resistive loads: (mW) (DLn IOLn) VOH) (DHn IOHn) where: summation over outputs I/Os. IOLn IOHn appropriate values driver percentage time being driven percentage time being driven 5-13
May.
Series
difficult obtain exact value this factor, since determined primarily external system parameters. However, practice this simplified cases where device either driving CMOS loads driving loads. CMOS loads approximated purely capacitive loads, allowing this term treated zero. loads source significant current state, high state, allowing second summation ignored. duty cycle assumed dynamic outputs driving loads, this approximated (mW) IOLn/2 IOLm) (TTL loads) where dynamic outputs static outputs. Dynamic power dissipation internal gates: (mW) IDDOP fg)/1000 where: number gates toggling frequency clock frequency internal logic Note: actual toggle rates known, rule thumb assume that average used gate toggling half input clock frequency. Dynamic power dissipation outputs: (mW) VDD2 (COUT Cn)/1000 where: clocking frequency output output load capacitance output COUT output capacitance from Characteristics Global formula dynamic consumption: Example: Static calculation 100-pin with 3000 used gates, inputs, I/Os input mode, outputs tri-stated. pull-ups pull-downs. Half pins VDD, half VSS. Input clock toggling. this example only current calculation desired, term equations dropped. 3000 PLIO ((10 5)/2 Dynamic Calculation take 16-bit resettable ripple counter which approximately gates, operating clock frequency MHz, which gives average clock frequency MHz/16 each each output. There static outputs this device. Operation 6-mA outputs used loaded output buffers driving CMOS loads. 33/16/1000 33/16 2)/1000 22.5 Figure Typical Test Conditions
Typical Test Conditions
specification purposes, improved output loading scheme been defined TEMIC high-drive mA), high-speed devices. schematic below (Figure describes typical conditions testing these devices, using standard loading scheme commonly available high-end ATE. Compared no-load condition, this provides following advantages: Output load more representative "real life" conditions during transitions. Transient energy absorbed line prevent reflections which would lead inaccurate measurements.
D.U.T.
Comp
5-14
Rev.
May.

0.5µm Series series ULCs well suited conversion medium- to-large

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