2-Mbit (128K Pseudo Static Wide voltage range: 2.70V-3.30V Access

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2-Mbit (128K Pseudo Static Wide voltage range: 2.70V-3.30V Access

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WCMC2016V7B
2-Mbit (128K Pseudo Static
Wide voltage range: 2.70V-3.30V Access Time: Ultra-low active power Typical active current: Ultra-low standby power Automatic power-down when deselected CMOS optimum speed/power Offered 48-ball package standby mode when deselected HIGH both HIGH). input/output pins (I/O0 through I/O15) placed high-impedance state when: deselected HIGH), outputs disabled HIGH), both Byte High Enable Byte Enable disabled (BHE, HIGH), during Write operation LOW). Writing device accomplished asserting Chip Enable (CE) Write Enable (WE) inputs LOW. Byte Enable (BLE) LOW, then data from pins (I/O0 through I/O7), written into location specified address pins through A17). Byte High Enable (BHE) LOW, then data from pins (I/O8 through I/O15) written into location specified address pins through A16). Reading from device accomplished asserting Chip Enable (CE) Output Enable (OE) inputs while forcing Write Enable (WE) HIGH. Byte Enable (BLE) LOW, then data from memory location specified address pins will appear I/O0 I/O7. Byte High Enable (BHE) LOW, then data from memory will appear I/O8 I/O15. Refer truth table complete description read write modes
Functional Description
WCMC2016V7B high-performance CMOS Pseudo Static organized 128K words bits that supports asynchronous memory interface. This device features advanced circuit design provide ultra-low active current. This ideal providing more battery life portable applications such cellular telephones. device into
Logic Block Diagram
DATA DRIVERS
DECODER
128K Array
SENSE AMPS
I/O0 I/O7 I/O8 I/O15
COLUMN DECODER
Power-Down Circuit
Weida Semiconductor, Inc. Document 38-14036 Rev.
Revised 2004
Configuration[1,
48-ball VFBGA
View I/O8 I/O9 I/O14 I/O15
WCMC2016V7B
I/O10 I/O11 I/O12 I/O13
I/O1 I/O3 I/O4 I/O5
I/O0 I/O2 I/O6 I/O7
Product Portfolio
Power Dissipation Product Min. WCMC2016V7B 2.70 Range Typ.[3] Max. 3.30 Speed (ns) Operating ICC(mA) 1MHz Typ.[3] Max. fmax Typ.[3] Max. Standby ISB2(µA) Typ.[3] Max.
Note: Ball ball VFBGA package used upgrade density respectively. connect"-not connected internally die. Typical values included reference only guaranteed tested. Typical values measured VCC(typ.), 25°C.
Document 38-14036 Rev.
Page
Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Storage Temperature -65°C 150°C Ambient Temperature with Power Applied. -55°C 125°C Supply Voltage Ground Potential -0.4V 4.6V
WCMC2016V7B
Voltage Applied Outputs High State[4, .-0.4V 3.7V Input Voltage[4, .-0.4V 3.7V Output Current into Outputs (LOW). Static Discharge Voltage. >2001V (per MIL-STD-883, Method 3015) Latch-Up Current >200
Operating Range
Device WCMC2016V7B Range Industrial Ambient Temperature -25°C +85°C 2.70V 3.30V
Electrical Characteristics (Over Operating Range)
WCMC2016V7B-55 Parameter Description Supply Voltage Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Leakage Current Output Leakage Current Operating Supply Current VOUT VCC, Output Disabled fMAX 1/tRC VCCmax IOUT CMOS levels -0.1 0.1mA VCC= 2.7V 3.3V 2.70V 2.70V 0.8* -0.4 Test Conditions Min. Typ.[3] Max. 0.8* 0.4V -0.4 WCMC2016V7B-70 Min. Typ.[3] Max. Unit 0.4V
ISB1
Automatic Power-Down Current CMOS Inputs
0.2V 3.3V 0.2V, 0.2V) fMAX (Address Data Only), (OE, BLE), 3.30V 0.2V 0.2V 0.2V, 3.30V 3.3V
ISB2
Automatic Power-Down Current CMOS Inputs
Notes: VIL(MIN) -0.5V pulse durations less than VIH(Max) 0.5V pulse durations less than Overshoot undershoot specifications characterized 100% tested.
Capacitance[7]
Parameter COUT Description Input Capacitance Output Capacitance Test Conditions 25°C, MHz, VCC(typ) Max. Unit Page
Document 38-14036 Rev.
Thermal Resistance[7]
Description Thermal Resistance (Junction Ambient) Thermal Resistance (Junction Case) Test Conditions Test conditions follow standard test methods procedures measuring thermal impedence, JESD51. Symbol
WCMC2016V7B
Unit °C/W °C/W
Test Loads Waveforms
OUTPUT INCLUDING SCOPE INPUT PULSES Fall Time V/ns
Rise Time V/ns Equivalentto:
EQUIVALENT OUTPUT Unit
Parameters
3.0V 22000 22000 11000 1.50
Note: Tested initially after design process changes that affect these parameters.
Document 38-14036 Rev.
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Switching Characteristics Over Operating Range[8]
ns[9] Parameter Read Cycle tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tDBE tLZBE tHZBE tSK[9] Write tSCE tPWE tHZWE tLZWE Cycle[12] Write Cycle Time Write Address Set-Up Write Address Hold from Write Address Set-Up Write Start Pulse Width BLE/BHE Write Data Set-Up Write Data Hold from Write HIGH High-Z[10, Low-Z[10, Read Cycle Time Address Data Valid Data Hold from Address Change Data Valid Data Valid
[10,
WCMC2016V7B
Min. Max. Unit
Description
Min. 55[9]
Max.
HIGH High Z[10, Z[10, Z[10, HIGH High
BLE/BHE Data Valid BLE/BHE Z[10, BLE/BHE HIGH HIGH Address Skew Z[10,
Notes: Test conditions parameters other than tri-state parameters assume signal transition time ns/V, timing reference levels VCC(typ)/2, input pulse levels VCC(typ.), output loading specified IOL/IOH shown Test Loads Waveforms" section. achieve 55-ns performance, read access should controlled. this case tACE critical parameter satisfied when addresses stable prior chip enable going active. 70-ns cycle, addresses must stable within after start read cycle. tHZOE, tHZCE, tHZBE, tHZWE transitions measured when outputs enter high-impedance state. High-Z Low-Z parameters characterized 100% tested. internal Write time memory defined overlap VIL, and/or VIL. signals must ACTIVE initiate write these signals terminate write going INACTIVE. data input set-up hold timing should referenced edge signal that terminates write.
Document 38-14036 Rev.
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Switching Waveforms
Read Cycle (Address Transition Controlled)[13, ADDRESS
WCMC2016V7B
tOHA
DATA VALID
DATA
PREVIOUS DATA VALID
Read Cycle Controlled)[13,
ADDRESS
tHZCE
tACE
BHE/BLE
tLZBE
tDBE
tHZBE tHZOE HIGH IMPEDANCE
DATA SUPPLY CURRENT
tLZOE HIGH IMPEDANCE tLZCE
tDOE DATA VALID
Notes: HIGH Read Cycle. 55-ns Cycle, addresses must toggle once read started device. 70-ns Cycle, addresses must stable within after start read cycle. Device continuously selected. VIL.
Document 38-14036 Rev.
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Switching Waveforms (continued)
Write Cycle Controlled)[11,
WCMC2016V7B
ADDRESS tSCE
tPWE
BHE/BLE
DATA
DON'T CARE
VALID DATA tHZOE
Write Cycle Controlled)[11,
ADDRESS tSCE
tPWE
BHE/BLE
HZOE DATA
DON'T CARE
VALID DATA
Notes: Data high-impedance VIH. Chip Enable goes INACTIVE with VIH, output remains high-impedance state. During DON'T CARE period DATA waveform, I/Os output state input signals should applied.
Document 38-14036 Rev.
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Switching Waveforms (continued)
Write Cycle Controlled, LOW)[17,
WCMC2016V7B
ADDRESS tSCE
BHE/BLE
tPWE
DATA
DON'T CARE
tLZWE
VALID DATA tHZWE
Write Cycle (BHE/BLE Controlled, LOW)[17, ADDRESS
tSCE BHE/BLE
tPWE
DATA
DON'T CARE
VALID DATA
Document 38-14036 Rev.
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Truth Table[19]
Inputs/Outputs High High Data (I/O0-I/O15) Data (I/O0-I/O7); High (I/O8-I/O15) High (I/O0-I/O7); Data (I/O8-I/O15) High High High Data (I/O0-I/O15) Data (I/O0-I/O7); High (I/O8-I/O15) High (I/O0-I/O7); Data (I/O8-I/O15) Mode
WCMC2016V7B
Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Deselect/Power-Down Deselect/Power-Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write
Ordering Information
Speed (ns) Ordering Code WCMC2016V7B-FVI55 WCMC2016V7B-FVI70 Package Name BV48A BV48A Package Type 48-ball Very Fine Pitch 48-ball Very Fine Pitch Operating Range Industrial Industrial
Note: Logic HIGH, Logic LOW, Don't Care
Document 38-14036 Rev.
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Package
48-Lead VFBGA BV48A
WCMC2016V7B
51-85150-*B
Document 38-14036 Rev.
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Weida Semiconductor, Inc., 2004. information contained herein subject change without notice. Weida Semiconductor assumes responsibility circuitry other than circuitry embodied Weida Semiconductor product. does convey imply license under patent other rights. Weida Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Weida Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Weida Semiconductor against charges.
Document History Page
Document Title: WCMC2016V7B 2-Mbit (128K Pseudo Static Document Number: 38-14036 REV. 215621 218183 230490 Issue Date Orig. Change Description Change Datasheet
WCMC2016V7B
Changed ball package pinout from Change from Advance Preliminary Fixed package name typos page page Modified Input voltage Maximum ratings limit from 3.3V 3.7V
Document 38-14036 Rev.
Page

2-Mbit (128K Pseudo Static Wide voltage range: 2.70V-3.30V Access

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