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BluetoothBaseband FEATURES Parallel host interface (3100 only) co


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IS11LV3100 IS11LV3101
BluetoothBaseband
FEATURES Parallel host interface (3100 only) connects directly
PCMCIATM, CompactFlashTM, many microprocessor buses
ISSI
DESCRIPTION
IS11LV3100/3101 provides BluetoothLink Control Link Management functions that support data/3 voice channels compliant with BluetoothSpecification 1.1. IS11LV3100/3101 contains RISC microprocessor large on-chip SRAM easy implementation into notebook PCs, PDAs, internet appliances other devices requiring power, cost effective Bluetoothfunctionality. addition UART interfaces, IS11LV3100 implements parallel host interface that connected wide variety buses such PCMCIATM, CompactFlashTM, microprocessor buses, eliminating need glue logic components. IS11LV3100/3101 optimized work with ISSI's IS11LV5010 transceiver Bluetoothapplications through 7-pin BlueRFinterface. This interface allows interoperability with BlueRFcompliant transceivers. interface consists bidirectional transmit receive data line, three IS11LV3100-to-IS11LV5010 unidirectional control lines power timing control, 3-wire serial data accessing IS11LV5010's internal registers. IS11LV3100/3101 available cost, small footprint, industry standard packages LQFP-80 LFBGA-81.
PRELIMINARY INFORMATION JULY 2002
Full-speed device compliant 1.1. High-speed UART 1.843 Mbits/sec Large on-chip SRAM Hardware implemented BluetoothFEC, Data
Scrambling, CRC/HEC, encryption/decryption, authentication generation
Fully supports point-to-multipoint,
traffic channels
Supports RSSI channel quality measurement
each link piconet
Support transmit power control Support A-law/µ-law CVSD codec Compliant Bluetoothspecification version
BlueRFinterface
component ISSI's family complete hardware
software Bluetoothsolutions, optimized with ISSI's IS11LV5010 transceiver
APPLICATIONS Battery Powered Portable Handheld Devices Laptop Computers PDAs Modems Internet Access Points Cordless Cellular Phones PCMCIATM, Card, CompactFlash(3100)
Bluetoothand BlueRFare trademarks owned Bluetooth SIG, Inc. used ISSI under license. PCMCIAand CompactFlashare trademarks their respective organizations. Copyright 2002 Integrated Silicon Solution, Inc. rights reserved. ISSI reserves right make changes this specification products time without notice. ISSI assumes liability arising application information, products services described herein. Customers advised obtain latest version this device specification before relying published information before placing orders products.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
PRELIMINARY INFORMATION Rev. 07/16/02
IS11LV3100, IS11LV3101
ISSI
BLOCK DIAGRAM
A0-A8 D0-D8 CTRL's Host (3100) Frequency Hopping Generation RSSI
BDDATA Link Control State Machine CRC/HEC Encryption Scrambler BnDEN BDCLK BDATA1 BXTLEN BPKTCTL BnPWR RXDATA CRC/HEC Encryption Descrambler RXCLK
Tx/Rx Buffers
SRAM Power Control Timing Control CVSD
PCMCLK PCMSYNC PCMTX PCMRX
nRTS nCTS
UART
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
PRELIMINARY INFORMATION Rev. 07/16/02
IS11LV3100, IS11LV3101
ASSIGNMENT LFBGA-81
ISSI
HnWAIT RXCLK DHDATA0 HDATA1 HDATA3
BDATA1 VDD_RFIO RXDATA VDD_I/O HDATA2
BnPWR BnDEN BPKTCTL nRTS nCTS HADDR7
BDCLK BXTLEN
VDD_CORE
XTLIN
XTLOUT
nRESET XOUT/BCFG HnWAIT VDD_CORE HRESET HnREG HnOE HADDR4 HnINT PCMTX PCMRX
TESTSE XBYPASS nRSTO XTLOUT2 XTLIN2 TESTMD HADDR8
HnINPACK PCMSYNC PCMCLK HnIOWR HnWR HADDR3 HnIORD VDD_I/O HADDR2 HnCE HADDR1 HADDR0 HDATA10
HADDR6 HADDR5
VDD_CORE HDATA11 HDATA4 HDATA5
VDD_I/O HDATA12 HDATA13 HDATA14 HDATA15 HDATA6 HDATA7 HDATA8 HDATA9
LQFP-80
BDATA1 BnPWR BDCLK VDD_RFIO BDDATA BnDEN BXTLEN RXCLK RXDATA BPKTCTL XTLOUT2 XLTLIN2 HDATA0 HDATA1 HDATA2 HDATA3 HDATA4 HDATA5 VDD_CORE
TESTMD PCMTX PCMRX PCMSYNC PCMCLK HnIORD HnlOWR HnWR HnOE HnCE HADDR7 HADDR6 HADDR5 HADDR4 HADDR3 VDD_I/O HADDR2 HADDR1
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
PRELIMINARY INFORMATION Rev. 07/16/02
IS11LV3100, IS11LV3101
DESCRIPTION
Description
LQFP-80 LFBGA-81 Name BDATA1 GPIO Type Description
ISSI
transmit mode, this receives transmit data from baseband 1MHz data rate. receive mode, this sends receive data baseband 1MHz data rate. This basically reset PHY. When asserted (low), should lower-power mode. Dbus serial clock MHz. Serial data port. This provides variety control data chip, including TX_ON, RX_ON, SYNTH_ON, ACG_CTRL, PLL_CTRL. also passes RSSI data from chip baseband. Data transferred rising edge BDCLK. 3-wire Dbus enable pin. BDDATA should only wiggle when BnDEN held low. This shut down clock logic powersaving sleep mode. transmit mode, this turns signals start transmit data. This should after tuned synthesizer hopping frequency. receive mode, this controls estimation different states: state used estimation fast acquisition high state used slower estimation. Recovered 1MHz receive clock. Recovered data input 1MHz symbol rate.
BnPWR BDCLK BDDATA
BnDEN BXTLEN BPKTCTL
RXCL RXDATA
GPIO2[3] GPIO2[2]
Host Processor Interfaces
LQFP-80 39,38,37 35,34, LFBGA-81 Name HADDR [7:0] J6,J5,J3 H8,H7,H6 H5,H3,J9 J8,J7 HnCE HnOE HnWR Active chip select Active output enable memory read operation Active write enable memory write operation HDATA [15:8] GPIO1 [7:0] 16-bit parallel from host HADDR[8] HDATA[7:0] GPIO2[7] Address from host processor 16-bit parallel from host GPIO Type Description Address from host processor
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
PRELIMINARY INFORMATION Rev. 07/16/02
IS11LV3100, IS11LV3101
DESCRIPTION Continued:
Host Processor Interfaces Continued:
LQFP-80 LFBGA-81 Name HnIOWR HnIORD HnREG HRESET GPIO Type Description Active write Active read ISelect between config memory space Reset from host processor Acknowledge operation Active interrupt host processor
ISSI
HnINPACK GPIO2[6] HnINT HnWAIT nRSTO XTLOUT2 XTLIN2 GPIO2[5] GPIO2[4] GPIO2[1] GPIO2[0]
Active wait IS11LV3100/3101 hold Watch-dog timer reset output frequency crystal output frequency crystal (32/32.768/40KHz)
Interfaces
LQFP-80 LFBGA-81 Name DGPIO Type U-I/O U-I/O Description data data
UART Interfaces
LQFP-80 LFBGA-81 Name nCTS nRTS GPIO GPIO0[0] GPIO0[1] GPIO0[2] GPIO0[3] Type Description UART clear send UART request send UART transmit data UART receive data
Interfaces
LQFP-80 LFBGA-81 Name PCMCLK GPIO GPIO0[4] Type Description 256KHz data clock output frame strobe output serial data input serial data output
PCMSYNC GPIO0[5] PCMRX PCMTX GPIO0[6] GPIO0[7]
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
PRELIMINARY INFORMATION Rev. 07/16/02
IS11LV3100, IS11LV3101
ISSI
GPIO Type OD-U Description serial clock serial data
Interfaces
LQFP-80 LFBGA-81 Name
Miscellaneous Interfaces
LQFP-80 LFBGA-81 Name nRESET XTALIN XTALOUT XBYPASS XOUT/BCFG GPID Type Description Hardware Reset Crystal Input Crystal Output Disable bypass internal PLL. test mode, this outputs synthesized clock from PLL. normal mode, this determines power-on boot configuration. Test mode enable Test scan enable
TESTMD TESTSE
Power
LQFP-80 LFBGA-81 Name VDD_CORE VDD_RFIO VDD_IO GPID Type Description CORE (2.5v) pins (3.3v 2.5v) rest pins (3.3v) both CORE
Note: Output OD-U Open-drain input/output with 50kOhm internal pull-up 2.5v Input with 50kOhm internal pull-up 2.5v I-D= Input with 50kOhm internal pull-down I-US Schmitt-triggered Input with 50kOhm internal pull-up 2.5v Input/output I/O-U Input/output with 50kOhm internal pull-up 2.5v I/O-D= Input/output with 50kOhm internal pull-down U-I/O Differential input/output Crystal input single-ended clock input Crystal output Power pin. Except I-US type pins, which must appropriately connected board, other pins left floating used.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
PRELIMINARY INFORMATION Rev. 07/16/02
IS11LV3100, IS11LV3101
FUNCTIONAL DESCRIPTION
IS11LV3100 IS11LV3101 provide BluetoothLink Control (LC), Link Management (LM) Host Communication Interface (HCI) functions single chip hosted Bluetoothapplication. channel related coding decoding such forward error correction (FEC), scrambling, cyclic redundancy check (CRC), optional data encryption implemented directly hardware. This addition PCM/CVSD audio transcoder function, which also implemented hardware. avoid missing real-time events, timing critical operations such synthesizer on/off timing control, receive data symbol clock recovery, TX/RX frequency hopping calculation, master/slave switch, etc. also supported directly hardware. Power-management link quality measurement supports also provided IS11LV3100 IS11LV3101 hardware. facilitate communication with host, IS11LV3100 IS11LV3101 implement full-speed 1.1compliant device interface, high-speed UART interface (for communication speed 1.8432 Mbits/sec), parallel host interface. addition, interface allows IS11LV3100 IS11LV3101 store configuration parameters small-footprint serial E2PROM. same E2PROM also store firmware that IS11LV3100 IS11LV3101 will automatically upload into internal SRAM upon reset.
ISSI
device. addition BlueRFinterface, IS11LV3100 IS11LV3101 also programmed receive recovered symbol clock demodulated data directly from BluetoothPHY device during receive slot. This allows IS11LV3100 IS11LV3101 provide better receive performance when linked with ISSI's IS11LV5010 device.
CRC/HEC Cyclic Redundancy Check/ Header Error Check
protect data from transmission error, Bluetoothpacket headers encoded with header-error-check packets payloads encoded with CRC. either error error detected receive side, packet must retransmitted. automatically disabled packets Bluetoothspecification.
Scrambler/De-scrambler
main purpose data scrambling randomize transmit data avoid long sequences 1's, which cause unwanted DC-offset receive circuit. randomized data, with frequent transitions between also help symbol clock tracking performance.
Forward Error Correction
After packet CRC/HEC-encoded, scrambled, optionally encrypted (see below), further encoded with forward error correction code. Depending packet type field, either applied. code provides another layer protection over channel noise. results error checking used measuring link quality.
Physical Layer Interface
IS11LV3100 IS11LV3101 support bi-directional BlueRFinterface protocol with RXMODE2 receive mode. When interfacing with BlueRFTM-compatible device, IS11LV3100 IS11LV3101 sends/ receives data 1MHz symbol rate over same piece wire. direction data controlled internal state machine, which synchronized with device over control signals. These control signals also provide crucial packet timing information well power-down, sleep mode control device. access internal registers device, BlueRFinterface defines 3-wire SPI-like serial interface (Dbus). Through this 3-wire Dbus, IS11LV3100 IS11LV3101 retrieve RSSI information from device well provide fine-grain control, such synthesizer programming DC-offset tuning,
Authentication/Encryption Generation
order establish secure communication link, Bluetoothspecification defines process authentication/encryption generation. This process implemented entirely IS11LV3100. During connection establishing states time during connection state, IS11LV3100 IS11LV3101 firmware invoke generation hardware generate keys, then exchange keys with peer through messages.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
PRELIMINARY INFORMATION Rev. 07/16/02
IS11LV3100, IS11LV3101
Encryption/Decryption
encrypting decrypting outgoing incoming messages with authentication/encryption keys, secure communication link then established. IS11LV3100 IS11LV3101 implement encryption/ decryption engine hardware ensure encryption decryption done real-time. Once channel enabled secure communication, encryption/decryption engine automatically engages during transmit/receive operation. encryption applied after CRC/HEC coding before scrambling.
ISSI
Power Management
IS11LV3100 IS11LV3101 currently support Bluetoothsniff hold mode (and will support park mode when demand picks up). During these modes, both IS11LV3100 IS11LV3101 companion IS11LV5010 chips shut down save power. IS11LV3100 IS11LV3101 wake after specified amount time when programmable counter expires. This counter clocked either main crystal second optional, low-power, frequency crystal which activated during low-power sleep mode. During normal connection when devices sleep mode, IS11LV3100 IS11LV3101 programmed shut down nonessential blocks, including onchip microprocessor, per-cycle basis conserve power.
Frequency Hopping
Bluetoothstandard uses frequency hopping spread spectrum technique avoid channel congestion. hopping sequences computed from device address clock node master, vary between 79-hop 23-hop depending region where device resides. IS11LV3100 IS11LV3101 implement this hopping frequency computation directly hardware avoid confusion release firmware from tedious timing critical operations.
PCM/CVSD Encoding/Decoding
audio data, IS11LV3100 IS11LV3101 implement both A-law/m-law CVSD transcoding functions hardware support Bluetoothaudio requirements. Both CVSD encoding provide audio-data compression better sound quality over linearly sampled data.
Timing Control
IS11LV3100 IS11LV3101 implement programmable hardware keep track critical timing events Bluetooth piconet. This hardware allows IS11LV3100 IS11LV3101 control timing many Bluetooth-specific operations down submicrosecond level. example, IS11LV3100 IS11LV3101 programmed accommodate different delays through circuits well different timing requirement synthesizer stabilize. This allows firmware fine-tune interface better performance. IS11LV3100 IS11LV3101 receive logic automatically readjust estimated master timing upon detection every master transmit, whether transmission heading not. This ensures slave device always sync with master long master transmitting. IS11LV3100 IS11LV3101 compute slot-offset between master native clock, saves offset, later restores timing from saved offset; crucial operation scatter-net implementation.
Host Processor Interface (3100 only)
high-speed communication with host, IS11LV3100 implements parallel host-processor interface. This interface hooked PCMCIATM, CompactFlashTM, many microprocessor memory buses directly. And, since parallel bus, provides virtually unlimited bandwidth Bluetoothtransport-layer communication.
USB/UART
addition parallel Host Processor Interface, separate UART interfaces also provided. interface follows standard v1.1 device specification. UART interface implements 4-wire interface with optional automatic nCTS/nRTS flow control avoid losing data overrun. implementation supports baud rates 1.8432 Mbits second.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
PRELIMINARY INFORMATION Rev. 07/16/02
IS11LV3100, IS11LV3101
ISSI
Interface
IS11LV3100 IS11LV3101 implement master interface communication with slave devices such serial E2PROM. This interface allows IS11LV3100 IS11LV3101 store Bluetoothspecific configuration data such device address authentication keys between power-on. also provides boot source IS11LV3100. Currently, IS11LV3100 IS11LV3101 automatically upload firmware upon power-on from either interface parallel host interface.
On-Chip Microprocessor/SRAM
enable implementation full Host Control Interface (HCI), IS11LV3100 IS11LV3101 include on-chip, 32-bit RISC microprocessor large onchip SRAM. Among many things, firmware, running microprocessor, implements data buffering controls flow data between various hardware modules IS11LV3100. addition, firmware also implements algorithmic/heuristic logic that otherwise cannot easily done hardware.
GPIO
generic operations, GPIO pins provided. These pins organized into groups pins. Each individually configured input output, open-drain pin. When configured input open-drain pin, optional filter applied before value sampled. Once sampled, values read register directly embedded MPU. values watched monitoring logic, which looks combination values edges triggers interrupts MPU. limited number available pins, GPIO module shares pins with other functional modules. Upon power-on, GPIO control over shared pins embedded needs disable GPIO function restore specially assigned function.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
PRELIMINARY INFORMATION Rev. 07/16/02
IS11LV3100, IS11LV3101
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Vother TSTG Parameter Terminal Voltage with Respect Applied Voltage Other Pins Storage Temperature Operating Temperature Value +125 Unit
ISSI
Note: Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. These devices electrostatic sensitive. Devices should transported stored antistatic containers. Equipment personnel contacting devices need properly grounded. Cover work benches with grounded conductive mats.
OPERATING RANGE
Symbol VDD_IO VDD_RF Parameter Supply Voltage Core Supply Voltage Supply Voltage 2.25
TYP.
MAX. 2.75
UNIT
CAPACITANCE
Symbol CI/O Parameter Input Capacitance Input/Output Capacitance Conditions Max. 7.213 7.461 Unit
Note: Tested initially after design process changes that affect these parameters.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
PRELIMINARY INFORMATION Rev. 07/16/02
IS11LV3100, IS11LV3101
ELECTRICAL CHARACTERISTICS 2.5V, unless otherwise noted)
Symbol IDD_CONN IDD_PEAK IDD_SB Parameter Current Comsumption Connection Current Comsumption Peak Standby Current Input HIGH Voltage Input Voltage Output HIGH Voltage Output Voltage Output High Leakage Output Leakage Test Conditions VDD=2.5V, VDD_IO=3.3V VDD_RF=2.5V VDD=2.5V, VDD_IO=3.3V VDD_RF=2.5V VDD=2.5V, VDD_IO=3.3V VDD_RF=2.5V Min. Typ. VDD_IO
ISSI
Max. Unit
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
PRELIMINARY INFORMATION Rev. 07/16/02
IS11LV3100, IS11LV3101
ORDERING INFORMATION Extended Range: +85°C
Order Part IS11LV3100-B IS11LV3100-LQ Package LFBGA LQFP
ISSI
Extended Range: +85°C
Order Part IS11LV3101-B IS11LV3101-LQ Package LFBGA LQFP
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
PRELIMINARY INFORMATION Rev. 07/16/02

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