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Intel® PXA800F Cellular Processor
Developer's Manual
July 2003 Revision 0.75
Order Number: 252-569
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PXA800F Cellular Processor Developer's Manual Preliminary
Abstract
Intel® PXA800F Cellular Processor with Intel® XScaleTechnology advanced system solution today's GSM/GPRS mobile phones. This high-performance, power efficient processor fully integrated baseband solution that features Intel XScale microarchitecture Intel® Micro Signal Architecture (Intel® MSA). integration on-chip flash memory SRAM greatly increases processing power while reducing power consumption. PXA800F cellular processor enables development powerful, cost-effective wireless devices capable running rich data applications. includes development platform full-featured quad-band voice/data handset that scalable across multiple tiers. This manual provides high level overview subsystem features, detailed architecture signal descriptions, memory register mappings, specific peripheral chapters that include functional descriptions register bitmaps designers their development cellular handsets with PXA800F cellular processor. Application developers should this manual gain better understanding GSM/GPRS baseband implementation, while validation engineers should creating functional tests.
Revision History
Revision Description
Document name changed Intel PXA800F Cellular Processor Developer's Manual; Updated block diagrams, electrical timing information moved upcoming Intel PXA800F Cellular Processor Electrical, Mechanical Thermal Specification. Updated memory register map, signal descriptions interface
0.75
PXA800F Cellular Processor Developer's Manual Preliminary
Additional References
ARM* Architecture Version Specification (Document number 0100D-10),
ARM® Architecture Reference Manual (Document number 0100B)
ARM* Developer Suite Developer Guide ARM* Multi-ICE System Design Considerations, Application Note Intel® XScaleCore Developer's Manual (available online http://developer.intel.com/
design/intelxscale)
more general information, following documents websites helpful:
Sony Memory Stick Standard, Format Specification Version Infrared Data Association Serial Infrared Physical Layer Specification Version 1.3, October
1998 available www.irda.org
Specification, Royal Philips Electronics, order #9398 10011 (Secure Digital) Memory Card Specifications Part Physical Layer Specification,
September 2001, Version 1.01, Card Specification, Version 1.0, 2001, published Association (see http://www.sdcard.org).
MultiMediaCard System Specification Version 2.11 available www.mmca.org GSM11.11 Specification SIM-ME Interface Version 3.16.0 available
http://www.etsi.org/. also standard 7816-3
IEEE Std. 1149.1-1990 Standard Test Access Port Boundary-Scan Architecture
State Data
This preliminary release Intel® PXA800F Cellular Processor Developer's Manual. contains most current information that Intel able provide date publication. Although particular feature descriptions, timings, pin-outs specified, this information subject change, Intel® Corporation assumes liability errors contained within this document. Revisions this document will continue needed until PXA800F cellular processor released production.
PXA800F Cellular Processor Developer's Manual Preliminary
Contents
Introduction
Product Overview Features. Architecture Overview. Memory Subsystem Overview 2.2.1 Intel XScale Microarchitecture Memory Subsystem 2.2.2 Intel Memory Subsystem. 2.2.3 GSM/GPRS Baseband Logic Memory Subsystem Intel XScale Microarchitecture Peripherals 2.3.1 General Purpose Input/Output Pins (GPIO) 2.3.2 UARTs 2.3.3 UICC Interfaces. 2.3.4 I2C* Interface 2.3.5 Device Controller 2.3.6 CSSP Synchronous Serial Port 2.3.7 Real Time Clock 2.3.8 1-Wire* Interface 2.3.9 Memory Stick* Interface. 2.3.10 MultiMedia Card/Secure Digital (MMC/SD) Interface 2.3.11 Keypad Interface. 2.3.12 Clock 2.3.13 Interface Intel GSM/GPRS Peripherals 2.4.1 Synchronous Serial Ports DSSP [1:5] 2.4.2 Timing Control Unit 2.4.3 Interrupt Controllers 2.4.4 Digital Audio Interface DSSP6 2.4.5 Slow Clock Module 2.4.6 Viterbi Accelerator 2.4.7 Cipher Accelerator 2.4.8 High Speed Logger 2.4.9 Timers 2.4.10 Interface Bottom Connector Multiplexed Pins. 3.1.1 TF-BGA Ballout Assignments 3.1.2 Multiplexed Selection Buffer Selection.
Architecture Signals Overview
Signal Descriptions
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
System Memory Map. 4.1.1 Memory Map. 4.1.2 Register Clocking 5.1.1 Clock Frequencies Generation 5.1.2 Clock Configurations. 5.1.3 Interface Frequencies Power Management. 5.2.1 Overview. 5.2.2 External Power Management 5.2.3 Power-Off. 5.2.4 Power-On/Off-Sequence PXA800F Processor. Analog Baseband Requirements PXA800F Processor Overview. Serial Interface. 6.3.1 Synchronous Serial Ports. 6.3.2 Synchronous Serial Ports Operation Control. Oscillator Control
Clock Power
Interface
Appendix Ball Array. Appendix Package Diagram.
PXA800F Cellular Processor Developer's Manual Preliminary
Tables
Signal Descriptions. Default Bottom Connection Multiplexed Pins Example Additional Bottom Connection Multiplexed Pins Ballout Table. IOPCR Addresses Default Definitions. IOMCRG0 Register 0x42A00400 IOMCRG1 Register 0x42A00404 IOMCRG2 Register 0x42A00408 IOMCRG3 Register @0x42A00400C IOMCRG4 Register 0x42A00410 IOMCRG5 Register 0x42A00414 IOMCRG6 Register 0x42A00418 IOMCRG7 Register 0x42A0041C IOMCRG8 Register 0x42A00420 IOMCRS0 Register 0x42A01000 IOMCRS1 Register 0x42A01004 IOMCRS2 Register 0x42A01008 PXA800F Processor Top-Level Memory Intel® Peripherals Intel® XScale Microarchitecture Flash Intel® XScale Microarchitecture Peripherals Register Address PXA800F Processor's External Interface Frequencies Power Domain Groups Time Duration Values
PXA800F Cellular Processor Developer's Manual Preliminary
Figures
Block Diagram Memory Subsystem. XScale Microarchitecture Peripherals GSM/GPRS Peripherals. Selection Example. Programmable Buffers. PXA800F Processor Power Reset Sequence PXA800F Processor Power On/Off Timing Diagram. External Components PXA800F Processor Design. PXA800F Processor Generic Radio Interface. PXA800F Processor Serial Interfaces. Frame Format.
PXA800F Cellular Processor Developer's Manual Preliminary
viii
Introduction
Product Overview
Intel® PXA800F Cellular Processor with Intel® XScaleTechnology GSM/GPRS baseband system solution next generation wireless products. high-performance, powerefficient platform that integrates Intel XScale microarchitecture (ARM* Version architecture compliant), Intel® Micro Signal Architecture (Intel MSA), GSM/GPRS baseband communication logic, integrated on-chip Intel flash memory, integrated on-chip SRAM. Intel high performance digital signal processor/microcontroller. combined, this provides performance headroom support compute-intensive voice data applications next generation handset designs. PXA800F cellular processor highly scalable device with selectable performance peripherals that allow customers design wide range solutions such
Basic GSM/GPRS phone highly capable phone design built using PXA800F cellular High performance GSM/GPRS phone this design implements PXA800F cellular
processor with both Intel XScale Intel cores running utilizing on-chip memory arrays processor running Intel XScale core Intel core MHz.
PXA800F cellular processor uses 241-pin TF-BGA package configuration.
Features
Intel XScale microarchitecture subsystem:
Operates selectable clock frequencies High performance instruction data cache MByte on-chip Intel flash memory KByte on-chip SRAM External memory controller which supports following: MHz, 16-bit interface [104 MB/s] Asynchronous page, synchronous burst mode flash, SRAM 1.8V LP-SDRAM, MByte partitions, latency Asynchronous such external display controller synchronous/asynchronous chip selects, these used chip selects, SDRAM chip selects
interrupt controllers slow clocking control Three UARTs data, Bluetooth* IrDA applications
PXA800F Cellular Processor Developer's Manual Preliminary
Introduction
Universal Serial (USB) interface, compliant general purpose peripherals supporting discrete control/status, debounce,
transition detection: tolerant, 1.8V tolerant CSSP, synchronous serial port Four pulse width modulators timers plus watchdog Clock power management controllers MultiMedia Card/Secure Digital (MMC/SD) Real time clock function Dallas 1-Wire* interface Sony* Memory Stick* interface interface UICC interface Keypad rotary encoder interface Programmable frequency clock output interface power management communication
Intel Micro Signal Architecture subsystem:
Intel Micro Signal Architecture processor KByte banks on-chip data SRAM KByte on-chip flash Multi-protocol synchronous ports external baseband I/Q, voiceband, auxiliary ADC/DAC, synthesizer control, digital audio interface (DAI)
digital audio interface stereo hi-fi output
GSM/GPRS Baseband Logic:
Dedicated timing control unit (TCU) GSM/GPRS interrupt controller Cipher hardware accelerator Viterbi accelerator which provides Viterbi decoding, error correction equalization High speed data logger (HSL)
PXA800F Cellular Processor Developer's Manual Preliminary
Architecture Signals Overview
Architecture Overview
Intel® PXA800F Cellular Processor with Intel® XScaleTechnology operates maximum frequency processes GSM/GPRS protocol stack. also computing headroom process many other applications. Intel XScale miroarchitecture subsystem features instruction cache data cache, on-chip flash SRAM, memory controller, controller, interrupt controller, general purpose controller. PXA800F cellular processor also contains Intel subsystem. This unit interfaces with external GSM/GPRS mixed signal solutions, transfers CODEC data, transfers baseband data. This data processed digital signal processing engine operating frequency MHz. Intel core contains instruction cache, on-chip flash SRAM. GSM/GPRS baseband logic contains dedicated timing control unit (TCU), GSM/GPRS interrupt controller, cipher hardware accelerator, Viterbi accelerator high speed data logger (HSL). addition, sophisticated power management, clock reset controller.
Figure
PXA800F Cellular Processor Block Diagram
JTAG
JTAG CTRL
Intel XScaleCore
External Memory
InterruptController GSMIRQCtrl I-Cache D-Cache MBFlash SRAM Memory Controller
XScaleCorePeripherals
Bridge/DMA Controller
KeypadIF Rotary Encoders Wire Reserved 3xTimers/WDT GPIOs M/NClockOut UART1,2,3 CSSP GSM_SIM MMC/SD UICC GSM_SlowCLK
Intel MSACore
Clocks
Chip-level Power Management RTC/VCXO/PLL Power Control
Flash SRAM SRAM DMACtrl GSMIRQCtrl Viterbi Accelerator Cipher Accelerator Band DSSP1 Band DSSP2 Voiceband DSSP3 Auxilliary DSSP4 RFControlDSSP5 DAIDSSP6
PXA800F Cellular Processor Developer's Manual Preliminary
Architecture Signals Overview
Memory Subsystem Overview
PXA800F cellular processor achieves high performance from internal memory subsystem. memory controller that allows wide range external memory components used depending level sophistication performance required handset designer.
Figure
Memory Subsystem
External Memory Misc
Intel® XScale@
Cache, Flash
External Radio Interface
Intel® GSM/GPRS Baseband Logic Block
SRAM Flash,SRAM
2.2.1
Intel XScale Microarchitecture Memory Subsystem
Intel XScale microarchitecure contains instruction data cache. also on-chip MByte block Intel flash memory that supplies code data storage. addition flash array, KByte block on-chip SRAM. Both memory arrays wide, support burst reads writes, operate MHz, regardless core operating frequency. Intel XScale microarchitecture also contains memory controller that manages accesses external LP-SDRAM partitions CL=2/3), synchronous burst SRAM flash/ROM subsystems. read/write transaction internal system destined external memory access claimed memory controller, data returned from, written into, memory after suitable delay depending memory access time. memory controller supports five chip-select signals enable various memory module types addition LPSDRAM chip-selects. address range each five16-bit wide external memory banks Parameters memory configuration registers independently select memory type access mode (synchronous asynchronous) each memory bank. external also supports devices such external display controller.
PXA800F Cellular Processor Developer's Manual Preliminary
Architecture Signals Overview
2.2.2
Intel Memory Subsystem
Intel core integrated SRAM memory. performs microcontroller-like instructions using separate eight address pointers. special instructions maximize performance GSM/GPRS including Viterbi instructions filtering instructions. Intel flash array supports synchronous interface with KByte array Intel program storage. Intel processor dual bank KByte SRAM array.
2.2.3
GSM/GPRS Baseband Logic Memory Subsystem
Both timing control unit (TCU) cipher hardware accelerator, which part GSM/GPRS baseband logic block, have dedicated blocks SRAM that neither visible used customer specific applications.
Intel XScale Microarchitecture Peripherals
PXA800F cellular processor variety peripherals that controlled Intel XScale microarchitecture.
Figure
Intel XScale Microarchitecture Peripherals
Intel® XScaleI/O: UARTs, USB, I2C, Keypad, RTC, XSSP, GSM_SIM PWM, MMC/SD, GPIOs,
Intel® XScale@
ICache DCache Flash SRAM
External Radio Interface External Radio Interface
Intel® GSM/GPRS Baseband Logic Block
SRAM SRAM SRAM Flash
2.3.1
General Purpose Input/Output Pins (GPIO)
PXA800F cellular processor provides 61general purpose peripherals supporting discrete control/status, debounce, transition detection. Each GPIO individually programmed either input output. default configuration PXA800F cellular processor provides these GPIOs, however, they configured other peripherals such UARTs, PWM, I2C, etc. multiplexing peripheral functions with these GPIOs, providing greater flexibility. This selectable through register programming IOPCR, IOMCRG IOMCRS registers.
PXA800F Cellular Processor Developer's Manual Preliminary
Architecture Signals Overview
Note:
these GPIO/muxed peripherals tolerant while 1.8V tolerant. default state these GPIOs will configured input pins.
2.3.2
UARTs
PXA800F cellular processor three separate UARTs that compatible with 16550 16750 industry standards. full function UART1 supports full modem control capabilities with maximum baud rate 921,600 bits second. UART2 UART3 similar UART1, however they only support modem control pins, nCTS nRTS, both support Bluetooth* module infrared transmitter receiver.
2.3.3
UICC Interfaces
card provided PXA800F cellular processor contains user data access network supports small applications typically used secure communication. interface also dedicated voltage which supplied external power management flexible voltage programming. UICC interface also provided, supports both transfer protocols.
2.3.4
I2C* Interface
interface common serial interface used interface external peripherals such external power management Both standard (100 Kbps) fast-dash mode (400 Kbps) supported.
2.3.5
Device Controller
This 2-wire client device supports eight endpoints operates half-duplex baudrate Mbps. This module functions client only, does perform host functions. This interface compliant.
2.3.6
CSSP Synchronous Serial Port
This 4-wire, full duplex synchronous serial interface. supports several industry standard protocols. rates MHz.
2.3.7
1-Wire* Interface
This serial interface communicates with smart battery management PXA800F cellular processor provides 1.8V 3.0V 1-wire interface depending this signal selected through muxing table. 1-Wire* interface available pin-muxing options multiple pins. Users this interface must provide appropriate level shifting proper operation, depending choice being used implement 1-Wire* functionality.
PXA800F Cellular Processor Developer's Manual Preliminary
Architecture Signals Overview
2.3.8
Memory Stick* Interface
This interface allows Intel XScale microarchitecture access Sony* Memory Stick* device allows PXA800F cellular processor based mobile station include removable non-volatile memory feature.
2.3.9
MultiMedia Card/Secure Digital (MMC/SD) Interface
MMC/SD controller supports both multimedia card (MMC) secure digital (SD) communication protocols. This controller based System Specification V2.11 memory card (secure digital memory card) Specification Version 1.0. PXA800F cellular processor supports both MMC/SD mode mode. application specifies mode communication controller. controller supports cards mode, mode combination both. Only card supported time.
2.3.10
Keypad Interface
keypad interface independent port that allows PXA800F cellular processor phones access standard keypads. supports keypad matrix rows columns. keypad interface also supports rotary encoders, direct inputs.
2.3.11
Clock
This frequency programmable, 1.8V clock output. default frequency this clock MHz, however frequency reduced programming fractional bits. There bits bits. combination these divided bits then multiplied against default clock provide reduced clock output.
2.3.12
Interface
PXA800F cellular processor four pulse-width modulated outputs buzzer battery charger.
2.3.13
Timing Control Unit
central module PXA800F cellular processor. calibrated downlink (base station) timing generates clocks events. This includes quarter clock, clock, slot timing, frame timing. uses SRAM array that stores commands events. executes these commands pre-specified quarter clock cycles frame. general purpose output bits that asserted/deasserted quartertick frame. These outputs precisely time synthesizer programming, power ramp-up ramp-down, Intel interrupts.
PXA800F Cellular Processor Developer's Manual Preliminary
Architecture Signals Overview
2.3.14
Interrupt Controllers
PXA800F cellular processor second interrupt controllers designed handle events generated TCU. special interface between these controllers allows direct, system-timed generation Intel interrupts.
2.3.15
Slow Clock Module
This module works conjunction with main clock control power management blocks. Like interrupt controllers, mating device with TCU. runs clock used freewheel downlink (base station) timing while phone standby mode.
2.3.16
Real Time Clock
PXA800F cellular processor power real time clock (RTC) that maintains time-of-day information even when phone powers down. uses crystal, capacitive spec load requires external capacitors.
2.3.17
Timers
Intel XScale microarchitecture subsystem three programmable timers watchdog available.
PXA800F Cellular Processor Developer's Manual Preliminary
Architecture Signals Overview
GSM/GPRS Peripherals
digital signal processing unit GSM/GPRS digital baseband logic block also interface with number peripherals include analog baseband module interface.
Figure
GSM/GPRS Peripherals
XScaleExternal Memory Display, Intel XScale
Intel® XScale@
ICache DCache Flash SRAM
Intel® GSM/GPRS I/O: TCO, I2S, DSSPx, TCO, I2S, DSSPx,
Intel® GSM/GPRS Baseband Logic Block
SRAM Flash
2.4.1
Synchronous Serial Ports DSSP [1:5]
These five synchronous serial ports used communication with analog mixed signal baseband module which interfaces with interface. example, DSSP1 frame used transmit bits transmit data analog baseband, while DSSP2 frame used receive bits samples from analog baseband. DSSP4 used auxiliary serial port read write analog baseband module's control registers, DDSP3 used serial port voiceband interface. DSSP5 used serial port interface with interface control registers.
2.4.2
Digital Audio Interface DSSP6
Full type approval testing requires special interface order perform exact testing speech coder/decoder SLR/RLR performance analog acoustic devices. facilitates this testing providing capability insert extract speech data both transmit receive directions. This interface complies with Section 3GPP ETSI Specification.
PXA800F Cellular Processor Developer's Manual Preliminary
Architecture Signals Overview
2.4.3
Viterbi Accelerator
Viterbi Accelerator provides hardware assist Viterbi error decoding equalization. loads Intel MSA, freeing MIPS other tasks while saving power during these tasks.
2.4.4
Cipher Accelerator
This module provides fast, lower power generation Cipher data streams used encrypt decrypt voice data. Like Viterbi Accelerator, also loads Intel frees MIPS other tasks.
2.4.5
High Speed Logger
high speed logger logs real time Intel software events. intended debug diagnostic use. interfaces external card, which runs special diagnostic software.
2.4.6
Interface
This interface transfers hi-fidelity (full bandwidth) digital audio data when combined with InterIntegrated Circuit Sound compatible audio codec. This accomplished power, fourpin serial interface. This interface features sampling frequencies through KHz, 32-bit data frame support left right channels.
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
This section provides description PXA800F cellular processor signals. simplicity, signals arranged functional groups according their interface. This section lists signals capital letters, uses indicate active state. column provided describe whether dedicated multiplexed signal, whether input, output, I/O.
Table
Signal Descriptions
Signal Name CPU_JTAG
CP_TCLK CP_TDI CP_TMS CP_TRST# CP_TDO JTAG test clock JTAG test data input JTAG test JTAG test reset JTAG test data output
Description
High Speed Logger
HSL_DATA[4:0] HSL_CLK Data Data clock
Keypad
KPD_R[7:0] KPD_C[5:0] Keypad matrix returns Keypad matrix outputs
Rotary Encoder
DK_1A DK_1B DK_2A DK_2B Direct Key1 Rotary Encoder Direct Key2 Rotary Encoder Direct Key3 Rotary Encoder Direct Key4 Rotary Encoder
GSM_SIM_CLK GSM_SIM_DIO GSM_SIM_RST# clock output Data card Active reset output card
UICC
UICC_CLK UICC_DIO UICC_RST# UICC clock output UICC data UICC reset
Pulse Width Modulator
PWM[3:0] Pulse width modulators
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Signal Name
Output Clock
Description
MN_CLK_OUTO
Programmable Frequency output clock
USB+ USBD positive differential pair negative differential pair
XScale Microarchitecture Synchronous Serial Port (CSSP)
CSSP_CLK CSSP_FRM CSSP_TX CSSP_RX Serial data clock Frame Sync/Chip Select/Latch Enable Serial Data Serial Data
Full Function UART1 Data
UART1_RX UART1_CTS# UART1_RTS# UART1_TX UART1_DSR# UART1_DTR# UART1_RI# UART1_DCD# Full function UART receive Full function UART clear send Full function UART ready send Full function UART transmit Full function UART data ready (SPIO) Full function UART data terminal ready (SPIO) Full function UART ring indicator (SPIO) Full function UART data carrier detect (SPIO)
UART2
UART2_RX UART2_TX UART2_CTS# UART2_RTS# UART2 receive UART2 transmit UART2 clear send UART2 ready send
UART3
UART3_RX UART3_TX UART3_CTS# UART3_RTS# UART3 receive UART3 transmit UART3 clear send UART3 ready send
Radio Interface
TCO3 TCO0 TCO[10:6] TCO4 TCO1 TCO5 TCO2 RX_ENA1 Enable receiver front (LNA, mixers) RX_ENA2- Enable receiver back amp, PGA) BAND_SEL[4:0] Selects bands. Switches transceiver GSM, DCS, bands TX_ENA Enable transmitter VCO, control loop VLO_ENA Enables (Regulator Enable) DRAIN_SW_ENA Controls switch. Selects signal path PA_NEGV_ENA Enable negative supply (only GaAs
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Signal Name
Interface
Description
TCO14 TCO13 TCO12 TCO11 TCO[23:15]
RXON Baseband receive section power output TXON Baseband transmit section power output ATSM Advance baseband transmit timing state machine output ARSM Advance baseband receive timing state machine output Spare TCOs
NOTE: Although preliminary assignments Timing Control Outputs (TCOs) assumed, TCOs completely configurable, programmed control signals Timing Control Outputs
TCO[10:0] TCO[23:11] Primary TCO's, intended command/control baseband mixed signal components Secondary TCO's usually multiplexed with other functions
Clocks
VCXO_ON VCXO OSC_32KHZ_IN OSC_32KHZ_OUT VCXO_ON signal that enables power management power VCTCXO system clock clock input clock output
1-Wire Interface
ONE_WIRE_DQ 1-Wire* Interface, open drain
Interface
I2C_SDA I2C_SCL I/OD I/OD data/address clock
ABBCLK
ABBCLK ABBCLK_EN ABB_RESET# Master data clock DSSP MCLK enable control Baseband reset
DSSP1 Baseband)
DSSP1_TX DSSP1_FRM Transmit serial data Frame sync/chip select/latch enable
DSSP2 Baseband)
DSSP2_RX DSSP2_FRM Receive serial data Frame sync/chip select/latch enable
DSSP3 Voiceband
DSSP3_TX DSSP3_RX DSSP3_FRM DSSP3_CLK Transmit serial data Receive serial data Frame sync/chip select/latch enable Serial data clock Bluetooth only
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Signal Name
DSSP4 Auxiliary
Description
DSSP4_TX DSSP4_RX DSSP4_FRM
Transmit serial data Receive serial data Frame sync/chip select/latch enable
DSSP5 Control)
DSSP5_TX_RX DSSP5_FRM DSSP5_CLK Transmit/receive serial data, direction programming IOPCR register Frame sync/chip select/latch enable Serial data clock
DSSP6 (DAI)
DSSP6_TX DSSP6_RX DSSP6_CLK DSSP6_FRM Transmit serial data Receive serial data Serial data clock Frame sync/chip select/latch enable
MiscelLaneous
ALARM PMIC_INTR# Alerts power management resume Interrupt input from power management alert battery status
Interface
I2S_SYSCLK S_FSYNC I2S_DO I2S_DI I2S_BITCLK
Sync Serial System clock Sync Serial frame Sync Serial data Sync Serial Data Sync Serial Clock
External Memory
EXT_ADDR[24:1] EXT_DATA[15:0] EXT_CS#[5:1] EXT_OE# EXT_WE# EXT_DQM[1:0] EXT_SDCS#[1:0] EXT_SDCAS# EXT_SDRAS# EXT_SDCLK[1:0] EXT_SDCKE EXT_RDY EXT_PWE# Address bus, external devices Data bus, 16-bit, bi-directional, external devices Chip selects, non-SDRAM memories (Async SRAM, LCD, flash) Output Enable Write strobe strobe (SDRAM, Async SRAM, flash, LCD) Byte mask control (SDRAM, Async SRAM, flash) SDRAM chip selects SDRAM column address strobe, burst flash address valid (ADV#) SDRAM address strobe SDCLK0 Async memory burst flash, SDCLK1 SDRAM SDCLK enable Wait signal burst flash VLIO device write enable
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Signal Name
GPIO
Description
GPIO 63:62,60,57:0
General purpose (GPIO used internally)
MultiMedia Card/Secure Digital MMC/SD
MM_CLK MM_CMD MM_DAT0 MM_DAT1 MMC, Modes: clock, output MMC, Modes: Command/response tokens, bidirectional Mode: Command/data, output MMC, Modes: Data, bidirectional Mode: data response token, input Mode: Data (4-bit transfers), bidirectional MMC, Modes: used Mode: Data (4-bit transfers), bidirectional Mode: used Mode: chip select, output Mode: Data (4-bit transfers), bidirectional Mode: used Mode: chip select, output
MM_DAT2_CS0
MM_DAT3_CS1
Sony Memory Stick
MS_SCLK MS_DIO MS_BS Serial protocol clock Serial protocol data Serial protocol state
Power Ground
VCCP_SIM VSSP_ABB VCCP_ABB VSSP_RF VCCP_RF VSS_RTC VCC_RTC VSSA_PLL2 VCCA_PLL2 VSSP_3V VCCP_3V VSSP_1P8V_2 VCCP_1P8V_2 VSSP_1P8V_1 VCCP_1P8V_1 VSS_CORE VCC_CORE VPP_1P8V_10V VCCH_1P8V Voltage selected power management chip voltage determined Analog Baseband voltage determined Synthesizer interface Real time clock voltage power VCC/GND VCC/VDD VCC/VDD Core Core VCC/VDD, 1.2V Flash program voltage, 1.8V normal, 10.5 programming flash voltage
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Bottom Connector Multiplexed
PXA800F cellular processor allows flexible multiplexing, multiple signal combinations configured work with special purpose port known bottom connector. Table provides example eight PXA800F cellular processor pins grouped together default GPIOs. They 1.8V tolerant located corner package. Some pins have more pins multiplexed than others. Table provides examples some many combinations that PXA800F cellular processor affords designer. example, configuration could used convenient port interface.
Table
Default Bottom Connection Multiplexed Pins
Ball
Default
GPIO33 GPIO54 GPIO57 GPIO56 GPIO27 GPIO55 GPIO53 GPIO52
MUX_CLK0 UART1_RX DSSP6_TX DSSP6_RX DSSP6_FRM DSSP6_CLK UART2_RX UART2_TX
UART1_TX
DSSP3_TX DSSP3_RX DSSP3_FRM DSSP3_CLK HSL_DATA1 HSL_DATA0
HSL_CLK HSL_DATA4 HSL_DATA3 HSL_DATA2 DSSP3_TX DSSP3_RX
CSSP_TX CSSP_RX UART2_RTS# UART2_CTS# UART1_DTR# UART1_DSR#
UART1_RTS# UART1_CTS# CSSP_FRM CSSP_CLK UART1_RI# UART1_DCD#
Table
Example Additional Bottom Connection Multiplexed Pins
Ball Config
GPIO33 GPIO54 GPIO57 GPIO56 GPIO27 GPIO55 GPIO53 GPIO52
Config
GPIO33 GPIO54 DSSP6_TX DSSP6_RX DSSP6_FRM DSSP6_CLK GPIO53 GPIO52
Config
MUX_CLK0 GPIO54 DSSP3_TX DSSP3_RX DSSP3_FRM DSSP3_CLK UART2_RX UART2_TX
Config
GPIO33 GPIO54 HSL_CLK HSL_DATA4 HSL_DATA3 HSL_DATA2 HSL_DATA1 HSL_DATA0
Config
GPIO33 GPIO54 GPIO57 GPIO56 UART2_RTS# UART2_CTS# GPIO53 GPIO52
Config
GPIO33 GPIO54 CSSP_TX CSSP_RX CSSP_FRM CSSP_CLK GPIO53 GPIO52
Config
UART1_TX UART1_RX UART1_RTS# UART1_CTS# UART1_RI# UART1_DCD# UART1_DTR# UART1_DSR#
3.1.1
TF-BGA Ballout Assignments
Table shows signals multiplexed each ball/pin well associated voltage pin. Software controls multiplexing Multiplexing Control Register General (IOMCRG) Multiplexing Control Register Special (IOMCRS) control register arrays. IOMCRG registers selecting those pins which have four multiplexing options, IOMCRS registers used selecting those pins which have five nine multiplexing options. These registers only define which type signal assigned given ball/pin. ball/pin selected also particular voltage assigned (please column left table) user should careful match appropriate voltage levels when interfacing PXA800F cellular processor with other third party components.
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Figure provides example address location bits required select particular function.
Figure
Selection Example
3.0V
GPIO44
0000
I2S_DI
0001
CSSP_RX
0010
HSL_DATA1
0011
IOPCR DSSP3_RX
0100
IOMCRS2
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Table
Volt.
Ballout Table
Function
I2S_DI I2S_FSYNC
Ball
Default function
GPIO44 GPIO43 VSSP_3V GPIO6 VCC_CORE VSS_CORE EXT_ADDR3 VCCP_1P8V_2 EXT_ADDR19 VSSP_1P8V_2 EXT_ADDR10 EXT_ADDR13 EXT_ADDR16 GPIO33 VCCP_1P8V_2 GPIO56 GPIO27 GPIO8 GPIO9 GPIO4 GPIO5 GPIO32 VSS_CORE VSSP_1P8V_2 EXT_ ADDR7 VCCP_1P8V_2 EXT_DQM1 VCCP_1P8V_2 VCCP_1P8V_2 VCCP_1P8V_2 GPIO54 GPIO57 VSSP_1P8V_2 GPIO55 USB# VCCP_3V GPIO7 VPP_1P8V_10V VCCH_1P8V EXT_ADDR4 VSSP_1P8V_2 EXT_DQM0 VCCP_1P8V_2 VSSP_1P8V_2 EXT_ADDR14
Function
CSSP_RX HSL_DATA0
Function
HSL_DATA1
Function
DSSP3_RX
Function
Function
Function
Function
MM_DAT0
MS_DIO
GSM_SIM_DIO
UICC_
GPIO18
GPIO2
GPIO11 GPIO8 GPIO5 MUX_CLK0 UART1_TX
DSSP6_RX DSSP6_ MM_CMD MM_DAT1 MM_DAT2_CS0 MM_DAT3_CS1 I2C_SDA
DSSP3_RX DSSP3_ MS_SCLK CSSP_TX GSM_SIM_CLK TCO22 CSSP_CLK
HSL_DATA4 HSL_DATA3 GSM_SIM_RS# HSL_CLK UICC_CLK PWM0 DSSP3_CLK
CSSP_RX UART2_RTS# UICCRST# DSSP3_TX
UART1_CS# CSSP_FRM UART1_RI#
GSM_SIM_DIO
UICC_DIO
TCO23
PWM1
GSM_SIM_RST#
UICC_RST#
ONE_WIRE_DQ
GPIO14
GPIO49
UART1_RX DSSP6_TX DSSP3_TX HSL_CLK CSSP_TX UART1_RTS#
DSSP6_CLK
DSSP3_CLK
HSL_DATA2
UART2_CTS#
CSSP_CLK
UART1_DCD#
MM_CLK
MS_BS
GPIO17
GPIO48
GPIO7
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Volt.
Ball
Default function
MN_CLK_OUT0 VSSP_ 1P8V_2 GPIO52 GPIO42 GPIO53 VSSP_3V GPIO46 GPIO45 VCCP_3V VCCH_1P8V VCCP_ 1P8V_2 EXT_ADDR5 EXT_ADDR8 EXT_ ADDR18 EXT_WE# EXT_ ADDR11 VSSP_ 1P8V_2 GPIO26 GPIO41 GPIO40 GPIO39 VCCP_ 1P8V_2 GPIO47 TCO12 TCO14 TCO13 GPIO2 VCCH_1P8V EXT_ADDR2 EXT_ADDR6 VCC_CORE VSS_CORE EXT_ADDR9 EXT_ ADDR12 EXT_ ADDR15 VCC_CORE GPIO51 GPIO50 VSS_CORE ABBCLK VCCP_ABB VSSP_ABB TCO11 ABBCLK_EN
Function
PWM0
Function
MHz_CLK
Function
Function
Function
Function
Function
Function
UART2_TX DK_2B UART2_RX
HSL_ DATA0 PWM3 HSL_ DATA1
DSSP3_RX TCO22 DSSP3_TX
UART1_DSR#
UART1_DTR#
MHz_CLK
I2S_DO I2S_SYSCLK
HSL_ DATA3 CSSP_TX HSL_ DATA2 DSSP3_ GSM_SIM_CLK UICC_CLK
GPIO16 GPIO13 GPIO3
GPIO9
PWM1 DK_2A DK_1B DK_1A
MUX_ CLK0 PWM2 PWM1 PWM0 TCO21 TCO20 TCO19 UART3_ UART3_
VCCP_ VCCP_ VCCP_
I2S_BITCLK
HSL_ DATA4
ONE_WIRE_DQ
I2C_SCL
CSSP_
DSSP3_
GPIO19 GPIO15
GPIO12
GPIO6
EXT_ SDCS0# EXT_ SDCS1#
Reserved Reserved
VCCP_
VCCP_ VCCP_
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Volt.
Ball
Default function
GPIO22 GPIO21 VCCP_ 1P8V_2 GPIO29 VSSP_ 1P8V_2 DSSP3_TX DSSP3_RX DSSP3_ DSSP4_RX DSSP4_ KPD_C5 KPD_C3 KPD_C4 VCC_CORE VSS_CORE ABB_ RESET# VSSP_ABB VCCP_ABB DSSP4_TX VCC_CORE KPD_C2 KPD_C1 VCCP_ 1P8V_2 EXT_ SDCLK0 VSSP_ 1P8V_2 DSSP2_RX DSSP2_ DSSP1_ DSSP1_TX VSS_CORE KPD_C0 VCC_CORE VSSP_ 1P8V_2 GPIO30 VSS_CORE VCXO_ON DSSP5_CLK DSSP5_
Function
Function
Function
Function
Function
Function
Function
Function
EXT_ ADDR23 EXT_ ADDR22
EXT_SDCKE
Reserved
VCCP_ VCCP_ VCCP_ VCCP_ VCCP_
TCO17 Reserved TCO18
Reserved
Reserved
VCCP_
VCCP_
Reserved Reserved
UART3_TX
VCCP_ VCCP_ VCCP_ VCCP_
Reserved
EXT_ SDCLK1
Reserved
VCCP_ VCCP_ VCCP_
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Volt.
VCCP_
Ball
Default function
DSSP5_TX_RX VCC_CORE KPD_R5 KPD_R4 KPD_R3 VCC_CORE VSS_CORE GPIO19 VSSP_RF VCCP_RF GPIO20 VSS_CORE KPD_R2 GPIO60 GPIO23 EXT_CS0# VCCP_ 1P8V_2 GPIO15 GPIO18 GPIO17 GPIO16 GPIO13 GPIO25 EXT_ ADDR21 EXT_ ADDR20 VCCP_ 1P8V_2 VSSP_ 1P8V_2 VCCP_RF GPIO14 VSSP_RF GPIO11 VCC_CORE VSS_CORE EXT_DATA8 VCC_CORE VSS_CORE EXT_DATA5 VCC_CORE VSS_CORE KPD_R1 KPD_R0 I2C_SDA
Function
Function
Function
Function
Function
Function
Function
Function
TCO15 TCO16 Reserved
UART3_ RTS# UART3_ CTS#
Reserved Reserved
VCCP_
TCO9
13MHz_CLK
VCCP_
TCO10
PWM0
Reserved EXT_ ADDR24 EXT_CS3# EXT_CS4# PWM2
VCCP_ VCCP_ VCCP_ VCCP_ VCCP_
TCO5 TCO8 TCO7 TCO6 TCO3 EXT_CS1# GPIO0 GPIO1 PWM1
VCCP_
TCO4
VCCP_
TCO1
GPIO45
Reserved Reserved
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Volt.
Ball
Default function
EXT_RDY VSSP_1 P8V_2 VCXO GPIO12 GPIO10 VSSA_PLL1 CP_TCLK GPIO35 EXT_OE# EXT_DATA2 EXT_DATA3 EXT_DATA4 EXT_DATA6 EXT_ DATA14 GPIO28 ALARM GPIO3 EXT_PWE# I2C_SCL VCCA_PLL2 VCCA_PLL1 VSSA_PLL2 CP_TDI CP_TDO GPIO24 VCCP_ 1P8V_1 VSSP_ 1P8V_1 VSSP_ 1P8V_1 VCCP_ 1P8V_1 EXT_ DATA13 EXT_DATA7 GPIO37 GPIO31 GPIO1 GPIO62 KPD_R7 GSM_SIM_ GSM_SIM_ RST# PMIC_INTR# CP_TMS GPIO34 GPIO38 VSSP_ 1P8V_1 EXT_DATA1
Function
KPD_R6
Function
Function
Function
Function
Function
Function
Function
VCC_ VCCP_ VCCP_
TCO2 TCO0
PWM2 PWM3
VCC_
UART3_RX
CSSP_RX
DSSP3_RX
GPIO43 EXT_ SDRAS# UART3_ Reserved
TCO18 PWM2
UART3_ ONE_WIRE_DQ
UART2_ RTS# 13MHz_CLK
EXT_CS2#
PWM1
VCC_ VCC_
GPIO28
TCO20 EXT_ SDCAS# TCO16 TCO17 Reserved UICC_DIO UICC_RST#
PWM1 UART3_ UART3_ RTS# UART3_
CSSP_FRM
DSSP3_
UART2_TX UART2_ CTS#
GSM_SIM_DIO GSM_SIM_CLK
UICC_ UICC_
TCO21 UART3_TX
PWM2 CSSP_TX
EXT_ CS5# DSSP3_TX
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Volt.
Ball
Default function
VCCP_ 1P8V_1 EXT_ DATA11 VSSP_ 1P8V_1 VSSP_ 1P8V_1 EXT_ ADDR17 VSSP_ 1P8V_1 GPIO63 VCC_RTC OSC_32KHZ_IN GSM_SIM_ VCCP_SIM VSSP_ 1P8V_1 CP_TRST# VCCP_ 1P8V_1 EXT_ADDR1 EXT_DATA0 EXT_DATA9 EXT_ DATA10 EXT_ DATA12 VCCP_ 1P8V_1 EXT_ DATA15 VCCP_ 1P8V_1 GPIO36 RESET_IN# VSS_RTC OSC_32KHZ_
Function
Function
Function
Function
Function
Function
Function
Function
GPIO30
GPIO4
TCO15
UART3_ CTS#
UART2_RX
GSM_SIM_RST#
UICC_ RST#
VCC_ VCC_
UICC_CLK
GPIO20
GPIO32 GPIO44 GPIO29
GPIO26
VCC_
TCO19
PWM0
CSSP_CLK
DSSP3_
VCC_
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
3.1.2
Multiplexed Selection Buffer Selection
mentioned section 3.1.1, pins that have multiple functions selected programming either IOCRMG (general) IOCRMS (special) registers. Table provides register address location those particular pins default mode IOPCR register, well indicating controlled general special control register. Parameter Control Register (IOPCR) defines parameters given pin. This register allows assignment different slew rates strength given output buffer. enables input hysteresis, internal pull-up pull-down resistors pull-up value selection. Figure shows programmable attributes PXA800F cellular processor buffers.
Figure
Programmable Buffers
Pullup Enable Load Select Core Hysterisis Enable Pulldown Enable Output Tri-state Enable From Core
Slew Rate Control Strength Control IOPCRBit Definition
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Table
IOPCR Definitions
Parameter Control Register template (IOPCR) Control HYSTEN PUEN PDEN LDSEL
Physical Address 0x42A0_0004 0x42A0_03C0
Reserved Reserved OUTENB
Reset
Bits
31:13 12:10
Access
Name
Reserved INDLY OUTENB Reserved Output Enable (outenb Cell) Output Tri-State Output Enabled
Description
Output Drive Strength (str[2:0] Cell) 000: mA@3V, mA@1.8V 001: mA@3V, mA@1.8V 010: mA@3V, mA@1.8V 011: mA@3V, mA@1.8V 100: mA@3V, mA@1.8V 101: mA@3V, mA@1.8V 110: mA@3V, mA@1.8V 111: mA@3V, mA@1.8V Output Drive Slew Rate (slw[1:0] Cell) Slow Medium Slow Medium Fast Fast Hysteresis Enable (hysten Cell) Hysteresis Enabled Hysteresis Disabled Pull-up Enable (puen Cell) Pull-up Enabled Pull-up Disabled Pull-down Enable (pden Cell) Pull-down Enabled Pull-down Disabled Pull-up Value Select (ldsel Cell) 200K@3V, 400K@1.8V 100K@3V, 200K@1.8V
HYSTEN
PUEN
PDEN
LDSEL
When function that corresponds bi-directional signal (such GSM_SIM_DIO) selected pad, then input output direction controlled directly logic that utilizes that signal, controlling signal routed when that bi-directional signal function chosen. only exception signal DSSP5_TX_RX signal which (OUTEN) IOPCR used control direction. Normal usage transmit only from DSSP_TX_RX analog baseband chip.
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Table
IOPCR Addresses Default Definitions
Default Function
GPIO44 GPIO43 VSSP_3V GPIO6 VCC_CORE VSS_CORE EXT_ADDR3 VCCP_1P8V_2 EXT_ADDR19 VSSP_1P8V_2 EXT_ADDR10 EXT_ADDR13 EXT_ADDR16 GPIO33 VCCP_1P8V_2 GPIO56 GPIO27 GPIO8 GPIO9 GPIO4 GPIO5 GPIO32 VSS_CORE VSSP_1P8V_2 EXT_ADDR7 VCCP_1P8V_2 EXT_DQM1 VCCP_1P8V_2 VCCP_1P8V_2 VCCP_1P8V_2 GPIO54 GPIO57 VSSP_1P8V_2 GPIO55 USB+ USBVCCP_3V GPIO7 VPP_1P8V_10V VCCH_1P8V EXT_ADDR4 VSSP_1P8V_2 EXT_DQM0
IOPCR Addr
0x42A0_03C0 0x42A0_03BC 0x42A0_03A8 0x42A0_0374 0x42A0_0348 0x42A0_0320 0x42A0_030C 0x42A0_02FC 0x42A0_02EC 0x42A0_02D8 0x42A0_02D4 0x42A0_0004 0x42A0_0008 0x42A0_03B4 0x42A0_03A4 0x42A0_039C 0x42A0_035C 0x42A0_0338 0x42A0_02E8 0x42A0_02E0 0x42A0_02D0 0x42A0_03AC 0x42A0_036C 0x42A0_033C
IOPCR Default
0x00dd 0x00dd 0x00dd 0x0158 0x0158 0x0158 0x0158 0x0158 0x017d 0x017d 0x017d 0x00dd 0x00dd 0x00dd 0x00dd 0x00dd 0x0158 0x0158 0x017d 0x017d 0x017d 0x00dd 0x0158 0x0158
IOMCRG/S Addr
0x42A0_1008 0x42A0_0420 0x42A0_1008 0x42A0_0420 0x42A0_041C 0x42A0_041C 0x42A0_041C 0x42A0_041C 0x42A0_0418 0x42A0_1004 0x42A0_1004 0x42A0_1000 0x42A0_1000 0x42A0_0420 0x42A0_1008 0x42A0_0420 0x42A0_041C 0x42A0_041C 0x42A0_0418 0x42A0_1004 0x42A0_1004 0x42A0_0420 0x42A0_0420 0x42A0_041C
IOMCR
IOMCRS2 IOMCRG8 IOMCRS2 IOMCRG8 IOMCRG7 IOMCRG7 IOMCRG7 IOMCRG7 IOMCRG6 IOMCRS1 IOMCRS1 IOMCRS0 IOMCRS0 IOMCRG8 IOMCRS2 IOMCRG8 IOMCRG7 IOMCRG7 IOMCRG6 IOMCRS1 IOMCRS1 IOMCRG8 IOMCRG8 IOMCRG7
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Default Function
VCCP_1P8V_2 VSSP_1P8V_2 EXT_ADDR14 MN_CLK_OUT0 VSSP_1P8V_2 GPIO52 GPIO42 GPIO53 VSSP_3V GPIO46 GPIO45 VCCP_3V VCCH_1P8V VCCP_1P8V_2 EXT_ADDR5 EXT_ADDR8 EXT_ADDR18 EXT_WE# EXT_ADDR11 VSSP_1P8V_2 GPIO26 GPIO41 GPIO40 GPIO39 VCCP_1P8V_2 GPIO47 TCO12 TCO14 TCO13 GPIO2 VCCH_1P8V EXT_ADDR2 EXT_ADDR6 VCC_CORE VSS_CORE EXT_ADDR9 EXT_ADDR12 EXT_ADDR15 VCC_CORE GPIO51 GPIO50 VSS_CORE ABBCLK VCCP_ABB VSSP_ABB
IOPCR Addr
0x42A0_0308 0x42A0_02F4 0x42A0_02C4 0x42A0_02C0 0x42A0_02C8 0x42A0_0020 0x42A0_0018 0x42A0_0368 0x42A0_0354 0x42A0_0350 0x42A0_032C 0x42A0_0318 0x42A0_02F0 0x42A0_02BC 0x42A0_02B4 0x42A0_02B0 0x42A0_0024 0x42A0_0030 0x42A0_0028 0x42A0_002C 0x42A0_03A0 0x42A0_0378 0x42A0_0360 0x42A0_0324 0x42A0_0314 0x42A0_0300 0x42A0_02A4 0x42A0_02A0 0x42A0_0040
IOPCR Default
0x0158 0x0170 0x017d 0x017d 0x017d 0x00dd 0x00dd 0x0158 0x0158 0x0158 0x0150 0x0158 0x017d 0x017d 0x017d 0x017d 0x00dd 0x00d0 0x00d0 0x00d0 0x00dd 0x0158 0x0158 0x0158 0x0150 0x0158 0x015c 0x015c 0x00d0
IOMCRG/S Addr
0x42A0_041C 0x42A0_0418 0x42A0_1004 0x42A0_0418 0x42A0_1004 0x42A0_0400 0x42A0_1000 0x42A0_0420 0x42A0_041C 0x42A0_041C 0x42A0_041C 0x42A0_041C 0x42A0_0418 0x42A0_0418 0x42A0_1004 0x42A0_1004 0x42A0_0400 0x42A0_0400 0x42A0_0400 0x42A0_0400 0x42A0_0420 0x42A0_0420 0x42A0_041C 0x42A0_041C 0x42A0_041C 0x42A0_041C 0x42A0_0418 0x42A0_0418 0x42A0_0400
IOMCR
IOMCRG7 IOMCRG6 IOMCRS1 IOMCRG6 IOMCRS1 IOMCRG0 IOMCRS0 IOMCRG8 IOMCRG7 IOMCRG7 IOMCRG7 IOMCRG7 IOMCRG6 IOMCRG6 IOMCRS1 IOMCRS1 IOMCRG0 IOMCRG0 IOMCRG0 IOMCRG0 IOMCRG8 IOMCRG8 IOMCRG7 IOMCRG7 IOMCRG7 IOMCRG7 IOMCRG6 IOMCRG6 IOMCRG0
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Default Function
TCO11 ABBCLK_EN GPIO22 GPIO21 VCCP_1P8V_2 GPIO29 VSSP_1P8V_2 DSSP3_TX DSSP3_RX DSSP3_FRM DSSP4_RX DSSP4_FRM KPD_C5 KPD_C3 KPD_C4 VCC_CORE VSS_CORE ABB_RESET# VSSP_ABB VCCP_ABB DSSP4_TX VCC_CORE KPD_C2 KPD_C1 VCCP_1P8V_2 EXT_SDCLK0 VSSP_1P8V_2 DSSP2_RX DSSP2_FRM DSSP1_FRM DSSP1_TX VSS_CORE KPD_C0 VCC_CORE VSSP_1P8V_2 GPIO30 VSS_CORE VCXO_ON DSSP5_CLK DSSP5_FRM DSSP5_TX_RX VCC_CORE KPD_R5 KPD_R4
IOPCR Addr
0x42A0_0034 0x42A0_0044 0x42A0_0298 0x42A0_0294 0x42A0_028C 0x42A0_0050 0x42A0_004C 0x42A0_0048 0x42A0_0054 0x42A0_0058 0x42A0_0288 0x42A0_0278 0x42A0_027C 0x42A0_0060 0x42A0_005C 0x42A0_0270 0x42A0_026C 0x42A0_0260 0x42A0_0078 0x42A0_006C 0x42A0_007C 0x42A0_0080 0x42A0_0268 0x42A0_0258 0x42A0_0094 0x42A0_0084 0x42A0_0088 0x42A0_008C 0x42A0_024C 0x42A0_0248
IOPCR Default
0x00d0 0x00d8 0x015a 0x015a 0x015a 0x00d0 0x00d8 0x00db 0x00d8 0x00db 0x0178 0x0178 0x0178 0x00d0 0x00d0 0x0178 0x0178 0x0158 0x00d8 0x00d8 0x00d8 0x00d0 0x0178 0x015c 0x00d8 0x00db 0x00db 0x00db 0x017a 0x017a
IOMCRG/S Addr
0x42A0_0400 0x42A0_0400 0x42A0_0418 0x42A0_0418 0x42A0_0418 0x42A0_0400 0x42A0_0400 0x42A0_0400 0x42A0_0400 0x42A0_0400 0x42A0_0418 0x42A0_0418 0x42A0_0418 0x42A0_0404 0x42A0_0400 0x42A0_0418 0x42A0_0418 0x42A0_0414 0x42A0_0404 0x42A0_0404 0x42A0_0404 0x42A0_0404 0x42A0_0414 0x42A0_0414 0x42A0_0404 0x42A0_0404 0x42A0_0404 0x42A0_0404 0x42A0_0414 0x42A0_0414
IOMCR
IOMCRG0 IOMCRG0 IOMCRG6 IOMCRG6 IOMCRG6 IOMCRG0 IOMCRG0 IOMCRG0 IOMCRG0 IOMCRG0 IOMCRG6 IOMCRG6 IOMCRG6 IOMCRG1 IOMCRG0 IOMCRG6 IOMCRG6 IOMCRG5 IOMCRG1 IOMCRG1 IOMCRG1 IOMCRG1 IOMCRG5 IOMCRG5 IOMCRG1 IOMCRG1 IOMCRG1 IOMCRG1 IOMCRG5 IOMCRG5
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Default Function
KPD_R3 VCC_CORE VSS_CORE GPIO19 VSSP_RF VCCP_RF GPIO20 VSS_CORE KPD_R2 GPIO60 GPIO23 EXT_CS0# VCCP_1P8V_2 GPIO15 GPIO18 GPIO17 GPIO16 GPIO13 GPIO25 EXT_ADDR21 EXT_ADDR20 VCCP_1P8V_2 VSSP_1P8V_2 VCCP_RF GPIO14 VSSP_RF GPIO11 VCC_CORE VSS_CORE EXT_DATA8 VCC_CORE VSS_CORE EXT_DATA5 VCC_CORE VSS_CORE KPD_R1 KPD_R0 C_SDA EXT_RDY VSSP_1P8V_2 VCXO GPIO12 GPIO10 VSSA_PLL1 CP_TCLK
IOPCR Addr
0x42A0_0244 0x42A0_00A8 0x42A0_00A4 0x42A0_0240 0x42A0_0234 0x42A0_0230 0x42A0_0228 0x42A0_00B8 0x42A0_00AC 0x42A0_00B0 0x42A0_00B4 0x42A0_00C4 0x42A0_0224 0x42A0_021C 0x42A0_0218 0x42A0_00BC 0x42A0_00D0 0x42A0_0148 0x42A0_0188 0x42A0_020C 0x42A0_0208 0x42A0_0200 0x42A0_0210 0x42A0_00CC 0x42A0_00D4
IOPCR Default
0x017a 0x00da 0x00da 0x017a 0x015a 0x015c 0x0150 0x00da 0x00da 0x00da 0x00da 0x00da 0x015c 0x0158 0x0158 0x00da 0x00db 0x0158 0x0158 0x017a 0x017a 0x0178 0x015c 0x00da 0x00db
IOMCRG/S Addr
0x42A0_0414 0x42A0_0404 0x42A0_0404 0x42A0_0414 0x42A0_0414 0x42A0_0414 0x42A0_0414 0x42A0_0404 0x42A0_0404 0x42A0_0404 0x42A0_0404 0x42A0_0408 0x42A0_0414 0x42A0_0414 0x42A0_0414 0x42A0_0404 0x42A0_0408 0x42A0_040C 0x42A0_040C 0x42A0_0414 0x42A0_0414 0x42A0_0410 0x42A0_0414 0x42A0_0408 0x42A0_0408
IOMCR
IOMCRG5 IOMCRG1 IOMCRG1 IOMCRG5 IOMCRG5 IOMCRG5 IOMCRG5 IOMCRG1 IOMCRG1 IOMCRG1 IOMCRG1 IOMCRG2 IOMCRG5 IOMCRG5 IOMCRG5 IOMCRG1 IOMCRG2 IOMCRG3 IOMCRG3 IOMCRG5 IOMCRG5 IOMCRG4 IOMCRG5 IOMCRG2 IOMCRG2
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Default Function
GPIO35 EXT_OE# EXT_DATA2 EXT_DATA3 EXT_DATA4 EXT_DATA6 EXT_DATA14 GPIO28 ALARM GPIO3 EXT_PWE# I2C_SCL VCCA_PLL2 VCCA_PLL1 VSSA_PLL2 CP_TDI CP_TDO GPIO24 VCCP_1P8V_1 VSSP_1P8V_1 VSSP_1P8V_1 VCCP_1P8V_1 EXT_DATA13 EXT_DATA7 GPIO37 GPIO31 GPIO1 GPIO62 KPD_R7 GSM_SIM_DIO GSM_SIM_RST# PMIC_INTR# CP_TMS GPIO34 GPIO38 VSSP_1P8V_1 EXT_DATA1 VCCP_1P8V_1 EXT_DATA11 VSSP_1P8V_1 VSSP_1P8V_1 EXT_ADDR17 VSSP_1P8V_1 GPIO63 VCC_RTC
IOPCR Addr
0x42A0_0120 0x42A0_013C 0x42A0_0158 0x42A0_016C 0x42A0_017C 0x42A0_0194 0x42A0_0198 0x42A0_01BC 0x42A0_01F4 0x42A0_01F8 0x42A0_01FC 0x42A0_0134 0x42A0_018C 0x42A0_01A0 0x42A0_01B4 0x42A0_01C4 0x42A0_01D0 0x42A0_01F0 0x42A0_01EC 0x42A0_00F0 0x42A0_00EC 0x42A0_0118 0x42A0_012C 0x42A0_014C 0x42A0_0174 0x42A0_01B0 0x42A0_01CC
IOPCR Default
0x017d 0x0158 0x0158 0x0158 0x0158 0x0158 0x0158 0x015c 0x017d 0x0158 0x0178 0x015c 0x0158 0x0158 0x017d 0x015c 0x017d 0x017d 0x017a 0x00d8 0x00d8 0x017b 0x017d 0x0158 0x0158 0x0158 0x017d
IOMCRG/S Addr
0x42A0_0408 0x42A0_040C 0x42A0_040C 0x42A0_040C 0x42A0_040C 0x42A0_0410 0x42A0_0410 0x42A0_0410 0x42A0_0410 0x42A0_0410 0x42A0_0410 0x42A0_040C 0x42A0_040C 0x42A0_0410 0x42A0_1000 0x42A0_0410 0x42A0_1000 0x42A0_1000 0x42A0_0410 0x42A0_0408 0x42A0_0408 0x42A0_0408 0x42A0_040C 0x42A0_040C 0x42A0_040C 0x42A0_0410 0x42A0_1000
IOMCR
IOMCRG2 IOMCRG3 IOMCRG3 IOMCRG3 IOMCRG3 IOMCRG4 IOMCRG4 IOMCRG4 IOMCRG4 IOMCRG4 IOMCRG4 IOMCRG3 IOMCRG3 IOMCRG4 IOMCRS0 IOMCRG4 IOMCRS0 IOMCRS0 IOMCRG4 IOMCRG2 IOMCRG2 IOMCRG2 IOMCRG3 IOMCRG3 IOMCRG3 IOMCRG4 IOMCRS0
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Default Function
OSC_32KHZ_IN GSM_SIM_CLK VCCP_SIM VSSP_1P8V_1 CP_TRST# VCCP_1P8V_1 EXT_ADDR1 EXT_DATA0 EXT_DATA9 EXT_DATA10 EXT_DATA12 VCCP_1P8V_1 EXT_DATA15 VCCP_1P8V_1 GPIO36 RESET_IN# VSS_RTC OSC_32KHZ_OUT
IOPCR Addr
0x42A0_00F4 0x42A0_0130 0x42A0_0140 0x42A0_0154 0x42A0_0168 0x42A0_0180 0x42A0_01A4 0x42A0_01C8
IOPCR Default
0x00d0 0x0158 0x0158 0x0158 0x0158 0x0158 0x0158 0x017d
IOMCRG/S Addr
0x42A0_0408 0x42A0_040C 0x42A0_040C 0x42A0_040C 0x42A0_040C 0x42A0_040C 0x42A0_0410 0x42A0_1000
IOMCR
IOMCRG2 IOMCRG3 IOMCRG3 IOMCRG3 IOMCRG3 IOMCRG3 IOMCRG4 IOMCRS0
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
following tables describe which IOMCR register selected multiplexed ball/ appropriate bit(s) program. Table IOMCRG0 Register 0x42A0_0400
Field
Field Signal Mapping
USB+ USBGPIO46 I2S_DO HSL_DATA3 GPIO47 I2S_BITCLK HSL_DATA4 ONE_WIRE_DQ TCO14 TCO13 TCO12 TCO11 ABBCLK ABBCLK_EN DSSP3_FRM DSSP3_RX DSSP3_TX DSSP4_RX DSSP4_FRM DSSP4_TX
11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Table
IOMCRG1 Register 0x42A0_0404
Field
11:10 13:12 15:14 17:16
Field Signal Mapping
ABB_RESET# DSSP2_FRM DSSP2_RX DSSP1_FRM DSSP1_TX DSSP5_CLK DSSP5_FRM DSSP5_TX_RX VCXO_ON GPIO20 TCO10 PWM0 GPIO19 TCO9 13MHz_CLK GPIO18 TCO8 GPIO17 TCO7 GPIO16 TCO6 PWM1 GPIO15 TCO5 GPIO14 TCO4
19:18
21:20
23:22
25:24
27:26
29:28
31:30
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Table
IOMCRG2 Register 0x42A0_0408
Field
Field Signal Mapping
GPIO13 TCO3 GPIO12 TCO2 PWM2 GPIO11 TCO1 GPIO10 TCO0 PWM3 VCXO GSM_SIM_RST# UICC_RST# GSM_SIM_DIO UICC_DIO GSM_SIM_CLK UICC_CLK PMIC_INTR# CP_TCLK CP_TDI CP_TMS CP_TRST# CP_TDO GPIO34 TCO21 PWM2 EXT_CS5# GPIO35 UART3_RX CSSP_RX DSSP3_RX
11:10
13:12
15:14 17:16 19:18 21:20 23:22 25:24 27:26
29:28
31:30
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Table
IOMCRG3 Register 0x42A0_040C
Field Field Signal Mapping
11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 GPIO38 UART3_TX CSSP_TX DSSP3_TX EXT_ADDR1 GPIO20 GPIO24 EXT_CS2# PWM1 EXT_OE# EXT_DATA0 EXT_DATA8 GPIO45 EXT_DATA1 EXT_DATA9 GPIO32 EXT_DATA2 EXT_DATA10 GPIO44 EXT_DATA3 EXT_DATA11 GPIO30 EXT_DATA4 EXT_DATA12 GPIO29 EXT_DATA5 EXT_DATA13 GPIO28
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Table
IOMCRG4 Register 0x42A0_0410
Field
Field Signal Mapping
EXT_DATA6 EXT_DATA14 GPIO43 EXT_DATA7 EXT_DATA15 GPIO26 EXT_ADDR17 GPIO4 GPIO28 EXT_SDRAS# UART3_TX Reserved GPIO31 EXT_SDCAS# UART3_RX ALARM RESET_IN# OSC_32KHZ_OUT OSC_32KHZ_IN KPD_R7 GPIO3 TCO18 UART3_TX UART2_RTS# EXT_PWE# PWM2 ONE_WIRE_DQ 13MHz_CLK I2C_SCL I2C_SDA
11:10
13:12
15:14 17:16 19:18 21:20 23:22
25:24
27:26
29:28 31:30
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Table
IOMCRG5 Register 0x42A_0414
Field
Field Signal Mapping
KPD_R0 Reserved KPD_R1 Reserved EXT_RDY KPD_R6 EXT_ADDR20 GPIO1 EXT_ADDR21 GPIO0 GPIO25 EXT_CS1# EXT_CS0# EXT_CS4# GPIO23 EXT_CS3# PWM2 GPIO60 EXT_ADDR24 KPD_R2 Reserved KPD_R3 Reserved KPD_R4 TCO16 UART3_CTS# Reserved KPD_R5 TCO15 UART3_RTS# Reserved GPIO30 EXT_SDCLK1 Reserved EXT_SDCLK0 UART3_TX KPD_C0 Reserved
11:10
13:12
15:14
17:16
19:18
21:20
23:22
25:24
27:26
29:28
31:30
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Table
IOMCRG6 Register 0x42A0_0418
Field
Field Signal Mapping
KPD_C1 Reserved KPD_C2 Reserved KPD_C3 Reserved KPD_C4 TCO18 Reserved KPD_C5 TCO17 Reserved GPIO29 EXT_SDCKE Reserved GPIO21 EXT_ADDR22 GPIO22 EXT_ADDR23 GPIO50 EXT_SDCS1# Reserved GPIO51 EXT_SDCS0# Reserved GPIO41 DK_2A PWM2 TCO21 GPIO42 DK_2B PWM3 TCO22 GPIO54 UART1_RX GPIO33 MUX_CLK0 UART1_TX
11:10
13:12
15:14
17:16
19:18
21:20
23:22
25:24
27:26
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Field
Field Signal Mapping
GPIO26 PWM1 MUX_CLK0 MN_CLK_OUT0 PWM0 13MHz_CLK
29:28
31:30
Table
IOMCRG7 Register 0x42A0_041C
Field
Field Signal Mapping
EXT_ADDR16 GPIO5 EXT_ADDR15 GPIO6 EXT_ADDR14 GPIO7 EXT_ADDR13 GPIO8 EXT_ADDR12 EXT_ADDR11 GPIO9 EXT_ADDR10 GPIO11 EXT_ADDR9 GPIO12 EXT_WE# EXT_DQM1 GPIO49 EXT_DQM0 GPIO48 EXT_ADDR19 GPIO2 EXT_ADDR18 GPIO3 EXT_ADDR8 GPIO13 EXT_ADDR7 GPIO14 EXT_ADDR6 GPIO15
11:10
13:12
15:14 17:16 19:18
21:20
23:22
25:24
27:26
29:28
31:30
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Table
IOMCRG8 Register 0x42A_0420
Field
Field Signal Mapping
EXT_ADDR5 GPIO16 EXT_ADDR4 GPIO17 EXT_ADDR3 GPIO18 EXT_ADDR2 GPIO19 GPIO32 I2C_SDA CSSP_CLK DSSP3_CLK GPIO2 I2C_SCL CSSP_FRM DSSP3_FRM GPIO7 MM_CLK MS_BS GPIO4 MM_DAT2_CS0 GSM_SIM_CLK UICC_CLK GPIO43 I2S_FSYNC HSL_DATA0
11:10
13:12
0000
15:14
0001 0010 0011
17:16
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Table
IOMCRS0 Register 0x42A0_1000
Field Field Signal Mapping
0000 0001 0010 0011 0100 0000 0001 0010 0011 0100 0101 0110 0111 1000 0000 0001 0010 11:8 0011 0100 0101 0110 0000 0001 15:12 0010 0011 0100 0101 0000 0001 19:16 0010 0011 0100 0000 0001 23:20 0010 0011 0100 0101 GPIO8 MM_CMD MS_SCLK GSM_SIM_RST# UICC_RST# GPIO9 MM_DAT1 CSSP_TX HSL_CLK DSSP3_TX GSM_SIM_DIO UICC_DIO TCO23 PWM1 GPIO45 I2S_SYSCLK CSSP_TX HSL_DATA2 DSSP3_TX GSM_SIM_CLK UICC_CLK GPIO37 TCO20 PWM1 CSSP_FRM DSSP3_FRM 13MHz_CLK GPIO36 TCO19 PWM0 CSSP_CLK DSSP3_CLK GPIO63 TCO15 UART3_CTS# UART2_RX GSM_SIM_RST# UICC_RST#
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Field
Field Signal Mapping
0000 0001 GPIO1 TCO16 UART3_RTS# UART2_TX GSM_SIM_DIO UICC_DIO GPIO62 TCO17 UART3_RX UART2_CTS# GSM_SIM_CLK UICC_CLK
27:24
0010 0011 0100 0101 0000 0001
31:28
0010 0011 0100 0101
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Table
IOMCRS1 Register 0x42A0_1004
Field Field Signal Mapping
0000 0001 0010 0011 0100 0000 0001 0010 0011 0100 0000 0001 11:8 0010 0011 0100 0000 0001 15:12 0010 0011 0100 0000 0001 0010 19:16 0011 0100 0101 0110 0000 0001 0010 23:20 0011 0100 0101 0110 0000 0001 27:24 0010 0011 0100 0101 GPIO39 DK_1A PWM0 TCO19 UART3_TX GPIO40 DK_1B PWM1 TCO20 UART3_RX GPIO52 UART2_TX HSL_DATA0 DSSP3_RX UART1_DSR# GPIO53 UART2_RX HSL_DATA1 DSSP3_TX UART1_DTR# GPIO55 DSSP6_CLK DSSP3_CLK HSL_DATA2 UART2_CTS# CSSP_CLK UART1_DCD# GPIO27 DSSP6_FRM DSSP3_FRM HSL_DATA3 UART2_RTS# CSSP_FRM UART1_RI# GPIO56 DSSP6_RX DSSP3_RX HSL_DATA4 CSSP_RX UART1_CTS#
PXA800F Cellular Processor Developer's Manual Preliminary
Signal Descriptions
Field
Field Signal Mapping
0000 0001 GPIO57 DSSP6_TX DSSP3_TX HSL_CLK CSSP_TX UART1_RTS#
31:28
0010 0011 0100 0101
Table
IOMCRS2 Register 0x42A0_1008
Field Field Signal Mapping
0000 0001 0010 0011 0100 0101 0110 0000 0001 0010 0011 0100 0000 0001 11:8 0010 0011 0100 GPIO5 MM_DAT3_CS1 TCO22 PWM0 GSM_SIM_RST# UICC_RST# ONE_WIRE_DQ GPIO6 MM_DAT0 MS_DIO GSM_SIM_DIO UICC_DIO GPIO44 I2S_DI CSSP_RX HSL_DATA1 DSSP3_RX
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
This chapter provides memory register maps PXA800F cellular processor thatconsist addresses various configuration, control status registers.
System Memory
memory Intel XScale microarchitecture consists address space. divided into blocks 64MB each. Table provides top-level memory PXA800F cellular processor that shows major device reserved area mappings.
Table
PXA800F Cellular Processor Top-Level Memory
Address Range
0xFC00_0000 0xFFFF_FFFF 0xE400_0000 0xFBFF_FFFF 0xE000_0000 0xE3FF_FFFF 0xD400_0000 0xDFFF_FFFF 0xD000_0000 0xD3FF_FFFF 0xC400_0000 0xCFFF_FFFF 0xC000_0000 0xC3FF_FFFF 0xB000_0000 0xBFFF_FFFF 0xAC00_0000 0xACFF_FFFF 0xA800_0000 0xA8FF_FFFF 0xA400_0000 0xA4FF_FFFF 0xA000_0000 0xA0FF_FFFF 0x8800_0000 0x9FFF_FFFF 0x8400_0000 0x87FF_FFFF 0x8000_0000 0x83FF_FFFF 0x5400_0000 0x7FFF_FFFF 0x5000_0000 0x53FF_FFFF 0x4C00_0000 0x4FFF_FFFF 0x4800_0000 0x4BFF_FFFF 0x4400_0000 0x47FF_FFFF 0x4000_0000 0x43FF_FFFF 0x1C00_0000 0x3FFF_FFFF 0x1800_0000 0x1BFF_FFFF 0x1400_0000 0x17FF_FFFF 0x1000_0000 0x13FF_FFFF 0x0C00_0000 0x0DFF_FFFF 0x0800_0000 0x0AFF_FFFF 0x0400_0000 0x05FF_FFFF 0x0000_0000 0x01FF_FFFF Reserved Reserved Reserved Reserved Reserved Reserved Intel Peripheral Peripherals Reserved SDRAM Partition (Not used; only lower 16MB valid) SDRAM Partition (Not used; only lower 16MB valid) SDRAM Partition (only lower 16MB valid) SDRAM Partition (only lower 16MB valid) Reserved Reserved Intel XScale microarchitecture flash Reserved Reserved Reserved Memory Controller Configuration Registers Reserved Intel XScale microarchitecture peripherals Reserved Intel XScale microarchitecture SRAM Static Chip Select, (Only lower 32MB valid) Static Chip Select, (Only lower 32MB valid) Static Chip Select, (Only lower 32MB valid) Static Chip Select, (Only lower 32MB valid) Static Chip Select, (Only lower 32MB valid) Reserved (only lower 32MB valid)
Module
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Table
Intel Peripherals
Address Range
0xC0F0_0000 0xC0FF_FFFF 0xC0E0_0000 0xC0EF_FFFF 0xC0D0_0000 0xC0DF_FFFF 0xC0C0_0000 0xC0CF_FFFF 0xC0B0_0000 0xC0BF_FFFF 0xC0A0_0000 0xC0AF_FFFF 0xC090_0000 0xC09F_FFFF 0xC088_0000 0xC08F_FFFF 0xC080_0000 0xC087_FFFF 0xC030_0000 0xC030_0FFF 0xC020_0000 0xC020_3FFF 0xC010_0000 0xC010_7FFF 0xC000_0000 0xC000_7FFF Cipher Accelerator DSSP1 (Baseband DSSP2 (Baseband DSSP3 (Voiceband Serial Port) DSSP4 (Auxiliary serial port) DSSP5 (Serial Control) DSSP6 (Digital Audio Interface) Timer Reserved Reserved Reserved Reserved
Module
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Table
Intel XScale Microarchitecture Peripherals
Address Range
0x42E0_0000 0x43FF_FFFF 0x42D0_0000 0x42DF_FFFF 0x42C0_0000 0x42CF_FFFF 0x42B0_0000 0x42BF_FFFF 0x42A0_0000 0x42AF_FFFF 0x4290_0000 0x429F_FFFF 0x4280_0000 0x428F_FFFF 0x4270_0000 0x427F_FFFF 0x4260_0000 0x426F_FFFF 0x4250_0000 0x425F_FFFF 0x4240_0000 0x424F_FFFF 0x4230_0000 0x423F_FFFF 0x4220_0000 0x422F_FFFF 0x4210_0000 0x421F_FFFF 0x4200_0000 0x420F_FFFF 0x41F0_0000 0x41FF_FFFF 0x41E0_0000 0x41EF_FFFF 0x41D0_0000 0x41DF_FFFF 0x41C0_0000 0x41CF_FFFF 0x41B0_0000 0x41BF_FFFF 0x41A0_0000 0x41AF_FFFF 0x4190_0000 0x419F_FFFF 0x4180_0000 0x418F_FFFF 0x4170_0000 0x417F_FFFF 0x4160_0000 0x416F_FFFF 0x4150_0000 0x415F_FFFF 0x4140_0000 0x414F_FFFF 0x4130_0000 0x413F_FFFF 0x4120_0000 0x412F_FFFF 0x4110_0000 0x411F_FFFF 0x4100_0000 0x410F_FFFF 0x40F0_0000 0x40FF_FFFF 0x40E0_0000 0x40EF_FFFF 0x40D0_0000 0x40DF_FFFF 0x40C0_0000 0x40CF_FFFF 0x40B0_0000 0x40BF_FFFF 0x40A0_0000 0x40A_FFFF 0x4090_0000 0x409F_FFFF 0x4080_0000 0x408F_FFFF 0x4070_0000 0x407F_FFFF Reserved Reserved Reserved Reserved Control/Status Registers Real Time Clock Slow Clock Interface Timing Control Unit (TCU) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1-Wire Interface Reserved Reserved Reserved Memory Stick* Interface Reserved UICC Interface Keypad Interface Reserved Reserved Reserved MMC/SD Interface CSSP Power Manager (Pwr Mgnt Registers Intel® XScale) GPIO Intel XScale Interrupt Control PWM[1], PWM[3] PWM[0], PWM[2] Timers Reserved Reserved UART
Module
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Address Range
0x4060_0000 0x406_FFFF 0x4050_0000 0x405_FFFF 0x4040_0000 0x404_FFFF 0x4030_0000 0x403_FFFF 0x4020_0000 0x402F_FFFF 0x4010_0000 0x401F_FFFF 0x4000_0000 0x400F_FFFF Reserved Reserved UART UART Controller
Module
4.1.1
Register
Table lists individual register addresses PXA800F cellular processor peripherals.
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Table Register Address
Unit Controller Address
0x4000_0000 0x4000_0000 0x4000_0004 0x4000_0008 0x4000_000C 0x4000_0010 0x4000_0014 0x4000_0018 0x4000_001C 0x4000_0020 0x4000_0024 0x4000_0028 0x4000_002C 0x4000_0030 0x4000_0034 0x4000_0038 0x4000_003C 0x4000_0040 0x4000_0044 0x4000_0048 0x4000_004C 0x4000_0050 0x4000_0054 0x4000_0058 0x4000_005C 0x4000_0060 0x4000_0064 0x4000_0068 0x4000_ 006C 0x4000_0070 0x4000_0074 0x4000_0078 0x4000_007C 0x4000_00A0 0x4000_00F0 0x4000_0100 0x4000_0104 DCSR0 DCSR1 DCSR2 DCSR3 DCSR4 DCSR5 DCSR6 DCSR7 DCSR8 DCSR9 DCSR10 DCSR11 DCSR12 DCSR13 DCSR14 DCSR15 DCSR16 DCSR17 DCSR18 DCSR19 DCSR20 DCSR21 DCSR22 DCSR23 DCSR24 DCSR25 DCSR26 DCSR27 DCSR28 DCSR29 DCSR30 DCSR31 DALGN DINT DRCMR0 DRCMR1 Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Control Status Register channel Alignment Register Interrupt Register Request Channel Register source0 Request Channel Register source1
Register Symbol
Register Description
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x4000_0108 0x4000_010C 0x4000_0110 0x4000_0114 0x4000_0118 0x4000_011C 0x4000_0120 0x4000_0124 0x4000_0128 0x4000_012C 0x4000_0130 0x4000_0134 0x4000_0138 0x4000_013C 0x4000_0140 0x4000_0144 0x4000_0148 0x4000_014C 0x4000_0150 0x4000_0154 0x4000_0158 0x4000_015C 0x4000_0160 0x4000_0164 0x4000_0168 0x4000_016C 0x4000_0170 0x4000_0174 0x4000_0178 0x4000_017C 0x4000_0180 0x4000_0184 0x4000_0188 0x4000_018C 0x4000_0190 0x4000_0194 0x4000_0198 0x4000_019C 0x4000_01A0
Register Symbol
DRCMR2 DRCMR3 DRCMR4 DRCMR5 DRCMR6 DRCMR7 DRCMR8 DRCMR9 DRCMR10 DRCMR11 DRCMR12 DRCMR13 DRCMR14 DRCMR15 DRCMR16 DRCMR17 DRCMR18 DRCMR19 DRCMR20 DRCMR21 DRCMR22 DRCMR23 DRCMR24 DRCMR25 DRCMR26 DRCMR27 DRCMR28 DRCMR29 DRCMR30 DRCMR31 DRCMR32 DRCMR33 DRCMR34 DRCMR35 DRCMR36 DRCMR37 DRCMR38 DRCMR39 DRCMR40
Register Description
Request Channel Register source2 Request Channel Register source3 Request Channel Register source4 Request Channel Register source5 Request Channel Register source6 Request Channel Register source7 Request Channel Register source8 Request Channel Register source9 Request Channel Register source10 Request Channel Register source11 Request Channel Register source12 Request Channel Register source13 Request Channel Register source14 Request Channel Register source15 Request Channel Register source16 Request Channel Register source17 Request Channel Register source18 Request Channel Register source19 Request Channel Register source20 Request Channel Register source21 Request Channel Register source22 Request Channel Register source23 Request Channel Register source24 Request Channel Register source25 Request Channel Register source26 Request Channel Register source27 Request Channel Register source28 Request Channel Register source29 Request Channel Register source30 Request Channel Register source31 Request Channel Register source32 Request Channel Register source33 Request Channel Register source34 Request Channel Register source35 Request Channel Register source36 Request Channel Register source37 Request Channel Register source38 Request Channel Register source39 Request Channel Register source40
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x4000_01A4 0x4000_01A8 0x4000_01AC 0x4000_01B0 0x4000_01B4 0x4000_01B8 0x4000_01BC 0x4000_01C0 0x4000_01C4 0x4000_01C8 0x4000_01CC 0x4000_01D0 0x4000_01D4 0x4000_01D8 0x4000_01DC 0x4000 _01E0 0x4000_01E4 0x4000_01E8 0x4000_01EC 0x4000_01F0 0x4000_01F4 0x4000_01F8 0x4000_01FC 0x4000_0200 0x4000_0204 0x400_0208 0x4000_020C 0x4000_0210 0x4000_0214 0x4000_0218 0x4000_021C 0x4000_0220 0x4000_0224 0x4000_0228 0x4000_022C 0x4000_0230 0x4000_0234 0x4000_0238 0x4000_023C
Register Symbol
DRCMR41 DRCMR42 DRCMR43 DRCMR44 DRCMR45 DRCMR46 DRCMR47 DRCMR48 DRCMR49 DRCMR50 DRCMR51 DRCMR52 DRCMR53 DRCMR54 DRCMR55 DRCMR56 DRCMR57 DRCMR58 DRCMR59 DRCMR60 DRCMR61 DRCMR62 DRCMR63 DDADR0 DSADR0 DTADR0 DCMD0 DDADR1 DSADR1 DTADR1 DCMD1 DDADR2 DSADR2 DTADR2 DCMD2 DDADR3 DSADR3 DTADR3 DCMD3
Register Description
Request Channel Register source41 Request Channel Register source42 Request Channel Register source43 Request Channel Register source44 Request Channel Register source45 Request Channel Register source46 Request Channel Register source47 Request Channel Register source48 Request Channel Register source49 Request Channel Register source50 Request Channel Register source51 Request Channel Register source52 Request Channel Register source53 Request Channel Register source54 Request Channel Register source55 Request Channel Register source56 Request Channel Register source57 Request Channel Register source58 Request Channel Register source59 Request Channel Register source60 Request Channel Register source61 Request Channel Register source62 Request Channel Register source63 Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x4000_0240 0x4000_0244 0x4000_0248 0x4000_024C 0x4000_0250 0x4000_0254 0x4000_0258 0x4000_025C 0x4000_0260 0x4000_0264 0x4000_0268 0x4000_026C 0x4000_0270 0x4000_0274 0x4000_0278 0x4000_027C 0x4000_0280 0x4000_0284 0x4000_0288 0x4000_028C 0x4000_0290 0x4000_0294 0x4000_0298 0x4000_029C 0x4000_02A0 0x4000_02A4 0x4000_02A8 0x400 _02AC 0x4000_02B0 0x4000_02B4 0x4000_02B8 0x4000_02BC 0x4000_02C0 0x4000_02C4 0x4000_02C8 0x4000_02CC 0x4000_02D0 0x4000_02D4 0x4000_02D8
Register Symbol
DDADR4 DSADR4 DTADR4 DCMD4 DDADR5 DSADR5 DTADR5 DCMD5 DDADR6 DSADR6 DTADR6 DCMD6 DDADR7 DSADR7 DTADR7 DCMD7 DDADR8 DSADR8 DTADR8 DCMD8 DDADR9 DSADR9 DTADR9 DCMD9 DDADR10 DSADR10 DTADR10 DCMD10 DDADR11 DSADR11 DTADR11 DCMD11 DDADR12 DSADR12 DTADR12 DCMD12 DDADR13 DSADR13 DTADR13
Register Description
Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x4000_02DC 0x4000_02E0 0x4000_02E4 0x4000_02E8 0x4000_02EC 0x4000_02F0 0x4000_02F4 0x4000_02F8 0x4000_02FC 0x4000_0300 0x4000_0304 0x4000_0308 0x4000_030C 0x4000_0310 0x4000_0314 0x4000_0318 0x4000_031C 0x4000_0320 0x4000_0324 0x4000_0328 0x400 _032C 0x4000_0330 0x4000_0334 0x4000_0338 0x4000_033C 0x4000_0340 0x4000_0344 0x4000_0348 0x4000_034C 0x4000_0350 0x4000_0354 0x4000_0358 0x4000_035C 0x4000_0360 0x4000_0364 0x4000_0368 0x4000_036C 0x4000_0370 0x4000_0374
Register Symbol
DCMD13 DDADR14 DSADR14 DTADR14 DCMD14 DDADR15 DSADR15 DTADR15 DCMD15 DDADR16 DSADR16 DTADR16 DCMD16 DDADR17 DSADR17 DTADR17 DCMD17 DDADR18 DSADR18 DTADR18 DCMD18 DDADR19 DSADR19 DTADR19 DCMD19 DDADR20 DSADR20 DTADR20 DCMD20 DDADR21 DSADR21 DTADR21 DCMD21 DDADR22 DSADR22 DTADR22 DCMD22 DDADR23 DSADR23
Register Description
Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x4000_0378 0x4000_037C 0x4000_0380 0x4000_0384 0x4000_0388 0x4000_038C 0x4000_0390 0x4000_0394 0x4000_0398 0x4000_039C 0x4000_03A0 0x4000_03A4 0x4000_03A8 0x4000_03AC 0x4000_03B0 0x4000_03B4 0x4000_03B8 0x4000_03BC 0x4000_03C0 0x4000_03C4 0x4000_03C8 0x4000_03CC 0x4000_03D0 0x4000_03D4 0x4000_03D8 0x4000_03DC 0x4000_03E0 0x4000_03E4 0x4000_03E8 0x4000_03EC 0x4000_03F0 0x4000_03F4 0x4000_03F8 0x4000_03FC 0x4000_0400 0x4000_10FC 0x4000_1100 0x4000_1104 0x4000_1108
Register Symbol
DTADR23 DCMD23 DDADR24 DSADR24 DTADR24 DCMD24 DDADR25 DSADR25 DTADR25 DCMD25 DDADR26 DSADR26 DTADR26 DCMD26 DDADR27 DSADR27 DTADR27 DCMD27 DDADR28 DSADR28 DTADR28 DCMD28 DDADR29 DSADR29 DTADR29 DCMD29 DDADR30 DSADR30 DTADR30 DCMD30 DDADR31 DSADR31 DTADR31 DCMD31 Reserved DRCMR64 DRCMR65 DRCMR66
Register Description
Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel Descriptor Address Register channel Source Address Register channel Target Address Register channel Command Address Register channel
Request Channel Register source64 Request Channel Register source65 Request Channel Register source66
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x4000_110C 0x4000_1110 0x400F_FFFF
Register Symbol
DRCMR67 Reserved
Register Description
Request Channel Register source67
UART
0x4010_0000 0x4010_0000 0x4010_0000 0x4010_0000 0x4010_0004 0x4010_0004 0x4010_0008 0x4010_0008 0x4010_000C 0x4010_0010 0x4010_0014 0x4010_0018 0x4010_001C 0x4010_0020 0x4010_0024 0x4010_0028 0x4010_002C 0x4010_0030 0x401F_FFFF (DLAB (DLAB (DLAB (DLAB (DLAB Reserved Receive BUFFER Register (read only) Transmit Holding Register (write only) Divisor Latch Register Divisor Latch Register High Interrupt Enable Register (R/W) Interrupt I.D. Register (read only) FIFO Control Register (write only) Line Control Register (R/W) Modem Control Register (R/W) Line Status Register (Read only) Modem Status Register (Read only) Scratch Register (R/W) Slow Infrared Select Register (Read/Write) FIFO Occupancy Register (Read only) AutoBaud Control Register (Read/Write) AutoBaud Count Register (Read only)
UART
0x4020_0000 0x4020_0000 0x4020_0000 0x4020_0000 0x4020_0004 0x4020_0004 0x4020_0008 0x4020_0008 0x4020_000C 0x4020_0010 0x4020_0014 0x4020_0018 0x4020_001C 0x4020_0020 0x4020_0024 0x4020_0028 0x4020_002C (DLAB (DLAB (DLAB (DLAB (DLAB Receive BUFFER Register (read only) Transmit Holding Register (write only) Divisor Latch Register Divisor Latch Register High Interrupt Enable Register (R/W) Interrupt I.D. Register (read only) FIFO Control Register (write only) Line Control Register (R/W) Modem Control Register (R/W) Line Status Register (Read only) Modem Status Register (Read only) Scratch Register (R/W) Slow Infrared Select Register (Read/Write) FIFO Occupancy Register (Read only) AutoBaud Control Register (Read/Write) AutoBaud Count Register (Read only)
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x4020_00300x402F_FFFF
Register Symbol
Reserved
Register Description
0x4030_0000 0x4030_1690 0x4030_1698 0x4030_16A0 0x4030_1688 0x4030_16A8 0x4030_1680 0x4030_1684 0x405F_FFFF ISAR IDBR Reserved IBMR Reserved Monitor Register Control Register Status Register Slave Address Register Data Buffer Register
0x4060_0000 0x4060_0000 0x4060_0080 0x4060_00A0 0x4060_0100 0x4060_0180 0x4060_0400 0x4060_0404 0x4060_0408 0x4060_0410 0x4060_0414 0x4060_0418 0x4060_041C 0x4060_0420 0x4060_0424 0x4060_0428 0x4060_042C 0x4060_0450 0x4060_0458 0x4060_0460 0x4060_0464 UDDR1 UDDR0 UDDR5 UDDR6 UDDR3 UDCCR Reserved Reserved UDCCS0 UDCCS1 UDCCS2 UDCCS3 UDCCS4 UDCCS5 UDCCS6 UDCCS7 UICR0 UISR0 UFNHR UFNLR Endpoint Data Register Endpoint Data Register Endpoint Data Register Endpoint Data Register Endpoint Data Register control register Reserved Reserved Endpoint Control/Status Register Endpoint (IN) Control/Status Register Endpoint (OUT) Control/Status Register Endpoint (IN) Control/Status Register Endpoint (OUT) Control/Status Register Endpoint (Interrupt) Control/Status Register Endpoint (IN) Control/Status Register Endpoint (OUT) Control/Status Register Interrupt Control Register Status Interrupt Register Frame Number Register High Frame Number Register
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x4060_0468 0x4060_046C 0x4060_0470 0x4060_0474 0x4060_0800 0x4060_0900 0x4060_0980 0x4060_0B80 0x406F_FFFF
Register Symbol
UBCR2 UBCR4 UBCR7 Reserved UDDR2 UDDR7 UDDR4 Reserved
Register Description
Byte Count Register Byte Count Register Byte Count Register
Endpoint Data Register Endpoint Data Register Endpoint Data Register
UART
0x4070_0000 0x4070_0000 0x4070_0000 0x4070_0000 0x4070_0004 0x4070_0004 0x4070_0008 0x407 _0008 0x4070_000C 0x4070_0010 0x4070_0014 0x4070_0018 0x407_001C 0x4070_0020 0x4070_0024 0x4070_0028 0x4070_002C 0x4070_0030 0x409F_FFFF (DLAB (DLAB (DLAB (DLAB (DLAB Reserved Receive BUFFER Register (read only) Transmit Holding Register (write only) Divisor Latch Register Divisor Latch Register High Interrupt Enable Register (R/W) Interrupt I.D. Register (read only) FIFO Control Register (write only) Line Control Register (R/W) Modem Control Register (R/W) Line Status Register (Read only) Modem Status Register (Read only) Scratch Register (R/W) Slow Infrared Select Register (Read/Write) FIFO Occupancy Register (Read only) AutoBaud Control Register (Read/Write) AutoBaud Count Register (Read only)
Timer
0x40A0_0000 0x40A0_0000 0x40A0_0004 0x40A0_0008 0x40A0_000C 0x40A0_0010 0x40A0_0014 0x40A0_0018 0x40A0_001C TCCR TMR1[0] TMR1[1] TMR1[2] TMR2[0] TMR2[1] TMR2[2] TMR3[0] Timers clock control Timer match register Timer match register Timer match register Timer match register Timer match register Timer match register Timer match register
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x40A0_0020 0x40A0_0024 0x40A0_0028 0x40A0_002C 0x40A0_0030 0x40A0_0034 0x40A0_0038 0x40A0_003C 0x40A0_0040 0x40A0_0044 0x40A0_0048 0x40A0_004C 0x40A0_0050 0x40A0_0054 0x40A0_0058 0x40A0_005C 0x40A0_0060 0x40A0_0064 0x40A0_0068 0x40A0_006C 0x40A0_0070 0x40A0_0074 0x40A0_0078 0x40A0_007C 0x40A0_0080 0x40A0_0084 0x40A0_0088 0x40A0_008C 0x40A0_0090 0x40A0_0094 0x40A0_0098 0x40A0_009C 0x40A0_00A0 0x40A0_00A4 0x40A0_00A8 0x40A0_00AC
Register Symbol
TMR3[1] TMR3[2] TCR1 TCR2 TCR3 TSR1 TSR2 TSR3 TIER1 TIER2 TIER3 TPLVR1 TPLVR2 TPLVR3 TPLCR1 TPLCR2 TPLCR3 TWMER TWMR TWVR TWSR TICR1 TICR2 TICR3 TWICR TCER TCMR TILR1 TILR2 TILR3 TWCR TWFAR TWSAR TCVWR0 TCVWR1 TCVWR2
Register Description
Timer match register Timer match register Timer count register (Read only) Timer count register (Read only) Timer count register (Read only) Timer status register Timer status register Timer status register Timer interrupt enable register timer Timer interrupt enable register timer Timer interrupt enable register timer Timer preload value register Timer preload value register Timer preload value register Timer preload control register Timer preload control register Timer preload control register Timer watchdog match enable register Timer watchdog match register Timer watchdog value register (Read only) Timer watchdog status register Timer interrupt clear register Timer interrupt clear register Timer interrupt clear register Timer watchdog interrupt clear register Timer count enable register Timer count mode register Timer Interrupt Length register Timer Interrupt Length register Timer Interrupt Length register Reset counter value zero. Timers Watchdog First Access register Timers Watchdog Second Access register Timer Counter value write-read request Timer Counter value write-read request Timer Counter value write-read request
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x40A0_00B0 0x40AF_FFFF
Register Symbol
Reserved
Register Description
0x40B0_0000 0x40B0_0000 0x40B0_0004 0x40B0_0008 0x40B0_000C 0x40B0_03FF PWM_CTRL0 PWDUTY0 PERVAL0 Reserved Control Register Duty Cycle Register Period Control Register
0x40B0_0400 0x40B0_0400 0x40B0_0404 0x40B0_0408 0x40B0_040C 0x40BF_FFFF PWM_CTRL2 PWDUTY2 PERVAL2 Reserved 2Control Register 2Duty Cycle Register 2Period Control Register
0x40C0_0000 0x40C0_0000 0x40C0_0004 0x40C0_0008 0x40C0_000C 0x40C0_03FF PWM_CTRL1 PWDUTY1 PERVAL1 Reserved 1Control Register 1Duty Cycle Register 1Period Control Register
0x40C0_0400 0x40C0_0400 0x40C0_0404 0x40C0_0408 0x40C0_040C 0x40CF_FFFF PWM_CTRL3 PWDUTY3 PERVAL3 Reserved Control Register Duty Cycle Register Period Control Register
Interrupt Control
0x40D0_0000 0x40D0_0000 0x40D0_0004 0x40D0_0008 0x40D0_000C 0x40D0_0010 0x40D0_0014 0x40D0_0018 0x40D0_001C 0x40D0_0098 0x40D0_0020 0x40DF_FFFF ICIP ICMR ICLR ICFP ICPR ICCR ICHP IPR0 IPR31 Reserved Interrupt Controller Pending Register Interrupt Controller mask Register (R/W) Interrupt Controller Level Register (R/W) Interrupt Controller Pending Register Interrupt Controller Pending Register Interrupt Controller Control Register (R/W) Interrupt Controller Highest Priority Register Interrupt Priority Registers interrupts (R/W)
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit GPIO
Address
0x40E0_0000 0x40E0_0000 0x40E0_0004 0x40E0_0008 0x40E0_000C 0x40E0_0010 0x40E0_0014 0x40E0_0018 0x40E0_001C 0x40E0_0020 0x40E0_0024 0x40E0_0028 0x40E0_002C 0x40E0_0030 0x40E0_0034 0x40E0_0038 0x40E0_003C 0x40E0_0040 0x40E0_0044 0x40E0_0048 0x40E0_004C 0x40E0_0050 0x40E0_0054 0x40E0_0058 0x40E0_005C 0x40E0_0060 0x40E0_0064 0x40E0_0068 0x40E0_006C 0x40E0_0070
Register Symbol
Register Description
GPLR_x GPLR_y Reserved GPDR_x GPDR_y Reserved GPSR_x GPSR_y Reserved GPCR_x GPCR_y Reserved GSTR_x GSTR_y Reserved GRHR_x GRHR_y Reserved GFLR_x GFLR_y Reserved GRER_x GRER_y Reserved GFER_x GFER_y Reserved GDBR_x GDBR_y
GPIO pin-level register GPIO<31:0> GPIO pin-level register GPIO<63:32>
GPIO direction register GPIO<31:0> GPIO direction register GPIO<63:32>
GPIO output register GPIO<31:0> GPIO output register GPIO<63:32>
GPIO output clear register GPIO<31:0> GPIO output clear register GPIO <63:32>
GPIO source type register GPIO<31:0> GPIO source type register GPIO<63:32>
GPIO rising-edge/high level detect enable register GPIO<31:0> GPIO rising-edge/high level detect enable register GPIO<63:32>
GPIO falling-edge/low level detect enable register GPIO<31:0> GPIO falling-edge/low level detect enable register GPIO<63:32>
GPIO rising edge detect register GPIO<31:0> GPIO rising edge detect register GPIO<63:32>
GPIO falling edge detect register GPIO<31:0> GPIO falling edge detect register GPIO<63:32>
GPIO debounce control register GPIO<31:0> GPIO debounce control register GPIO<63:32>
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x40E0_0074 0x40E0_0078 0x40E0_007C 0x40E0_0080 0x40E0_0084 0x40E0_0088 0x40E0_008C 0x40E0_0090 0x40E0_0094 0x40E0_0098 0x40E0_009C 0x40E0_00A0 0x40E0_00A4 0x40E0_00A8 0x40E0_00AC 0x40E0_00B0 0x40E0_00B4 0x40E0_00B8 0x40E0_00BC 0x40EF_FFFF
Register Symbol
Reserved GDCR GIMR_x GIMR_y Reserved GIRR_x GIRR_y Reserved GICR_x GICR_y Reserved GSLR Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Register Description
GPIO debounce clock control register GPIO interrupt mask register GPIO<31:0> GPIO interrupt mask register GPIO<63:32>
GPIO Interrupt request register GPIO<31:0> GPIO Interrupt request register GPIO<63:32>
GPIO interrupt clear register GPIO<31:0> GPIO interrupt clear register GPIO<63:32>
GPIO status latch register
Power Management
0x40F0_0000 0x40F0_0000 0x40F0_0004 0x40F0_0008 0x40F0_000C 0x40F0_0010 0x40F0_0014 0x40F0_0018 0x40F0_001C 0x40F0_0020 0x40F0_0024 0x40F0_0028 0x40F0_002C Reserved XPSR FCCR Reserved Reserved UCCR CGCR XPRR1 XPRR2 XCGR XRSR Reserved UART clock control register Clocks generation control register Intel XScale programmable reset register Intel XScale programmable reset register Intel XScale clock gating register reset status register Intel XScale Status Register Frequency change control register
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x40F0_0030 0x40F0_0034 0x40F0_0038 0x40F0_003C 0x40F0_0040 0x40F0_00FC 0x40F0_0100 0x40F0_0104 0x40F0_07FC 0x40F0_0104 0x40F0_03FC 0x40F0_0400 0x40F0_0404 0x40F0_0408 0x40F0_040C 0x40F0_0410 0x40F0_0414 0x40F0_0418 0x40F0_041C 0x40F0_0420 0x40F0_0424 0x40F0_0428 0x40F0_042C 0x40F0_0430 0x40F0_0434 0x40F0_0438 0x40F0 043C 0x40F0_0440 0x40F0_0444 0x40F0_0448 0x40F0_044C 0x40F0_0450 0x40F0_07FC 0x40F0_0800 0x40F0_0FFC 0x40F0_2008
Register Symbol
GPCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved XMPR0 XMPR1 XMPR2 XMPR3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved XDRR DPSR
Register Description
general purpose clock generation control register, used clock divisor
Intel XScale module power register Intel XScale module power register Intel XScale module power register Intel XScale module power register
Intel XScale dummy read register Intel power status register
CSSP
0x4100_0000 0x4100_0000 0x4100_0004 0x4100_0008 C_SSCR0 C_SSCR1 C_SSSR control register control register status register
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x4100_000C 0x4100_0010 0x4100_0014 0x4100_0024 0x4100_0028 0x4100_002C
Register Symbol
C_SSITR C_SSDR Reserved C_SSTO C_SSPSP
Register Description
interrupt test register data write register/SSP data read register
time register programmable serial protocol
MMC/SD
0x4110_0000 0x4110_0000 0x4110_0004 0x4110_0008 0x4110_000c 0x4110_0010 0x4110_0014 0x4110_0018 0x4110_001c 0x4110_0020 0x4110_0024 0x4110_0028 0x4110_002c 0x4110_0030 0x4110_0034 0x4110_0038 0x4110_003c 0x4110_0040 0x4110_0044 0x4110_0048 0x413F FFFF MMC_STRPCL MMC_STAT MMC_CLKRT MMC_SPI MMC_CMDAT MMC_RESTO MMC_RDTO MMC_BLKLEN MMC_NUMBLK MMC_PRTBUF MMC_I_MASK MMC_I_REG MMC_CMD MMC_ARGH MMC_ARGL MMC_RES MMC_RXFIFO MMC_TXFIFO Reserved Reserved Control start stop clock status register (read only) clock rate mode control bits Command/response/data sequence control Expected response time Expected data read time Block length data transaction Number blocks, block mode Partial MMC_TXFIFO FIFO written Interrupt Mask Interrupt Register (read only) Index current command part current command argument part current command argument Response FIFO (read only) Receive FIFO (read only) Transmit FIFO (write only)
Reserved Keypad Interface
0x4140_0144 0x4150_0000 0x4150 0000 0x4150 0008 0x4150 0010 0x4150 0018 0x4150 0020 0x4150 0028 0x4150 0030
KPDK KPREC KPMK KPAS KPASMKP0 KPASMKP1
Keypad interface control register Keypad interface direct register Keypad interface rotary encoder count register Keypad interface matrix register Keypad interface automatic scan register Keypad interface automatic scan multiple press register Keypad interface automatic scan multiple press register
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x4150 0038 0x4150 0040 0x4150 0048
Register Symbol
KPASMKP2 Reserved KPKDI
Register Description
Keypad interface automatic scan multiple press register
Keypad interface debounce interval register
UICC
0x4160_0000 0x416F_FFFF 0x4160_0000 0x4160_0004 0x4160_0008 0x4160_000C 0x4160_0010 0x4160_0014 0x4160_0018 0x4160_001C 0x4160_0020 0x4160_0024 0x4160_0028 0x4160_002C 0x4160_0030 0x4160_0034 0x4160_0038 0x4160_003C 0x4160_0040 0x4160_0044 0x4160_0048 0x416F_FFFF EGTR BGTR CLKR CWTR BWTR Reserved Receive buffer (read only) Transmit buffer (write only) Interrupt Enable (R/W) Interrupt I.D. (R/W) FIFO Control (R/W) FIFO Status (Read only) Error Control (R/W) Line Control (R/W) Card Control register (R/W) Line Status (Read only) Extra Guard Time register (R/W) Block Guard Time register (R/W) Time register (R/W) Clock register (R/W) Divisor Latch register (Byte, R/W) Factor Latch Register (R/W) Character Waiting Time Register (R/W) Block Waiting Time Register (R/W)
Memory Stick* Interface
4180_0000 4180_0000 4180_0004 4180_0008 4180_000C 4180_0010 4180_0014 4180_0018 4180_001C 4180_0020 418F_FFFF 0x41B0_0000 0x41B0 0084 0x41B0 0184 MSCMR MSCRSR MSINT MSINTEN MSCR2 MSACD MSRXFIFO MSTXFIFO Reserved Reserved Reserved Reserved MSHC Command register MSHC Control Status register MSHC Intr Status register MSHC interrupt enable register MSHC Control Register MSHC Command register MSHC Receive FIFO MSHC Transmit FIFO
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x41B0 0200 0x41B0 0204 0x41B0 0208 0x41B0 020C 0x41B0 0210 0x41B0 0214 0x41BF FFFF
Register Symbol
Reserved Reserved Reserved Reserved Reserved Reserved
Register Description
1-Wire* Master
0x41C0_0000 0x41C0 0000 0x41C0 0004 0x41C0 0008 0x41C0 000C 0x41C0 0010 0x41C0 001C 0x41CF FFFF 0x41D0 0160 0x41DF FFFF 0x41E0 0160 0x41EF FFFF 0x41F0 0160 0x41FF FFFF 0x4200_0000 0x4200_0000 0x4200_0004 0x4200_0008 0x4200_000C 0x4200_0010 0x4200_0014 0x4200_0018 0x4200_001C 0x4200_0020 0x4200_0024 0x4200_0028 0x4200_002C 0x4200_0030 0x4200_0034 0x4200_0038 0x4200_003C 0x4200_0040 W1CMDR W1TRR W1INTR W1IER W1CDR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Command Register Transmit Receive Buffer Interrupt Register Interrupt Enable Register Clock Divisor Register
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x4200_0044 0x4200_0048 0x4200_004C 0x4200_0050 0x4200_0054 0x4200_0058 0x4200_005C 0x4200_0060 0x4200_0064 0x4200_0068 0x4200_006C 0x4200_0070 0x4200_0074 0x4200_0078 0x4200_007C 0x4200_0080 0x4200_008 0x4200_00FF 0x4200 0100 0x4200 0104 0x4200 0108 0x4200 010C 0x4200 0110 0x4200 0114 0x4200 0118 0x4200 011C 0x4200 0120 0x4200 0124 0x4200 0128 0x4200 012C 0x4200 0130 0x4200 0134 0x4200 0138 0x4200 013C 0x4200 0140 0x4200 0144 0x4200 0148 0x4200 014C 0x4200 0150
Register Symbol
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Register Description
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x4200 0154 0x4200 0158 0x4200 015C 0x4200 0160 0x4200 0164 0x4200 0168 0x4200 016C 0x4200 0170 0x4200 0174 0x4200 0178 0x4200 017C 0x4200 0180 0x4200 0x4200 01FF 0x4200 0200 0x4200 0204 0x4200 0208 0x4200_FFFF 0x4210_0000 0x4210_FFFF 0x4220_0000 0x4220_0000 0x4220_0004 0x4220_0008 0x4220_000C 0x4220_0010 0x4220_0014 0x4220_0018
Register Symbol
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Register Description
Timing Control Unit
0x4260_0000 0x4260_0000 0x4260_0004 0x4260_0008 0x4260_000C 0x4260_0010 0x4260_0014 0x4260_0018 0x4260_001C 0x4260_0020 FIFO NumInstr Status ExceptionEnable Control NearlyFull Level NearlyEmpty Level WriteIdx ReadIdx (7:0); Sets level NearlyFull exception (7:0); Sets level NearlyEmpty exception. (7:0); Location where next event written layer means write cycle (7:0); Location where next event read from preparation execution. (15:0); Entry point instructions (7:0); instructions FIFO (7:0); Gives reason exception occurred (6:0); Enable each exceptions reported status register
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x4260_0024 0x4260_0028 0x4260_0030 0x4260_0040 0x4260_0044 0x4260_0048 0x4260_004C 0x4260_0400 0x4260_07FC 0x4260_0800 0x426F_FFFF
Register Symbol
PreScale DeltaTimer EventLog GPOAClr GPOASet GPOBClr GPOBSet Reserved Reserved
Register Description
(5:0); Prescalar count Accessible debug purposes particularly event UnderFlow (15:0); When logging enabled, this register returns events 16-bit form. (15:0); position clears GPOA(n). read this register returns state GPOA. (15:0); position sets GPOA(n). read this register returns state GPOA. (15:0); position clears GPOB(n). read this register returns state GPOB. (15:0); position sets GPOB(n). read this register returns state GPOB.
Interface
0x4270_0000 0x4270_0000 0x4270_0004 0x4270_0008 0x4270_000C, 0x4270_0014 0x4270_0010 0x4270_0018 0x4270_001C 0x427F_FFFF SMSMR SMBRR SMSCR SMDR SMSSR SMSCMR Reserved Character Model Register Rate Register module Control Register Data Register. Physically register. Mapped registers, Transmit Data other Receive Data Status Register Smart Card Model register
Slow
0x4280_0000 0x4280_0000 0x4280_0004 0x4280_0008 0x4280_000C 0x4280_0010 0x4280_0014 0x4280_0018 0x4280_001C 0x4280_0020 0x4280_0024 0x4280_0028 WakeUp1 WakeUp2 WakeDly OscOn1 OscOn2 SSnap1 SSnap2 Fsnap StatCtrl SCntInt1 SCntInt2 (15:0); Slow Count Value which re-enable clock (4:0); Bits 20:16 WakeUp Register (7:0); Time period oscillator stabilization (15:0); Defines time which high speed oscillator should restarted, having accounted required settling times (4:0); Bits 20:16 OscOn Register (15:0); Slow count value associated with most recently executed snapshot command (4:0); Bits 20:16 SSnap Register (12:0); Snapshot command offset next slow edge defined terms high sped clock edge count. (10:0); Control Register (15:0); Slow count value interrupt during sleep period (4:0); Bits 20:16 SCntInt Register
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x4280_002C 0x4280_0030 0x4280_0034 0x4280_0038 0x428F_FFFF
Register Symbol
SCnt1 SCnt2 ScntLoad Reserved
Register Description
(15:0); Test register allow slow count read (4:0); Bits 20:16 Slow count read register (9:0); Test register allow slow counter loaded with test data
0x4290_0000 0x4290_0000 0x4290_0004 0x4290_0008 0x4290_000C 0x4290_0010 0x429F_FFFF RCNR RTAR RTSR RTTR Reserved Count Register Alarm Register Status Register Timer Trim Register
Control/ Status Registers
0x42A0_0000
0x42A0_0000 0x42A0_0004 0x42A0_03C0 0x42A0_03C4 0x42A0_03FC 0x42A0_0400 0x42A0_0420 0x42A0_0424 0x42A0_07FC 0x42A0_0800 0x42A0_0804 0x42A0_0BFC 0x42A0_0C00 0x42A0_0C04 0x42A0_0CFC 0x42A0_0D00 0x42A0_0D04 0x42A0_0FFC 0x42A0_1000 0x42A0_1004 0x42A0_1008 0x42AF_FFFF
Reserved IOPCR Reserved IOMCRG Reserved GCSR0 Reserved RTCRR Reserved LCDCR Reserved IOMCRS Reserved Multiplexing Control Register, Special Control Register Real Time Clock Reset Register General Control/Status Register Multiplexing Control Register, General Parameter Control Register
Memory Controller
0x4800_0000 0x4800_0000 0x4800_0004 0x4800_0008 MDCNFG MDREFR MSC0 SDRAM Configuration Register SDRAM Refresh Control Register Static Memory Control Register
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0x4800_000C 0x4800_0010 0x4800_0014 0x4800_0018 0x4800_001C 0x4800_0020 0x4800_0024 0x4800_0028 0x4800_002C 0x4800_0030 0x4800_0034 0x4800_0038 0x4800_003C 0x4800_0040 0x4800_0044 0x4800_0048 0x4800_004C 0x4800_0050 0x4800_0054 0x4800_0058 0x4800_005C 0x4800_0060 0x4800_0064 0x4BFF_FFFF 0xC080_0000 0xC080_0004 0xC080_0008 0xC080_000C 0xC080_0010 0xC080_0014 0xC080_0018 0xC080_001C
Register Symbol
MSC1 MSC2 Reserved Reserved SXCNFG Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MDMRS Reserved Reserved BSCNTR0 BSCNTR1 Reserved MDMRSLP BSCNTR2 BSCNTR3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Register Description
Static Memory Control Register Static Memory Control Register
Synchronous Static Memory Control Register
value written SDRAM
Transistor buffer strengths system memory output buffers Transistor buffer strengths system memory output buffers
Special power value written SDRAM Transistor buffer strengths system memory output buffers Transistor buffer strengths system memory output buffers
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0xC080_0020 0xC080_0024 0xC080_0028 0xC080_002C 0xC080_0030 0xC080_0034 0xC080_0038 0xC080_003C 0xC080_0040 0xC080_0044 0xC080_0048 0xC080_004C 0xC080_0050 0xC080_0054 0xC080_0058 0xC080_005C 0xC080_0060 0xC080_0064 0xC080_0068 0xC080_006C 0xC080_0070 0xC080_0074 0xC080_0078 0xC080_007C 0xC080_0080 0xC080_0084 0xC080_0088 0xC080_008C 0xC080_0090 0xC080_0094 0xC080_0098 0xC080_009C 0xC080_00A0 0xC080_00A4 0xC080_00A8 0xC080_00AC 0xC080_00B0 0xC08F_FFFF
Register Symbol
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Register Description
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit DSSP6 (Digital Audio Interface)
Address
0xC088_0000 0xC08F_FFFF 0xC088_0000 0xC088_0004 0xC088_0008 0xC088_000C 0xC088_0010 0xC088_0014 0xC088_0024 0xC088_0028 0xC088_002C 0xC088_0030 0xC08F_FFFF
Register Symbol
Register Description
SS6CR0 SS6CR1 SS6SR SS6ITR SS6DR (write/read) Reserved SS6TO SS6PSP Reserved
SSP6 Control Register SSP6 Control Register SSP6 Status Register SSP6 Interrupt Test Register SSP6 Data Write Register/SSP Data Read Register
SSP6 Time Register SSP6 Programmable Serial Protocol Register
DSSP5 (Serial Control)
0xC090_0000 0xC090_0000 0xC090_0004 0xC090_0008 0xC090_000C 0xC090_0010 0xC090_0014 0xC090_0024 0xC090_0028 0xC090_002C 0xC090_0030 0xC09F_FFFF SS5CR0 SS5CR1 SS5SR SS5ITR SS5DR (write/ read) Reserved SS5TO SS5PSP Reserved SSP5 Time Register SSP5 Programmable Serial Protocol Register SSP5 Control Register SSP5 Control Register SSP5 Status Register SSP5 Interrupt Test Register SSP5 Data Write Register/SSP Data Read Register
DSSP4 (Auxiliary Serial Port)
0xC0A0_0000
0xC0A0_0000 0xC0A0_0004 0xC0A0_0008 0xC0A0_000C 0xC0A0_0010 0xC0A0_0014 0xC0A0_0024 0xC0A0_0028 0xC0A0_002C 0xC0A0_0030 0xC0AF_FFFF
SS4CR0 SS4CR1 SS4SR SS4ITR SS4DR (write/ read) Reserved SS4TO SS4PSP Reserved
SSP4 Control Register SSP4 Control Register SSP4 Status Register SSP4 Interrupt Test Register SSP4 Data Write Register/SSP Data Read Register
SSP4 Time Register SSP4 Programmable Serial Protocol Register
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit DSSP3 (Voiceband Serial Port Bluetooth* wireless technology)
Address
Register Symbol
Register Description
0xC0B0_0000
0xC0B0_0000 0xC0B0_0004 0xC0B0_0008 0xC0B0_000C 0xC0B0_0010 0xC0B0_0014 0xC0B0_0024 0xC0B0_0028 0xC0B0_002C 0xC0B0_0030 0xC0BF_FFFF
SS3CR0 SS3CR1 SS3SR SS3ITR SS3DR (write/ read) Reserved SS3TO SS3PSP Reserved
SSP3 Control Register SSP3 Control Register SSP3 Status Register SSP3 Interrupt Test Register SSP3 Data Write Register/SSP Data Read Register
SSP3 Time Register SSP3 Programmable Serial Protocol Register
DSSP2 (Baseband
0xC0C0_0000 0xC0C0_0000 0xC0C0_0004 0xC0C0_0008 0xC0C0_000C 0xC0C0_0010 0xC0C0_0014 0xC0C0_0024 0xC0C0_0028 0xC0C0_002C 0xC0C0_0030 0xC0CF_FFFF SS2CR0 SS2CR1 SS2SR SS2ITR SS2DR (write/ read) Reserved SS2TO SS2PSP Reserved SSP2 Time Register SSP2 Programmable Serial Protocol Register SSP2 Control Register SSP2 Control Register SSP2 Status Register SSP2 Interrupt Test Register SSP2 Data Write Register/SSP Data Read Register
DSSP1 (Baseband
0xC0D0_0000 0xC0D0_0000 0xC0D0_0004 0xC0D0_0008 0xC0D0_000C 0xC0D0_0010 0xC0D0_0014 0xC0D0_0024 0xC0D0_0028 0xC0D0_002C 0xC0D0_0030 0xC0DF_FFFF SS1CR0 SS1CR1 SS1SR SS1ITR SS1DR (write/ read) Reserved SS1TO SS1PSP Reserved SSP1 Time Register SSP1 Programmable Serial Protocol Register SSP1 Control Register SSP1 Control Register SSP1 Status Register SSP1 Interrupt Test Register SSP1 Data Write Register/SSP Data Read Register
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit Cipher Accelerator
Address
0xC0E0_0000 0xC0E0_0000 0xC0E0_0002 0xC0E0_0004 0xC0E0_0006 0xC0E0_0008 0xC0E0_000A 0xC0E0_000C 0xC0EF_FFFF
Register Symbol
Register Description
Control Test Address Data Parity Reverse Reserved
(15:0); Control status coprocessor (15:0); Provides view internal coprocessor state (15:0); Provides access program counter stack pointer (15:0); Provides access data (15:0); Returns parity word written (15:0); Returns bit-reverse word written
0xC0F0_0000 0xC0F0_0000 0xC0F0_0004 0xC0F0_0008 0xC0F0_000C 0xC0F0_0010 0xC0F0_0014 0xC0F0_0018 0xC0F0_001C 0xC0F0_005C 0xC0F0_0060 0xC0F0_0064 0xC0F0_007C 0xC0F0_0080 0xC0F0_0084 0xC0FF_FFFF 0xE000_0100 0xE000_0104 0xE000_0108 0xFFCO_2000 0xFFC0_2004 0xFFC0_2008 0xFFC0_200C 0xFFC0_2010 0xFFC0_2014 0xFFC0_2018 0xFFC0_201C SACR0 SACR1 Reserved SASR0 Reserved SAIMR SAICR Reserved Reserved Reserved SADR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Serial Audio Data Register FIFO access Register) Serial Audio Interrupt Mask Register Serial Audio Interrupt Clear Register Serial Audio I2S/MSB-Justified Interface FIFO Status Register Global Control Register Serial Audio I2S/MSB-Justified Control Register
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0xFFC0_20200xFFC0_21FF 0xFFC0_22000xFFC0_23FC
Register Symbol
Reserved Reserved
Register Description
IRQCtrl
0xFFC8_0000 0xFFC8_0000 0xFFC8_0004 0xFFC8_0008 Enable Register Enable CrossAssert Enable EIRQ Enable Bank Enable Bank Enable Bank Enable Bank Enable Bank Enable Reserved (15:0); Each when clear masks corresponding number, when enables that number (7:0); Each when clear masks corresponding number, when enables that number (0); When clear masks CrossAssert input, when enables CrossAssert input. (2:0); Each when cleared masks corresponding Error number, when enables that Error number. (15:0); Each when clear masks corresponding number, when enables that number (15:0); Each when clear masks corresponding number when enables that number (15:0); Each when clear masks corresponding number when enables that number (15:0); Each when clear masks corresponding number when enables that number (15:0); Each when clear masks corresponding number when enables that number
0xFFC8_000C
0xFFC8_0020
0xFFC8_0024
0xFFC8_0028
0xFFC8_002C
0xFFC8_0030 0xFFC8_0034 0xFFC8_003E
previous IRQCtrl addresses Read, when written, only corresponding bits actual register. Clearing these register bits achieved writing addresses FFC8_0020 FFC8_003F shown below. register entries shown italics only generated function number inputs required, defined (gNH/16) rounded nearest integer. Unused register bits always read back 0x0.
0xFFC8_0040 0xFFC8_0044 Enable Register Enable (15:0); Each when clear masks corresponding number, when enables that number (7:0); Each when clear masks corresponding number, when enables that number (2:0); Each when clear masks corresponding Error number, when enables that Error number (15:0); Each when clear masks corresponding number, when enables that number (15:0); Each when clear masks corresponding number when enables that number (15:0); Each when clear masks corresponding number when enables that number (15:0); Each when clear masks corresponding number when enables that number
0xFFC8_0048
EIRQ Enable
0xFFC8_0060
Bank Enable Bank Enable Bank Enable Bank Enable
0xFFC8_0064
0xFFC8_0068
0xFFC8_006C
PXA800F Cellular Processor Developer's Manual Preliminary
Memory Register
Unit
Address
0xFFC8_0070 0xFFC8_0074 0xFFC8_007E
Register Symbol
Bank Enable Reserved
Register Description
(15:0); Each when clear masks corresponding number when enables that number
FFC8_0020 FFC8_003F addresses write-only when written, only clear corresponding bits actual register. Data bits that clear during Write affect corresponding register bits. bits these registers, refer addresses FFC8_0000 FFC8_0018. Register entries shown italics generated function number inputs required, defined (gNH/16) rounded nearest integer.
0xFFC8_0080 Current Interrupt Priority (3:0); When IRQs active, register reads back 0x000F. When active, register reads back priority level highest priority interrupt, range 0x0000 0x000F. Test purposes only (6:0); When IRQs active, register reads back 0x007F. When active, register reads back number highest priority interrupt, range 0x0000 where n(HWI) SWI, XSWI, EIRQ, HWI's. (15:0); When read, returns 16-bit value. Each indicates that there active intr that level, with zero indicating level (highest). (0); IRQCtrl Reset Flag. Must cleared normal operation. Default reset value (15:0); Each bit, when set, indicates over- underflow corresponding counter. (7:0); This bit, when set, indicates overflow register. (0); This bit, when set, indicates over- underflow XSWI counter. (6:0); When IRQ.s active, register will read back 0x007F. When active, register will read back number highest priority interrupt, range 0x0000 where n(HWI) SWI, XSWI, EIRQ, HWI.s. This register provides exactly same information register. (3:0); Defined priority level, (3:0); Defined priority level, (3:0); Defined priority level, (3:0); Defined priority level, (3:0); Defined priority level, (3:0); Defined priority level, (3:0); Defined priority level, (3:0); Defined priority l
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