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Device Handbook
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com
MII5V1-1.0
Copyright 2004 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Printed recycled paper
Preliminary
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Contents
Chapter Revision Dates About this Handbook
Contact Altera Typographic Conventions
Section Device Family Data Sheet
Revision History
Chapter Introduction
Features
Chapter Architecture
Logic Array Blocks Interconnects Control Signals Logic Elements Chain Register Chain addnsub Signal Operating Modes MultiTrack Interconnect 2-15 Global Signals 2-20 User Flash Memory Block 2-23 Storage 2-24 Internal Oscillator 2-24 Program, Erase Busy Signals 2-24 Auto-Increment Addressing 2-25 Serial Interface 2-25 Block Logic Array Interface 2-25 MultiVolt Core 2-27 Structure 2-28 Fast Connection 2-29 Blocks 2-29 Standards Banks 2-31 Schmitt Trigger 2-35 Output Enable Signals 2-35 Programmable Drive Strength 2-36 Slew-Rate Control 2-37
Altera Corporation Preliminary
Contents
Device Handbook
Open-Drain Output Programmable Ground Pins Hold Programmable Pull-Up Resistor MultiVolt Interface
2-37 2-37 2-37 2-38 2-38
Chapter JTAG In-System Programmability
IEEE Std. 1149.1 (JTAG) Boundary Scan Support JTAG Translator System Programmability IEEE 1532 Support Standard Test Programming Language (STAPL) Programming Sequence Programming Real-Time Design Security Programming with External Hardware
Chapter Socketing Power-On Reset Devices
Socketing Hot-Socketing Specifications Socketing Feature Implementation Devices Power-On Reset Circuitry Power-Up Characteristics
Chapter Switching Characteristics
Operating Conditions Absolute Maximum Ratings Recommended Operating Conditions Programming/Erasure Specifications Electrical Characteristics Standard Specifications Hold Specifications Power-Up Timing JTAG Timing Specifications Power Consumption Timing Model Specifications 5-10 Preliminary Final Timing 5-11 Performance 5-12 Internal Timing Parameters 5-13 External Timing Parameters 5-20 External Timing Delay Adders 5-24 Maximum Input Output Clock Rates 5-27
Chapter Reference Ordering Information
Device Pin-Outs Ordering Information
Preliminary
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Contents
Contents
Dual Marking
Section Layout Guidelines
Revision History Section II-1
Chapter Package Information
Device Package Cross Reference Thermal Resistance Package Outlines 100-Pin Plastic Thin Quad Flat Pack (TQFP) 144-Pin Plastic Thin Quad Flat Pack (TQFP) 256-Pin Non-Thermally Enhanced FineLine Ball-Grid Array 324-Pin Non-Thermally Enhanced FineLine Ball-Grid Array
Chapter Designing with FineLine Packages
Introduction Overview Packages Layout Terminology Escape Routing Multi-Layer PCBs Vias Capture Surface Land Stringer Layout FineLine Packages Surface Land Dimension Capture Layout Dimension Signal Line Space Trace Width Number Layers 8-10 Conclusion 8-12
Chapter Using Devices Multi-Voltage Systems
Standards MultiVolt Core Operation 5.0-V Device Compatibility Recommended Operating Condition 5.0-V Compatibility Hot-Socketing 9-10 Power-Up Sequencing 9-10 Power-On Reset 9-10 Conclusion 9-10
Section III. User Flash Memory
Revision History Section III-1
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Preliminary
Contents
Device Handbook
Chapter Using User Flash Memory Devices
Array Description 10-1 Memory Organization 10-1 Using Accessing Storage 10-2 Functional Description 10-2 Address Register 10-5 Data Register 10-6 Program/Erase Control Block 10-7 Oscillator 10-7 Operating Modes 10-8 Read/Stream Read 10-8 Program 10-10 Erase 10-11 Programming Reading with JTAG 10-12 Software Support Block 10-12 Serial Peripheral Interface 10-14 Parallel Interface 10-21 None (Altera Serial Interface) 10-23 Creating Memory Content File 10-24 Conclusion 10-27
Chapter Using User Flash Memory Data Storage Manufacturing Flow
Manufacturing Data Storing Manufacturing Data Reading Manufacturing Data from Data Storage Using JTAG Interface Generating Programming File Conclusion 11-1 11-2 11-4 11-5 11-8 11-8
Chapter Replacing Serial EEPROMs with User Flash Memory
12-1 Standard Interface Protocols 12-2 List Vendors Devices 12-3 Conclusion 12-15
Section In-System Programmability
Revision History Section IV-1
Chapter In-System Programmability Guidelines Devices
General Guidelines Operating Conditions Interrupting In-System Programming MultiVolt Devices Power-Up Sequences Pins Tri-Stated during In-System Programming Pull-Up Pull-Down JTAG Pins During In-System Programming
Preliminary
13-1 13-1 13-3 13-3 13-3 13-4
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Contents
Contents
IEEE Std. 1149.1 Signals 13-5 Signal 13-5 Programming Download Cable 13-5 Disabling IEEE Std. 1149.1 Circuitry 13-6 Working with Different Voltage Levels 13-6 Sequential Concurrent Programming 13-7 Sequential Programming 13-7 Concurrent Programming 13-7 Troubleshooting Guidelines 13-9 Invalid Unrecognized Device Messages 13-9 Troubleshooting Tips 13-10 Embedded Processors 13-11 Processor Memory Requirements 13-11 Porting Player 13-12 In-Circuit Testers 13-12 Conclusion 13-12
Chapter IEEE 1149.1 (JTAG) Boundary-Scan Testing Devices
IEEE Std. 1149.1 Architecture 14-2 IEEE Std. 1149.1 Boundary-Scan Register 14-4 Boundary-Scan Cells Device 14-5 JTAG Pins Power Pins 14-6 IEEE Std. 1149.1 Operation Control 14-6 SAMPLE/PRELOAD Instruction Mode 14-10 EXTEST Instruction Mode 14-13 BYPASS Instruction Mode 14-15 IDCODE Instruction Mode 14-16 USERCODE Instruction Mode 14-16 CLAMP Instruction Mode 14-17 HIGHZ Instruction Mode 14-17 Voltage Support JTAG Chain 14-17 Disabling IEEE Std. 1149.1 Circuitry 14-18 Guidelines IEEE Std. 1149.1 Boundary-Scan Testing 14-19 Boundary-Scan Description Language (BSDL) Support 14-19 Conclusion 14-19
Chapter Using STAPL Embedded Processor
Embedded Systems 15-1 Connecting JTAG Chain Embedded Processor 15-1 Board Layout 15-4 Software Development 15-5 Files (.jam .jbc) 15-6 Generating Files 15-6 Players 15-8 Updating Devices Using 15-18 Conclusion 15-21
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Preliminary
Contents
Device Handbook
Chapter Using Agilent 3070 Tester In-System Programming
Product Agilent 3070 16-1 Device Support 16-1 Agilent 3070 Development Flow without Software 16-1 Step Create Test Fixture 16-3 Step Create Serial Vector Format File 16-4 Step Convert Files Files 16-5 Step Create Executable Tests from Files 16-5 Step Compile Executable Tests 16-8 Step Debug Test 16-9 Development Flow Agilent 3070 with Software 16-10 Programming Times 16-12 Guidelines 16-13 Conclusion 16-13
Section Design Considerations
Revision History Section
Chapter Understanding Timing Devices
External Timing Parameters Internal Timing Parameters Internal Timing Parameters Timing Models Calculating Timing Delays Timing Model Quartus Timing Analyzer Conclusion 17-1 17-2 17-3 17-4 17-5 17-8 17-9
Chapter Understanding Evaluating Power Devices
Power Devices 18-1 Power Estimation Using Power Calculator Spreadsheet 18-3 Device Section 18-3 ICCSTANDBY Section 18-4 Dynamic Power Section 18-5 Logic Array Dynamic Power Section 18-6 General Power Section 18-10 Total Power Section 18-11 Thermal Analysis Section 18-12 Power Saving Techniques 18-14 Conclusion 18-15
viii Preliminary
Altera Corporation
Chapter Revision Dates
Chapter Introduction Revised: Part number:
March 2004 MII51001-1.0
Chapter Architecture Revised: March 2004 Part number: MII51002-1.0 Chapter JTAG In-System Programmability Revised: March 2004 Part number: MII51003-1.0 Chapter Socketing Power-On Reset Devices Revised: March 2004 Part number: MII51004-1.0 Chapter Switching Characteristics Revised: March 2004 Part number: MII51005-1.0 Chapter Reference Ordering Information Revised: March 2004 Part number: MII51006-1.0 Chapter Package Information Revised: March 2004 Part number: MII51007-1.0 Chapter Designing with FineLine Packages Revised: March 2004 Part number: MII51008-1.0 Chapter Using Devices Multi-Voltage Systems Revised: March 2004 Part number: MII51009-1.0 Chapter Using User Flash Memory Devices Revised: March 2004 Part number: MII51010-1.0
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Preliminary
Chapter Revision Dates
Device Handbook
Chapter Using User Flash Memory Data Storage Manufacturing Flow Revised: March 2004 Part number: MII51011-1.0 Chapter Replacing Serial EEPROMs with User Flash Memory Revised: March 2004 Part number: MII51012-1.0 Chapter In-System Programmability Guidelines Devices Revised: March 2004 Part number: MII51013-1.0 Chapter IEEE 1149.1 (JTAG) Boundary-Scan Testing Devices Revised: March 2004 Part number: MII51014-1.0 Chapter Using STAPL Embedded Processor Revised: March 2004 Part number: MII51015-1.0 Chapter Using Agilent 3070 Tester In-System Programming Revised: March 2004 Part number: MII51016-1.0 Chapter Understanding Timing Devices Revised: March 2004 Part number: MII51017-1.0 Chapter Understanding Evaluating Power Devices Revised: March 2004 Part number: MII51018-1.0 Appendix A.ASCII Code Table Revised: March 2004
Preliminary
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About this Handbook
This handbook provides comprehensive information about Altera® MAX® family devices.
Contact Altera
Information Type
Technical support
most up-to-date information about Altera products, Altera world-wide site www.altera.com. technical support this product, www.altera.com/mysupport. additional information about Altera products, consult sources shown below. Canada
www.altera.com/mysupport/ (800) 800-EPLD (3753) (7:00 a.m. 5:00 p.m. Pacific Time)
Other Locations
altera.com/mysupport/ (408) 544-7000 (7:00 a.m. 5:00 p.m. Pacific Time) www.altera.com lit_req@altera.com (408) 544-7000 (7:30 a.m. 5:30 p.m. Pacific Time) ftp.altera.com
Product literature Altera literature services Non-technical customer service site Note table:
www.altera.com lit_req@altera.com (800) 767-3753 ftp.altera.com
also contact your local Altera sales office sales representative.
Typographic Conventions
Visual
Bold Type with Initial Capital Letters bold type
This document uses typographic conventions shown below.
Meaning
Command names, dialog titles, checkbox options, dialog options shown bold, initial capital letters. Example: Save dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, software utility names shown bold type. Examples: fMAX, \qdesigns directory, drive, chiptrip.gdf file. Document titles shown italic type with initial capital letters. Example: High-Speed Board Design.
Italic Type with Initial Capital Letters
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Preliminary
Typographic Conventions
Device Handbook
Visual
Italic type
Meaning
Internal timing parameters variables shown italic type. Examples: tPIA, Variable names enclosed angle brackets shown italic type. Example: <file name>, <project name>.pof file.
Initial Capital Letters "Subheading Title"
Keyboard keys menu names shown with initial capital letters. Examples: Delete key, Options menu. References sections within document titles on-line help topics shown quotation marks. Example: "Typographic Conventions." Signal port names shown lowercase Courier type. Examples: data1, tdi, input. Active-low signals denoted suffix e.g., resetn. Anything that must typed exactly appears shown Courier type. example: Also, sections actual file, such Report File, references parts files (e.g., AHDL keyword SUBDESIGN), well logic function names (e.g., TRI) shown Courier.
Courier type
etc.
Numbered steps used list items when sequence items important, such steps listed procedure. Bullets used list items when sequence items important. checkmark indicates procedure that consists step only. hand points information that requires special attention. caution indicates required information that needs special consideration understanding should read prior starting continuing with procedure process. warning indicates information that should read prior starting continuing procedure processes angled arrow indicates should press Enter key. feet direct more information particular topic.
Preliminary
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Section Device Family Data Sheet
This section provides designers with data sheet specifications MAX® devices. chapters contain feature definitions internal architecture, Joint Test Action Group (JTAG) in-system programmability (ISP) information, operating conditions, timing parameters, ordering information devices. This section includes following chapters:
Chapter Introduction Chapter Architecture Chapter JTAG In-System Programmability Chapter Socketing Power-On Reset Devices Chapter Switching Characteristics Chapter Reference Ordering Information
Revision History
table below shows revision history Chapters through Chapter(s)
Date/Version
March 2004, v1.0 March 2004, v1.0 March 2004, v1.0 March 2004, v1.0 March 2004, v1.0 March 2004, v1.0 Initial Release. Initial Release. Initial Release. Initial Release. Initial Release. Initial Release.
Changes Made
Altera Corporation
Section Preliminary
Revision History
Device Handbook
Section Preliminary
Altera Corporation
Chapter Introduction
MII51001-1.0
Introduction
MAX® family instant-on, non-volatile CPLDs based 0.18-µm, 6-layer-metal-flash process, with densities from 2,210 logic elements (LEs) (128 2,210 equivalent macrocells) non-volatile storage Kbits. devices offer high counts, fast performance, reliable fitting versus other CPLD architectures. Featuring MultiVoltcore, user flash memory (UFM) block, enhanced in-system programmability (ISP), devices designed reduce cost power while providing programmable solutions applications such bridging, expansion, power-on reset (POR) sequencing control, device configuration control. following shows main sections CPLD Family Data Sheet: Section Page
Features Functional Description Logic Array Blocks. Logic Elements MultiTrack Interconnect 2-15 Global Signals 2-20 User Flash Memory Block. 2-23 MultiVolt Core 2-27 Structure 2-28 IEEE Std. 1149.1 (JTAG) Boundary Scan Support System Programmability Socketing Power-On Reset Circuitry. Operating Conditions Power Consumption Timing Model Specifications 5-10 Device Pin-Outs Ordering Information
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Features
Features
Low-cost, low-power CPLD Instant-on, non-volatile architecture Standby current Provides fast propagation delay clock-to-output times Provides four global clocks with clocks available logic array block (LAB) block Kbits non-volatile storage MultiVolt core enabling external supply voltages device either V/2.5 MultiVolt interface supporting 3.3-V, 2.5-V, 1.8-V, 1.5-V logic levels Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, programmable pull-up resistors Schmitt triggers enabling noise tolerant inputs (programmable pin) Fully compliant with Peripheral Component Interconnect Special Interest Group (PCI SIG) Local Specification, Revision 3.3-V operation Supports hot-socketing Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 circuitry compliant with IEEE Std. 1532
Table shows device features.
Table 1-1. Device Features Feature
Typical Equivalent Macrocells Equivalent Macrocell Range Size (bits) Maximum User pins tPD1 (ns) fCNT (MHz) (ns) (ns) Notes Table 1-1:
tPD1 represents pin-to-pin delay worst case placement with full diagonal path across device combinational logic implemented single that adjacent output pin. maximum frequency limited standard clock input pin. 16-bit counter critical delay will faster than this number.
EPM240
8,192
EPM570
8,192
EPM1270
1,270 1,270 8,192
EPM2210
2,210 1,700 1,270 2,210 8,192
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Introduction
more information equivalent macrocells, refer Logic Element Macrocell Conversion Methodology white paper.
devices available three speed grades: with being fastest. These speed grades represent overall relative performance, specific timing parameter. propagation delay timing numbers within each speed grade density, "Timing Model Specifications" page 5-10. Table shows device speedgrade offerings.
Table 1-2. Speed Grades Speed Grade Device
EPM240 EPM570 EPM1270 EPM2210
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Features
devices available space-saving FineLine BGA® thin quad flat pack (TQFP) packages (see Tables 1-4). devices support vertical migration within same package (e.g., migrate between EPM570, EPM1270, EPM2210 devices 256-pin FineLine package). Vertical migration means that migrate devices whose dedicated pins JTAG pins same power pins subsets supersets given package across device densities. largest density package highest number power pins; must layout largest planned density package provide necessary power pins migration. migration across densities, cross reference available pins using device pin-outs planned densities given package type identify which pins migrated. Quartus® software automatically cross reference place pins when given device migration list.
Table 1-3. Packages User Pins Device
EPM240 EPM570 EPM1270 EPM2210
100-Pin TQFP
144-Pin TQFP
256-Pin FineLine
324-Pin FineLine
Table 1-4. TQPF FineLine Package Sizes Package
Pitch (mm) Area (mm2) Length width
100-Pin TQFP
144-Pin TQFP
256-Pin FineLine 324-Pin FineLine
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Introduction
devices have internal voltage regulator which supports external supply voltages regulating supply down internal operating voltage devices with ordering code only accept external supply voltage. Table shows external supply voltages supported family.
Table 1-5. External Supply Voltages EPM240 EPM570 EPM1270 EPM2210
Devices
EPM240G EPM570G EPM1270G EPM2210G
MultiVolt core external supply voltage (VCCINT) MultiVolt interface voltage levels (VCCIO) Notes Table 1-5:
devices with ordering code have internal voltage regulator only accept their VCCINT pins. Contact Altera availability these devices. devices operate internally
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Chapter Architecture
MII51002-1.0
Functional Description
MAX® devices contain two-dimensional row- column-based architecture implement custom logic. Column interconnect provide signal interconnects between logic array blocks (LABs). logic array consists LABs, with logic elements (LEs) each LAB. small unit logic providing efficient implementation user logic functions. LABs grouped into rows columns across device. MultiTrackinterconnect provides fast granular timing delays between LABs. fast routing between provides minimum timing delay added levels logic versus globally routed interconnect structures. Figure shows functional block diagram device.
Figure 2-1. Device Block Diagram
Logic Element
Logic Element
Logic Element
Logic Element
Logic Element
Logic Element
Logic Array BLock (LAB)
MultiTrack Interconnect Logic Element Logic Element Logic Element
Logic Element
Logic Element
Logic Element
MultiTrack Interconnect
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device pins element (IOE) located ends rows columns around periphery device. Each contains bidirectional buffer with several advanced features. pins support Schmitt trigger inputs various singleended standards, such 33-MHz, 32-bit LVTTL. devices provide global clock network. global clock network consists four global clock lines that drive throughout entire device, providing clocks resources within device. global clock lines also used control signals such clear, preset, output enable. Each device contains flash memory block within floorplan. EPM240 device, this block located left side device. EPM570, EPM1270, EPM2210 devices, flash memory block located bottom-left area device. majority this flash memory storage partitioned dedicated configuration flash memory block. configuration flash memory block provides nonvolatile storage SRAM configuration information. configuration flash memory automatically downloads configures logic power-up providing instant-on operation.
Chapter Socketing Power-On Reset Devices more information configuration upon power-up. portion flash memory within device partitioned into small block user data. This user flash memory (UFM) block provides 8,192 bits general-purpose user storage. provides programmable port connections logic array reading writing. There three rows adjacent this block, with column numbers varying device.
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Architecture
Table shows number rows columns each device well number rows columns adjacent flash memory area EPM570, EPM1270, EPM2210 devices. long rows full rows that extend from side blocks other. short rows adjacent block; their length shown width columns.
Table 2-1. Device Resources Rows Devices
EPM240 EPM570 EPM1270 EPM2210 Note Table 2-1:
width number columns length.
Blocks
Columns Long Rows
Short Rows (Width)
Figure shows floorplan device.
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Logic Array Blocks
Figure 2-2. Device Floorplan
Blocks
Note
Blocks Logic Array Blocks Logic Array Blocks
GCLK Inputs Blocks
GCLK Inputs
Block Configuration Flash Memory Block
Note Figure 2-2:
device shown EPM570 device. EPM1270 EPM2210 devices have similar floorplan with more LABs. EPM240 devices, configuration flash memory block rotated left degrees covering left side device.
Logic Array Blocks
Each consists LEs, carry chains, control signals, local interconnect, look-up table (LUT) chain, register chain connection lines. local interconnect transfers signals between same LAB. chain connections transfer output LE's adjacent fast sequential connections within same LAB. Register chain connections transfer output LE's register adjacent LE's register within LAB. Quartus® software places associated logic within adjacent LABs, allowing local, chain, register chain connections performance area efficiency. Figure shows LAB.
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Architecture
Figure 2-3. Structure
Interconnect
Column Interconnect
Fast Connection DirectLink interconnect from adjacent DirectLink interconnect adjacent
Logic Element Local Interconnect
Fast connection DirectLink interconnect from adjacent
DirectLink interconnect adjacent
Note Figure 2-3:
Only from LABs adjacent IOEs.
Interconnects
local interconnect drive within same LAB. local interconnect driven column interconnects outputs within same LAB. Neighboring LABs, from left right also drive LAB's local interconnect through DirectLink connection. DirectLink connection feature minimizes column interconnects, providing higher performance flexibility. Each drive other through fast local DirectLink interconnects. Figure shows DirectLink connection.
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Logic Array Blocks
Figure 2-4. DirectLink Connection
DirectLink interconnect from left output DirectLink interconnect from right output
DirectLink interconnect left Local Interconnect
Logic Element
DirectLink interconnect right
Control Signals
Each contains dedicated logic driving control signals LEs. control signals include clocks, clock enables, asynchronous clears, synchronous clear, asynchronous preset/load, synchronous load, add/subtract control signals, providing maximum control signals time. Although synchronous load clear signals generally used when implementing counters, they also used with other functions. Each clocks clock enable signals. Each LAB's clock clock enable signals linked. example, particular using labclk1 signal also uses labclkena1. uses both rising falling edges clock, also uses both LAB-wide clock signals. De-asserting clock enable signal turns LAB-wide clock. Each asynchronous clear signals asynchronous load/preset signal. asynchronous load acts preset when asynchronous load data input tied high.
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Architecture
With LAB-wide addnsub control signal, single implement one-bit adder subtractor. This saves resources improves performance logic functions such correlators signed multipliers that alternate between addition subtraction depending data. column clocks [3.0], driven global clock network, local interconnect generate LAB-wide control signals. MultiTrackinterconnect structure drives local interconnect non-global control signal generation. MultiTrack interconnect's inherent skew allows clock control signal distribution addition data. Figure shows control signal generation circuit. Figure 2-5. LAB-Wide Control Signals
Dedicated Column Clocks Local Interconnect Local Interconnect
Local Interconnect Local Interconnect Local Interconnect Local Interconnect labclk1
labclkena1
labclkena2
syncload
labclr2
addnsub
labclk2
asyncload labpre
labclr1
synclr
Logic Elements
smallest unit logic architecture, compact provides advanced features with efficient logic utilization. Each contains four-input LUT, which function generator that implement function four variables. addition, each contains programmable register carry chain with carry select capability. single also supports dynamic single addition subtraction mode selectable LAB-wide control signal. Each drives types interconnects: local, row, column, chain, register chain, DirectLink interconnects. Figure 2-6.
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Logic Elements
Figure 2-6.
Register chain routing from previous LAB-wide Register Bypass Synchronous Load LAB-wide Packed Synchronous Register Select Clear
Carry-In addnsub Carry-In1 Carry-In0
Programmable Register chain routing next Row, column, DirectLink routing
data1 data2 data3 data4
CLRN
Look-Up Table (LUT)
Carry Chain
Synchronous Load Clear Logic
PRN/ALD ADATA
Row, column, DirectLink routing
labclr1 labclr2 labpre/aload Chip-Wide Reset (DEV_CLRn)
Asynchronous Clear/Preset/ Load Logic
Local Routing
Clock Clock Enable Select labclk1 labclk2 labclkena1 labclkena2
Register Feedback
Register chain output
Carry-Out0 Carry-Out1 Carry-Out
Each LE's programmable register configured operation. Each register data, true asynchronous load data, clock, clock enable, clear, asynchronous load/preset inputs. Global signals, general-purpose pins, drive register's clock clear control signals. Either general-purpose pins drive clock enable, preset, asynchronous load, asynchronous data. asynchronous load data input comes from data3 input combinational functions, output bypasses register drives directly outputs. Each three outputs that drive local, row, column routing resources. register output drive these three outputs independently. outputs drive column DirectLink routing connections drives local interconnect resources. This allows drive output while register drives another output. This register packing feature improves device utilization because device register unrelated functions. Another special packing mode allows register output feed back into
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Architecture
same that register packed with fan-out LUT. This provides another mechanism improved fitting. also drive registered unregistered versions output.
Chain Register Chain
addition three general routing outputs, within have chain register chain outputs. chain connections allow LUTs within same cascade together wide input functions. Register chain outputs allow registers within same cascade together. register chain output allows LUTs single combinational function registers used unrelated shift register implementation. These resources speed connections between LABs while saving local interconnect resources. "MultiTrack Interconnect" page 2-15 more information chain register chain connections.
addnsub Signal
LE's dynamic adder/subtractor feature saves logic resources using implement both adder subtractor. This feature controlled LAB-wide control signal addnsub. addnsub signal sets perform either computes addition; subtraction computed adding two's complement intended subtractor. LAB-wide signal converts two's complement inverting bits within setting carry-in which adds least significant (LSB). adder/subtractor must placed first LAB, where LAB-wide addnsub signal automatically sets carry-in Quartus Compiler automatically places uses adder/subtractor feature when using adder/subtractor parameterized functions.
Operating Modes
operate following modes:
Normal mode Dynamic arithmetic mode
Each mode uses resources differently. each mode, eight available inputs four data inputs from local interconnect, carry-in0 carry-in1 from previous carry-in from previous carry-chain LAB, register chain connection directed different destinations implement desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous
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Logic Elements
preset/load, synchronous clear, synchronous load, clock enable control register. These LAB-wide signals available modes. addnsub control signal allowed arithmetic mode. Quartus software, conjunction with parameterized functions such library parameterized modules (LPM) functions, automatically chooses appropriate mode common functions such counters, adders, subtractors, arithmetic functions.
Normal Mode
normal mode suitable general logic applications combinational functions. normal mode, four data inputs from local interconnect inputs four-input (see Figure 2-7). Quartus Compiler automatically selects carry-in data3 signal inputs LUT. Each chain connections drive combinational output directly next LAB. Asynchronous load data register comes from data3 input normal mode support packed registers. Figure 2-7. Normal Mode
sload sclear (LAB Wide) (LAB Wide) Register chain connection aload (LAB Wide)
addnsub (LAB Wide)
data1 data2 data3 (from cout previous data4
4-Input
ALD/PRE ADATA CLRN
Row, column, DirectLink routing Row, column, DirectLink routing
clock (LAB Wide) (LAB Wide) aclr (LAB Wide)
Local routing
chain connection Register chain output
Register Feedback
Note Figure 2-7:
This signal only allowed normal mode adder/subtractor chain.
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Architecture
Dynamic Arithmetic Mode
dynamic arithmetic mode ideal implementing adders, counters, accumulators, wide parity functions, comparators. dynamic arithmetic mode uses four 2-input LUTs configurable dynamic adder/subtractor. first 2-input LUTs compute summations based possible carry-in other LUTs generate carry outputs chains carry select circuitry. shown Figure 2-8, carry-in signal selects either carry-in0 carry-in1 chain. selected chain's logic level turn determines which parallel generated combinational registered output. example, when implementing adder, output selection possible calculated sums: data1 data2 carry data1 data2 carry-in1 other LUTs data1 data2 signals generate possible carry-out signals: carry other carry carry-in0 signal acts carry select carry-out0 output carry-in1 acts carry select carry-out1 output. arithmetic mode drive registered unregistered versions output. dynamic arithmetic mode also offers clock enable, counter enable, synchronous up/down control, synchronous clear, synchronous load, dynamic adder/subtractor options. local interconnect data inputs generate counter enable synchronous up/down control signals. synchronous clear synchronous load options LABwide signals that affect registers LAB. Quartus software automatically places registers that used counter into other LABs. addnsub LAB-wide signal controls whether acts adder subtractor.
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Logic Elements
Figure 2-8. Dynamic Arithmetic Mode
Carry-In Carry-In0 Carry-In1 addnsub (LAB Wide) sload sclear (LAB Wide) (LAB Wide) Register chain connection aload (LAB Wide)
data1 data2 data3
ALD/PRE ADATA CLRN
Row, column, direct link routing Row, column, direct link routing
clock (LAB Wide) (LAB Wide) aclr (LAB Wide)
Local routing
chain connection Register chain output Register Feedback
Carry-Out0 Carry-Out1
Note Figure 2-8:
addnsub signal tied carry input first carry chain only.
Carry-Select Chain
carry-select chain provides very fast carry-select function between dynamic arithmetic mode. carry-select chain uses redundant carry calculation increase speed carry functions. configured calculate outputs possible carry-in carryin parallel. carry-in0 carry-in1 signals from lowerorder feed forward into higher-order parallel carry chain feed into both next portion carry chain. Carryselect chains begin within LAB. speed advantage carry-select chain parallel precomputation carry chains. Since carry-in selects precomputed carry chain, every critical path. Only propagation delays between carry-in generation part critical path. This feature allows architecture implement high-speed counters, adders, multipliers, parity functions, comparators arbitrary width.
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Architecture
Figure shows carry-select circuitry 10-bit full adder. portion generates bits using input signals appropriate carry-in bit; routed output register bypassed simple adders used accumulator functions. Another portion generates carryout bits. LAB-wide carry-in selects which chain used addition given inputs. carry-in signal each chain, carry-in0 carry-in1, selects carry-out carry forward carry-in signal next-higher-order bit. final carry-out signal routed where local, row, column interconnects.
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2-13 Device Handbook, Volume
Logic Elements
Figure 2-9. Carry Select Chain
Carry-In
Sum1
Carry-In Carry-In0 Carry-In1
Sum2
data1 data2
Sum3
Sum4
Sum5
Sum6
Carry-Out0
Carry-Out1
Sum7
Sum8
Sum9
Sum10
adjacent Carry-Out
Quartus software automatically creates carry chain logic during design processing, designer create manually during design entry. Parameterized functions such functions automatically take advantage carry chains appropriate functions. Quartus software creates carry chains longer than linking adjacent LABs within same together automatically. carry chain extend horizontally full row, they extend between rows.
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Architecture
Clear Preset Logic Control
LAB-wide signals control logic register's clear preset signals. directly supports asynchronous clear preset function. register preset achieved through asynchronous load logic high. direct asynchronous preset does require NOT-gate push-back technique. devices support simultaneous preset/asynchronous load clear signals. asynchronous clear signal takes precedence both signals asserted simultaneously. Each supports clears preset signal. addition clear preset ports, devices provide chipwide reset (DEV_CLRn) that resets registers device. option before compilation Quartus software controls this pin. This chip-wide reset overrides other control signals. Driving this signal before during power-up prevents user mode from releasing clears within design. This allows control when clear released device that just been powered-up. chip-wide reset function, DEV_CLRn regular pin.
MultiTrack Interconnect
architecture, connections between LEs, UFM, device pins provided MultiTrack interconnect structure. MultiTrack interconnect consists continuous, performanceoptimized routing lines used inter- intra-design block connectivity. Quartus Compiler automatically places critical design paths faster interconnects improve design performance. MultiTrack interconnect consists column interconnects that span fixed distances. routing structure with fixed length resources devices allows predictable short delays between logic levels instead large delays associated with global long routing lines. Dedicated interconnects route signals from LABs within same row. These resources include:
DirectLink interconnects between LABs interconnects traversing four LABs right left
DirectLink interconnect allows drive into local interconnect left right neighbors. DirectLink interconnect provides fast communication between adjacent LABs and/or blocks without using interconnect resources.
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MultiTrack Interconnect
interconnects span four LABs used fast connections four-LAB region. Every interconnects drive either left right. Figure 2-10 shows interconnect connections from LAB. interconnects drive driven IOEs. interfacing, primary horizontal neighbor drive given interconnect. interconnects that drive right, primary right neighbor drive interconnect. interconnects that drive left, primary left neighbor drive interconnect. interconnects drive other interconnects extend range LABs they drive. interconnects also drive interconnects connections from another. Figure 2-10. Interconnect Connections
Adjacent Drive onto Another LAB's Interconnect Interconnect Driving Left Column Interconnects Interconnect Driving Right
Neighbor
Primary
Neighbor
Notes Figure 2-10:
interconnects drive interconnects. This pattern repeated every row.
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Architecture
column interconnect operates similarly interconnect. Each column LABs served dedicated column interconnect, which vertically routes signals from LABs column IOEs. These column resources include:
chain interconnects within Register chain interconnects within interconnects traversing distance four LABs down direction
devices include enhanced interconnect structure within LABs routing output input connections faster using chain connections register chain connections. chain connection allows combinational output directly drive fast input right below bypassing local interconnect. These resources used high-speed connection wide fan-in functions from same LAB. register chain connection allows register output connect directly register input next fast shift registers. Quartus Compiler automatically takes advantage these resources improve utilization performance. Figure 2-11 shows chain register chain interconnects.
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MultiTrack Interconnect
Figure 2-11. Chain Register Chain Interconnects
Local Interconnect Routing Among Chain Routing Adjacent
Register Chain Routing Adjacent LE's Register Input
Local Interconnect
interconnects span four LABs down from source LAB. Every interconnects drive either down. Figure 2-12 shows interconnect connections from column. interconnects drive driven column IOEs. interconnection, primary vertical neighbor drive given interconnect. interconnects drive each other extend their range well drive interconnects column-to-column connections.
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Architecture
Figure 2-12. Interconnect Connections
Note
Interconnect Drives Local Interconnects Four Rows
Interconnect Driving
Interconnect
Adjacent drive onto neighboring LAB's interconnect
Local Interconnect
Interconnect Driving Down
Note Figure 2-12:
Each interconnect drive either down four rows.
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Global Signals
block communicates with logic array similar LAB-to-LAB interfaces. block connects column interconnects local interconnect regions driven column interconnects. This block also DirectLink interconnects fast connections from neighboring LAB. more information interface logic array, "User Flash Memory Block" page 2-23. Table shows device's routing scheme.
Table 2-2. Device Routing Scheme Source Destination Register Local DirectLink Chain Chain
Chain Register Chain Local Interconnect DirectLink Interconnect Interconnect Interconnect Block Column Note Table 2-2:
These categories interconnects.
Column Fast Block
Global Signals
Each device four dual-purpose dedicated clock pins (GCLK[3.0], pins left side pins right side) that drive global clock network clocking, shown Figure 2-13. These four pins also used general-purpose they used drive global clock network. four global clock lines global clock network drive throughout entire device. global clock network provide clocks resources within device including LEs, local interconnect, IOEs, block. global clock lines also used global
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Architecture
control signals, such clock enables, synchronous asynchronous clears, presets, output enables, protocol control signals such TRDY IRDY PCI. Internal logic drive global clock network internally- generated global clocks control signals. Figure 2-13 shows various sources that drive global clock network. Figure 2-13. Global Clock Generation
GCLK0 GCLK1 GCLK2 GCLK3 Logic Array(1)
Global Clock Network
Note Figure 2-13:
MultiTrack interconnect route logic array-generated global clock signal.
global clock network drives individual column signals, column clocks [3.0], that span entire column from bottom device. Unused global clocks control signals column turned column clock buffers shown Figure 2-14. column clocks [3.0] multiplexed down clock signals clear signal. Other control signal types route from global clock network into local interconnect. "LAB Control Signals" page more information.
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Global Signals
Figure 2-14. Global Clock Network
Block Region
Note
Column clock[3.0]
Column clock[3.0]
Block Region Block Configuration Flash Memory Block Block Region
Notes Figure 2-14:
column clocks block regions provide high fan-out output enable signals. column clocks drive block.
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Architecture
User Flash Memory Block
devices feature single block, which used like serial EEPROM storing non-volatile information 8,192 bits. block connects logic array through MultiTrack interconnect, allowing interface block. Figure 2-15 shows block interface signals. logic array used create customer interface protocol logic interface block data outside device. block offers following features:
Non-volatile storage 16-bit wide 8,192 total bits sectors partitioned sector erase Built-in internal oscillator that optionally drives logic array Program, erase, busy signals Auto-increment addressing Serial interface logic array with programmable interface
Figure 2-15. Block Interface Signals
Block
PROGRAM ERASE
Program Erase Control
RTP_BUSY BUSY
OSC_ENA
ARCLK
Sector Sector
Address Register ARSHFT
ARDin DRDin DRCLK DRSHFT Data Register DRDout
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User Flash Memory Block
Storage
Each device stores 8,192 bits data block. Table shows data size, sector, address sizes block.
Table 2-3. Array Size Device
EPM240 EPM570 EPM1270 EPM2210
Total Bits
8,192
Sectors
(4,096 bits/sector)
Address Bits
Data Width
There locations with 9-bit addressing ranging from 000h 1FFh. Sector address space 000h 0FFh Sector address space from 100h 1FFh. data width bits data. Quartus software automatically creates logic accommodate smaller read program data widths. Erasure involves individual sector erasing (i.e., erase sector erase sector required erase entire block). Since sector erase required before program write, having sectors enables sector size data left untouched while other sector erased programmed with data.
Internal Oscillator
shown Figure 2-15, dedicated circuitry within block contains oscillator. dedicated circuitry uses this internally read program operations. This oscillator's divide output driven block logic array interface logic clock source general-purpose logic clocking. output signal frequency ranges from (preliminary), exact frequency programmable.
Program, Erase Busy Signals
block's dedicated circuitry automatically generates necessary internal program erase algorithm once PROGRAM ERASE input signals have been asserted. PROGRAM ERASE signal must asserted until busy signal deasserts, indicating internal program erase operation completed. block also supports JTAG interface programming and/or reading.
more information programming erasing block, Chapter Using User Flash Memory Devices.
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Architecture
Auto-Increment Addressing
block supports standard read stream read operations. stream read supported with auto-increment address feature. Deasserting ARSHIFT signal while clocking ARCLK signal increments address register value read consecutive locations from array.
Serial Interface
block supports serial interface with serial address data signals. internal shift registers within block address data bits bits wide, respectively. Quartus software automatically generates interface logic parallel address data interface block. Other standard protocol interfaces such also automatically generated logic Quartus software.
more information interface signals Quartus LE-based alternate interfaces, Chapter Using User Flash Memory Devices.
Block Logic Array Interface
block small partition flash memory which contains configuration flash memory block shown Figures 2-2. block EPM240 device located left side device adjacent left most column. block EPM570, EPM1270, EPM2210 devices located bottom left portion device. input output signals interface types interconnects interconnect, interconnect, DirectLink interconnect to/from adjacent rows). signals also driven from global clocks, GCLK[3.0]. interface region EPM240 device shown Figure 2-16. interface regions EPM570, EPM1270, EPM2210 devices shown Figure 2-17.
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User Flash Memory Block
Figure 2-16. EPM240 Block Interface
Configuration Flash Memory Block Block
Note
PROGRAM ERASE OSC_ENA RTP_BUSY
DRDin DRCLK DRSHFT ARin ARCLK ARSHFT DRDout BUSY
Note Figure 2-16:
block inputs outputs drive to/from types interconnects, only DirectLink interconnects from adjacent LABs.
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Architecture
Figure 2-17. EPM570, EPM1270 EPM2210 Block Interface
Configuration Flash Memory Block RTP_BUSY BUSY DRDout DRDin DRDCLK DRDSHFT ARDin PROGRAM ERASE OSC_ENA ARCLK ARSHFT Block
MultiVolt Core
architecture supports MultiVoltcore feature, which allows devices support multiple levels VCCINT supply. internal voltage regulator provides necessary 1.8-V internal voltage supply device. voltage regulator supports 3.3-V 2.5-V supplies inputs supply 1.8-V internal voltage device, shown Figure 2-18. voltage regulator guaranteed voltages that between maximum recommended 2.5-V operating voltage minimum recommended 3.3-V operating voltage. external 1.8-V supplies, devices with designation ordering code required. voltage regulator these devices bypassed support 1.8-V external supply path 1.8-V internal supply. Contact Altera latest information regarding devices.
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Structure
Figure 2-18. MultiVolt Core Feature Devices
3.3-V 2.5-V VCCINT Pins
Voltage Regulator
1.8-V VCCINT Pins
1.8-V Core Voltage
1.8-V Core Voltage
Device
Device With Ordering Code
Structure
IOEs support many features, including:
LVTTL LVCMOS standards 3.3-V, 32-bit, 33-MHz compliance Joint Test Action Group (JTAG) boundary-scan test (BST) support Programmable drive strength control Weak pull-up resistors during power-up system programming Slew-rate control Tri-state buffers with individual output enable control Bus-hold circuitry Programmable pull-up resistors user mode Unique output enable Open-drain outputs Schmitt trigger inputs Fast connection
device IOEs contain bidirectional buffer. Figure 2-19 shows structure. Registers from adjacent LABs drive driven from IOE's bidirectional buffers. Quartus software automatically attempts place registers adjacent with fast connection achieve fastest possible clock-to-output registered output enable timing. input registers, Quartus software automatically routes register guarantee zero hold time. timing assignments Quartus software achieve desired timing.
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Architecture
Fast Connection
dedicated fast connection from adjacent IOEs within block provides faster output delays clock-to-output propagation delays. This connection exists data output signals, output enable signals input signals. Figures 2-20, 2-21, 2-22 illustrate fast connection. Figure 2-19. Structure
Data_in Fast_out
Data_out
DEV_OE Optional Clamp VCCIO VCCIO Programmable Pull-Up
Drive Strength Control Open-Drain Output Slew Control Optional Bus-Hold Circuit
Optional Schmitt Trigger Input
Note Figure 2-19:
Available EPM1270 EPM2210 devices only.
Blocks
IOEs located blocks around periphery device. There seven IOEs block maximum EPM240 device) four IOEs column block. Each column block interfaces with adjacent MultiTrack
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Structure
interconnect distribute signals throughout device. blocks drive row, column, DirectLink interconnects. column blocks drive column interconnects. Figure 2-20 shows block connects logic array. Figure 2-20. Block Connection Interconnect Note
Interconnects
Interconnects Block Local Interconnect
data_out [6.0]
[6.0]
fast_out [6.0]
Block
data_in[6.0]
Direct Link Interconnect Adjacent Local Interconnect
Direct Link Interconnect from Adjacent Block Contains Seven IOEs
Column clock [3.0]
Note Figure 2-20:
Each seven IOEs block have data_out fast_out output, output, data_in input.
Figure 2-21 shows column block connects logic array.
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Architecture
Figure 2-21. Column Block Connection Interconnect
Note
Column Block Contains IOEs data_in [3.0]
Column Block
data_out [3.0] Block Local Interconnect
[3.0]
fast_out [3.0]
Fast Interconnect Column Path Clock [3.0]
Interconnects
Local Interconnect Interconnects
Local Interconnect
Local Interconnect Interconnects
Note Figure 2-21:
Each four IOEs column block have data_out fast_out output, output, data_in input.
Standards Banks
device IOEs support following standards:
3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS
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Structure
1.5-V LVCMOS 3.3-V
Table describes standards supported devices.
Table 2-4. Standards Standard
3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V Note Table 2-4:
3.3-V supported Bank EPM1270 EPM2210 devices.
Type
Single-ended Single-ended Single-ended Single-ended Single-ended
Output Supply Voltage (VCCIO)
EPM240 EPM570 devices support banks, shown Figure 2-22. Each these banks support LVTTL LVCMOS standards shown Table 2-4. supported these devices banks.
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Architecture
Figure 2-22. Banks EPM240 EPM570
Notes (1),
Bank
Bank
Banks Support 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS
Notes Figure 2-22:
Figure 2-22 view silicon die. Figure 2-22 graphic representation only. Refer list Quartus software exact locations.
EPM1270 EPM2210 devices support four banks, shown Figure 2-23. Each these banks support LVTTL LVCMOS standards shown Table 2-4. supported Bank Bank supports clamping diode inputs drive compliance outputs. must Bank designs requiring compliant pins. Quartus software automatically places pins this bank assigned with standard.
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Structure
Figure 2-23. Banks EPM1270 EPM2210
Bank
Notes (1),
Banks Support 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS Bank
Also Supports 3.3-V Standard
Bank
Bank
Notes Figure 2-23:
Figure 2-23 view silicon die. Figure 2-23 graphic representation only. Refer list Quartus software exact locations.
Each bank dedicated VCCIO pins which determine voltage standard support that bank. single device support 1.5-V, 1.8-V, 2.5-V, 3.3-V interfaces; each individual bank support different standard. Each bank support multiple standards with same VCCIO input output pins. example, when VCCIO Bank support LVTTL, LVCMOS, 3.3-V PCI. VCCIO powers both input output buffers devices. JTAG pins devices dedicated pins that cannot used regular pins. pins TMS, TDI, TDO, support standards shown Table page 2-32 except PCI. These pins reside Bank devices their standard support controlled VCCIO setting Bank
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Architecture
Compliance
EPM1270 EPM2210 devices compliant with applications well 3.3-V electrical specifications Local Specification Revision 2.2. These devices also large enough support intellectual property (IP) cores. Table shows device speed grades that meet timing specifications.
Table 2-5. Devices Speed Grades that Support 3.3-V Electrical Specifications Meet Timing Note Device
EPM1270 EPM2210 Note Table 2-5:
This table contains preliminary information.
33-MHz
Speed Grades Speed Grades
Schmitt Trigger
input buffer each device optional Schmitt trigger setting 3.3-V 2.5-V standards. Schmitt trigger allows input buffers respond slow input edge rates with fast output edge rate. Most importantly, Schmitt triggers provide hysteresis input buffer, preventing slow rising noisy input signals from ringing oscillating input signal driven into logic array. This provides system noise tolerance inputs, adds small, nominal input delay. JTAG input pins (TMS, TCK, TDI) have Schmitt trigger buffers which always enabled.
Output Enable Signals
Each output buffer supports output enable signals tristate control. output enable signal originate from GCLK[3.0] global signals from MultiTrack interconnect. MultiTrack interconnect routes output enable signals allows unique output enable each output bidirectional pin.
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Structure
devices also provide chip-wide output enable (DEV_OE) control output enable every output design. option before compilation Quartus software controls this pin. this option turned outputs chip operate normally when DEV_OE asserted. When de-asserted, outputs tri-stated. this option turned off, DEV_OE disabled when device operates user mode available user pin.
Programmable Drive Strength
output buffer each device levels programmable drive strength control each LVTTL LVCMOS standards. Programmable drive strength provides system noise reduction control high performance designs. Although separate slew-rate control feature exists, using lower drive strength setting provides signal slew rate control reduce system noise signal overshoot without large delay adder associated with slew-rate control feature. Table shows possible settings standards with drive strength control. standard always with alternate setting.
Table 2-6. Programmable Drive Strength Standard
3.3-V LVTTL
Note
IOH/IOL Current Strength Setting (mA)
3.3-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
Note Table 2-6:
current strength numbers shown condition VOUT minimum, where minimum specified standard. current strength numbers shown condition VOUT maximum, where maximum specified standard. 2.5-V LVTTL/LVCMOS, condition VOUT condition VOUT
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Architecture
Slew-Rate Control
output buffer each device programmable output slew-rate control that configured noise highspeed performance. faster slew rate provides high-speed transitions high-performance systems. However, these fast transitions introduce noise transients into system. slow slew rate reduces system noise, adds nominal output delay rising falling edges. lower voltage standard (e.g., 1.8-V LVTTL) larger output delay when slow slew enabled. Each individual slewrate control, allowing designer specify slew rate pin-by-pin basis. slew-rate control affects both rising falling edges.
Open-Drain Output
devices provide optional open-drain (equivalent opencollector) output each pin. This open-drain output enables device provide system-level control signals (e.g., interrupt write enable signals) that asserted several devices. This output also provide additional wired-OR plane.
Programmable Ground Pins
Each unused devices used additional ground pin. This programmable ground feature does require associated device. Quartus software, unused pins programmable global default basis they individually assigned. Unused pins also have option being tri-stated input pins.
Hold
Each device provides optional bus-hold feature. bus-hold circuitry hold signal last-driven state. Since bus-hold feature holds last-driven state until next input signal present, external pull-up pull-down resistor necessary hold signal level when tri-stated. bus-hold circuitry also pulls undriven pins away from input threshold voltage where noise cause unintended high-frequency switching. designer select this feature individually each pin. bus-hold output will drive higher than VCCIO prevent overdriving signals. bus-hold feature enabled, device cannot programmable pull-up option.
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Structure
bus-hold circuitry uses resistor with nominal resistance (RBH) approximately pull signal level last driven state. Table 5-11 page gives specific sustaining current each VCCIO voltage level driven through this resistor overdrive current used identify next-driven input level. bus-hold circuitry only active after device fully initialized. bus-hold circuit captures value present moment user mode entered.
Programmable Pull-Up Resistor
Each device provides optional programmable pull-up resistor during user mode. designer enables this feature pin, pull-up resistor (approximately holds output VCCIO level output pin's bank.
MultiVolt Interface
architecture supports MultiVolt interface feature, which allows devices packages interface with systems different supply voltages. devices have pins internal operation (VCCINT), four sets input buffers output driver buffers (VCCIO).
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Architecture
Connect VCCIO pins either 1.5-V, 2.5-V, 3.3-V power supply, depending output requirements. output levels compatible with systems same voltage power supply (i.e., when VCCIO pins connected 1.5-V power supply, output levels compatible with 1.5-V systems). When VCCIO pins connected 3.3-V power supply, output high compatible with 3.3-V 5.0-V systems. Table summarizes MultiVolt support.
Table 2-7. MultiVolt Support VCCIO
Notes Table 2-7:
Note Output Signal
Input Signal
drive inputs higher than VCCIO less than including overshoot, disable clamping diode. However, drive 5.0-V inputs device, enable clamping diode prevent from rising above When VCCIO 1.5-V 2.5-V 3.3-V input signal feeds input pin, higher leakage current expected. When VCCIO 1.8-V, device drive 1.5-V device with 1.8-V tolerant inputs. When VCCIO 2.5-V, device drive 1.5-V 1.8-V device with 2.5-V tolerant inputs. When VCCIO 3.3-V 2.5-V input signal feeds input pin, VCCIO supply current will slightly larger than expected. devices 5.0-V tolerant with external resistor internal clamp diode EPM1270 EPM2210 devices. When VCCIO 3.3-V, device drive 1.5-V, 1.8-V, 2.5-V device with 3.3-V tolerant inputs. When VCCIO 3.3-V, device drive device with 5.0-V inputs 5.0-V CMOS inputs. case 5.0V CMOS, open-drain setting with internal clamp diode (available only EPM1270 EPM2210 devices) external resistor required.
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Structure
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Chapter JTAG In-System Programmability
MII51003-1.0
IEEE Std. 1149.1 (JTAG) Boundary Scan Support
MAX® devices provide Joint Test Action Group (JTAG) boundaryscan test (BST) circuitry that complies with IEEE Std. 1149.1-2001 specification. JTAG boundary-scan testing performed time after VCCINT VCCIO1 have been fully powered. devices also JTAG port in-system programming together with either Quartus® software hardware using Programming Object Files (.pof), JamStandard Test Programming Language (STAPL) Files (.jam) Byte-Code Files (.jbc). JTAG pins support 1.5-V, 1.8-V, 2.5-V, 3.3-V standards. supported voltage level standard determined VCCIO bank where resides. dedicated JTAG pins reside Bank devices. devices support JTAG instructions shown Table 3-1.
Table 3-1. JTAG Instructions (Part JTAG Instruction
SAMPLE/PRELOAD
Instruction Code
0000 0101
Description
Allows snapshot signals device pins captured examined during normal device operation, permits initial data pattern output device pins. Allows external circuitry board-level interconnects tested forcing test pattern output pins capturing test results input pins. Places 1-bit bypass register between pins, which allows boundary scan test data pass synchronously through selected devices adjacent devices during normal device operation. Selects 32-bit USERCODE register places between pins, allowing USERCODE serially shifted TDO. This register defaults specified Quartus software. Selects IDCODE register places between TDO, allowing IDCODE serially shifted TDO. Places 1-bit bypass register between pins, which allows boundary scan test data pass synchronously through selected devices adjacent devices during normal device operation, while tri-stating pins.
EXTEST
0000 1111
BYPASS
1111 1111
USERCODE
0000 0111
IDCODE HIGHZ
0000 0110 0000 1011
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IEEE Std. 1149.1 (JTAG) Boundary Scan Support
Table 3-1. JTAG Instructions (Part JTAG Instruction
CLAMP
Instruction Code
0000 1010
Description
Places 1-bit bypass register between pins, which allows boundary scan test data pass synchronously through selected devices adjacent devices during normal device operation, while holding pins state defined data boundary-scan register. This instruction allows user define their scan chain between logic array. This instruction also used custom logic JTAG interfaces. This instruction allows user define their scan chain between logic array. This instruction also used custom logic JTAG interfaces. IEEE 1532 instructions used when programming device JTAG port.
USER0
0000 1100
USER1
0000 1110
IEEE 1532 instructions
Notes Table 3-1:
HIGHZ, CLAMP, EXTEST instructions disable weak pull-up resistors hold features. These instructions shown 1532 BSDL files, which will posted Altera® site www.altera.com when they available.
device instruction register length bits USERCODE register length bits. Tables show boundary-scan register length device IDCODE information devices.
Table 3-2. Boundary-Scan Register Length Device
EPM240 EPM570 EPM1270 EPM2210
Boundary-Scan Register Length
Table 3-3. 32-Bit Device IDCODE Binary IDCODE Bits) Device
EPM240 EPM570 EPM1270
Version Bits)
0000 0000 0000
Part Number
0010 0000 1010 0001 0010 0000 1010 0010 0010 0000 1010 0011
Manufacturer Identity Bits)
0110 1110 0110 1110 0110 1110
Bit)
IDCODE
0x020A10DD 0x020A20DD 0x020A30DD
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JTAG In-System Programmability
Table 3-3. 32-Bit Device IDCODE Binary IDCODE Bits) Device
EPM2210
Version Bits)
0000
Part Number
0010 0000 1010 0100
Manufacturer Identity Bits)
0110 1110
Bit)
IDCODE
0x020A40DD
Notes Table 3-2:
most significant (MSB) left. IDCODE's least significant (LSB) always
JTAG characteristics, refer Chapter Switching Characteristics. more information JTAG BST, Chapter IEEE 1149.1 (JTAG) Boundary-Scan Testing Devices.
JTAG Translator
JTAG translator feature allows access JTAG state signals when either USER0 USER1 instruction issued JTAG TAP. USER0 USER1 instructions bring JTAG boundary scan chain (TDI) through user logic instead device's boundary scan cells. Each USER instruction allows unique userdefined JTAG chain into logic array.
General-Purpose Flash Loader
JTAG translator ability interface JTAG non-JTAG devices ideal general-purpose flash memory devices (such Intel Fujitsu based devices) that require programming during in-circuit test. flash memory devices used FPGA configuration part system memory. many cases, device already connected these devices configuration control logic between FPGA flash device. Unlike ISP-capable CPLD devices, bulk flash devices have JTAG pins connections. small flash devices, common serial JTAG scan chain connected device program nonJTAG flash device. This slow inefficient most cases impractical large parallel flash devices. Using device's JTAG translator general-purpose flash loader program verify flash contents provides fast cost-effective means in-circuit programming during test. Figure shows being used general-purpose flash loader.
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System Programmability
Figure 3-1. JTAG Translator General-Purpose Flash Loader
Device Flash Memory Device DQ[7.0] A[20.0] RY/BY TDO_U TDI_U TMS_U TCK_U SHIFT_U CLKDR_U UPDATE_U RUNIDLE_U USER1_U DQ[7.0] A[20.0] RY/BY GeneralPurpose Flash Loader Logic (1),
Notes Figure 3-1:
This block implemented LEs. This function will supported future version Quartus software.
System Programmability
devices programmed in-system industry standard 4-pin IEEE Std. 1149.1 (JTAG) interface. system programmability (ISP) offers quick, efficient iterations during design development debugging cycles. logic, circuitry, interconnects architecture configured with flash-based SRAM configuration elements. These SRAM elements require configuration data loaded each time device powered. process loading SRAM data called configuration. on-chip configuration flash memory block stores SRAM element's configuration data. configuration flash memory block stores design's configuration pattern reprogrammable flash array. During ISP, JTAG circuitry programs design pattern into configuration flash memory block's non-volatile flash array. JTAG controller internally generate high programming voltages required program configuration flash memory cells, allowing in-system programming with recommended operating external voltage supplies (i.e., V/2.5 performed anytime after VCCINT VCCIO bank have been fully powered device completed configuration
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power-up time. During in-system programming, pins tristated weakly pulled-up VCCIO eliminate board conflicts. pull-up value ranges from These devices also offer ISP_DONE that provides safe operation when in-system programming interrupted. This ISP_DONE bit, which last programmed, prevents pins from driving until programmed.
IEEE 1532 Support
JTAG circuitry instruction devices compliant IEEE 1532-2002 programming specification. This provides industry-standard hardware software in-system programming among multiple vendor programmable logic devices (PLDs) JTAG chain. 1532 BSDL files will released Altera site when available.
Standard Test Programming Language (STAPL)
STAPL JEDEC standard, JESD71, used program devices with in-circuit testers, PCs, embedded processors. byte code also supported devices. These software programming protocols provide compact embedded solution programming devices.
more information, Chapter Using STAPL Embedded Processor.
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Programming Sequence
During in-system programming, 1532 instructions, addresses, data shifted into device through input pin. Data shifted through output compared against expected data. Programming pattern into device requires following steps. stand-alone verification programmed pattern involves only stages These steps automatically executed third-party programmers, Quartus® software, STAPL Byte-Code Players. Enter enter stage ensures that pins transition smoothly from user mode mode. Check Before program verify process, silicon checked. time required read this silicon relatively small compared overall programming time. Bulk Erase Erasing device in-system involves shifting instruction erase device applying erase pulse(s). erase pulse automatically generated internally waiting run/test/idle state specified erase pulse time Program Programming device in-system involves shifting address, data, program instruction generating program pulse program flash cells. program pulse automatically generated internally waiting run/test/idle state specified program pulse time This process repeated each address configuration flash memory block. Verify Verifying device in-system involves shifting addresses, applying verify instruction generate read pulse, shifting data comparison. This process repeated each configuration flash memory address. Exit exit stage ensures that pins transition smoothly from mode user mode.
frequencies MHz, erase programming takes less than second EPM240 EPM570 devices. Erase programming times less than seconds EPM1270 less than three seconds EPM2210 devices. frequency operate devices providing slight improvements these times.
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Programming
Quartus software, with POF, Jam, files, supports programming each user flash memory (UFM) block sector independent from logic array design pattern stored configuration flash memory block. This allows updating reading contents through without altering current logic array design, vice versa. default, these programming files methods will program both entire flash memory contents, which includes configuration flash memory block contents. stand-alone embedded STAPL player Byte-Code Player provides action commands programming reading entire flash memory (UFM configuration flash memory together each independently).
more information, Chapter Using STAPL Embedded Processor.
Real-Time
real-time feature allows program configuration flash memory block using with information while current design operates SRAM logic array pins. After configuration flash memory block configured SRAM-based logic array pins power-up, configuration flash memory block ready programming file update. With real-time ISP, programming file updated into device without halting original design's operation, saving down-time costs remote field upgrades. updated configuration flash memory block configures design into SRAM upon next power cycle. also possible execute immediate configuration SRAM without power cycle using specific sequence commands. configuration SRAM without power cycle takes specific amount time (tCONFIG). During this time, pins tri-stated weakly pulled-up VCCIO. Quartus software, STAPL player, Byte-Code Player provides designer with option control real-time used) allows designer control timeline design configuration into SRAM (immediately upon next power cycle).
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Design Security
devices contain programmable security that controls access data programmed into configuration flash memory block. When this programmed, design programming information, stored configuration flash memory block, cannot copied retrieved. This feature provides high level design security because programmed data within flash memory cells invisible. security that controls this function, well other programmed data, reset only when device erased. SRAM also invisible cannot accessed regardless security setting. block data protected security accessible through JTAG logic array connections.
Programming with External Hardware
devices programmed downloading information in-circuit testers, embedded processors, Altera® ByteblasterMVTM, MasterBlasterTM, ByteBlasteTMr USB-Blaster cables, through universal serial (USB)-based Altera Programming Unit (APU) with appropriate adapter. Microsystems, System General, other programming hardware manufacturers provide programming support Altera devices. Check their sites device support information.
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Chapter Socketing Power-On Reset Devices
MII51004-1.0
Socketing
MAX® devices offer socketing, also known plug-in swap, power sequencing support. Designers insert remove board system during operation without undesirable effects system bus. socketing feature removes some difficulty designers face when using components printed circuit boards (PCBs) that contain mixture 3.3-, 2.5-, 1.8-, 1.5-V devices. device socketing feature provides:
Board device insertion removal Support power-up sequence Non-intrusive buffers system buses during insertion
Hot-Socketing Specifications
devices offer three features required socketing capability listed above without external components special design requirements. following hot-socketing specifications:
device driven before during power-up powerdown without damage device itself. pins remain tri-stated during power-up. device does drive before during power-up, thereby affecting other buses operation. Signal pins drive VCCIO VCCINT power supplies. External input signals pins device internally power VCCIO VCCINT power supplies device internal paths.
Devices Driven before Power-Up
Signals driven into device pins GCLK[3.0] pins before during power-up power-down without damaging device. devices support power-up power-down sequence (VCCIO1, VCCIO2, VCCIO3, VCCIO4, VCCINT), simplifying system-level design.
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Socketing
Pins Remain Tri-Stated during Power-Up
device that does support hot-socketing interrupt system operation cause contention driving before during power-up. socketing situation, device's output buffers turned during system power-up. devices drive until device attains proper operating conditions fully configured. "Power-On Reset Circuitry" page information about turn-on voltages.
Signal Pins Drive VCCIO VCCINT Power Supplies
devices have current path from pins GCLK[3.0] pins VCCIO VCCINT pins before during power-up. device inserted into removed from) system board that powered without damaging interfering with system-board operation. When socketing, devices have minimal effect signal integrity backplane.
Specifications
power power down VCCIO VCCINT pins sequence. There ramp rate requirements devices. During socketing, capacitance less than devices meet following socketing specification:
socketing specification IIOPIN socketing specification dependent signal voltages board capacitance: IIOPIN (v/t) capacitance where capacitance pin, trace, connector capacitance. devices immune latch-up when socketing.
Socketing Feature Implementation Devices
socketing feature turns (tri-states) output buffer during power-up event (either VCCINT VCCIO supplies) power down. hot-socket circuit generates internal HOTSCKT signal when either VCCINT VCCIO below threshold voltage. HOTSCKT signal cuts output buffer make sure that current (except weak pull-up leaking) leaks through pin. When ramps very slowly, still relatively even after power-on reset (POR) signal released device configuration complete.
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Each clock following circuitry, shown Figure 4-1. Figure 4-1. Socketing Circuit Block Diagram Devices
Power Reset Monitor
VCCIO
Weak Pull-Up Resistor
Output Enable
Voltage Tolerance Control
Socket
Input Buffer Logic Array
circuit monitors VCCINT VCCIO voltage levels keeps pins tri-stated until device completed flash memory configuration SRAM logic. weak pull-up resistor from VCCIO present keep pins from floating. 3.3-V tolerance control circuit permits pins driven before VCCIO and/or VCCINT powered, prevents pins from driving when device fully powered operational. hotsocket circuit prevents pins from internally powering VCCIO VCCINT when driven external signals before device powered.
information 5.0-V tolerance, Chapter Using Devices Multi-Voltage Systems. Figure shows transistor level cross section device buffers. This design ensures that output buffers drive when VCCIO powered before VCCINT voltage higher than VCCIO. This also applies sudden voltage spikes during insertion. VPAD leakage current charges 3.3-V tolerant circuit capacitance.
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Figure 4-2. Transistor-Level Diagram Device Buffers
VPAD Signal Larger VCCIO VPAD VCCIO Larger VCCIO VPAD Ensures 3.0-V Tolerance Hot-Socket Protection
Signal
well
well
substrate
CMOS output drivers pins intrinsically provide electrostatic discharge (ESD) protection. There cases consider voltage strikes: positive voltage negative voltage zap. positive voltage occurs when positive voltage present charge event. This cause (Drain)/PSubstrate junction N-channel drain break down (Drain)/P-Substrate/N+ (Source) intrinsic bipolar transistor turns discharge current from GND. dashed line (see Figure 4-3) shows current discharge path during positive zap.
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Figure 4-3. Protection During Positive Voltage
Source
PMOS
Gate
Drain Drain P-Substrate
NMOS
Gate
Source
When receives negative that less than -0.7 (0.7 voltage drop across diode), intrinsic P-Substrate/N+ drain diode forward biased. Hence, discharge current path from pin, shown Figure 4-4.
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Figure 4-4. Protection During Negative Voltage
Source
PMOS
Gate
Drain Drain P-Substrate
NMOS
Gate
Source
Power-On Reset Circuitry
devices have circuits VCCINT VCCIO voltage levels during power-up. circuit monitors these voltages triggering download from non-volatile configuration flash memory block SRAM logic maintaining tri-state pins before during this process. When device enters user mode, circuit releases pins user functionality continues monitor VCCINT voltage level detect brown-out condition. there VCCINT voltage below operational level during user mode, circuit resets device re-triggers SRAM download. bank VCCIO levels monitored after initial power-up transition into user mode functionality.
Power-Up Characteristics
When power applied device, circuit monitors VCCINT begins SRAM download maximum voltage 2.375 1.71 devices with ordering code. From this voltage reference, SRAM download entry into user mode takes maximum depending device density. Entry into user mode gated whether VCCIO banks powered with sufficient operating voltage. VCCINT VCCIO powered simultaneously, device enters user mode within specifications. VCCIO powered more
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than after VCCINT, device does enter user mode until after VCCIO pins powered. Figure shows device behavior during power-up. Figure 4-5. Power-Up Characteristics Devices
VCCINT
2.375
Note
CONFIG
Tri-State
User Mode Operation
Tri-State
Notes Figure 4-5:
Figure assumes VCCIO banks power simultaneously with VCCINT profile shown. not, tCONFIG stretches until VCCIO banks powered. Voltages tCONFIG begin user mode operation exit maximum numbers. device still operational brown-out conditions down does meet specifications which defined recommended operating condition ranges VCCINT VCCIO.
After SRAM configuration, registers device cleared released into user function before tri-states released. release clears after tri-states released, DEV_CLRn option. hold tri-states beyond power-up configuration time, DEV_OE option.
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Chapter Switching Characteristics
MII51005-1.0
Operating Conditions
Tables through 5-13 provide information absolute maximum ratings, recommended operating conditions, electrical characteristics, other specifications MAX® devices.
Absolute Maximum Ratings
Table shows absolute maximum ratings device family.
Table 5-1. Device Absolute Maximum Ratings Symbol
VCCINT VCCIO IOUT TSTG TAMB
Notes (1), Minimum
-0.5 -0.5 -2.0
Parameter
Conditions
Maximum
Unit
Internal Supply voltage With respect ground Supply Voltage input voltage output current, Storage temperature Ambient temperature Junction temperature bias Under bias TQFP packages under bias
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Operating Conditions
Recommended Operating Conditions
Table shows device family recommended operating conditions.
Table 5-2. Device Recommended Operating Conditions (Part Symbol
VCCINT
Parameter
3.3-V supply voltage internal logic 2.5-V supply voltage internal logic 1.8-V supply voltage internal logic (MAX devices with ordering code)
Conditions
Minimum
3.00
Maximum
3.60
Unit
2.375
2.625
1.71
1.89
VCCIO
Supply voltage buffers, 3.3-V operation Supply voltage buffers, 2.5-V operation Supply voltage buffers, 1.8-V operation Supply voltage buffers, 1.5-V operation
3.00
3.60
2.375
2.625
1.71
1.89
1.425
1.575
Input voltage Output voltage Operating junction temperature
(4), (5),
-0.5
VCCIO
commercial industrial
Input rise time Input fall time
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Table 5-2. Device Recommended Operating Conditions (Part Symbol
tRSCHMITT tFSCHMITT
Parameter
Schmitt trigger input rise time Schmitt trigger input fall time
Conditions
Minimum
Maximum
Unit
Programming/Erasure Specifications
Table shows device family programming/erasure specifications.
Table 5-3. Device Programming/Erasure Specifications Parameter
Erase reprogram cycles
Minimum
Typical
Maximum
Unit
Cycles
Electrical Characteristics
Table shows device family electrical characteristics.
Table 5-4. Device Electrical Characteristics (Part Symbol
ICCSTANDBY
Note Typical Maximum
Parameter
Conditions
Minimum
Unit
Input leakage VCCIOmax (10) current Tri-stated leakage current VCCIOmax (10)
supply devices current (standby) Devices with (11) ordering code Hysteresis Schmitt trigger input Value pull-up resistor during power-up in-system programming VCCIO VCCIO VCCIO (12) VCCIO (12) VCCIO (12) VCCIO (12)
VSCHMITT
RPULLUP
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Table 5-4. Device Electrical Characteristics (Part Symbol
Note Typical Maximum
Parameter
Input capacitance user Input capacitance dual-purpose GCLK/user
Conditions
Minimum
Unit
CGCLK
Standard Specifications
Tables through 5-10 show device family standard specifications.
Table 5-5. 3.3-V LVTTL Specifications Symbol
VCCIO
Parameter
supply voltage High-level input voltage Low-level input voltage
Conditions
Minimum
-0.5
Maximum
Unit
High-level output (13) voltage Low-level output voltage (13)
0.45
Table 5-6. 3.3-V LVCMOS Specifications (Part Symbol
VCCIO
Parameter
supply voltage High-level input voltage Low-level input voltage
Conditions
Minimum
-0.5
Maximum
Unit
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Table 5-6. 3.3-V LVCMOS Specifications (Part Symbol
Parameter
Conditions
Minimum
VCCIO
Maximum
Unit
High-level output VCCIO 3.0, voltage -0.1 Low-level output voltage VCCIO 3.0,
Table 5-7. 2.5-V Specifications Symbol
VCCIO
Parameter
supply voltage High-level input voltage Low-level input voltage
Conditions
Minimum
2.375 -0.5
Maximum
2.625
Unit
High-level output -0.1 voltage (13)
Low-level output voltage
(13)
Table 5-8. 1.8-V Specifications Symbol
VCCIO
Parameter
supply voltage High-level input voltage Low-level input voltage
Conditions
Minimum
1.71 0.65 VCCIO -0.3 VCCIO 0.45
Maximum
1.89 2.25 0.35 VCCIO
Unit
High-level output (13) voltage Low-level output voltage (13)
0.45
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Table 5-9. 1.5-V Specifications Symbol
VCCIO
Parameter
supply voltage High-level input voltage Low-level input voltage
Conditions
Minimum
1.425 0.65 VCCIO -0.3 0.75 VCCIO
Maximum
1.575 VCCIO 0.35 VCCIO
Unit
High-level output (13) voltage Low-level output voltage (13)
0.25 VCCIO
Table 5-10. 3.3-V Specifications Symbol
VCCIO
Parameter
supply voltage High-level input voltage Low-level input voltage
Conditions
Minimum
VCCIO -0.5 VCCIO
Typical
Maximum
VCCIO VCCIO
Unit
High-level -500 output voltage Low-level output voltage
VCCIO
Hold Specifications
Table 5-11 shows device family hold specifications.
Table 5-11. Hold Specifications (Part VCCIO Level Parameter Conditions
sustaining current High sustaining current (maximum) (minimum)
Unit
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Table 5-11. Hold Specifications (Part VCCIO Level Parameter Conditions
overdrive current High overdrive current VCCIO VCCIO
-200
-300
-500
Unit
-160
Power-Up Timing
Table 5-12 shows power-up timing characteristics devices.
Table 5-12. Power-Up Timing Symbol
tCONFIG
Note (14) Device
EPM240 EPM570 EPM1270 EPM2210
Parameter
amount time from when VCCINT reaches 2.375 until device enters user mode (15)
Unit
JTAG Timing Specifications
Figure shows timing waveforms JTAG signals.
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Figure 5-1. JTAG Timing Waveforms
tJPZX tJSSU Signal Captured Signal Driven tJSH JPCO JPXZ JPSU
tJSZX
tJSCO
tJSXZ
Table 5-13 shows JTAG Timing parameters values devices.
Table 5-13. JTAG Timing Parameters (Part Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX
Parameter
clock period clock high time clock time JTAG port setup time JTAG port hold time JTAG port clock output JTAG port high impedance valid output JTAG port valid output high impedance Capture register setup time Capture register hold time
Unit
tJPXZ
tJSSU tJSH
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Table 5-13. JTAG Timing Parameters (Part Symbol
tJSCO tJSZX
Parameter
Update register clock output Update register high impedance valid output Update register valid output high impedance
Unit
tJSXZ
Notes Tables through 5-13:
Operating Requirements Altera Devices Data Sheet. Conditions beyond those listed Table cause permanent damage device. Additionally, device operation absolute maximum ratings extended periods time have adverse affects device. Maximum VCCINT devices devices with ordering code, Minimum input -0.5 During transitions, inputs undershoot -2.0 input currents less than periods shorter than During transitions, inputs overshoot voltages shown following table based upon input duty cycle. case equivalent 100% duty cycle. more information 5.0-V tolerance refer Chapter Using Devices Multi-Voltage Systems. Max. Duty Cycle 100% (DC) pins, including clock, I/O, JTAG pins, driven before VCCINT VCCIO powered. Contact Altera Applications more information. This specification applies user flash memory (UFM) configuration flash memory blocks (CFM). Typical values VCCINT VCCIO This value specified normal device operation. value vary during power-up. This applies VCCIO settings (3.3, 2.5, 1.8, ground, load, toggling inputs. pull-up resistance values will lower external source drives higher than VCCIO. Drive strength programmable according values Table 2-6. These numbers preliminary. more information trigger voltage, refer Chapter Socketing Power-On Reset Devices.
(10) (11) (12) (13) (14) (15)
Power Consumption
Designers Altera® power calculator estimate device power. Chapter Understanding Evaluating Power Devices more information.
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Timing Model Specifications
devices timing analyzed with Altera Quartus software, variety popular industry-standard simulators timing analyzers, with timing model shown Figures through 5-3. Figure shows timing model devices. devices have predictable internal delays that enable designer determine worst-case timing design. software provides timing simulation, point-to-point delay prediction, detailed timing analysis device-wide performance evaluation.
Figure 5-2. Device Timing Model
Output Output Enable Data Delay
Data-In/LUT Chain User Flash Memory Input Routing Delay Logic Element
Delay
tIODR tIOE
Output Routing Delay
Input Delay
LOCAL
Register Control Delay
tPRE tCLR
FASTIO
Output Delay
INPUT
GLOB Global Input Delay
Adjacent Register Delays
From Adjacent
Data-Out
timing characteristics signal path derived from timing model parameters particular device. External timing parameters, which represent pin-to-pin timing delays, calculated internal parameters. Refer Chapter Understanding Timing Devices more information. This section describes specifies performance, internal, external, timing specifications. specifications representative worst-case supply voltage junction temperature conditions.
Preliminary Final Timing
Timing models have either preliminary final status. Quartus® software issues informational message during design compilation timing models preliminary. Table 5-14 shows status device timing models.
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Preliminary status means timing model subject change. Initially, timing numbers created using simulation results, process data, other known parameters. These tests used make preliminary numbers close actual timing parameters possible. Final timing numbers based actual device operation testing. These numbers reflect actual performance device under worstcase voltage junction temperature conditions.
Table 5-14. Device Timing Model Status Device
EPM240 EPM570 EPM1270 EPM2210
Preliminary
Final
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Performance
Table 5-15 shows device performance some common designs. performance values were obtained with Quartus software compilation megafunctions. These performance values based EPM1270 device target.
Table 5-15. Device Performance Resource Used
Design Size Function
16-bit counter 64-bit counter multiplexer multiplexer 16-bit function 16-bit decoder with single address line
Resources Used Mode
Performance Speed Grade
154.0
Blocks
Speed Grade
265.5 118.6
Speed Grade
215.6 96.4 11.6
Unit
None Parallel
10.0
10.0
10.0
Notes Table 5-15:
This design binary loadable counter. This design configured read-only operation. Read write ability increases number used. This design asynchronous.
Internal Timing Parameters
Internal timing parameters specified speed grade basis independent device density. Tables 5-16 through 5-23 describe device internal timing microparameters logic elements (LEs), input/output elements (IOEs), structures, MultiTrackinterconnects.
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more explanations descriptions each internal timing microparameters symbol, refer Chapter Understanding Timing Devices.
Table 5-16. Internal Timing Microparameters Speed Grade
tLUT tCLR tPRE tCLKHL combinational delay register clear delay register preset delay register setup time before clock register hold time after clock register clock-tooutput delay Minimum clock high time Register control delay
Symbol
Parameter
Speed Grade
Speed Grade
Unit
Table 5-17. Internal Timing Microparameters (Part Speed Grade
tFASTIO tGLOB Data output delay from adjacent Block input buffer delay input buffer delay global signal Internally generated output enable delay Input routing delay Output delay buffer delay
Symbol
Parameter
Speed Grade
Speed Grade
Unit
tIOE
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Table 5-17. Internal Timing Microparameters (Part Speed Grade
Output buffer disable delay Output buffer enable delay
Symbol
Parameter
Speed Grade
Speed Grade
Unit
Tables 5-18 through 5-21 show adder delays microparameters when using standard other than 3.3-V LVTTL with drive strength. These values should added microparameters, shown Table 5-17.
Table 5-18. Microparameter Adders Fast Slew Rate Speed Grade Standard
3.3-V LVTTL 3.3-V LVCMOS 3.3-V 2.5-V LVTTL 2.5-V LVCMOS 1.8-V LVTTL 1.8-V LVCMOS 1.5-V LVCMOS
Speed Grade
Speed Grade Unit
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Table 5-19. Microparameter Adders Slow Slew Rate Speed Grade Standard
3.3-V LVTTL 3.3-V LVCMOS 3.3-V 2.5-V LVTTL 2.5-V LVCMOS
Speed Grade
Speed Grade Unit
Table 5-20. Microparameter Adders Fast Slew Rate Speed Grade Standard
3.3-V LVTTL 3.3-V LVCMOS 3.3-V 2.5-V LVTTL 2.5-V LVCMOS 1.8-V LVTTL 1.8-V LVCMOS 1.5-V LVCMOS
Speed Grade
Speed Grade Unit
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Table 5-21. MIcroparameter Adders Slow Slew Rate Speed Grade Standard
3.3-V LVTTL 3.3-V LVCMOS 3.3-V 2.5-V LVTTL 2.5-V LVCMOS
Speed Grade
Speed Grade Unit
Table 5-22. Block Internal Timing Microparameters (Part Speed Grade Speed Grade Speed Grade Symbol
tACLK
Parameter
Maximum allowed address register clock frequency Address register shift signal setup address register clock Address register shift signal hold address register clock Address register data setup address register clock Address register data hold from address register clock Maximum allowed data register clock frequency Data register shift signal setup data register clock Data register shift signal hold from data register clock
Unit
tASU
tADS
tADH
tDCLK tDSS
tDSH
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Table 5-22. Block Internal Timing Microparameters (Part Speed Grade Speed Grade Speed Grade Symbol
tDDS
Parameter
Data register data setup data register clock Data register data hold from data register clock Program signal data clock hold time Maximum delay between Program rising edge busy signal rising edge Minimum delay allowed from busy signal going program signal going Maximum length busy pulse during program Minimum erase signal address clock hold time Maximum delay between erase rising edge busy signal rising edge Minimum delay allowed from busy signal going erase signal going Maximum length Busy pulse during Erase Maximum read access time Delay from data register clock data register output Delay from oscillator enable signal
Unit
tDDH
tPPMX
tEPMX
tDCO tCDO
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Timing Model Specifications
Figures through show read, program, erase waveforms block timing parameters shown Table 5-23. Figure 5-3. Read Waveforms
ARShft ARClk ARDin DRShft DRClk DRDin DRDout Program Erase Busy Address Bits Load from Data Bits tDCO tADS tDSS tDCLK tDSH tASU tACLK tADH
Figure 5-4. Program Waveforms
ARShft ARClk ARDin DRShft DRClk DRDin DRDout Program Erase Busy Address Bits Data Bits
Program Pulse
tASU
tACLK
tADH
tADS tDSS
tDCLK
tDSH
tDDS
tDDH
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Figure 5-5. Erase Waveforms
ARShft ARClk ARDin DRShft DRClk DRDin DRDout Program Erase Busy Address Bits Erase Pulse tADS tASU tACLK tADH
Table 5-23. Routing Delay Internal Timing Microparameters Speed Grade Speed Grade Speed Grade Symbol
tLOCAL
Parameter
Column interconnect delay interconnect delay Local interconnect delay
Unit
Note Tables 5-16 through 5-23:
Contact Altera Applications more information.
External Timing Parameters
External timing parameters specified device density speed grade. external timing parameters shown 3.3-V LVTTL standard with maximum drive strength fast slew rate. external timing using standards other than LVTTL different current strengths, standard input output delay adders Tables 5-28 through 5-30.
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Timing Model Specifications
Table 5-24 shows external timing parameters EPM240 devices.
Table 5-24. EPM240 Global Clock External Timing Parameters Speed Grade Speed Grade Speed Grade Symbol
tPD1
Parameter
Worst case delay through lookup table (LUT) Best case delay through Global clock setup time Global clock hold time Global clock output delay Global clock high time Global clock time Minimum global clock period 16-bit counter Maximum global clock frequency 16-bit counter
Conditions
Unit
tPD2
tCNT
fCNT
304.0
265.5
215.6
Note Table 5-24:
maximum frequency limited standard clock input pin. 16-bit counter internal critical delay runs faster than this number.
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Table 5-25 shows external timing parameters EPM570 devices.
Table 5-25. EPM570 Global Clock External Timing Parameters Speed Grade Speed Grade Speed Grade Symbol
tPD1
Parameter
Worst case delay through Best case delay through Global clock setup time Global clock hold time Global clock output delay Global clock high time Global clock time Minimum global clock period 16-bit counter Maximum global clock frequency 16-bit counter
Conditions
10pF
Unit
tPD2
10pF
tCNT
10pF
fCNT
304.0
265.5
215.6
Note Table 5-25:
maximum frequency limited standard clock input pin. 16-bit counter internal critical delay runs faster than this number.
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Timing Model Specifications
Table 5-26 shows external timing parameters EPM1270 devices
Table 5-26. EPM1270 Global Clock External Timing Parameters Speed Grade Speed Grade Speed Grade Symbol
tPD1
Parameter
Worst case delay through Best case delay through Global clock setup time Global clock hold time Global clock output delay Global clock high time Global clock time Minimum global clock period 16-bit counter Maximum global clock frequency 16-bit counter
Conditions
10pF
Unit
tPD2
10pF
tCNT
10pF
fCNT
304.0
265.5
215.6
Note Table 5-26:
maximum frequency limited standard clock input pin. 16-bit counter internal critical delay runs faster than this number.
5-22 Device Handbook, Volume
Core Version a.b.c variable
Altera Corporation March 2004
Switching Characteristics
Table 5-27 shows external timing parameters EPM2210 devices.
Table 5-27. EPM2210 Global Clock External Timing Parameters Speed Grade Speed Grade Speed Grade Symbol
tPD1
Parameter
Worst case delay through Best case delay through Global clock setup time Global clock hold time Global clock output delay Global clock high time Global clock time Minimum global clock period 16-bit counter Maximum global clock frequency 16-bit counter
Conditions
10pF
Unit
10.5
tPD2
10pF
tCNT
10pF
fCNT
304.0
265.5
215.6
Note Table 5-27:
maximum frequency limited standard clock input pin. 16-bit counter internal critical delay runs faster than this number.
External Timing Delay Adders
delay timing parameters standard input output adders input delays specified speed grade independent device density.
Altera Corporation March 2004
Core Version a.b.c variable
5-23 Device Handbook, Volume
Timing Model Specifications
Tables 5-28 through 5-30 show adder delays associated with pins packages. standard selected other than LVTTL with unit value fast slew rate, selected input delay adder external timing parameters shown Tables 5-24 through 5-27. output delay adder external shown Tables 5-24 through 5-27.
Table 5-28. External Timing Input Delay Adders (Part Speed Grade Standard
3.3-V LVTTL Without Schmitt Trigger With Schmitt Trigger 3.3-V LVCMOS Without Schmitt Trigger With Schmitt Trigger 3.3-V Without Schmitt Trigger With Schmitt Trigger 2.5-V LVTTL Without Schmitt Trigger With Schmitt Trigger 2.5-V LVCMOS Without Schmitt Trigger With Schmitt Trigger 1.8-V LVTTL Without Schmitt Trigger
Speed Grade
Speed Grade Unit
5-24 Device Handbook, Volume
Core Version a.b.c variable
Altera Corporation March 2004
Switching Characteristics
Table 5-28. External Timing Input Delay Adders (Part Speed Grade Standard
1.8-V LVCMOS 1.5-V LVCMOS Without Schmitt Trigger Without Schmitt Trigger
Speed Grade
Speed Grade Unit
Table 5-29. External Timing Output Delay Adders Fast Slew Rate Speed Grade Standard
3.3-V LVTTL 3.3-V LVCMOS 3.3-V 2.5-V LVTTL 2.5-V LVCMOS 1.8-V LVTTL 1.8-V LVCMOS 1.5-V LVCMOS
Speed Grade
Speed Grade Unit
Table 5-30. External Timing Output Delay Adders Slow Slew Rate (Part Speed Grade Standard
3.3-V LVTTL
Speed Grade
Speed Grade Unit
Altera Corporation March 2004
Core Version a.b.c variable
5-25 Device Handbook, Volume
Timing Model Specifications
Table 5-30. External Timing Output Delay Adders Slow Slew Rate (Part Speed Grade Standard
3.3-V LVCMOS 3.3-V 2.5-V LVTTL 2.5-V LVCMOS
Speed Grade
Speed Grade Unit
Note Tables 5-28 through 5-30:
Contact Altera Applications more information.
Maximum Input Output Clock Rates
Tables 5-31 5-32 show maximum input output clock rates standa
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