MII51001-1.0 MAX® family instant-on, non-volatile CPLDs based 0.1

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MII51001-1.0 MAX® family instant-on, non-volatile CPLDs based 0.1

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Chapter
MII51001-1.0
MAX® family instant-on, non-volatile CPLDs based 0.18-µm, 6-layer-metal-flash process, with densities from 2,210 logic elements (LEs) (128 2,210 equivalent macrocells) non-volatile storage Kbits. devices offer high counts, fast performance, reliable fitting versus other CPLD architectures. Featuring MultiVoltcore, user flash memory (UFM) block, enhanced in-system programmability (ISP), devices designed reduce cost power while providing programmable solutions applications such bridging, expansion, power-on reset (POR) sequencing control, device configuration control. following shows main sections CPLD Family Data Sheet: Section Page
Features Functional Description Logic Array Blocks. Logic Elements MultiTrack Interconnect 2-15 Global Signals 2-20 User Flash Memory Block. 2-23 MultiVolt Core 2-27 Structure 2-28 IEEE Std. 1149.1 (JTAG) Boundary Scan Support System Programmability Socketing Power-On Reset Circuitry. Operating Conditions Power Consumption Timing Model Specifications 5-10 Device Pin-Outs Ordering Information
Altera Corporation March 2004
Core Version a.b.c variable
Preliminary
Features
Features
Low-cost, low-power CPLD Instant-on, non-volatile architecture Standby current Provides fast propagation delay clock-to-output times Provides four global clocks with clocks available logic array block (LAB) block Kbits non-volatile storage MultiVolt core enabling external supply voltages device either V/2.5 MultiVolt interface supporting 3.3-V, 2.5-V, 1.8-V, 1.5-V logic levels Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, programmable pull-up resistors Schmitt triggers enabling noise tolerant inputs (programmable pin) Fully compliant with Peripheral Component Interconnect Special Interest Group (PCI SIG) Local Specification, Revision 3.3-V operation Supports hot-socketing Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 circuitry compliant with IEEE Std. 1532
Table shows device features.
Table 1-1. Device Features Feature
Typical Equivalent Macrocells Equivalent Macrocell Range Size (bits) Maximum User pins tPD1 (ns) fCNT (MHz) (ns) (ns) Notes Table 1-1:
tPD1 represents pin-to-pin delay worst case placement with full diagonal path across device combinational logic implemented single that adjacent output pin. maximum frequency limited standard clock input pin. 16-bit counter critical delay will faster than this number.
EPM240
8,192
EPM570
8,192
EPM1270
1,270 1,270 8,192
EPM2210
2,210 1,700 1,270 2,210 8,192
Device Handbook, Volume
Core Version a.b.c variable
Altera Corporation March 2004
more information equivalent macrocells, refer Logic Element Macrocell Conversion Methodology white paper.
devices available three speed grades: with being fastest. These speed grades represent overall relative performance, specific timing parameter. propagation delay timing numbers within each speed grade density, "Timing Model Specifications" page 5-10. Table shows device speedgrade offerings.
Table 1-2. Speed Grades Speed Grade Device
EPM240 EPM570 EPM1270 EPM2210
Altera Corporation March 2004
Core Version a.b.c variable
Device Handbook, Volume
Features
devices available space-saving FineLine BGA® thin quad flat pack (TQFP) packages (see Tables 1-4). devices support vertical migration within same package (e.g., migrate between EPM570, EPM1270, EPM2210 devices 256-pin FineLine package). Vertical migration means that migrate devices whose dedicated pins JTAG pins same power pins subsets supersets given package across device densities. largest density package highest number power pins; must layout largest planned density package provide necessary power pins migration. migration across densities, cross reference available pins using device pin-outs planned densities given package type identify which pins migrated. Quartus® software automatically cross reference place pins when given device migration list.
Table 1-3. Packages User Pins Device
EPM240 EPM570 EPM1270 EPM2210
100-Pin TQFP
144-Pin TQFP
256-Pin FineLine
324-Pin FineLine
Table 1-4. TQPF FineLine Package Sizes Package
Pitch (mm) Area (mm2) Length width
100-Pin TQFP
144-Pin TQFP
256-Pin FineLine 324-Pin FineLine
Device Handbook, Volume
Core Version a.b.c variable
Altera Corporation March 2004
devices have internal voltage regulator which supports external supply voltages regulating supply down internal operating voltage devices with ordering code only accept external supply voltage. Table shows external supply voltages supported family.
Table 1-5. External Supply Voltages EPM240 EPM570 EPM1270 EPM2210
Devices
EPM240G EPM570G EPM1270G EPM2210G
MultiVolt core external supply voltage (VCCINT) MultiVolt interface voltage levels (VCCIO) Notes Table 1-5:
devices with ordering code have internal voltage regulator only accept their VCCINT pins. Contact Altera availability these devices. devices operate internally
Altera Corporation March 2004
Core Version a.b.c variable
Device Handbook, Volume
Features
Device Handbook, Volume
Core Version a.b.c variable
Altera Corporation March 2004

MII51001-1.0 MAX® family instant-on, non-volatile CPLDs based 0.1

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