SY10 INTRODUCTION Date: August 2002 SY10 accurate time

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SY10 INTRODUCTION Date: August 2002 SY10 accurate time

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SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
SY10
INTRODUCTION
Date: August 2002
SY10 accurate time frequency source that been designed subsystem level module. module designed work within ATM, SONET, SDH, wireless systems where synchronization vital. SY10 excellent synchronization solution timing, with jitter wander compliance specified within ITU-T Recommendations G.812/G.813 Bellcore GR1244-CORE. SY10 enhanced version SY01 designed Stratum Stratum also holds certain features that make useful SONET Minimum Clock (SMC) other kinds system clocks.
FEATURES
synchronization solution timing, jitter wander concerns single module. Complies with ITU-T Recommendations G.812/813 Bellcore GR-1244-CORE Stratum Stratum applications. Supports modes operation: Locked, Holdover Free-run. Accepts reference inputs from independent sources from 8KHz 77.76MHz Provides output from 8KHz 77.76MHz (Two user select fixed 8KHz) Loop filtering utilizing specific software application digital signal processor (DSP). Continuously monitors evaluate input reference signals. Phase build-out output clock. Creates history buffer Holdover mode operation. Alarm status signals messages. Host interface configuring remote monitoring. Supports Master/Slave configuration SY10 with minimum phase error between clocks. Provides "hit-less" switching during switching between clocks. compatible with pins SY01 module. Small dimensions 1.82 1.82 inch. (0.60 inch with mechanical cover)
APPLICATION
SY10, Synchronous Equipment Clock (SEC), fulfills clock regeneration function STRATUM equipment for: ATM, SDH, PDH, SONET networks. designed network system manufacturers such Access Switches, Core Switches, Cross Connects, Digital Multiplexers-Exchangers, SDH/SONET equipment. unit also suitable PCS, WLL, Wireless Base Stations. Wherever Timing unit with high performance specifications required, SY10 embedded within network system provide necessary frequencies interfaces.
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SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
Alarms Statuses
Ex.Ref.1 Ex.Ref.2 Ex.Ref.3 Ex.Ref.4 Ex.Ref.5 Ex.Ref.6
OCXO MUX, FPD, Counters Logic
(RAM, FLASH)
Output Synthesizer
Control Inputs
JTAG
Figure functional block diagram SY10.
DESCRIPTION
SY10 synchronization module Digital (DPLL), which utilizes application specific software digital signal processor (DSP). complemented fast hardware logic (FPGA) where multiplexers, counters, dividers, phase detectors, output frequency converters other control logic circuits completely implemented. functional block diagram with maximum configuration shown figure module three phase lock loop primary PLL, secondary utility PLL. primary utilizes Direct Digital Synthesis (DDS) technique combined with high stability OCXO order provide accurate fast DPLL response eliminates requirement OCXO with high pullability. primary loop bandwidth loop that filters major part wander jitter input. output primary connected secondary synthesizer that also DPLL with wider loop bandwidth. secondary loop also another input that comes from pin. Depending master-slave mode, secondary loop utilizes either inputs. output secondary connected utility that analog phase lock loop. outputs secondary utility provide three independent output signals. serial communication interface provides flow messages between module host processor. JTAG interface provides easy access future software upgrade re-programming without removing module from system.
SY10 software provides several features such switching between references inputs basis monitoring estimation input signals internal state diagram; real time calculation filtering algorithm jitter wander according approved standards; alarm, status messaging functions using output pins serial communication port.
other configurations, please contact Raltron.
module operates following three timing modes:
Free-run this mode, unit unlocked either inputs. accuracy output frequencies this mode ±4.6ppm. Free-run mode typically used when master clock source required, valid history data Holdover mode, immediately following system power-up before network synchronization achieved. Free-run Mode, SY10 provides timing synchronization signals that based accuracy on-board oscillators only, synchronized reference signals.
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SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
Holdover this mode, module lost reference inputs utilizing stored timing data, called history, control output frequency. Holdover Mode typically used while network synchronization temporarily disrupted. Holdover Mode, SY10 provides timing, based data from history buffer, while unlocked external reference signal. history data determined while device locked external reference signal. stability output signal holdover mode depends primarily stability on-board oscillator environment effects where clock mounted. SY10 uses OCXO on-board oscillator other types oscillators available. Locked Reference this mode, output module phase locked input references. output frequency tracks selected input reference. "Locked Reference Modes" typically used when slave clock source synchronized network. these modes, SY10 provides timing signals, which synchronized, references inputs (REF1 REF6). input reference signals have variety nominal frequencies, which typically specified user. When modes selected unit goes through reference evaluation, then frequency acquisition, finally phase locking.
Local Reference Oscillator
Depending type clock, local reference oscillator selected. example: Stratum type clock, local oscillator high stability SC-cut OCXO that meets this standard requirements frequency drift jitter noise.
Input References
SY10 module accepts input references REF1 REF6. users specify frequencies within range 77.76 MHz. input reference signals HCMOS/TTL levels with timing characteristic accordance with Bellcore GR-1244-core 3.2.1.R3-1 equivalent standards. Please note that user must specify input frequencies time order.
Monitoring Evaluation Input References
Using advanced algorithm input references continuously monitored evaluated module. There three techniques used algorithm each reference, presence reference, frequency offset during time when unit phase locked reference, frequency offset when unit phase locked reference. SY10 rejects reference signals whose frequency accuracy offset more than PPM. given event that requires switching operation mode, timing module unit performs reference evaluation test target reference. Since such evaluation continuous process, switching takes very short time (typically less then second). Providing successful evaluation, unit switches frequency phase locking mode. other hand, reference qualified unit switches holdover mode.
Filtering DPLL
SY10 dynamically changes loop bandwidth according status DPLL. primary there five stages that DPLL goes through before phase lock mode achieved. first stage frequency acquisition that takes place until frequency becomes equal reference. second stage phase acquisition stage that takes place until phase reference acquired. other stages tracking stages (hint: DPLL locked tracks phase reference with very loop bandwidth). This method three tracking stages ensures minimum locking time minimum phase jumps shifts during acquisition transition. also provides phase build-out during switching rearrangement. secondary operates similarly primary with exception wider bandwidth (hint: only three stages) first frequency acquisition, second phase acquisition third tracking mode. Please detail state diagram.
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SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
History Buffer HOLDOVER mode
Frequency timing data continuously collected history buffer during time when unit locked input references. history buffer actually circular buffer memory that keeps valid data HOLDOVER mode during last seconds operation. When SY10 enters HOLDOVER mode data from buffer validated processed. history buffer cleared writing HLRST CFG2 register.
Output Signals
SY10 module provides three output signals OUT, OUT1 OUT2. outputs generated internal oscillators VCXO scaled output frequency converters. VCXO oscillators used module providing independent frequency types third (OPT OUT2) derived from them. performance module significantly depends output oscillator special care taken define their specifications. used VCXO high quality crystal oscillators with very output jitter. frequency oscillator specified according network application where SY10 will used. frequency converters divide signal from oscillator specified frequencies.
Indications
SY10 provides detailed monitoring indication operation unit. types monitoring status indicating provided: Visual indication: Using board color mounted LED's that indicate operating mode SY10. indicators mainly placed system troubleshooting, testing. Electronic indications: Using digital outputs that report status alarms from SY10. These alarms mainly used communication between module network equipment.
internal indicators are:
Signal Holdover REF1 REF2 REF3:. REF4: REF5 REF6 FREERUN UNLOCK ALARM super light LED, when module holdover mode. green LED, when module locked reference green LED, when module locked reference green LED, when module locked reference green LED, when module locked reference green LED, when module locked reference green LED, when module locked reference orange LED, when unit free running mode. LED, when module locked selected reference signal. LED, when there alarm module
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SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
Control
Several controls pins available user control operation SY10 Primary PLL. three external inputs CNT1, CNT2 CNT3 provide feature change state operation. Below, truth table shows behavior SY10 module according control inputs states.
CNT3 CNT2 CNT1 MODE OPERATION Free-run Locked REF1 Locked REF2 Holdover Locked REF3 Locked REF4 Locked REF5 Locked REF6
change operation Secondary (Master-Slave) change using MS/FR control pin.
MS/FR MODE OPERATION open) Master (default) Slave explanation about MS/FR below.
state operation changed also using serial communication port, please below.
SY10 State Machine Primary
state machine SY10 module controlled using interfaces: three external control pins CNT1, CNT2 CNT3. setting bits (CON0, CON1, CON2 CON3) CFG1 register using serial peripheral interface (SPI). After reset module three external control pins control function user change setting register CFG1. setting module ignores states control pins bits CFG1 register state engine control. figure below shown simplified stated diagram SY10 module. FREE
FREQ. PHASE LOCKING
REFERENCE SWITCHING
HOLDOVER
Figure SY10 state diagram Primary PLL. RALTRON ELECTRONICS CORP. 10651 N.W.19 Florida 33172 U.S.A. Tel: 593-6033 Fax: 305-594-3973 e-mail: sales@raltron.com Internet: http://www.raltron.com
SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
(FREERUN) path runs until control signals (CNT1,2,3 pins CON0,1,2,3 bits CFG1 register) zero there valid history available acquisition buffer holdover. (FREERUN_ REFERENCE_SWITCHING) path runs when there change control signals. (REFERENCE_SWITCHING_FREERUN) path runs when control signals were changed zero free-run mode selected. (REFERENCE_SWITCHING) path runs until appropriate reference selected. unit Auto Switching mode (bit AUTOEN CFG2 register module will switch following conditions: reference that selected control signals, selected reference available will switch based Priority Table (registers PR4). references available will holdover (path unit Manual Switching mode (bit AUTOEN CFG2 register module will switch following conditions: reference that selected control signals, selected reference available will holdover (path (FREQ&PHASE_LOCKING_FREERUN) path runs when control signals were changed zero free-run mode selected. (HOLDOVER_FREERUN) path runs when control signals were changed zero free-run mode selected there valid history available acquisition buffer holdover. path runs when reference switching successfully finished reference qualified changes control signals. (REFERENCE_SWITCHING_HOLDOVER) path runs following conditions: control signals were changed (0011) holdover mode selected. module Auto Switching mode (bit AUTOEN CFG2 register module will switch holdover none reference available. module Manual Switching mode (bit AUTOEN CFG2 register selected reference qualified reference lost during process evaluation. path runs following conditions: another reference selected changing control signals. module Auto Switching mode (bit AUTOEN CFG2 register module will switch reference switching least references available when currently selected reference failing. unit operate Revertive mode (bit REVEN CFG2 register previously lost reference back module will switch reuse same reference. (HOLDOVER_ REFERENCE_SWITCHING) path runs following conditions: current selected reference reacquired other reference selected changing control signals. unit operate Revertive mode (bit REVEN CFG2 register previously lost reference back module will switch reuse same reference.
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SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
(FREQ&PHASE_LOCKING) path runs until frequency acquisition phase locking progress with changes control pins. module goes through intermediate states order accomplish phase tracking. There three basic intermediate steps that include frequency acquiring, phase acquisition tracking. Tracking have additional steps depending bandwidth achieved. (HOLDOVER) path runs until holdover mode progress with changes control signals. (FREQ&PHASE_LOCKING_ HOLDOVER) path runs following conditions: used reference lost detected bad, control signals were changed (0011) holdover mode selected. (FREERUN_HOLDOVER) path runs only control signals were changed (0011) valid history buffer holdover operation available holdover mode selected.
SY10 Master-Slave Operation Secondary
systems where clock redundancy required possible connect SY10 such connection shown figure below. module pins dedicated this feature MS/FR MS/FR control input selects module will operate master (logic high) slave system. input signal that comes from another clock module. system always clock "one" operates master second slave clock. When operating slave output SY10 also tracks master provides minimum phase difference between clocks. This very useful makes easier "hitless" switching references. Master-Slave control also done using communication setting register CFGREG1. Please more Memory Mapped Registers section. typical Master-Slave connection block diagram show figure below.
(Pin
SY10
(Pin
(Pin
SY10
(Pin
Figure Master Slave connection SY10.
state machine SY10 Master -Slave operation module controlled using interfaces: external control MS/FR. setting CFG1 register using serial peripheral interface (SPI). After reset module external control control function user change setting register CFG1. setting module ignores states control pins bits CFG1
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SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
register state engine control. figure below shown simplified stated diagram SY10 Master -Slave operation.
MASTER
SLAVE
Figure SY10 Master Slave state diagram
(MASTER) path runs until control signals MS/FR CFG1 register there valid signal pin. valid signal means either present within frequency offset window. (MASTER_SLAVE) path runs when there change MS/FR control signal from case CFGREG1 from there valid signal pin. (SLAVE_MASTER) path runs when there change MS/FR control signal from case CFGREG1 from there valid signal (signal disappeared). (SLAVE) path runs until control signal MS/FR CFG1 register there valid signal pin.
explanation below!
MS/FR shared input
Since MS/FR control input shares function special caution should taken drive signal MS/FR signal sampled processed internal software decisions made using following: change status Secondary from Master Slave using MS/FR user have change from keep logic period longer then 100ms communicating through SPI. within that period time MS/FR signal does change level there clock signal SCLK changing SCLK communication) operation will changed from Master Slave.
signal SCLK Sampes MS/FR >100ms Change SLAVE
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SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
maintain Slave mode while still communicating through signal MS/FR should high prior SCLK more then 100ms given time. Please timing constrains communication.
signal
SCLK Sampes MS/FR 100ms Change
change status Secondary from Slave Master signal MS/FR should high period longer then 100ms communicating through SPI.
signal SCLK Sampes MS/FR >100ms Change MASTER
maintain Master mode while still communicating through signal MS/FR should during SCLK more then 100ms given time. Please timing constrains communication.
signal
SCLK Sampes MS/FR 100ms Change
Changing mode operation done easier using communication interface please next paragraph. other configuration please contact Raltron Electronics Corp.
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SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
SERIAL COMMUNICATION
module configured, controlled monitored using board serial communication port provided SY10. There four pins available this features SCLK, MS/FR, DOUT. DOUT ports used transfer command data module. SCLK input used clock data transfer module MS/FR shared that provides frame synch signal. SY10 operates only slave device transfer data command should initiated microcontroller. micro-controller read write configuration registers read only from status registers mapped internally into SY10. Optionally interface implemented SPI.
SCLK
DOUT MS/FR
SY10
Figure serial communication
Communication Protocol
interface synchronous peripheral interface (SPI), master must provide clock signal initiate communication cycles. There read write cycles each communication cycle that consists clocks (8+8 bits). Data latched every rising edge clock input from most significant bit. maximal allowed frequency SCLK 10MHz tclk.
Write data cycle
master sends module bytes 8bits). First byte always command byte. second byte data byte contains information write. Command byte data format:
7(MSB) 0(LSB)
A5.A0 Module register address please table Read Write bit. used. Data byte format:
7(MSB) 0(LSB)
D7.D0 Content written register addressed A5:A0
Read data cycle
master sends module one-command byte receives from module information byte (see 1.2). Command byte data format:
7(MSB) 0(LSB)
A5.A0 Module register address please table Read Write bit. Data byte format:
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SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
7(MSB) 0(LSB)
D7-D0 Content read from module addressed A5:A0
Flowchart
Entry point received bytes
Received Address Valid?
SPIStatus ADDRESSERROR
received bytes
WRITE
Command Read Write? READ
received bytes
READ Fetch data from send
Command Read Write?
WRITE
SPIStatus SPIStatus OVERFLOW
Valid Data write MMR?
SPIStatus WRITEERROR
Write Data
Wait next byte
Reset
SPIStatus
Figure flowchart.
Timing diagrams
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SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
Please below timing diagram write read cycles. Please note that DOUT tri-state output. minimum value tclk 100ns time tout approximately 1sec. will latch data input data output DOUT every rising edge SCLK however operation mode changed operates request. Changes include clock polarity, length data etc. During read cycle master have provide pause between bytes minimum (twait 1ms).
tclk SCLK tout
DOUT MS/FR
Figure Write cycle 8-bit Parameter tclk Time prior transition Time hold after transition tds-Time data prior transition Time hold data after transition 100ns tclk/2 tclk/2 10ns
tclk SCLK
twait
DOUT
MS/FR
Figure Read cycle 8-bit
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SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
Memory Mapped Registers
There twenty-eight 8-bit registers accessible through serial port: registers write read data registers only read data from module. table memory registers their purpose.
Addr. Read Write Name CID7 SID7 HID7 CID6 SID6 HID6 Format CON3 CON2 CON1 CID1 SID1 HID1 CON0 CID0 SID0 HID0 Description
RFH1 RFH2 RFH3 RFH4 RFH5 RFH6 RFH7 RFH8 RST1 RST2 PSP1 PSP2 PMAX PMIN CFG1 CFG2 BW11 BW12
CID5 CID4 CID3 CID2 SID5 SID4 SID3 SID2 HID5 HID4 HID3 HID2 Table Memory registers.
4-bit priority references 4-bit priority references 4-bit priority references used Ref. frequency shift Ref. frequency shift Ref. frequency shift Ref. frequency shift Ref. frequency shift Ref. frequency shift used used References status References status Status Primary Status Secondary Utility Maximum frequency pull Minimum frequency pull Configuration Configuration Frequency acquisition PLL1 Bandwidth PLL1 Bandwidth PLL1 Frequency acquisition Bandwidth track PLL2 status register Customer register Software register Hardware register
Reference Priority Registers (PR1 PR4) address 00-03h There four registers that specify priority during switching. Every reference 4-bit priority references defined register. priority means that module event loosing reference will lock valid reference with higher priority available AUTOEN register CFG2 one. initial priority module overridden customer. highest priority 1111b lowest priority 0001b. priority zero (0000b) reference will used module status will "Reference present use". R10-R13 defines reference priority R20-R23 defines reference priority R30-R33 defines reference priority R40-R43 defines reference priority R50-R53 defines reference priority R60-R63 defines reference priority
default values are: PR1:0x78h PR2:0x56h PR3:0x34h PR4:0x12h
Frequency Shift Registers (RFH1-RFH8) address 04-0Bh.
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SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
registers indicate references nominal frequency parts million (ppm). resolution 0.5ppm. range ±63ppm. frequency above below ±63ppm range, shown respectively proper status indicated Reference Status Registers. format compliment example content RFS3 register 11000111 then third reference -28.5ppm
7(MSB) SIGN default values are: RFH1: 0xFFh RFH2: 0xFFh RFH3: 0xFFh RFH4: 0XFFh RFH5: 0xFFh RFH6: 0xFFh RFH7: 0xFFh RFH8: 0xFFh 0(LSB)
Reference Status Registers (RST1-RST2) address 0C-0Dh There reference status registers that hold information about status references. Each reference 2-bit status each register keep statuses four references. possible statuses are:
Binary number Status Present Present Reference Description Reference present evaluated Reference present frequency range Reference present Reference present frequency range
S10-S11 defines status reference S20-S21 defines status reference S30-S21 defines status reference S40-S41 defines status reference S50-S51 defines status reference S60-S61 defines status reference
default values are: RST1: 0x00h RST2: 0x00h
Status Registers (PSP1-PSP2) address 0E-0Fh Register PSP1 indicates status Primary PLL. register least significant bits indicate status most significant bits indicate reference loop. possible statuses Primary shown PSP1:
PS3-PS0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Status description locked. This status represents major error. Frequency Acquisition Phase Acquisition Tracking Bandwidth Tracking Bandwidth (SP1 only) Tracking Bandwidth (SP1 only) Tracking Bandwidth (SP1 only) Phase Build-out Holdover Free
possible reference bits are:
PS7-PS4 Status description
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SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
x000 x001 x010 x011 x100 x101 x110 0xxx 1xxx reference (module Free Holdover) Reference Reference Reference Reference Reference Reference Holdover History Buffer Available Holdover History Buffer Available
Register PSP2 indicates status Secondary PLL. register least significant bits indicate status Secondary most significant bits indicate status utility available.
SS3-SS0 0000 0001 0010 0011 0100 0101 0110 Status description locked. This status represents major error. Frequency Acquisition operating master clock Phase Acquisition operating master clock Tracking Bandwidth operating master clock Frequency Acquisition operating slave clock Phase Acquisition using operating slave clock Tracking Bandwidth using operating slave clock
possible utility status bits.
US3-US0 0000 0001 default values are: PSP1: 0x00h PSP2: 0x00h Status description locked Locked
Frequency Pull Range Registers (PMAX PMIN) address 10-11h These registers specify window pull-in range reference acceptance frequency window. PMAX register specifies maximum frequency window that module locked frequency beyond references will rejected. PMIN registers frequency window within references will accepted. PMAX must greater then PMIN both positive numbers. data format unsigned binary 8-bit number, example content PMAX register 00011110 PMIN 00011010 then pull range ±15ppm reference acceptance ±13ppm:
7(MSB) default values are: PMAX: 0x1Eh PMIN: 0x1Ah 0(LSB)
Configuration Registers (CFG1 CFG2) address 12-13h Register CFG1 used clock mode operation. user select which interface will used change mode operation setting CFG1 register (default) module will change state according three input pins CNT1, CNT2 CNT3. CFG1 register module will changed state according four bits (CON0, CON1, CON2 CON3) CFG1 registers. There bits modes operation:
CON3 CON2 CON1 CON0
Mode operation Free-run Lock Reference Lock Reference
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SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
Holdover Lock Reference Lock Reference Lock Reference Lock Reference used used
Other combinations supported ignored. Bits CFG1 reserved future ignored this set. CFG1 sets module Master Slave operation, (default) module operates Master module operates slave condition that signal (pin present. Register CFG2 used customer control behavior module application needs.
7(MSB) FREV RESET HLRST REVEN 0(LSB) AUTOEN
AUTOEN when logic high, enabling automatic switching other reference event loosing current reference according priority registers PR1-PR4. When logic low, will switch other reference. REVEN when high, will enable revertive operation. HLRST when high, will erase previous operation history holdover. RESET when high, will initiate internal reset module. FREV when high AUTOEN high will switch references based their frequency offset (select best available). when high Phase Build disabled.
default values are: CFG1: 0x00h CFG2: 0x00h
Frequency Acquisition Primary (FA1) address register determines bandwidth during frequency acquisition PLL. values FA0-7 represent frequency acquisition (0-256Hz).
default values are: FA1:
Bandwidth registers PLL1 (BW11, BW12) address 15-16h BW11 BW12 registers determine tracking bandwidth primary PLL. There four sets bits each representing corresponding tracking bandwidth. table below shows available combinations.
Bandwidth RALTRON ELECTRONICS CORP. 10651 N.W.19 Florida 33172 U.S.A. Tel: 593-6033 Fax: 305-594-3973 e-mail: sales@raltron.com Internet: http://www.raltron.com
SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
default values are: BW11: 0x23h BW12: 0x01h others 0.001Hz 0.01Hz 0.1Hz
Frequency Acquisition Bandwidth Track PLL2 (FB2) address register determines bandwidth Secondary frequency acquisition tracking modes. tables below represent available combinations B0-B3 (frequency acquisition) F0-F3 (tracking).
default value: FB2: 0x53h. Bandwidth 10Hz 20Hz 30Hz 40Hz 50Hz 60Hz 70Hz 80Hz 90Hz 100Hz 200Hz 300Hz 400Hz 500Hz 600Hz Bandwidth 10Hz 15Hz 20Hz 25Hz 30Hz 35Hz 40Hz 50Hz 60Hz 70Hz 80Hz 100Hz 200Hz
Status Register (SST) address register represents current status communication. address read only following values:
MESSAGE SPIERRSTATOK SPIERRRECOVERFLOW SPIERRINVALIDADDR SPIERRINVALIDWRITEADDR VALUE ACTION correct command received module more then bytes received before routine handled incorrect address received module incorrect write address value received module
Customer Register (CID) address register contains unique customer identification number.
default value: CID: 0x03h.
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SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
Software Register (SID) address register contains unique software identification number.
default value: SID: 0x18h. (will vary with updates)
Standard Timing Application Systems
typical timing application telecommunication equipment shown figure below. system consists Clock Cards (CC1 CC1) several Line Cards Clock Cards clock modules SY10 generate redundant signal references whole Line Cards high frequency synchronizer module SY05 high frequency reference signals communication (for e.g. transceivers). Clock Cards connected such provide Master/Slave operation clocks. local processors configure monitor SY10 module serial port SPI. reference signals optionally four status signals from each Clock Card (STATUS STATUS distributed Line Cards. STATUS signals HOLDOVER (pin SY10), FREERUN (pin ALARM (pin UNLOCK (pin they connected corresponding pins SY05 modules. particular application timing application that best fits please contact Raltron.
SY05
STATUS SERIAL PORT
SY10
(10) (25)
SY05
(25)
SERIAL PORT
SY10
(10)
STATUS
SY05
Figure typical timing application.
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SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
SPECIFICATIONS
Mechanical Power Supply Warm Current Supply Steady State Current Supply Operating Temperature Humidity Internal Oscillators Input Signals Number Inputs Input reference frequency Signal Level Time Reference characteristics Number Outputs Output Output Output Signal Level Jitter Tolerance Phase Transient Tolerance Wander Generation Wander Tolerance Jitter Generation Transfer Wander Transfer Frequency Output Performance Free accuracy Holdover frequency stability Initial Offset Temperature Drift Phase Build-Out DPLL bandwidth Lock Time Lock accuracy Stratum ±4.6ppm ±1x10
General Specifications
1.82" 1.82" 0.70" 1.8" 1.8" 0.60" 3.3VDC 700mA 25°C 400mA max. 25°C -20°C 70°C non-condensing OCXO 8kHz 77.76MHz HCMOS/TTL Compatible 8KHz 77.76MHZ 8KHz 77.76MHZ 8KHz HCMOS
Metal Module Varies from different oscillator used Other ranges available request SC-cut Stratum AT-cut stratum User selectable Bellcore: GR-1244-core 3.2.1.R3-1 User define User define 3.3V levels tolerant Bellcore: GR-1244-core ITU-T: G.813 Bellcore: GR-1244-core Bellcore: GR-1244-core ITU-T: G.812 Bellcore: GR-1244-core ITU-T: G.812 Bellcore: GR-1244-core ITU-T: G.812 Bellcore: GR-1244-core ITU-T: G.812
Output Signal
Signal Quality Performance
Stratum ±4.6ppm ±0.37x10
±1x10 ±8x10 ±1x10
±50x10
GR-1244-core ITU-T: G.812 Bellcore: GR-1244-core ITU-T: G.812 Bellcore: GR-1244-core ITU-T: G.812 Bellcore: GR-1244-core ITU-T: G.812 Bellcore: GR-1244-core ITU-T: G.812 adjustable 20Hz GR-1244-core
±280x10 ±1x10
0.001Hz <700 ±1x10
0.1Hz <100sec ±1x10
RALTRON ELECTRONICS CORP. 10651 N.W.19 Florida 33172 U.S.A. Tel: 593-6033 Fax: 305-594-3973 e-mail: sales@raltron.com Internet: http://www.raltron.com
SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
ASSIGNMENT
OUT1 SCLK DOUT
HOLDOVER FREERUN ALARM OUT2 MS/FR UNLOCK
Figure Bottom view 9,18,22,26,30 Name HOLDOVER FREERUN ALARM OUT2 MS/FR UNLOCK DOUT SCLK OUT1 Description Holdover Signal output high when unit holdover mode Reference Signal Indication section page Reference Signal Indication section page Reference Signal Indication section page Reference Signal Indication section page Reference Signal Indication section page Free-run Signal output high when unit free mode Reference Signal Indication section page Master/Slave Synchronizing output connected slave module SEC-IN Alarm signal output high when there alarm module. Optional Output secondary output synchronized signal Control Input external input selecting mode unit table. Control Input external input selecting mode unit table. Control Input external input selecting mode unit table. Master/Slave Selection Frame Input select master slave master/ slave operation clocks case using Frame synch signal communication. Unlocked Signal output high when unit locked references Ground Positive Voltage Supply Serial Data Output serial communication interface data output Synchronized Output output synchronized signal Serial Clock Input serial communication interface clock input Serial Data Input/ serial communication interface data input Optional Output secondary output synchronized signal,. Input input from second clock module master/slave operation clocks. External Reference Input input signal from reference External Reference Input input signal from reference External Reference Input input signal from reference External Reference Input input signal from reference External Reference Input input signal from reference External Reference Input input signal from reference
RALTRON ELECTRONICS CORP. 10651 N.W.19 Florida 33172 U.S.A. Tel: 593-6033 Fax: 305-594-3973 e-mail: sales@raltron.com Internet: http://www.raltron.com
SYNCHRONOUS EQUIPMENT STRATUM 3/3E CLOCK UNIT SY10
MECHANICAL DIMENSIONS
1.82 (46.23 SQ.)
.440 (11.18)
.085 (2.16)
1.60 (40.64)
MARKING AREA
1.700 (43.18)
.100 (2.54)
.065 (1.65) .076 (1.93)
PLCS)
.910 .200 (5.08)
.210 (4.57)
.100 (2.54)
1.400 ±.005 (35.56 ±.127)
Figure mechanical dimensions.
Figure shows mechanical dimension SY10 module. module supplied different types packaging: Metal Module without packaging
label module shows part number, factory name, week year production. Without metal cover maximum height reaches 0.60".
RALTRON ELECTRONICS CORP. 10651 N.W.19 Florida 33172 U.S.A. Tel: 593-6033 Fax: 305-594-3973 e-mail: sales@raltron.com Internet: http://www.raltron.com
.071 (1.82)
NOTES:
UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: ±.005 (.127 mm).
.910 (23.11)
.030 (0.76)
.060 PLCS) (1.52)
.630 (16.00)

SY10 INTRODUCTION Date: August 2002 SY10 accurate time

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