EBE51UD8ABFA (64M words bits, Rank) EBE51UD8ABFA words bits, rank
|
|
|
Top Searches for this datasheet
512MB Unbuffered DDR2 SDRAM DIMM
EBE51UD8ABFA (64M words bits, Rank)
EBE51UD8ABFA words bits, rank DDR2 SDRAM unbuffered module, mounting pieces 512M bits DDR2 SDRAM sealed FBGA (µBGA) package. Read write operations performed cross points /CK. This highspeed data transfer realized bits prefetchpipelined architecture. Data strobe (DQS /DQS) both read write available high speed reliable data design. setting extended mode register, on-chip Delay Locked Loop (DLL) enable disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors mounted beside each FBGA (µBGA) module board. Note: push components drop modules order avoid mechanical defects, which result electrical defects.
Features
240-pin socket type dual line memory module (DIMM) height: 30.0mm Lead pitch: 1.0mm 1.8V power supply Data rate: 533Mbps/400Mbps (max.) 1.8V (SSTL_18 compatible) Double-data-rate architecture: data transfers clock cycle Bi-directional, differential data strobe (DQS /DQS) transmitted/received with data, used capturing data receiver edge aligned with data READs: centeraligned with data WRITEs Differential clock inputs /CK) aligns transitions with transitions Commands entered each positive edge: data data mask referenced both edges Four internal banks concurrent operation (components) Data mask (DM) write data Burst lengths: /CAS Latency (CL): Auto precharge operation each burst access Auto refresh self refresh modes 7.8µs average periodic refresh interval Posted programmable additive latency better command data efficiency Off-Chip-Driver Impedance Adjustment On-DieTermination better signal quality /DQS disabled single-ended Data Strobe operation.
Document E0357E10 (Ver. 1.0) Date Published March 2003 Japan URL: http://www.elpida.com Elpida Memory, Inc. 2003
EBE51UD8ABFA
Ordering Information
Part number EBE51UD8ABFA-5C EBE51UD8ABFA-4A EBE51UD8ABFA-4C Data rate Mbps (max.) Component JEDEC speed (CL-tRCD-tRP) DDR2-533 (4-4-4) DDR2-400 (3-3-3) DDR2-400 (4-4-4) Package 240-pin DIMM Contact Gold Mounted devices EDE5108ABSE
Configurations
Front side
Back side
name VREF /DQS0 DQS0 /DQS1 DQS1 DQ10 DQ11 DQ16 DQ17 /DQS2 DQS2
name VDDQ VDDQ /CAS VDDQ VDDQ DQ32 DQ33 /DQS4 DQS4 DQ34 DQ35 DQ40
name DQ12 DQ13 /CK1 DQ14 DQ15 DQ20 DQ21 DQ22
name VDDQ /CK0 VDDQ /RAS /CS0 VDDQ ODT0 DQ36 DQ37 DQ38 DQ39 DQ44 DQ45
Preliminary Data Sheet E0357E10 (Ver. 1.0)
EBE51UD8ABFA
name DQ18 DQ19 DQ24 DQ25 /DQS3 DQS3 DQ26 DQ27 VDDQ CKE0 VDDQ name DQ41 /DQS5 DQS5 DQ42 DQ43 DQ48 DQ49 /DQS6 DQS6 DQ50 DQ51 DQ56 DQ57 /DQS7 DQS7 DQ58 DQ59 name DQ23 DQ28 DQ29 DQ30 DQ31 VDDQ VDDQ name DQ46 DQ47 DQ52 DQ53 /CK2 DQ54 DQ55 DQ60 DQ61 DQ62 DQ63 VDDSPD
Preliminary Data Sheet E0357E10 (Ver. 1.0)
EBE51UD8ABFA
name (AP) BA0, DQ63 /RAS /CAS /CS0 CKE0 /CK0 /CK2 DQS0 DQS7, /DQS0 /DQS7 VDDQ VDDSPD VREF ODT0 Function Address input address Column address Auto precharge Bank select address Data input/output address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input output data strobe Input mask Clock input serial Data input/output serial Serial address input Power internal circuit Power circuit Power serial EEPROM Input reference voltage Ground control connection
Preliminary Data Sheet E0357E10 (Ver. 1.0)
EBE51UD8ABFA
Serial Matrix
Byte Function described Number bytes utilized module manufacturer Total number bytes serial device Memory type Number address Number column address Number DIMM ranks Module data width Module data width continuation Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments bytes bytes DDR2 SDRAM SSTL 1.8V 3.75ns*1 5.0ns*1 0.5ns*1 0.6ns*1 None. 7.8µs None. Unbuffered Normal 0.1V 3.75ns*1 5.0ns*1 0.5ns*1 0.6ns*1 Undefined*1 5.0ns*1 Undefined*1 0.6ns*1
Voltage interface level this assembly SDRAM cycle time, -4A, SDRAM access from clock (tAC) -4A,
DIMM configuration type Refresh rate/type Primary SDRAM width Error checking SDRAM width Reserved SDRAM device attributes: Burst length supported SDRAM device attributes: Number banks SDRAM device SDRAM device attributes: /CAS latency Reserved DIMM type information SDRAM module attributes SDRAM device attributes: General Minimum clock cycle time -4A,
Maximum data access time (tAC) from clock -4A, Minimum clock cycle time -5C,
Maximum data access time (tAC) from clock -5C,
Preliminary Data Sheet E0357E10 (Ver. 1.0)
EBE51UD8ABFA
Byte
Function described Minimum precharge time (tRP) -5C, Minimum active active delay (tRRD) Minimum /RAS /CAS delay (tRCD) -5C, Minimum active precharge time (tRAS) Module rank density Address command setup time before clock (tIS) -4A,
Bit7
Bit6
Bit5 Bit4
Bit3
Bit2
Bit1 Bit0
value
Comments 15ns 20ns 7.5ns 15ns 20ns 45ns 512M bytes 0.5ns*1 0.6ns*1 0.5ns*1 0.6ns*1 0.35ns*1 0.4ns*1 0.35ns*1 0.4ns*1 15ns*1 7.5ns*1 10ns*1 7.5ns*1 Undefined 60ns*1 65ns*1 105ns*1 8ns*1 0.30ns*1 0.35ns*1 0.40ns*1 0.45ns*1 Undefined
Address command hold time after clock (tIH) -4A, Data input setup time before clock (tDS) -4A, Data input hold time after clock (tDH) -4A,
Write recovery time (tWR) Internal write read command delay (tWTR) -4A, Internal read precharge command delay (tRTP)
Memory analysis probe characteristics Extension Byte Active command period (tRC) -5C, -4A, Auto refresh active/ Auto refresh command cycle (tRFC) SDRAM cycle max. (tCK max.) Dout skew -4A, Data hold skew (tQHS) -4A,
relock time
Preliminary Data Sheet E0357E10 (Ver. 1.0)
EBE51UD8ABFA
Byte
Function described Revision Checksum bytes
Bit7
Bit6
Bit5 Bit4
Bit3
Bit2
Bit1 Bit0
value
Comments Rev.
Manufacturer's JEDEC code Manufacturer's JEDEC code Manufacturer's JEDEC code Manufacturing location Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number -4A, Module part number -5C,
Continuation code Elpida Memory
(ASCII-8bit code) (Space) Initial (Space) Year code (HEX) Week code (HEX)
Module part number Revision code Revision code Manufacturing date Manufacturing date Module serial number Manufacture specific data
Note: These specifications defined based component specification, module.
Preliminary Data Sheet E0357E10 (Ver. 1.0)
EBE51UD8ABFA
Block Diagram
/CS0 /DQS0 DQS0 /DQS DQS4 DQ32 DQ39 /DQS /DQS4
/DQS1 DQS1 DQ15 /DQS DQS5 /DQS5
DQ40 DQ47 /DQS
/DQS2 DQS2 DQ16 DQ23 /DQS DQS6 /DQS6
DQ48 DQ55 /DQS
/DQS3 DQS3 DQ24 DQ31 /DQS DQS7 /DQS7
/DQS DQ56 DQ63
BA1: SDRAMs A13: SDRAMs
Serial
/RAS
/RAS: SDRAMs /CAS: SDRAMs
/CAS CKE0 ODT0
/WE: SDRAMs CKE: SDRAMs ODT:SDRAMs Notes wiring maybe changed within byte. DQS, /DQS, ODT, CKE, relationships must meintained shown. Refer appropriate clock wiring topology under DIMM wiring details section this document.
VDDSPD VREF VDD, VDDQ
SDRAMs SDRAMs
512M bits DDR2 SDRAM bits EEPROM
SDRAMs
Preliminary Data Sheet E0357E10 (Ver. 1.0)
EBE51UD8ABFA
Logical Clock Structure
3DRAM loads (CK1 /CK1, /CK2)
DRAM
DRAM DIMM connector
DRAM
2DRAM loads (CK0 /CK0)
DRAM
DIMM connector
DRAM
Preliminary Data Sheet E0357E10 (Ver. 1.0)
EBE51UD8ABFA
Electrical Specifications
voltages referenced (GND). Absolute Maximum Ratings
Parameter Voltage relative Supply voltage relative Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VDD, VDDQ Tstg Value -0.5 +2.3 -0.5 +2.3 +150 Unit Note
Note: DDR2 SDRAM component specification. Caution Exposing device stress above those listed Absolute Maximum Ratings could cause permanent damage. device meant operated under conditions outside limits described operational section this specification Exposure Absolute Maximum Rating conditions extended periods affect device reliability.
Operating Conditions +70°C) (DDR2 SDRAM Component Specification)
Parameter Supply voltage Symbol VDD,VDDQ Input reference voltage Termination voltage Input high voltage Input voltage Input voltage level, inputs Input differential cross point voltage, inputs Input differential voltage, inputs VREF (DC) (DC) (DC) (DC) (DC) 0.49 VDDQ VREF 0.04 VREF 0.125 -0.3 -0.3 VDDQ 0.1V 0.50 VDDQ VREF VDDQ 0.51 VDDQ VREF 0.04 VDDQ VREF 0.125 VDDQ Unit Notes
VDDQ 0.1V VDDQ
Notes:
VDDQ must lower than equal VDD. allowed exceed 2.3V period shorter than equal 5ns. allowed outreach below down -1.0V period shorter than equal 5ns. (DC) specifies allowable execution each differential input. (DC) specifies input differential voltage required switching. (CK) assumed over VREF 0.18V, (CK) assumed under VREF 0.18V measurement.
Preliminary Data Sheet E0357E10 (Ver. 1.0)
EBE51UD8ABFA
Characteristics +70°C, VDD, VDDQ 1.8V 0.1V,
Parameter Symbol Grade max. Unit Test condition bank; (min.) (min.) inputs changing twice clock cycle; address control inputs changing once clock cycle bank; Burst (min.) (min.) IOUT 0mA; address control inputs changing once clock cycle banks idle; power-down mode; (max.); (min.) (min.); banks idle; (min.); (min.) address control inputs changing once clock cycle bank active; power-down mode; (max.); (min.) bank; active;/CS (min.); (min.); tRAS max; (min.); inputs changing twice clock cycle; address control inputs changing once clock cycle bank; Burst burst; address control inputs changing once clock cycle; outputs changing twice clock cycle; (min.) IOUT bank; Burst writes; continuous burst; address control inputs changing once clock cycle; inputs changing twice clock cycle; (min.) tRFC (min.) Self Refresh Mode; 0.2V Four bank interleaving READs (BL4) with auto precharge, (min.); Address control inputs change during Active, READ, WRITE commands.
Operating current (ACT-PRE)
IDD0
Operating current (ACT-READ-PRE) Idle power-down standby current Idle standby current Active power-down standby current
IDD1
IDD2P
IDD2N
IDD3P
Active standby current
IDD3N
Operating current (Burst read operating)
IDD4R
Operating current (Burst write operating) Auto-refresh current Self-refresh current Operating current (Bank interleaving)
IDD4W
IDD5 IDD6
IDD7
Characteristics +70°C, VDD, VDDQ 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter Symbol Value 0.603 0.603 VDDQ +13.4 -13.4 Unit Notes
Minimum required output pull-up under test load Maximum required output pull-down under test load Output timing measurement reference level VOTR Output minimum sink current Output minimum source current
Note:
VDDQ device under test referenced. VDDQ 1.7V; VOUT 1.42V. VDDQ 1.7V; VOUT 0.28V. value VREF applied receiving device expected VTT. After calibration 25°C, VDDQ 1.8V.
Preliminary Data Sheet E0357E10 (Ver. 1.0)
EBE51UD8ABFA
Capacitance 25°C, VDD, VDDQ 1.8V 0.1V)
Parameter Input capacitance Input capacitance Data input/output capacitance Symbol Pins max. Unit Notes
Address, /RAS, /CAS, /WE, /CS, CKE, DQS, /DQS,
Characteristics +70°C, VDD, VDDQ 1.8V 0.1V, (DDR2 SDRAM Component Specification)
Frequency (Mbps) Parameter /CAS latency Active read write command delay Precharge command period Active active/auto refresh command time output access time from output access time from high-level width low-level width half period Clock cycle time input hold time input setup time Control Address input pulse width each input input pulse width each input Data-out high-impedance time from CK,/CK Data-out low-impedance time from CK,/CK DQS-DQ skew associated signals hold skew factor DQ/DQS output hold time from Write command first latching transition input high pulse width input pulse width falling edge setup time falling edge hold time from Symbol tRCD tDQSCK tIPW tDIPW tDQSQ tQHS tDQSS tDQSH tDQSL tDSS tDSH min. -500 -450 0.45 0.45 min. (tCL, tCH) 3750 0.35 min. tQHS 0.25 0.35 0.35 max. +500 +450 0.55 0.55 8000 max. max. 0.25 -4A, min. (-4A) (-4C) (-4A) (-4C) (-4A) (-4C) (-4A) (-4C) -600 -500 0.45 0.45 min. (tCL, tCH) 5000 0.35 min. tQHS 0.25 0.35 0.35 max. (-4A) (-4C) +600 +500 0.55 0.55 8000 max. max. 0.25 Unit Notes
Mode register command cycle time tMRD Write preamble setup time tWPRES
Preliminary Data Sheet E0357E10 (Ver. 1.0)
EBE51UD8ABFA
Frequency (Mbps) Parameter Write postamble Write preamble Address control input hold time Symbol tWPST tWPRE min. 0.25 tRCD min. (tWR/tCK)+ (tRP/tCK) max. -4A, min. 0.25 tRCD min. (tWR/tCK)+ (tRP/tCK) max. Unit Notes
Address control input setup time Read preamble Read postamble Active precharge command Active auto-precharge delay Active bank active bank command period Write recovery time Auto precharge write recovery precharge time Internal write read command delay Exit self refresh command Exit power down non-read command Exit precharge power down read command Exit active power down read command Exit active power down read command (slow exit/low power mode) Output impedance test driver delay Auto refresh active/auto refresh command time Average periodic refresh interval tRPRE tRPST tRAS tRAP tRRD tDAL tWTR tXSC tXPNR tXPRD tXARD tXARDS tOIT tRFC tREFI
Notes: each terms above, already integer, round next highest integer. Additive Latency. define which active power down exit timing applied.
Preliminary Data Sheet E0357E10 (Ver. 1.0)
EBE51UD8ABFA
Electrical Characteristics Operating Conditions
Parameter turn-on delay turn-on turn-on (power down mode) turn-off delay turn-off turn-off (power down mode) Symbol tAOND tAON tAONPD tAOFD tAOF tAOFPD tAC(min) tAC(min) 2000 tAC(min) tAC(min) 2000 tAC(max) 1000 2tCK tAC(max) 1000 tAC(max) 2.5tCK tAC(max) 1000 Unit Notes
Notes: turn time when device leaves high impedance resistance begins turn turn time when resistance fully Both measured from tAOND. turn time when device starts turn resistance. turn time when high impedance. Both measured from tAOFD. Test Conditions
VSWING
VREF
/CLK
VREF
SLEW (VIH (ac) (ac))/t
Measurement point
Preliminary Data Sheet E0357E10 (Ver. 1.0)
EBE51UD8ABFA
Functions (input pin) master clock inputs. inputs except DMs, DQSs referred cross point rising edge VREF level. When read operation, DQSs referred cross point /CK. When write operation, referred cross point VREF level. DQSs write operation referred cross point /CK. (input pin) When low, commands data input. When high, inputs ignored. However, internal operations (bank active, burst operations, etc.) held. /RAS, /CAS, (input pins) These pins define operating commands (read, write, etc.) depending combinations their voltage levels. "Command operation". (input pins) address (AX0 AX13) determined level cross point rising edge VREF level bank active command cycle. Column address (AY0 AY9) loaded cross point rising edge VREF level read write command cycle. This column address becomes starting address burst operation. (AP) (input pin) defines precharge mode when precharge command, read command write command issued. high when precharge command issued, banks precharged. when precharge command issued, only bank that selected BA1, precharged. high when read write command, auto-precharge function enabled. While low, auto-precharge function disabled. (input pins) BA0, bank select signals (BA). memory array divided into bank bank bank bank (See Bank Select Signal Table) [Bank Select Signal Table]
Bank Bank Bank Bank
Remark: VIH. VIL. (input pin) controls power down self-refresh. power down self-refresh commands entered when driven exited when resumes high. level must kept cycle least, that changes cross point rising edge VREF level with proper setup time tIS, next rising edge level must kept with proper hold time tIH. (input output pins) Data input output from these pins. /DQS (input output pin) /DQS provide read data strobes output) write data strobes input).
Preliminary Data Sheet E0357E10 (Ver. 1.0)
EBE51UD8ABFA
(input pins): reference signal data input mask function. sampled cross point /DQS. VDDQ (power supply pins) 1.8V applied. (VDD internal circuit VDDQ output buffer.) VDDSPD (power supply pin) 1.8V applied (For serial EEPROM). (power supply pin) Ground connected.
Detailed Operation Part, Characteristics Timing Waveforms
Refer EDE5104ABSE, EDE5108ABSE, EDE5116ABSE datasheet (E0323E).
Preliminary Data Sheet E0357E10 (Ver. 1.0)
EBE51UD8ABFA
Physical Outline
Unit:
4.00 (DATUM -A-)
Component area (Front)
63.00 133.35 55.00
1.27 0.10
10.00
17.80
4.00
Component area (Back)
4.00
FULL
3.00
Detail
2.50 0.20
Detail 1.00 4.00
0.20 0.15
(DATUM -A-)
2.50 FULL
5.00
3.80
0.80 0.05
1.50 0.10
ECA-TS2-0093-01
Preliminary Data Sheet E0357E10 (Ver. 1.0)
30.00
EBE51UD8ABFA
CAUTION HANDLING MEMORY MODULES
When handling inserting memory modules, sure touch components modules, such memory ICs, chip capacitors chip resistors. necessary avoid undue mechanical stress these components prevent damaging them. particular, push module cover drop modules order protect from mechanical defects, which would electrical defects. When re-packing memory modules, sure modules touching each other. Modules contact with other modules cause excessive mechanical stress, which damage modules.
MDE0202
NOTES CMOS DEVICES
PRECAUTION AGAINST DEVICES
Exposing devices strong electric field cause destruction gate oxide ultimately degrade devices operation. Steps must taken stop generation static electricity much possible, quickly dissipate when once occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS DEVICES
connection CMOS devices input pins cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. unused pins must handled accordance with related specifications.
STATUS BEFORE INITIALIZATION DEVICES
Power-on does necessarily define initial status devices. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee output levels, settings contents registers. devices initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
CME0107
Preliminary Data Sheet E0357E10 (Ver. 1.0)
EBE51UD8ABFA
µBGA registered trademark Tessera, Inc.
information this document subject change without notice. Before using this document, confirm that this latest version.
part this document copied reproduced form means without prior written consent Elpida Memory, Inc. Elpida Memory, Inc. does assume liability infringement intellectual property rights (including limited patents, copyrights, circuit layout licenses) Elpida Memory, Inc. third parties arising from products information listed this document. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights Elpida Memory, Inc. others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. Elpida Memory, Inc. assumes responsibility losses incurred customers third parties arising from these circuits, software information. [Product applications] Elpida Memory, Inc. makes every attempt ensure that products high quality reliability. However, users instructed contact Elpida Memory's sales office before using product aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment life support, other such application which especially high quality reliability demanded where failure malfunction directly threaten human life cause risk bodily injury. [Product usage] Design your application that product used within ranges conditions guaranteed Elpida Memory, Inc., including maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions other related characteristics. Elpida Memory, Inc. bears responsibility failure damage when product used beyond guaranteed ranges conditions. Even within guaranteed ranges conditions, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Elpida Memory, Inc. products does cause bodily injury, fire other consequential damage operation Elpida Memory, Inc. product. [Usage environment] This product designed resistant electromagnetic waves radiation. This product must used non-condensing environment. export products technology described this document that controlled Foreign Exchange Foreign Trade Japan, must follow necessary procedures accordance with relevant laws regulations Japan. Also, export products/technology controlled U.S. export control regulations, another country's export control laws regulations, must follow necessary procedures accordance with such laws regulations. these products/technology sold, leased, transferred third party, third party granted license these products, that third party must made aware that they responsible compliance with relevant laws regulations.
M01E0107
Preliminary Data Sheet E0357E10 (Ver. 1.0)
Other recent searches
WM2639 - WM2639 WM2639 Datasheet
Pin16-14 - Pin16-14 Pin16-14 Datasheet
MW500-1530 - MW500-1530 MW500-1530 Datasheet
LM2904 - LM2904 LM2904 Datasheet
HIN201 - HIN201 HIN201 Datasheet
HIN213 - HIN213 HIN213 Datasheet
HCS160MS - HCS160MS HCS160MS Datasheet
2SK2097 - 2SK2097 2SK2097 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
