PRODUGT DESCRIPTION IOGEN* JTAG Boundary Scan Series us

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PRODUGT DESCRIPTION IOGEN* JTAG Boundary Scan Series us

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PRODUGT DESCRIPTION
IOGEN*
JTAG Boundary Scan
Series uses novel tool, 10GEN, compile large number permutations including logic type, JTAG, slew rate control, etc. With this tool, macros constructed user from library primitive components such input output buffers, termination resistors, JTAG control logic elements, etc. IOGEN creates these userspecified macros combining primitive elements together producing netlist, symbol, schematic, timing additional descriptive files. Cell generation based upon information contained cell templates. These templates categorize types such invertinglnon-inverting inputs, 3-state bidirectional, scan clock drivers, etc. Each template contains information about when applies, list ports cell type, list primitive instantiation required build list user parameters which must considered when making these choices. interface
Series cell includes JTAG logic which will built-in minimize impact performance gate overhead. Also, JTAG control scan data signals between l/Os connected automatically design. ,*!. Selectable Output drhre `%3, available from single l(Q$*$~p three cells paralleled .rn,$ from single output pin. (All JTAG outputs b$~r~'~ls parallelable, have higher current c,-m$brsions available.) Unused output drives ~F@s@'to drive highly loaded internal signals such C1-iwoks. Slew Rate Control a~++~$ Because high spetmhf 1/0, slew rate control outputs availa~(~%$[$~uce system noise well over-shoot ar@@$~@hoot output signals caused fast rise falltw:tiany output buffers have moderate (+80Y0)andslo$k@50Y0) slew control version.
able drive system backplanes while still occuThree##&lht oscillator macros available pying only single site sites 25$2 ~#%-s4rrays: non-inverting buffer, clock buffer, This licensed implementation provides high-performance Sc~mit$~igger versions. These macros configured interface drive FtlSC/CISC processor applica@~mic''hsonators from above with tions system speeds exceeding MHz. ~?~a~ crystals. PECL interface .'::!, ,)"~:. `;\* standard Pseudo voltage inputs created etiern~:i~'triternal Macrocell Library ,.\;*$i ,,,, ~,t:k logic functions special ciock control distribution `~:$,~ !brary been optimized from Motorola's chir.x brought directly onto chip either differWextensive H4Cm Series library provide most ,j~,.i: .,%$?, tiai"or single-ende~ configurations. popuiar efficient functions, including several scan differential PECL output buffer* provides ar@&@&de macros, library. ~?:$a .i$?. external PECL iogic function other ASIC F&2~%Q~@. Series internal celis have been selected interface Macroe $,.,. /<"l:~\,it-+' achieve highest efficiency top-down design methodolPCI (Peripheral Component lnte~:&~fi high-perogy. Experience with Synopsys synthesis toois resulted formance local-bus standard c~n'~n high-speed narrowing focus macro those funcpeflpherals proceeeor/memwy ~dms. procestions which maintain high level routability while maximizsor independent provides f&#it@ interface control, real estate utilization. error reporting, arbitrati@';''@@onalfeatures include 64This approach wiii continued future generations extension, interrupt,:=~cache support JTAG CMOS macro libraries, providing upward compatibility boundary scan. MR$@wies library includes functions specified hardware description language. compliant buffers. .!:.s .$'. Several types macrocells available high-drive sCi-LVD9"W@@dffera complementary output versions. High-drive versions provide Motorola's~+mentation Scalable Coherent interface-Lo@W3ftage Differential Signal (SCi-LVDS) buffers provid$&k&@~ower alternative high-speed interfaces. lnp$t$~supto311 achieved. f~:wations SCI-LVDS range from digital video *iW@$rnmunications tightly-coupled processor/cache inter"'@#es Systems longer limited slow buffers critical chip-to-chip paths. *(Consult your nearest Motorola Sales office availability). Special Functions Series library inciudes anaiog PLLs, BIST, JTAG functions. improved performance nets with high fanouts. exampies, CMND21 smailer delay better balanced than standard-drive CMND20 same fanout. Series internal cells optimized provide symmetric rise fall ratee without performance penalty. This aliows simpler timing calculations more reliable system operations.
o*iiq~*
MOTOROLA
Series
ARCHITECTURAL FEATURES
Series offers solutions many today's design problems. increasing application complexities place higher demands performance, clock skew management, testability, capability, workstation based design environments. This section describes special features Series that provide solutions these requirements.
Analog Phase Locked Loops
Motorola offers optional analog synchronize multiple ASIC chips clock synthesis. Optional analog PLLs diffused into three corners array require area within core. PLL's operate (VCO/2) with only phase plus jitter e&or.
Design Testability
time cost test ASIC increases exponentially complexity size ASIC grows. Using design-for-test (DFT) methodology allows large, complex ASICS efficiently economically tested. Motorola supports methodologies, including ESSD/ LSSD scan, JTAG boundary scan, BIST memories. ESSD/LSSD Scan library offers level sensitive latches edge sensitive flip-flops support LSSD ESSD scan design techniques. This enables manual automated design muxed-D style scan techniques. Commercially available ATPG (Automatic Test Pattern Generation) tools, such FastScanw, along with appropriate libraries, used perform automatic scan insertion, test vector generation, fault grading. JTAG Boundary Scan
J#ifi
VCO12 Frequency Range
Frequency multiplication Phase Error+ Jitter
Max. Clock Tree Delay 50f#$~ "'x'"' .,:i,i,.,,: ;.;1 <Iofls Max. Lock Time \,i.y `%,~y', (CMOS),7 (PECL) Pins APLL ~s>!:. .,,,, None External Component?&w .,.,. ,>+,
SRAM ~$~@rnpilers
Fe~,t@@AMand compiler provides access thousandk@f combinations single- dual-port SRAM bl~cks. These blocks synchronous with int,s$q~ BWfering self timed clocks simplified system ,g*igt$ .i3.,F,,:,> +.S:J fiese memories were designed high performance Motorola's JTAG JTAG control macrocells `"'!Qwpower with zero power when active. Several alternadesigned conform IEEE 1149.1 JTAG boundary ,,$? tives usually available each combination word scan specification. JTAG macrocells designe@do length depth. SRAMS have separate data input optimize performance minimize silicon overheq~"~, output busses. BIST capability optional cliffused embedding sequential multiplexing lo9ic wit~:$~' .$<.::}, metallized compiled blocks. **:,, *,f& sites array. .~$:( metallized SRAMS family synchronous sino Built-In Self Test `wr' -+::.$' ,,,,, x,,, dual-port blocks. These SRAMS gate array versions Built-in-Self-Test (BISQ~%llable based (not diffused). memories: "Pseudo-Random" BIST provQes~ Simple impleDiffused SRAMS available request thousands mentation, which requires gates#n@sdh achieve fault combinations single- dual-port configurations. coverage 99%. `Comparato~Q~$on other hand, more comprehensive desig~,,uf$g deterministic Singl~Port Dtiusecf SRAM march pattern which requir~'w~gate overhead, :>:: Words 131072 achieve 100°/0fault cover,~ge%k~ .,!? ~'.' Bits increments Dual-Port Diffused SRAM Clock Distributi,Q~L~anagement ASK'S W&**g integral part system design regul@~%Rd interfacing with multiple chips inclucfing other A$f&$%lcroproceseors memories. Optimizing petio~*.~$such systems rests maximizing communication-~,f&?een chips using synchronous interfaces. Clock ske~.@Rtrol distribution, both on-chip between chip%ls critical importance.The Motorola solution clock management clock tree control skew on-chip analog control clock skew between ASIC'S. Clock Distribution Motorola offers clock tree synthesis during layout build balanced clock distribution networks (clock trees). Clock trees load-balanced networks that synchronize clock signals on-chip sequential elements. Clock trees have minimal effect design routability, critical data paths, timing driven layout floorplanning. MI15C Series Words 65536 Bits increments following list limits single block memory. Single-Port Metal SRAM Words 4096 Bits increments Dual-Port Metal SRAM Words increments Bits increments Contact P~gremmable Words 32768 Bits increments
MOTOROLA
INTEGRATED
OPEN ARCHITECTURE
Open Architecture highly versatile powerful
DESIGN SYSTEM SOLUTION
Supports multiple technologies: Series, Series, H4CPIUS Series, H4EPIus Series Series
SYSTEM(OACS) offers design environment
Syste
design Motorola's Series CMOS arrays. OACS integrates several industry's most powerful design tools with selected Motorola high-productivity tools into standard verilog EDIF netlist based environments. information this Data Sheet reflects major versions OACS: OACS OACS OACS Motorola's point tool solution based Cadence Design System's Conceptm schematic editor, Synopsys' synthesis tools, Cadence's Verilog logic simulator. OACS Motorola's framework based solution using Mentor Graphics' Falconw Framework. This solution provides support Mentor's design entry tools QuickSim logic simulation.
OACS Design Flow
Supporled HP900017XX SPARC@ workstations ,*!. :k:,.
,P.<.\.@& .+*rit,
From conception your design ~&K*~on, will that OACS design flow accu,t4$@@&cient, flexible. design flow three basi~%% (see Figure design capture verification, p~:d>sign, post$<.>,. Iayout design verification.
Design Capture Ve&#ion pre-layout design p~e~"'by
customer
usin9
OACS Features Supported Third-Party Design Tools: Cadence
Concept~, Composerm, Verilog-XLm, XL@, Draculaw, Gate Ensemblem Verifault-
OACS tools develop .aq@~lb%.rlate ASIC product. addition schematic.,,@@tu&, designs synthesized using hardware @@tion language (HDL VHDL), equations, truth design maybe floorplanned optimize o~performance. PrediX, Motorola's floorpianning to.~@~W experimentation with various floorplans achiev~$#ii@d gate density performance goals. additi@; .!%W4N provides designer routability informatio~ tow~jde designer floorplanning phase. this
design phase, delay timing calculations, s~tltath~ verification, automatic test uattern generation, static Mentor Graphics $%}~,~?ing analysis performed: Pre-la~out simulations FastScanm, DFTAdvisor, ASICVectors Interfacem $$::.?.<+,~l+,,, estimated besfftypicai/worst-case delays based gate, Falcon~ Framework, Design Architectw, load, slew rate, floorplan driven estimated delays. QuickSim Itm, QuickPathw, AutoLogicW Prior release design layout, test vectors created customer must pass specific rules take full advantage Motorola's production test equipment.
Physical Design
Physical design, place route, performed Motorola's Option Development Engineers (ODE). dedicated each option works directly with customer satisfy their layout requirements. Options such timing driven layout clock tree synthesis available optimize silicon performance. Optionally, user choose PrediX (Integrated Placement Solution) perform macro placement target leave only routing ODE. PrediX only enables customer control actual placement critical paths within circuit, also improve accuracy estimated parasitic resulting estimated timing over that provided standard PrediX floorplan. Upon completion physical design, back-annotation data actual wire routing lengths parasitic provided customer post-layout verification. Estimated, pre-routed actual (back-annotated) capacitances Delays includes intrinsic, rise/fall time, output loading distributed delays Continuous process, temperature, variation Clock skew management: Analog macros voltage wire
Post-Layout Design Verification
clock-tree synthesis
post-layout design verification performed customer assure that physical layout design satisfies performance timing requirements. Post-layout simulations actual parasitic obtained from physical layout provide simulations that represent circuit's behavior silicon. Following successful post-layout design verification customer sign-off, Motorola begins manufacturing ASIC design.
MOTOROLA
Series
Behavioral Description
CREATE.BLOCK
Create Directory Structure
DESIGN_lNFO Collect Design Data
Verllog QuickSim Behavioral Simulation
ASIC_CONCEPT
Design compiler Logic Synthesis
Schematic Capture
!.:.s
N@/ists
Teat Compiler DFTAdvisor Test Synthesis
VerilogNatiists
EDIFIN Design Translation
Daeign Arohiteot S$&@qti&CAa@ure
~1,.:. .$w.? \$lit\~l. .~':.:.
Mentor
EDDM Database
Pinout Ring Definition
.Y:.*:;W .,.\
ASIC_CONFIG Control Files Verilog Functional Simulation pred[)( .*''"
Design File Creation
Sl~EPj'Design `*{y.i.li~i .!:+,,
File Creation Catfo/ f//es
rviing,
,JWicklm
Placement
Functional Slmulatlon
Estimated
&.o&Pre.ction
Metal Lanoths anddbs
QuickSlm Post Layout llming Simulation
:,.,.,.
ASIC_FaatScan
ATPG Fault Grading
Scan Test Patrems
QuickPath
Timing Analysis
FuncticmalTest Partems
Functional TestPatterns
TeatPAS Test Pattern Processing
Varified
TestPatterns
ASIC_RELEASE Release Files ED/F Nat/ist, Layout& Test Vector Data
Actual Metal
Gate Ensemble, Dracula Layout
Lengths Capacitances DECAL Back-Annotated Timing Actual 77ming Data QuickPath Timing Anaiyais
ASIC_MOTtVE
Timing Analysis Post-Layout Simulatin
ASIC_Verllog
QulckSlm Post Layout Tming Simulation
Release Motorola
Figure OACS Design Flow
Series
MOTOROLA
PACKAGING
studies. resultant action slow bake moisture from package shipping drypack bags QFPs, TEQFPs PBGA packages will shipped shield unit from moisture absorption. Units baked Motorola baked drypacked. trend towards Sur125 hours, cooled placed vacuum sealed face Mount Technology (SMT) with high density, thinner drypack with desiccant bags, humidity indicator card, packages (which more sensitive thermal stress failure identification stickers. during board mounting) Motorola conduct numer,*!. `%3, &<.\.&& .\"+;.,. Table Package Selection .?.$,;>~':" *#,t+. ::;,j~$j~] \&&f#& #q~@fq ;$': *,;gg~y, :'<:,::, !',,2 `.:<"; ;":.;' .":3! :%.: ~t;i.>.,j;.*. *.$.>< ,.'+TK@~ \.>NW} ~14ij `&`: 47@:j? :"247 CDAArray (Die Size) d~@:e3+P Cells "'YJ,$%J+ Programmable Signal $$%364 Power Ground Pads* ,+:,"~ Dedicated Power Drypack Protection
Ground Pads*
(CU)
(CU) (CU) (CU) TEQFP** (CD) 208TEQFP** (CD) PBGA (CU) PBGA (CU) PBGA (CU) PBGA (CU)
$m,:;' ,'x~;%,) "c$$i;::~" .2:.
,<.!. .4,:. "%&, .!?.:t.<\>:,\;>,\ ,.*.
Numbers indicate Wirebond pads available. each Am@P@ additional signal pins dedicated power QFP: Plastic Quad Flat Pack (CU) denotes Cavity Up#{~@\j@notes Cavity Down .(.,\> .$l:?,$?,l:: ,,\. TEQFP: QFP-type package with heat slug PBGA: Plastic Ball Grid Array -Prototypes su{,W~6TPAC packages, with production GTPACor OMPACpackages. Available ".J31:W7, Flexible power assignment when APL#$ used .\.i! ::\+.\" .<.~ `~-,' ",~i., **Prototypes will supplied in,~Icr~=@l packages; however, production parta supplied equivalent thermally enhanced package.
Qualified Package. (consult sales fo($q-tion status) M5C208 M5C307 array ties OVDD3 power planes together. Note: OMPAC package used $tJt?
,$.s.< .$/,.
,\\.,
.,<,
~:+~'s~>t,.
.~$.,, .,,. :\,,. .>,,.<, ,:.:$ :/+.!
$<,.>,
.,&\
.),4
Gate Ensemble, Dracula, Verifault, Venlog trademarks Cadence Design Systems, Inc.
HP&200/7XX Series trademark Hewlett-Packard, Inc.
ASICVectors Interface, AutoLogic, Design Architect, FastScan, QuickPath, QuickSim 17meBaseare trademarks Mentor Graphics Corp. CMTL, FeliX, GTPAC, HDC, H4C, H4CPlua, H4EPIus, M5C, IOGEN, MicroCool, OMPAC, OACS, Open Architecture System, PrediX, TestPAS trademarks Motorola, Inc. SPARC registered trademark SPARC International, Inc.
DesignWare, Design Compiler, Compiler, Test Compiler tradematlw SUN-4 registered trademark Mlcrosystema, Inc. MOTIVE registered trademark Quad Design Technology, Inc. trademark Xerox Corp. Synopsys, Inc.
Series
MOTOROLA
MACRO LIBRARY
following tables detail elements which make Series library. elements organized into following categories: Peripheral Macros, Internal Macrocells, Hard Macros, Power Macros. Peripheral Macros summarized function into three tables: Inputs, Bidirectional Outputs. Most Peripheral Macros built using IOGEN listed macro name this data sheet. Peripheral macros generated K)GEN referred Hard Macros. Gates Equivalent gate count (Internal Macrocells) System/Core Voltage definition: Volt System Volt Core 5/3.3 Volt Tolerant System Volt Co@$ Volt System Volt Core .,w,~:t$:f~ ,*.: .,e~,?>
I/es
IVGA1O
Input Logic
Logic
no]" no].
SCI-LVDS Input Logic ,.,$< `%"'*"' `.\t.i.&,.l. Irmut Loaic
nol"
t-lo
Logic
2,4,16 2,4,8,16
Logic
120,401
electrical specifications additional information
MOTOROLA
Series
MACRO LIBRARY
Series Output Macros
Outi.wt Logic
2,4,8,16 2,4,8,16 2,4,8,16 2,4,8,16
,+$,., ~e., <:$i~s'~'
.,,,.
\;:.
`+,~
.1.,O ,'$.
nolo
output #ogij.N ,,pg$ ,&-* GTL,Kk&&k&oaic
Series
MOTOROLA
MOTOROLA
Series
MACRO LIBRARY
AND/NOR, AND/OR, OR/NAND, OR/AND GATES
12,1-Input AND-OR-invert, Drive ,*!*
ICMTB03
ITBuFPH
/Non-lnvetting 3-State BUFFER Enable Drive
ICMTI03
INVTPH
Iinverting 3-State BUFFER Enable Drive
h15CSeries
MOTOROLA
MACRO LIBRARY
13FFRPH
FLIP-FLOP
W/Reset.
Drive
.&''''"T%
LATNH
ID-t.
W/Scan CMSL09 into D-Tvpe Drive
MOTOROLA
Series
MACRO LIBRARY
IALLVSS
.d&'@+SS,
VSS, VSSL
VR08
VR12
Input reference voltage inputs reference voltage other reduced swin interfaces which require termination voltage input reference sirxde operation
Series
MOTOROLA
MACROCELLEXAMPLES lX-Drive, Flip-Flop, Multiplexed Scan) Input
CMDF02
Ea25sEl
Rev. MACRO INPUT CAP.
SDI]SEICKI]QIQB
1.,::"::,.1
LXl_xlxl~lQIQBl
,-:wp ,%,.*.:
CMOS SWITCHING
CHARACTERISTICS
Parameter
(Input Edge Rate tr,tf=0.66ns)
v~.$~ ,.:,,.$), Nom. ,,$ws$~:~:'$ Vnn= T.#X;bC Unit 1.073 1.117 0.922 0.467 0.375 0.514 0.457 0.800 0.604 0.850 0.709
Rev.
FO=l FO=O CMDF02 tpLH tPHL Propagation Delay, Propagation Delay, 0.752 0.645 0.589 0.792- 0.833 .fl:&.Qj 0.879 0.631
(ne/pF) 0.870 0.738 0.929 0.946 1.807 1.248 1.827 1.367
tpLH tpHL
0.574 0.617 Output Rise Time, 0.135 o.21@:i 0.301 0.145 O*@q$ "0.260 1Outnut Fall Time. Outfmt Rise Time. :,fj$&&@ 0.346 0.178 o.206 &&j9 Outnut Fall Time. -T-. 0.332 Gapaclanca tanout= 0.046 (metalcapacitanceISnotmduoqa).
MOTOROLA
Series
MACROCELL lX-Drive, 2-input NAND Gate
EXAMPLES
CMND20
FUNCTION TABLE
MACRO CMND20
EQUIV. GATES Rev.
MACRO OUTPUTWINPUTS XIA,B CMND20
FO=O 0.176 0.107 0.207 0.089 0.180 0.121 FO=l CMND20 0.233 0.154 0.263 0.137 0.307 0.223
CMOS SWITCHING
CHARACTERISTICS Parameter
(Input Edge Rate tr,tf=0.66ns)
tj+f[
Propagation Delay, Propagation Delay,
Output Fall Time, Capacitanceper fanout= 0.046 (metalcapacitanceis included)+~.~iy ,.*,
,-:!. ,.$?,: ~.,,,:y .sl.+, ,$.:-. Nom. `".s 25.Q:@;$ unit FO=2 FO=4 .,,, ,.+,.?. .,~,,, .,., .,,,.,,':. 0.290 o>~;~b> o.631 0.202 ,<$$oig~ 0.486 0.659 0.320 T&h$33 &.282 0.475 1.200 0.690 ,Jk&% 0.936 0.528 .,., $.9.3$5
Rev.
(na/pF) 1.236 1.031 1.229 1.050 2.772 2.215
lX-Drive,
2-input Gate
#4CTiON TABLE
CMNR20
CMNR20
CMOS
Syrl,(
Swl~@~ '"+js:~ ,,\\,,$h. ,,s,.
CHARACTERISTICS
(Input Edge Rate tr,tf=0.66ns) Nom.
Ffev.S
Parameter FO=O
VDD=3.3 25.0°C
,.,>. >.,*.: ,,:*,\, "-,,."~ !\~:*.x:$,&.
`tf++L tPHl Propagation Delay,
FO=l
FO=2
0.382 0.150 0.389 0.182 0.615 0.276
FO=4
0.544 0.212 0.551 0.244 0.986 0.391
FO=8
0.867 0.336 0.875 0.369 1.727 0.620
Unit (na/pF)
1.756 0.672 1.762 0.676 4.027 1.245
CMNR20
0.301 0.221 0.120 0.089 0.227 0.308 Propagation Delay, 0.151 0.120 Output Rise Time, 0.245 0.430 Output Fall Time, 0.219 0.162 Capacitanceper fanout= 0.046 (metalcapacitanceis included).
Series
MOTOROLA
MACROCELLEXAMPLES
2X-Drive, 2-input Multiplexer
MACRO
EQUIV. GATES
0.297 0.452 0.476 0.616 0.117 0.128
FUNCTION TABLE
Propagation Delay, DO,D1to tp~, Propagation Delay, tPHL Output Rise Time, Output Fall Time,
0.327 o,@3@ .,<5.414 0.485 ,,,o.%@ 0.585 0.505 ,,<? 0.534 0.593 0.6@@Q~ &682 0.748 0.364 QiJ~Q,,<,j~.240 `~p,tt~ 0.244 0.361
0.531
0.717 0.711 0.880 0.610 0.594
0.634
0.720 0.639 0.718
1.341
1.265
Capacitance fanout 0.046 (metal capacitance incluid).
MOTOROLA
Series
MACROCELLEXAMPLES
COMPILERS
Series diffused RAMs compiled, single- dual- port static RAMs. Motorola's FeliX compiler used generate required data. acceptable configurations, FeliX provide several versions given with varying performance physical implementations. FeliX datasheet main source information understanding utilizing interest. following example datasheet single-port RAM. ,:!$,.
Series
MOTOROLA
MACROCELLEXAMPLES
MOTOROLA
Series
MACROCELLEXAMPLES
Metallized Single-Port
Series
MOTOROLA
ELECTRICAL
CHARACTERISTICS
Table Preliminary Electrical Considerations Series Arrays
testing, only. range wider simulation purposes%,, ,~:,-~ Notes: parameters characterized conditior@@er thermal equilibrium been established. Unused inputs must always tied approfw~at?+%gic voltage level (e.g., either VDD). This device contains circuitry protect tiB'W against damage high static voltages electric fields; however, advised that normal precautions taken tWiW#k$pplication voltage higher than maximum rated voltages this high impedance circuit. proper operation ra@'~,@ed that constrained range VSSS VOJSVDD.
MOTOROLA
Series
ELECTRICAL
CHARACTERISTICS
Tabie Preliminary Electrical Characteristics Series Arrays -4(I"C 85"C) 0VDD3,VDD,VDDL4 .3WQ.3V, OVDD5=5V+-10% Guaranteed
LVCMOS Inputs (3.3 Inputs Tolerant)
-0.3
v~+o.3 VDDti#T%~ ,~.,b~:&$,*~ ~?,,+.+ `:,}
LVTTL Inputs (3.3 Input Voltage, CMOS Inputs Tolerant)
LVCMOS Inputs (3.3 Inputs Tolerant) LVTTL Inputs (3.3 Input Leakage Current, Pull Resistor with Pullup Resistor with Pulldown Resistor Output High Current, CMOS,lTL Output Type (5V) Output High Current, Output Type Tolerant) Output High Current, 16rfIA LVCMOS, LVITL Output Type LVCMOS, LVITL Output Type LVCMOS, LVITL Output Type LVCMOS, LVITL Output Output Current, CMOS, Output :.,, .:t:.: Output Current, %}f,,.* Output Type$~o~erant) Output Currq@T%r 16mA LVCMOS, ~Output Type LVCfv&$&@~L `.4i,', Output Type OVDD3 =Min, Max= Volts OVDD3 =Min, Max= Volts 24.0 12.0 OVD~3 Min, IOH= -100 OVDD3 Min, IOH= -100@ Output Impedance OVDD3, OVDD5 Vout 0VDD3-0.2 OVDD5 =Min, ,,$$$, Min= 0,~i~V~5
OVDD3 +~x$j OVDD3
.,,.,
-4.0 -4.0 -24.0 -12.0 -6.0
%.&bfi
.,:, "yqVDD3 ~,,?\\.~VoH Min= OVDD3 ,+~}:"$
~y$y~, Output Type 2rn~i~$W'OS, LVITL Output Type $utqhiigh Voltage, LVCMOS %tput Voltage, LVCMOS
Output Leakage Current, 3-State Output Output Leakage Current, Open Drain Output (Device Off) Quiescent Supply Current
Output lmpedanceVoUt OVDD3, OVDD5 lout
Design Dependent
Site Macro 3.3V 10%, only. consult factory.
Series
MOTOROLA
ELECTRICAL
CHARACTERISTICS
Table Preliminary Eiectricai Characteristics PECL Receivers ('la -4(I"C 85"C) 0VDD3,VDD,VDDL=3.3VM.3V, OVD05=5VA100AGuaranteed
Characteristics PECL Receivers
VIDH
Differential input High Voltage, PECL Differential Input Differential Input Voltage, PECL Differential input Input Common Mode Voltage Range, VICM vlcM
VICM VICM Consuit factory vin=vDDv VDD=MSX
VIDL
vlcM
Input High Current, PECL Input Input Current, PECL Input Quiescent Supply Current PECL) Quiescent Supply Current PECL)
b/DD5-0.8 `$ii `X$t,. t>:$t:+;.+t, `":; ,'.%+,:~;~': :>"'.**' ,<$.J
Vin=Vss, VDD=MSX~.,,.,. .W+,
iD~*
iD~*
tested.
,,,>."
,;'> .,.i,{,:j> $>j> ,$$'*J ,*,.,?,.
~,:+:
!$,>
<$.i:+,,,, .s!JJ$,!!
Tabie Preliminary Electrical Characteristi@~&#15C Series Buffers 85"C) 0VDD3,VDD,VDDL=3.3Vti.@@ki OVOD5=5V*1O% Guaranteed
t,+qrim~ermics ,.,. mecenrers
input High Voitage input High Voltage
Input Voitage
`t$p$
Toiq#@~+@'
10.4750VDD3OVDD3+0.5
`.:J,.*, t%,\~,.s$'&: $.'. >,\\+\, $%,. Input Voltage (5W,Tck@r%t) input High Leaka&, Owrrent input Le$#a~ &rrent .J~" W.".$*} .p.:~ O<Vin<VDD, VDD= O<VI"<VDDYvD~=
-0.5
V())+
,>,,,
Characteristics Drivers
iout= -500 iout=1500 OVDD3= OVDD3= 0.90VDD3
+-R*
Out~@Hi@tWoltage
V(-JL
0~'~,@w
Voitage
vo~p&JP &put i+gh Voltage Minimum k$nm<"$ Output High Voitage Maximum Jj@;;in Output Voltage Minimum .$y,. ",:;;,'wo~]n Output High Voitage Mhimurn Tel) $8,.,,.*
~.,~ 1;$,,,,::):> ,.?,
Characteristics Drivers (Not Tested)
iout= OVDD3= iout= -115 OVDD3= lout=48 OVDD3= iout= OVDD3= OVDD3= lout= OVDD3= 0.30VDD3 0.60VDD3
v~mw Output Voitage Maximum
Output Voltage Maximum Tel) OVDD3 system raii supplied chip.
MOTOROLA
Series
ELECTRICAL CHARACTERISTICS
Table Preliminary Eiactricai Characteristics -40"C 85"C)
Characteristics Receivers
Input High Current, input input Current, Inputs Ref. Voltage
Vin=VTj VDD=Ms)(
.:*,
Vin=0.4V,
t.,.,*. t,+, ~l.$$)$ `$:.,:'8\ $},`"*4 .,.-
v"~()~ iDD*
(zf~) v~$q% (2/3) +0.2% ,,.\ Typicai Quiescent Supply Current J%,+s.-. Characteristics Drivers ,$~>~ty>? Output High Voitage, 20mA Output Macros 40mA Output Macros Output Voltage, IOH=-lO@, VDD= `<{~ .s"%~ ,.5, -0.05 +0.05 +0.05
voH*
ioH=-l O@l, VDD= ,,;$~$k,
ioL=20 VDD= ~;y$~>$,vb+.)
-0.05
[o~H lozL
20mA Output Macros 40mA Output Macros
>.s.;. :.$*,
loL=4'o vD~="t%#
Output Current High Output Current
Vou,=l ~$jVD# v~ut=O.~:~,~D=
Parametric production tested guarante,$ct:~.~". Notes: Recommended: 1.2V Vv@$~3) ~:.~ $:.$* 25f2/50f2.
Series
MOTOROLA
ELECTRICAL
CHARACTERISTICS
Table Preliminary Electrical Characteristics Series Buffers -40"C 85-C) VDDL=3.3W Guaranteed
Vc)s Vc)s
Output Offset Voltage Output Offset Voltage Output Impedance, Single Ended mismatch between change differential voltage between complementary states change output offset voltage between complementary states
RLOAD= External RLOAD= Internal ILOAD= ILOAD=
1125
AVOD
AVoS
RLOAD
,,>$.q RLOAD= 19!. .,.,.,+
~<,h ,,\b\,~.::?,t.\
Reoeiver Speoific#&s$
voltagee given with reepect re~.~
e~cuit ground voltage
VIDH VIDL
hput voltage range, vlAOr
Differential High Input threshold Differential Input threshold Receiver differential input impedance
IVGPD 9,@, mV5'J lVG~ ~@@lrtV $~,~4+Q#0mV R:==
2400
+100 +100
,JNiw? Specification ~Clock'
Clock signal duty cycle fall time, `""%*, `,,~;>, `d?~d$
ZLoA~= 100,
ZLOAD=100,
1'%0
tsKEwl*
tsK~w2*
ltPHLA tPLHBl ltPHE~$~HAl Differentiai skew ,,,r,~k~,,,,$ ltPDIFFl tPDIF~$, Channel-to-~an$ f!$kew
differential pair signals differential pair
ltPDIFFHUVT$#DfFFLHli tsKEws* Pulse.wih@fstortion
Receiver AC$@&#i@ions: This specification must maintained (100 <400 .,:* .'.!' .<ti&{*' throughout receiver common-mode operating range. $t$:t> ,.,-.,ij. *Skew.,~'&@MWments made point transition `W@N@$$Mrements made OVdifferential (the crossing single ended signals)
Tr_~*'
#>*:{\*. .$:::$l{
*.4: ~.,[.
Receiver
vo~= VoA-voFj
`dos= (V~A-Vo#2 AVos=lVOs(high)-VOJlow] AVoD=[VoD(high)-VoD(lowj
`GPD
VIDH= vlA-(high)vlB(lOW)
v,D~= v,~-(high)vlA(lOW) Figure LVDS Interface
MOTOROLA
Series
Notes:
Series
MOTOROLA
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Motorola rWew~t~@t make changes without further notice products herein. Motorola makes warranty, repreaanhtion guarantae regarding suitabi~'&.~r&u&s partkdar purpose, does Motorola assume liability arising application product circu[t,and limitationonsequential orhmkffmtdamages. `%@=Il" arameters anddovaryind~erent specificai$,%[aii?is Iiabillty, includlng without appiiq,~;:$~b~mting parameters, including "TypicaIa"must validated each wstomer application customer'stechnical e~erts. Motorola does rights northa rights others. Motorola products designed, intanded, authorlzad components license under Patent ,<:$sY$@ern,$Jntended SUr9iWIlmPlant tiY, other aPPkatlons Intended SUPCOrt eusrein life, other application which failure ,~8*torola Product could create situation where pereonal inlury death occur. Should Buyer purchase Motorola products such `%$;l$f?i!ended unauthorized application, EWyershall indemnity hold Motorola officara, employees, subaldiarfaa,afflllates, dlatrfbutoraharmless !2$';@gainst claims, costs, damages, expenses, reasonable attorney fees arising directly Indirectly, claim personal injury death associated with such unlntandad unauthorfzad use, even such claim aileges that Motorola negligent regarding design manufacture part. Motorola registeredtrademarks Motorola, Inc. Motorola, Inc. Equal
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PRODUGT DESCRIPTION IOGEN* JTAG Boundary Scan Series us

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