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Volt Asynchronous First-In/First-Out Queue Memory Configuration


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FQV01 FQV02 FQV03 FQV04 FQV05 FlexQAsync
Volt Asynchronous First-In/First-Out Queue
Memory Configuration
8,192 4,096 2,048 1,024
Device
FQV05 FQV04 FQV03 FQV02 FQV01
Features:
Industry leading First-In/First-Out Queues 50MHz) Independent Write Read cycle time Asynchronous simultaneous read write 3.3V power supply Fully expandable both word depth width Retransmit capability Full, Empty, Half Full flag indicators Available packages: 32-pin Plastic Lead Chip Carrier (PLCC) (0°C 70°C) Commercial operating temperature available access time 12ns above (-40°C 85°C) Industrial operating temperature available access time 25ns Pin-to-pin compatible with (72V01, 72V02, 72V03, 72V04, 72V05)
Product Description:
HBA's FlexQAsync FIFO offers industry leading 0.25um process technology memory densities from 8,192 System designer full flexibility implementing deeper wider queues using depth width expansion features. Full Empty indicators allow easy handshaking between transmitters receivers. Independent Write Read controls provide rate-matching capability. System designer re-read data from starting position using Retransmit (RET). Retransmit allows reset read pointer initial position. Half Full flag (HALF) available single device mode width expansion mode, depth expansion mode. These FlexQAsync devices have power consumption, hence minimizing system power requirements. addition, industry standard PLCC offered save system board space. These queues ideal applications such data communication, telecommunication, graphics, multiprocessing, test equipment, medical systems, network switching, etc.
3FA09C 2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
AUGUST 2003
Page
FQV01 FQV02 FQV03 FQV04 FQV05 FlexQAsync
WRITE DATA FULL FULL RESET FQV01 FQV02 FQV03 FQV04 FQV05
READ DATA EMPTY EMPTY RETRANSMIT EXPANSION HALF HALF
EXPANSION
FIRST LOAD FIRST
Figure Device Configuration Signal Flow Diagram
Block Diagram Single Asynchronous Queue 8,192 4,096 2,048 1,024
Write Control Logic Reset Logic
Write Pointer
Input Register
SRAM
Output Register
Output Buffer
Read Pointer
FIRST
EMPTY
Expansion Logic Read Control Logic Flag Logic
FULL HALF
Figure Device Architecture
3FA09C 2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
AUGUST 2003
Page
FQV01 FQV02 FQV03 FQV04 FQV05 FlexQAsync
Index
FULL
FIRST
EMPTY
HALF
PLCC (Drw J-01A; Order code: View
Figure Device Pin-Out
3FA09C 2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
AUGUST 2003
Page
FQV01 FQV02 FQV03 FQV04 FQV05 FlexQAsync
Symbol
Name
Input/ Output
Description
Reset required initialize Write Read pointers first position queue setting low. FULL will high; EMPTY will low. Writes data into queue during high transitions queue full yet. wide input data bus. Reads data from queue during high transitions queue empty. wide output data bus.
Reset
Input
Write
Input
Data Inputs
Input
Read
Input
Data Output
Output
FIRST
First Load/ Retransmit
Input
FIRST used differently depending mode. Depth Expansion Mode, grounded indicate first load. Single Device Mode, acts retransmit.
Expansion
Input
used indicate operations different modes. When grounded, indicates operation Single Device Mode. When tied Vcc, indicates operation Depth Expansion Mode. Queue full when FULL goes low. This prohibits further writes into queue._ assertion FULL synchronous falling edge_ deassertion synchronous rising edge Queue empty when EMPTY goes low. This prohibits further reads from queue. assertion EMPTY synchronous falling edge deassertion synchronous rising edge HALF used differently depending mode. Depth Expansion Mode, connected previous device's pin. When previous device reached last location memory, this will send pulses next_ device Daisy Chain. Single Device Mode, when grounded, this indicates queue half-full. 3.3V power supply. Ground. connection.
FULL
Full Flag
Output
EMPTY
Empty Flag
Output
HALF
Expansion Half Full Flag
Output
Power Ground Connection
Table Descriptions
3FA09C 2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
AUGUST 2003
Page
FQV01 FQV02 FQV03 FQV04 FQV05 FlexQAsync
Symbol
Rating
Terminal Voltage with respect Storage Temperature Output Current
Com'l Ind'l
-0.5 +125
Unit
VTERM TSTG IOUT
NOTES:
Absolute Ratings reference only. Permanent damage device occur extended period operation outside this range. Standard operation should fall within Recommended Operating Conditions.
Table Absolute Maximum Ratings
FQV05, FQV04, FQV03, FQV02, FQV01 Commercial 12ns, 25ns, 35ns Min. Typ. Max.
Industrial 25ns Min.
Symbol Parameter Recommended Operating Conditions
Typ.
Max.
Unit
Supply Voltage Com'l/Ind'l Supply Voltage Input High Voltage Com'l/Ind'l Input Voltage Com'l/Ind'l Operating Temperature
ILI(1) ICC1(2,3,4) ICC2
(2,5)
Electrical Characteristics
Input Leakage Current (any input) Output Leakage Current Output Logic Voltage, IOH=-2mA Output Logic Voltage,
Power Consumption
Active Power Supply Current Standby Current
Capacitance 1.0MHz Ambient Temperature (25°C) Symbol Parameter
Conditions VIN= VOUT=
Max.
Unit
Input Capacitance Output Capacitance
NOTES:
COUT(6)
Measurement with 0.4<=VIN<=Vcc Tested with outputs open (IOUT=0) Tested f=20MHz Typical Icc1=15+2*fs+0.02*CL*fc with Vcc=3.3V, tA=25°C, fs=WCLK frequency=RCLK frequency MHz, using levels), data switching fs/2, CL=Capacitive load inputs Vcc-0.2V GND+0.2V =RST=FIRST/RET=VIH) Design simulated, tested.
Table Specifications
3FA09C 2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
AUGUST 2003
Page
FQV01 FQV02 FQV03 FQV04 FQV05 FlexQAsync Commercial Industrial
FQV05-12 FQV04-12 FQV03-12 FQV02-12 FQV01-12 FQV05-25 FQV04-25 FQV03-25 FQV02-25 FQV01-25 Min.
FQV05-35 FQV04-35 FQV03-35 FQV02-35 FQV01-35 Min.
Symbol
tRPW tRLZ tWLZ tRHZ tWPW tRSTC tRST tRSTS tRSTR tRETC tRET tRETS tRETR tEFL tHFH, tFFH tRETF tREMPTY tRFULL tRPE tWEMPTY tWFULL tWHALF tRHALF tWPF tXOL tXOH tXIR tXIS
NOTES:
Parameter
Shift Frequency Read Cycle Time Access Time Read Recovery Time Read Pulse Width Read Pulse Data Write Pulse High Data (1,2) Data Valid from Read Pulse High Read Pulse High Data High Write Cycle Time Write Pulse Width Write Recovery Time Data Set-up Time Data Hold Time Reset Cycle Time Reset Pulse Width Reset Set-up Time Reset Recovery Time Retransmit Cycle Time Retransmit Pulse Width Retransmit Set-up Time Retransmit Recovery Time Reset Empty Flag Reset Half-Full Full Flag High Retransmit Flags Valid Read Empty Flag Read High Full Flag High Read Pulse Width after Empty Flag High Write High Empty Flag High Write Full Flag Write Half-Full Flag Read High Half-Full Flag High Write Pulse Width after Full Flag High Read/Write Read/Write High
Min.
28.5
22.2
Unit
Pulse Width Recovery Time Set-up Time
Design simulated, tested. Only applies read data flow-through mode.
Table Electrical Characteristics
3FA09C 2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
AUGUST 2003
Page
FQV01 FQV02 FQV03 FQV04 FQV05 FlexQAsync
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load
Table Test Condition
3.0V 1.5V 1.5V Refer Figure
3.3V
D.U.T. 30pF*
Figure Output Load *Includes scope capacitances.
3FA09C 2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
AUGUST 2003
Page
FQV01 FQV02 FQV03 FQV04 FQV05 FlexQAsync
Timing Diagrams
tRSTC tRST tRSTS tRSTS tRSTR
tEFL EMPTY tHFH, tFFH HALF, FULL
NOTES: EMPTY, FULL, HALF change status during Reset, valid tRSTC. near rising edge RST. Diagram Reset Timing
tRLZ tWPW
tRPW
tRHZ
Data Valid
Data Valid
Data Valid
Data Valid
Diagram Asynchronous Write Read Operation
3FA09C 2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
AUGUST 2003
Page
FQV01 FQV02 FQV03 FQV04 FQV05 FlexQAsync
Additional Reads
Last Write
tWFULL FULL
Ignored Write
First Read
First Write
tRFULL
Diagram Full Flag From Last Write First Read
Last Read
Ignored Read
First Write
Additional Writes
First Read
tREMPTY tWEMPTY
EMPTY
Q8-0
Valid
Valid
Diagram Empty Flag From Last Read First Write
tRETC tRET tRETS tRETF tRETR
HALF, EMPTY, FULL
Flag Valid
Diagram Retransmit
tWEMPTY
EMPTY tRPE
Diagram Minimum Timing Empty Flag Coincident Read Pulse
3FA09C 2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
AUGUST 2003
Page
FQV01 FQV02 FQV03 FQV04 FQV05 FlexQAsync
tRFULL
FULL tWPF
Diagram Minimum Timing Full Flag Coincident Write Pulse
tRHF tWHF HALF Half-Full Less More Than Half-Full Half-Full Less
Diagram Half-Full Flag Timing
Write Last Physical Location
tXOL tXOH
Read from Last Physical Location tXOL tXOH
Diagram Expansion
tXIS
tXIR
Write First Physical Location tXIS
Read from First Physical Location
Diagram Expansion
3FA09C 2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
AUGUST 2003
Page
FQV01 FQV02 FQV03 FQV04 FQV05 FlexQAsync
Operating Modes
Single Device Mode: When application requirements 256/512/1,024/2,048/4,096/8,192 words less, single device used. These devices Single Device Mode when Expansion (XI) grounded.
WRITE DATA FULL FULL RESET FQV01 FQV02 FQV03 FQV04 FQV05
READ DATA EMPTY EMPTY RETRANSMIT EXPANSION HALF HALF
EXPANSION
Figure Single Device Mode
Depth Expansion Mode: When application requirements greater than 256/512/1,024/2,048/4,096/8,192 words, multiple devices used Depth Expansion. These devices Depth Expansion Mode when following conditions met: first device's First Load (FIRST) must grounded. other devices' First Load (FIRST) must tied HIGH devices' Expansion (XO) must tied next devices' Expansion (XI) pin. Retransmit (RET) Half-Full Flag (HALF) non-functional Depth Expansion Mode. external logic required generate composite Full Flag (FULL) Empty Flag (EMPTY). This requires ORing Empty Full Flags.
DATA
FULL
FQV01 FQV02 EMPTY FQV03 FQV04 FQV05 FIRST
DATA
FULL
FULL
FQV01 FQV02 FQV03 FQV04 FQV05 FQV01 FQV02 FQV03 FQV04 FQV05
EMPTY
FIRST
EMPTY
FULL
EMPTY
FIRST
Figure Depth Expansion Mode
3FA09C 2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
AUGUST 2003
Page
FQV01 FQV02 FQV03 FQV04 FQV05 FlexQAsync
Usage Modes
Width Expansion Mode: When applications require increased word width, multiple devices used Width Expansion Mode. These devices Width Expansion Mode when same signals from multiple devices connected. word width achieved connecting additional devices. Status flags functional device.
HALF DATA (D17 FULL
HALF
FQV01 FQV02 FQV03 FQV04 FQV05
FQV01 FQV02 FQV03 FQV04 FQV05
EMPTY
DATA (Q17
Figure Width Expansion Mode
Bidirectional Mode: When applications require data buffering between systems that capable Read Write operations, pair devices used Bidirectional Mode. Both Depth Expansion Width Expansion used this mode.
FULL System FQV01 FQV02 FQV03 FQV04 FQV05 FQV01 FQV02 FQV03 FQV04 FQV05 FULL
EMPTYY
HALF System
EMPTY
HALF
Figure Bidirectional Mode
Data Flow-Through Mode: There types flow-through modes, read flow-through write flow-through. read flow-through mode, device allows single word read after word data been written into empty FIFO. data enabled after rising edge remains until goes from High. Then goes into three-state mode. EMPTY will have pulse showing temporary deassertion then would asserted. write flow_ through mode, device allows single word written after word data been read from full FIFO. causes FULL deasserted_ causes asserted again data word. word goes into FIFO rising edge must toggled when FULL asserted write data into FIFO increment write pointer.
3FA09C 2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
AUGUST 2003
Page
FQV01 FQV02 FQV03 FQV04 FQV05 FlexQAsync
Data
tRPE
EMPTY tWEMPTY tWLZ Data
tREMPTY
Data Valid
Diagram Read Data Flow-Through Mode
tWPF tRFULL FULL tWFULL
Data Data Data Valid
Data Valid
Diagram Write Data Flow-Through Mode
Compound Expansion Mode: Compound Expansion Mode combination Depth Width Expansion Modes achieve large FIFO arrays.
DATA FQV01 FQV02 FQV03 FQV04 FQV05 Depth Expansion Block FQV01 FQV02 FQV03 FQV04 FQV05 Depth Expansion Block FQV01 FQV02 FQV03 FQV04 FQV05 Depth Expansion Block
DATA
Figure Compound Expansion Mode
3FA09C 2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
AUGUST 2003
Page
FQV01 FQV02 FQV03 FQV04 FQV05 FlexQAsync
Order Information:
Device Family Device Type (8,192 (4,096 (2,048 (1,024 (512 *Speed Slower speeds available upon request. **Package Plastic Lead Chip Carrier (PLCC) Temperature Industrial only offered 25ns Power Speed (ns)* Package** Temperature Range Blank Commercial (0°C 70°C) Industrial (-40° 85°C)
Example:
FQV05L12J
12ns, PLCC, Commercial temp)
Document Revision History:
08/01/03
2107 North First Street, Suite Jose, 95131, Tel: 408.453.8885 Fax: 408.453.8886 www.hba.com
Taiwan Suite 8F-9, Shui-Lee Hsinchu, Taiwan, R.O.C. Tel: 886.3.516.9118 Fax: 886.3.516.9181 www.hba.com
Europe Technology B.V. Nijverheidslaan 1382 Weesp, Netherlands Tel: 31.294.280.914 Fax: 31.294.280.919 www.hba.com
3FA09C 2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
AUGUST 2003
Page

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